tms570ls: real-time interrupt module...
TRANSCRIPT
1
TMS570LS: Real-Time Interrupt Module (RTI)
2
RTI: Block Diagram
3
RTI: Main Features
• Two independent counter blocks for generating different time bases
• Each block consists of
– One 32-bit prescale counter
– One 32-bit free-running counter
– Two capture registers for capturing the prescale and free-running counters
• External event can be used for incrementing free-running counter 0
– Can be used for synchronizing with FlexRay bus communication cycle
• Four compare interrupts
– Each can use either of the two available free-running counters
– Automatic update of compare values to minimize CPU intervention
– Option to generate DMA request as well as the compare interrupt
• Two counter-overflow interrupts
– Generated when a free-running counter overflows and goes to zero
4
TMS570LS: Vectored Interrupt Manager (VIM)
5
VIM: Block Diagram
PRI
ORITY
DECODER
INT0
INT63
FIQ
IRQ
Phantom Interrupt
Address ISR0
Address ISR1
Address ISR61
Address ISR62
VIM RAM
VBUS
REGISTERS
VBUS P
IRQVECTADDR [31:0]
IRQACK }Vector Interrupt
Interfacefrom CPU
P
CHANNEL
MAPPING
P
e
r
i
p
h
e
r
a
l
B
u
s
I
n
t
e
r
f
a
c
e
6
VIM: Main Features
• VIM Hardware
– Dedicated Vector Interrupt interface to ARM CPU
– Hardware relocation of the IRQ vector address
– Hardware assistance for prioritizing and controlling interrupt sources
• VIM Functions
– 64 interrupt requests
– Map interrupt request to interrupt channel via programming.
– Provides programmable priority through interrupt request mapping
– Prioritizes the interrupt channels to the CPU
– Provides the CPU with the address of the interrupt service routine (ISR)
• VIM Modes
– Legacy ARM7 Mode (FIQ/IRQ)
– Vectored interrupt (FIQ/IRQ)
– Hardware vectored interrupt (IRQ only)
7
VIM: Interrupt Servicing Modes
Legacy ARM7 Interrupts
• FIQ/IRQ request
• Fetch from 0x18/0x1C
• Branch to ISR handler
• Load Interrupt offset
• Decision which ISR to execute (FIQIVEC / IRQIVEC)
• Branch to ISR
Vectored Interrupts
• FIQ/IRQ request
• Fetch from 0x18/0x1C
• Branch to ISR
(LDR PC, [PC, #-0x1B0]),
address for highest active
interrupt request derived from
IRQVECREG/FIQVECREG
Hardware Vectored Interrupts
• IRQ request (only)
• CPU reads IRQ vector
address instead of 0x18
• VIM provides address of
highest pending request
directly to CPU vector interface
• CPU branches directly to ISR
• Note - processor state after
IRQ entry: T flag = VECTOR[0],
LSB of vector address
determines if first instruction
of interrupt handler is ARM
or Thumb instruction
8
VIM: Channel Mapping - Default State
priority
high
low
• Note - NMI (Non-Maskable Interrupt): Channel 0 and Channel 1 are called NMI Channels and are non-maskable.
• Interrupt requests can be mapped to desired channel using CHANMAPx registers.
9
VIM: Input Channel Management
wake-up logic is asynchronous, but reset is synchronous
10
VIM: Wake-up Generation
Wake-up interrupt generation
detail of the interrupt
request input
(to global clock module)
11
VIM: Vector RAM
• not initialized after reset
• used for vectored interrupts
• 64 x32bit organization
• 32/16/8bit access
• VIM read has always priorityover peripheral bus interface
• RAM protected by parity
RAMVIM RAM address space
12
TMS570LS: Direct Memory Access (DMA)
13
DMA: Main Features
• 32 channels with individual enable
• 64 DMA requests
– Software and hardware DMA requests (event synchronization)
• Supports 8, 16, 32 or 64 bit transactions
• Multiple addressing modes for source/destination
– fixed, incrementing, indexed
• Auto Initiation
• Channel chaining capability
• 1 FIFO (First In First Out)
• One AHB master port (64 bit wide) to interface with the bus matrix
• One slave port to interface with VBUS for register interface
• Memory Protection for the address range DMA can access
14
DMA: Transfer Definitions
Element
RES
WES
11: Double-word, 64bit
10: Word, 32bit
01: Half-word, 16bit
00: Byte, 8bit
RES, Read Element
Size
WES, Write Element
Size
Element 1
Element 2
…..
Element N
…..
Frame
Frame 1
Frame 2
…..
Frame M
…..
Block
N = Element Transfer Count
(ETCOUNT)
M = Frame Transfer Count (FTCOUNT)
N∙M = Size of Block
15
DMA: Addressing Modes
• Constant
– Source/Destination address do not change
– e.g. SCI transmit and/or receive register (constant address)
• Post Increment
– Source/Destination address is post incremented by the element size(Byte, Half-word, Word, Double-word)
– e.g. RAM to RAM transfer
• Indexed
– Source/Destination address is post incremented as defined in the element index offset register and the frame index offset register
– Indexed addressing always works with Byte size
16
DMA: How to Start a Transfer?
• Software requests
– By setting bit x in SWCHENAS [31:0] register transfer (channel x) will be triggered.
• Hardware requests
– An active DMA request signal will trigger a DMA transaction.
– Up to 64 DMAREQ lines can be handled.
– Since DMA controller is clocked by HCLK, the duration of all DMA requests signals must be at least HCLK long.
• Triggered by other control packet
– When a control packet finishes the programmed number of transfersit can trigger another channel to initiate its transfers.
17
DMA: Frame or Block Trigger (TType)
18
DMA: Request Mapping/Control Packets
19
DMA: Channel Interrupts
• Each channel can be configured to generate interruptson several transfer conditions:
– FTC (Frame Transfer Complete) interrupt
– LFS (Last Frame Transfer Started) interrupt
– HBC (First Half of Block Complete) interrupt
– BTC (Block Transfer Complete) interrupt
– BER (Bus Error) interrupt
20
DMA: Memory Protection
0xFFF78000
0x08003FFF
0x08000000
0x00000000
Region 3
Region 3
Region 1
Region 0
System + Peripherals
RAM
No access restriction
Access restriction apply
0xFFFFFFFF
0xFFF78000
0x08003FFF
0x08000000
0x00000000
Region 3
Region 2
Region 1
Region 0
System + Peripherals
RAM
No access restriction
Access restriction apply
21
TMS570LS: General-Purpose I/O (GPIO)
22
GPIO: Block Diagram
External
pin
GIODSETx
GIODOUTx
GIODINx
GIOPDRx
GIODCLRx
High-level-interrupt
handling
Low-level-
interrupt
handlingGIOLVLSET
High priority
Low priorityInterrupt enable
Interrupt disable
GIOENASETGIOFLGGIOPOL
Rising edge
Falling edge
To VIM
To VIM
VB
US
GIOPULDIS
GIOPSL
GIODIRx
GIOENACLR GIOLVLCLR
GIOINTDET
OPEN
DRAIN
LOGIC
GATES
23
GPIO: Main Features
• Configurable as Input or Output via Direction Register
• Read/Write Registers
• Set Registers
• Clear Registers
• Separate Input Register
• Pull-up/Pull-down Configurability
• Open Drain Capability
• Interrupt Capability
– Configurable Priority
– Configurable Polarity: rising edge, falling edge, or both edges
24
TMS570LS: New High-End Timer (NHET)
25
• User-programmable Timing Co-Processor
• Provides high level and complex timing functions with low CPU overhead
• 128 word instruction RAM with Parity protection
• Dedicated DMA functionality (HTU) to transfer data from NHET to Data Ram w/o CPU
• Conditional program execution based on pin conditions and compares
• 32 input/output (I/O) channels (pins) for complex or classical timing functions such as capture, compare, PWM, GPIO
• Suppression filters eliminate undesired input frequencies
• Multiple 25-bit virtual counters for timers, event counters, and angle counters
• High Resolution I/Os and coarse resolutions implemented by sub loops for multiple resolution capability
High End Timer (HET)
32 I/O Channels
Host
interface
Address/Data Bus
Timer
RAM
Execution
Unit
Input/
Output
Unit
Compare
32 bit ALU
Register A, B, T
Instruction Register
Address Register
Interrupt Control
Operation Control
Program RAM Control RAM Data RAM
CPU wait control
Shadow registers Prescaler
Global & prescale control
register
I/O Control
RegisterSynchronizers
32 High Resolution Channels
26
NHET: Application Examples
Pulse Width Modulation
• Single / multi channel PWMs
• PWM with synchronous / asynchronous duty
cycle update
• PWM with synchronous period update
• Phase shift PWM's using RADM64 instruction
Frequency and Pulse Measurements
• Pulse width and period measurement (using
PCNT)
• Period measurement using PCNT in HR mode,
HRshare feature and 64 bit read access with
“auto read/clear” bit set
Other Features
• Frequency Modulated Output
• Pulse width count (using PWCNT)
• Time stamp (using WCAP)
• Event counter (using ECNT)
• Pulse accumulator example (using ECNT )
• Multi-resolution scheme
27
NHET: Timer RAM
• Timer RAM uses 4 RAM banks
• Each bank supports Dual Port Access (one RAM address may be written while another address is read)
• Third access possibility to RAM by CPU, TU or DMA
• RAM words are 96-bits wide (3*32bit, program, control, data)
• Write access by word (32bit) only
• Read access is allowed by8-bit, 16-bit and 32-bit
28
HETDSETHET[x]
HETDIR
HETDCLR
HETDOUT
HR control logic
HR flags, HR register
HR up / down counter (5 bits)
Timer data in
HR prescale driver
High resolution clock
HR compare data
Timer data out
Timer data inHETDIN
Loop
Resolution
Clock
NHET: I/O Structure
HETPDR
HETPULDIS
HETPSL
HET Pull Control Logic
29
NHET: Instruction Set OverviewMnemonic Instruction Name Cycles
ACMP Angle Compare 1
ACNT Angle Count 2
ADCNST Add Constant 2
ADM32 Add Move 32 1 or 2
APCNT Angle Period Count 1 or 2
BR Branch 1
CNT Count 1 or 2
DADM64 Data Add Move 64 2
DJNZ Decrement and Jump if Non-Zero 1
ECMP Equality Compare 1
ECNT Event Count 1
MCMP Magnitude Compare 1
MOV32 Move 32 1 or 2
MOV64 Move 64 1
PCNT Period/Pulse Count 1
PWCNT Pulse Width Count 1
RADM64 Register Add Move 64 1
SCMP Sequence Compare 1
SCNT Step Count 3
SHFT Shift 1
WCAP Software Capture Word 1
WCAPE Software Capture Word and Event Count 1
30
NHET: Command Line Assembler
• Invoking the NHET assembler (hetp.exe): hetp [options] input file
• Options:
– -c32 produces an output file containing assembler directives for the TMS570
CodeGen Tools
– -hc32 produces a C file and a header file. (used together with the -nx option)
– -nx specifies the x-th HET module on the device (used together with -hc32
option)
– -l (lowercase L) produces a listing file with the same name as the input file
with a .lst extension.
– -x produces a cross-reference table and appends it to the end of listing file.
• Example: hetp -hc32 -n0 pwm.het
• Input: pwm.het contains the assembly source of the HET program
• Output: pwm.c provides a C array, which contains the HET
program opcode
pwm.h provides a C structure, which allows a simple
access to the NHET fields from other C code
31
NHET: Time Base
• VCLK2 is used as base clock for the High End Timer
• A 6-bit prescaler dividing the system clock by a user-defined high-resolution (HR) prescale divide rate (hr) stored in the 6-bit HR prescale factor code (with a linear increment of codes).
• A 3-bit prescaler dividing the HR clock by a user-defined loop-resolution prescale divide rate (lr) stored in the 3-bit loop-resolution prescale factor code (with a power of 2 increment of codes).
High Resolution (HR)
prescaler (6 bits)Loop Resolution (LR)
prescaler (3 bits)VCLK2
Loop
Resolution
clock
High
Resolution
clock
32
TMS570LS: High-End Timer Transfer Unit
(HTU)
33
HTU: Block Diagram
34
HTU: Main Features
• CPU and DMA independent
• Master Port to access directly system memory
• HTU master accesses protected by dedicated Memory protection Unit
• One Slave port to interface with VBUS for register interface
• Maximum of 8 double control packets supporting dual buffer configuration
• Control packet information is stored in RAM protected by parity
• Event synchronization (HET transfer requests)
• Support 32 or 64 bits transaction
• Addressing modes for HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or 64bit)
• Each type of interrupt can be routed to either two different host CPUs
• One shot, circular and auto switch buffer transfer modes
• Request lost detection
35
LAB2: Using NHET as GIO
36
Overview
• In this project we will:
– Create our first HALCoGen Project
– Generate and Import code into Code Composer Studio
– Write code to turn on the LED on HET pin 1
– Build and Deploy our code to the microcontroller
37
Setting up a New HALCoGen Project
• Launch HALCoGen
– Start > Programs > Texas Instruments > HALCoGen
• File > New > Project
• Family:
– TMDX570
• Device:
– TMDX570LS20USB
• Name: Exercise
• Location: “C:\myWorkspace”
38
The Interface
39
Configuring the Peripherals
• Select the peripherals that are required for this project.
– In this lab we need only enable the GIO driver, uncheck all other drivers
• No further changes should be made, the source code can now be generated.
– To do this go to File > Generate Code
– Following, the folders on the right will populate with our new files
40
HALCoGen Help
• Information about the files
and functions that
HALCoGen creates can be
found in the HALCoGen
„Help‟ menu
• Help can be launched from
the main title bar under
Help -> Help Topics
41
Setting up Code Composer Studio 4
(CCS4)
• Launch CCS4
– Start > Programs > Texas Instruments > Code Composer Studio v4 >
Code Composer Studio v4
• When it launches, CCS will ask you to select a workspace, we will chose
“C:\myWorkspace”
• Once it loads, go to File > New > CCS Project
42
Setting up our Project
• Our project name needs to match the name of our HALCoGen Project,
Exercise
• Then Click “next”
• On the next page, make
sure that your project
type is set to ARM and
Debug and Release are
both checked
• Then Click “next”
43
Setting up our Project (cont.)
• We are not using any referenced projects so click “next” again
44
Setting up the Project (cont.)
• Lastly, set the Device Variant to “Cortex
R” and TMS570LS20216SPGE
• Click “Finish”
45
Getting Started
• On the left hand side in the “C/C++ Projects” explorer, open “sys_main.c”
• When ever you generate code in HALCoGen, the program overwrites user
code, except specific sections marked by “USER CODE BEGIN (x)” and
“USER CODE END”
– For code placement we will be referring to the number within the User
Code block
/* USER CODE BEGIN (0) */
/* USER CODE END */
46
Writing the Code
• Inside User Code 1, copy the code below.
• Then in User Code 3, copy the code below.
/* USER CODE BEGIN (1) */
#include "het.h"
/* USER CODE END */
/* USER CODE BEGIN (3) */
/* Set HET port pins to output */
gioSetDirection(hetPORT, 0xFFFFFFFF);
/* Set HET port pin 1 high */
gioSetBit(hetPORT, 1, 1);
/* Infinite loop */
while(1);
/* USER CODE END */
47
Notifications
• Lastly we must insert a function that would be called if interrupts were
enabled. Without these, the code will fail to build
/* USER CODE BEGIN (4) */
/* GIO Notification function not used, but required by compiler */
void gioNotification(int bit)
{
return;
}
/* USER CODE END */
48
Compiling the Project
• The code is now complete and we are ready to build our project.
– Go to Project > Build Active Project
• Now that we have our .out file, we need to program the microcontrollers Flash
memory.
49
Creating a Target Configuration
• Before we begin, we must make a new target configuration, this tells CCS4
what device this project is designed for.
– Target > New Target Configuration
• A new window will appear, we will make our file name “TMS570.ccxml”
• Click Finish
50
Creating a Target Configuration…
• A new tab will appear with a list of emulators and devices.
– Connection: Texas Instruments XDS100v2 USB Emulator
– In the text box labeled “Type Filter Text”, type “TMS570”.
• This will narrow the search down to just TMS570 devices, select
TMS570LS20216SPGE
– Click “Save” on the right
51
Flash Programming Configuration
• It is possible to make the flash programming process much faster by only the
necessary erasing and programming the necessary regions of flash memory.
– To do so go to Tools > On-Chip Flash
– In the window that appears on the right, under Erase Options, check
“Necessary Sectors Only (for Program Load)”
52
Programming the Flash
• We are now ready to program the flash.
– Go to Target > Debug Active Project
– A new window should appear as it programs the flash memory.
• This may take a few moments.
53
Testing our Program
• Click the green arrow on the debug tab to run our program
– Alternatively the program can be run without the debugger connected by
• Clicking the red square on the debug tab to terminate the debugger‟s connection
• Hit the reset button on the board and the NHET[1] LED should illuminate.
• Congratulations! You have completed the lab.
54
TMS570LS: Multi-Buffered Serial
Peripheral Interface (MibSPI)
55
SPI / MibSPI Features
• The SPI / MibSPI has the following attributes:
– 16-bit shift registerReceive buffer register
– 8-bit baud clock generatorSerial Clock (SPICLK) I/O pin
– Up to 4 Slave in, Master out (SPISIMO) I/O pins for faster data transfers
– Up to 4 Slave out, Master in (SPISOMI) I/O pins for faster data transfers
– SPI Enable (SPIENA) I/O pin (4 or 5-pin mode only)
– Slave Chip Select (SPISCS[7:0]) I/O pin (4 or 5-pin mode only)
• The SPI / MibSPI allows software to program the following options:
– SPISOMI / SPISIMO pin direction configuration
– SPICLK pin source (external/internal)
– MibSPI pins as functional or digital I/O pins
56
• For each Buffer, following features can be selected from 4 different combinations of Formats using the control fields in the buffer:
– SPICLK frequency ([VBUSPCLK]/2 through /256)
– Character length (2 to 16 bits)
– Phase (delay/no delay), Polarity (high or low)
– Enable/Disable Parity for transmit & receive
– Enable/Disable timers for ChipSelect Hold & Setup timers
– Direction of shifting, MSBit first or LSBit first
– Configurable Parallel modes to use multiple SIMO/SOMI pins
SPI / MibSPI Features
57
SPI / MibSPI Features
• In Multibuffer Mode (uses the Multibuffer RAM (up to 128 Buffers)), in addition to the above, many other features are configurable:
– Number of buffers for each peripheral (or data source/destination) or group (up to 8 transfer groupings)
– Number of DMA controlled buffers & number of DMA request channels (up to 8 for each of transmit & receive)
– Triggers for each groups, trigger types, trigger sources for individual groups (up to 14 external trigger sources & 1 internal trigger source)
– Number of DMA transfers for each buffer (up to 65536 for up to 8 buffers)
– Un-interrupted DMA buffer transfer (NOBREAK buffer)
58
Standard SPI Mode - Block DiagramVBUS Write VBUS Read
TX SHIFT REGISTER
TX BUF
RX BUF
nSPISCS[7:0]
nSPIENA
SPICLK
SPISIMO SPISOMI Pre
sca
le
Clo
ck P
ola
rity
Clo
ck P
ha
se
CLKMOD
Mode
Generation
Logic
DMA REQ EN
RX_DMA_REQ
RXOVRN
RXEMPTY
SPI BUF
SPI CLOCK GENERATION LOGIC
VBUS Clock
INT_LVL
RXOVR INT ENA
RX INT ENA
TX INT ENA
Kernel FSM
DMA REQ EN
TXFULL
RX SHIFT REGISTER
16
16 16
SPIDAT0 SPIDAT1
16
CHARLEN
TX_DMA_REQ
16
16
INT_REQ0
INT_REQ1
59
MibSPI Multibuffer Mode - Block Diagram
VBUS
TX SHIFT REGISTER
Multibuffer Control
nSPISCS[7:0]
nSPIENA
SPICLK
SPISIMO SPISOMI Pre
sca
le
Clo
ck P
ola
rity
Clo
ck P
ha
se
CLKMOD
Mode
Generation
Logic
DMAREQ[15:0]
Ctrl Field
SPI CLOCK GENERATION LOGICVBUS Clock
Kernel FSM
RX SHIFT REGISTER CHARLEN
16
Sequencer
FSM
SPIBUF Status
1616 16
16
16
Interrupt
Generator
DMA CONTROL LOGIC
Trigger CONTROL LOGIC
Crtl
Field
TX
Buffer
Stat
Field
RX
Buffer
Multibuffer RAM
16
Tick CounterTRG_SRC[13:0]
2
INTREQ[1:0]
SPI Kernel
Multibuffer Logic
60
MASTER SLAVE
(MASTER = 1 ; CLKMOD = 1) (MASTER = 0 ; CLKMOD = 0)
SPIDAT1 SPIDAT0
MSB LSB MSB LSB
WRITE TO SPIDAT1
SOMI
SIMO
SOMI
SIMO
SPICLK SPICLK
nSCS[7:0] nSCS
nENABLE nENABLE
WRITE TO SPIDAT0
SPICLK
SIMO
SOMI
WRITE TO SPIDAT0 (SLAVE)
nENABLE
WRITE TO SPIDAT1 (MASTER)
nSCS
Transfer Mode - Five Pin Option:
Hardware Handshake
61
CLOCK POLARITY = 0, CLOCK PHASE = 0
WRITE SPIDAT
SPICLK
SPISIMO
SPISOMI
SAMPLE IN
RECEPTION
MSB D6 D5 D4 D3 D2 D1
D0
LSB
D6 D5 D4 D3 D2 D1D7
CLOCK PHASE = 0 (SPICLK WITHOUT DELAY)
- DATA IS OUTPUT ON THE RISING EDGE OF SPICLK
- INPUT DATA IS LATCHED ON THE FALLING EDGE OF SPICLK
- A WRITE TO THE SPIDAT REGISTER STARTS SPICLK
1 2 3 4 5 6 7 8
Clock Options
62
SPI / MibSPI Parallel Mode
• In order to achieve higher data flow, the parallel mode of the SPI / MibSPI enables the module to send data over more than one data line (Parallel 2, or 4).
• Figure of Parallel Mode with Shift register MSB first:
• Notes:
– When parallel mode is used, the data length must be set as 16 bits
– If parity is enabled one additional SPICLK will trigger the parity bit transfer
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO
MI7
SO
MI6
SO
MI5
SO
MI4
SO
MI3
SO
MI2
SO
MI1
SO
MI0
SIM
O7
SIM
O6
SIM
O5
SIM
O4
SIM
O3
SIM
O2
SIM
O1
SIM
O0
MULTIPLEXER
DEMULTIPLEXER
PSIMO[7:0]
SOMI[7:0]
Parallel Mode
Shift Register as in
SPI / MibSPI
63
tC2TDELAY = (C2TDELAY / VCLK) + 2
tC2EDELAY = (C2EDELAY /
SPICLK)
tT2CDELAY = (T2CDELAY / VCLK) + 1
Timing Setup – Delay Register (SPIDELAY)
SCSx
ENAx
SPICLK
VBUSPCLK
SOMI
tT2EDELAY = (T2EDELAY /
SPICLK)
CSHOLD = 1 (held active/ dotted line)
CSHOLD = 0 (set CS high after transmission)
WDELAY
DATA
64
TMS570LS: Controller Area Network
(DCAN)
65
DCAN Architecture• Full CAN according to protocol
version 2.0 part A, B
• CAN Core
– handles all CAN protocol functions
• Message Handler
– controls data transfer between CAN Core, Message Interface registers and RAM
– handles acceptance filtering and interrupts
• Message RAM
– 32 or 64 mailboxes
• Registers and Message Object access (IFx)
– Status and configuration registers for module setup and indirect Message Object access through interface registers (IFx)
• Module Interface
– 32-bit interface to VBUS clock domain
DCAN
MessageRAMInterface
Module Interface
CAN Core
Message Handler
Registers & MO access
CTRL VBUSP
CAN_TX
MessageRAM
(8, 16 or 32 bit)INT requests DMA requests
VCLKA
CAN_CLK
CAN_RX
VCLK
Test Modes
only
66
DCAN Features Overview
• Full CAN according to protocol version 2.0 part A, B
• Standard and Extended Identifiers
• Programmable Bit Timing, Bit rates up to 1 MBit/s
• Up to 128 Message Objects (MO)
• Identifier Masks for each Message Object
• Programmable FIFO mode for Message Objects
• Dual clock feature
• Possible automatic retransmission of a frame in case of lost arbitration or error
• Bus diagnostic: Bus off, Bus error passive, Bus error warning, Bus stuck dominant
• Frame error report: CRC, Stuff, Form, Bit and Acknowledgement errors
• Programmable loop-back modes for self-test operation
• Suspend modes for debug support
• Parity check mechanism for all RAM modules
67
TMS570LS: FlexRay Controller
68
FlexRay Block Diagram
• FTU: FlexRay Transfer Unit
• IBF: Input Buffer
• OBF: Output Buffer
• INT: Interrupt Control
• TBF A/B: Transient Buffer RAM
• PRT A/B: FlexRay Channel Protocol Controller
• GTU: Global Time Unit
• SUC: System Universal Control
• FSP: Frame and Symbol Processing
• NEM: Network Management
69
FlexRay Key Features
• Open Bus System
• Support of redundant transmission channels
• Data rate of 10 Mbit/sec per channel
• Support of a fault tolerant synchronized global time base
• Static and dynamic data transmission (scalable)
– Deterministic data transmission
– Arbitration free transmission
• Fault tolerant and time triggered services implemented in hardware
• Support of optical and electrical physical layers
70
FlexRay on TMS570LS (1/2)
• Bosch FlexRay Core (E-Ray)
• Conform to FlexRay Protocol Specification V2.1
• Data rates of up to 10 Mbit/s on each of the 2 channels
• 8 Kbyte of Message RAM for storage of
– 128 message buffers with max. 48 byte data section or
– 30 message buffers with 254 byte data section
– Different payload lengths possible
• Parity Protection of Message RAM
• Message Handler controls
– Message RAM access arbitration
– Acceptance Filtering
– Maintaining the transmission schedule
– Providing status information
71
• Each message buffer can be configured as
– Receive buffer
– Transmit buffer
• Each message buffer can be assigned to
– Static segment of the Communication Cycle
– Dynamic segment of the Communication Cycle
– Part of a receive FIFO
• Direct CPU access to message buffers via input and output buffers
• Dedicated Transfer Unit (DMA-like) for automatic data transfer to and from message buffers without CPU interaction
• Filtering for frame ID, channel ID and cycle counter
• Maskable module interrupts
• Network Management supported
FlexRay on TMS570LS (2/2)
72
FlexRay Communication Structure
static
segment
dynamic
segment
symbol
windowNIT
static
segment
dynamic
segment
symbol
windowNIT
payloadhea
dertrailer CID payload
hea
dertrailer CID
the payload length can vary
slot 1 slot 2 slot 3 …slot
m-1slot m
m
+
1
m
+
2
m
+
3
dynamic
slot m+4
m
+
5
m
+
6
dynamic
slot 7
.
.
.
m
+
x
Cycle [n] Cycle [n+1] Cycle […]
73
FlexRay Communication Cycle
Static SegmentDynamic Segment
74
FlexRay Message Frame Format
75
FTU Data Transfer Scheme
FTU
TCR
TBAC
on
tro
l
VBUS
Data RAM
Array of
Struct {
Header,
Payload }
CPU
Message RAM
FlexRay
Header Partition
Data (Payload)
Partition
FlexRay Core
Pro
toc
ol C
on
tro
lle
r
Sta
te M
ac
hin
e
Fle
xR
ay B
us
Trigger Event Trigger
Interrupt
76
FlexRay Transfer Unit Key Features
• Data Transfer without CPU interaction
– From FlexRay Message RAM to Data RAM (Read)
– From Data RAM to FlexRay Message RAM (Write)
• Transfer Types
– data and header section
– header section only
– data section only
• Transfer Configuration RAM (with Parity)
– Configures the transfer sequence
– Parity protection
• Triggers to Start a Transfer
– CPU driven (single transfer sequence)
– Event driven (single or continuous transfer sequence)
77
FlexRay Transfer Unit Key Features…
• Different Transfer Conditions
– If the status flags (header section) of the respective message buffer has been updated
– If the data section of the respective message buffer has been updated
– Always
• Maskable interrupt generation when Message Buffer transfer is finished
• Memory Protection Unit
– One memory section (start- and end address) can be defined
– No memory section is setup after reset
78
TMS570LS: Local Interconnect Network
(LIN)
79
Typical LIN Applications
Rear Door Lock,
window
Mirror
Mirror
BCM
Gateway
Passenger´s Door
Lock, window
Driver´s Door
Lock, window
Fan
Damper
Door Control
Light
Light
Levelizer
Levelizer
Compressor
CAN
Climate Control
Wipers
Dashboard
Rear Wiper
Sun Roof
Driver´s Seat
Steering
wheel
Rear Door Lock,
window
80
LIN Communication Concept
• Single Master concept with max. 16 nodes in one LIN cluster
• LIN supports baud rates from 1 to 20KHz
• Single wire low cost bus system often used as a sub network to comfort CAN.
81
• Compatible with LIN 1.3 or 2.0
• LIN 2.0 Master Compliant
• HW LIN protocol handler
– Multi-buffered receive and transmit units
– Automatic checksum generationand validation
– ID masks for message filtering
– DMA capability
• Synch break detection
• Slave automatic synchronization
• Optional baud rate update
• Synchronization validation
• Automatic bit monitoring
• Automatic error detection
• SCI (UART) mode
– Max 3.125Mbps with 100MHz VCLK
BLIN
SCI
8 RECEIVE BUFFERS
8 TRANSMIT BUFFERS
INTERFACE
DMA
CONTROL
READ DATA BUS
WRITE DATA BUS
LINRX
LINTX
SCICLK
ADDRESS BUS
MASK
FILTERS
SYNCHRONIZER
COUNTER
TIMEOUT CONTROL
COMPARE
FSM
TXRX ERROR DETECTOR
(TED)
CHECKSUM CALCULATOR
BIT MONITOR
ID PARITY CHECKER
LIN Key Features
82
• Programmable Frame Format
1 Start Bit
1 to 8 Data Bits
0 or 1 Address Bit
0 or 1 Parity Bit
1 or 2 Stop Bits
• Asynchronous Communications Format
• 2 Multiprocessor Modes with Wake-up Capability Idle-Line Mode; Address-Bit Mode
• Programmable Baud Rate
– more than 16 700 000 different Baud Rates
• Error Detection
– Parity, Overrun and Framing Error
– Break Detect
• Noise Protection Capability
• Double-buffered Receive and Transmit Function
TMS570 LIN – SCI Mode Features
83
LAB3: PC Communication Using SCI
84
Overview
• In this project we will:
– Edit our existing HALCoGen project to setup the SCI module
– Write code that prompts the user to enter a characters which are echoed
in the PC terminal
85
Enabling the SCI Module
• Reopen the HALCoGen project
• Go back to the „Driver Enable‟ tab.
– For this lab we will be using the SCI and GIO modules
• Click the „VIM Channel 0-31‟ tab
86
Enabling the SCI Interrupt
• On this page you will see two subgroups
– The left group lists all available interrupts
– The right group allows you to enable these
interrupts
• Match the displayed setting below to enable the
LIN1/SCI1 High interrupt
87
Configuring the SCI Peripheral
• On the top bar of the ribbon click “SCI1”
• Now that we have enabled the interrupt, we need to tell the device when to
interrupt.
– For this lab we will select the “RX INT”, so that an interrupt is generated
whenever the SCI receives data
88
Regenerate our Code
• All of the setting for this project are complete.
• We will need to regenerate our code to apply the new settings.
– File > Generate Code
• As long as you typed all of your custom code inside the USER CODE
blocks, then you will not lose any code.
• Once this is complete reopen your project in Code Composer Studio
89
Communicating with the SCI Module
• In Code Composer Studio, insert the following into User Code 1 in the C/C++
perspective
• This will include the SCI header file as well as creating a variable that can later
be used for storing received SCI characters
/* USER CODE BEGIN (1) */
#include "het.h"
#include "sci.h"
/* Stores user character */
static unsigned char command;
/* USER CODE END */
90
Initializing the Modules
• Insert the following into User Code 3
/* USER CODE BEGIN (3) */
/* Enable IRQ */
_enable_IRQ();
/* Initialize SCI module */
sciInit();
/* Set HET port pins to output */
gioSetDirection(hetPORT, 0xFFFFFFFF);
/* Set HET port pin 1 high */
gioSetBit(hetPORT, 1, 1);
/* Send user prompt */
sciSend(sciREG1, 21, (unsigned char *)"Please press a key!\r\n");
/* Await user character */
sciReceive(sciREG1, 1, (unsigned char *)&command);
/* Infinite loop */
while(1);
/* USER CODE END */
91
Handling SCI Interrupts
• Lastly, insert this block into User Code 4 before the gioNotification
• Each interrupt on the microcontroller will respond by calling a notification
function in which you tell the TMS570 how to respond.
/* USER CODE BEGIN (4) */
/* Notification called upon reception of character */
void sciNotification(sciBASE_t *sci, unsigned flags)
{
/* Echo received character */
sciSend(sci, 1,(unsigned char *)&command);
/* Await further character */
sciReceive(sci, 1,(unsigned char *)&command);
}
92
Building and Deploying the Code
• The coding segment for this project is now complete, go ahead and build your
project and then program it to the flash.
93
Testing your code
• Upon Completion open the TMS570 console or preferred terminal program.
• Ensure the following properties
– Baud rate: 9600
– Data bits: 8
– No parity, 2 Stop bits
• Click the „Terminate All‟ box in CCS then hit reset on the board.
• You should now see the „Please press a key!‟ prompt in the console window.
• When a character is typed, the microcontroller will „echo‟ the character back to
the terminal program.
94
TMS570LS: External Memory Interface (EMIF)
95
EMIF: Block Diagram
96
EMIF: Main Features
• Interfaces to asynchronous memories
• 4 addressable chip selects of up to 16MB each
• 16-bit data bus width
• Programmable cycle timings
• Select strobe mode
• Extended wait mode
• Data bus parking
• Allows overlay of up to 4MB of on-chip flash to external memory via Parameter Overlay Module (POM)
97
TMS570LS: Multi-Buffered ADC (MibADC)
98
MibADC Block Diagram
CONTROL AND STATUS
SEQUENCER
ADIN31
.
.
.
.
.
.
.
.
.
.
ADIN0
VrefLO VrefHI VSSA VCCA
Chnsel Swtsel(Test / Cal)
Conversion
Group
Selection
ADEVT
Interrupt
requestsPERIPHERAL BUS (VBUS)
16
Internal
Event 1
Internal
Event 7
Event Logic EVENT
GROUP1
EVENT
FIFO
GROUP1
FIFO
GROUP2
FIFO
Result Formatting
- Channel ID mask
- 8/10/12 bit mode mask
DMA
requests
3
DMA requests
32
:1 M
ultip
lexe
r
GIO Control
5
.
.
Interrupt
Threshold
+ countersEVENT,GROUP1
GROUP2
3
Calibration &
Error
Correction
Ctrl Chn
ADC RAM
w/ Parity
GROUP2
w/ Autoinitializationw/ RAM Test
Self-test
& CalibrationSample
Cap
Discharge
10bit / 12bit
Analog – Digital Converter(successive approximation)
CAP Dis. FIFO empty
ADCL
K
6
Magnitude
Threshold
Interrupt
Sources
5
Prescaler
5VCLK
99
• Configurable 10-bit or 12-bit resolution
• Up to 24 channels (8 Shared Channels)
• Sequential multi-channel conversion in ascending order
• Two conversion modes
– Single conversion
– Continuous conversion
• Three conversion groups w/ programmable sample and acquisition times
– Two software- or event-triggered conversion groups: Group1 and Group2
– One event-triggered-only conversion group: Event Group
• Three size adjustable memory regions
– Channel identifier stored with conversion result
• Up to 8 event trigger options
• Enhanced interrupt capability w/ programmable interrupt threshold counter
• DMA request generation capability
• Power-down mode
• Embedded self-test & calibration
• External event pin (ADEVT) can be programmed as general-purpose I/O
MibADC Main Features
100
MibADC Operation Modes
• Conversion mode
– normal active mode for converting the selected external input voltage
• Sample Capacitor Discharge mode
– active mode that grounds the ADC sampling capacitor
• Calibration mode
– special active mode for calibration using internal reference voltages
• Self-test mode
– active mode for failure-detection using internal reference voltages
• Power-down mode
– inactive mode in which the ADC internal clock is stopped
101
MibADC Conversion Groups
Event group select
(ADEVSEL)
Event
group
FIFO
12 value
8 value
read
ADEVBUFFER
ADG1SEL ADG2SEL
Input Channel Select Registers
Group 1
FIFO
9 value 3 value
Group 2
FIFO
read
ADG1BUFFER
read
ADG2BUFFER
31 0 31 0 31 0
11 1 1
103
MibADC Interrupts
• Conversion Group End Interrupt
– All channels that are assigned to a particular group are converted
• Conversion Group Buffers Threshold Interrupt
– Number of conversion results exceed threshold register value
• Conversion Group Buffers Overrun Interrupt
– Number of ADC conversions exceed the number of buffers allocated for that conversion group
• Magnitude Threshold Interrupt
– Magnitude comparison of conversion result on up to six channels; alternately, comparison can be made between the conversion result from another channel.
• Parity Error Interrupt
– Parity error following a read from the ADC RAM
104
TMS570LS Support Structure
105
TMS570 Support Structure
• TMS570 Web Page: www.ti.com/TMS570
– Data Sheets
– Technical Reference Manual
– Application Notes
– Software & Tools Downloads and Updates
– Order Evaluation and Development Kits
• TMS570 Forum: http://e2e.ti.com/support/microcontrollers/tms570/default.aspx
– News and Announcements
– Useful Links
– Ask Technical Questions
– Search for Technical Content
• TMS570 WIKI:
http://processors.wiki.ti.com/index.php/Category:TMS570
– How to guides
– Intro Videos
– General Information
106
TMS570 Microcontroller Forum Overview
• Forum Guidelines:
– At least one person will monitor the forum at all times (work days)
– All questions posted in the forum will have a response in 24hrs or less
Forum Flow:
TMS570 Forum
TI E2E forum for
questions about
TMS570 devices
Answer Known ?
YES
Post Answer Within
24hrs
NO
Post ‘Question Received’
Confirmation Within
24hrs
Forward
Question to
World Wide
Team
World Wide Apps Team:
-United States
- Europe
-India
Post Answer
107
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