1

An Introduction toAn Introduction to TMS570LS MicrocontrollersTMS570LS Microcontrollers

from Texas Instrumentsfrom Texas Instruments

2

Agenda•

Introduction and Roadmap•

Development Tools: Hardware kits, Software tools•

Safety Overview and Modules–

Lab 1:TMS570 Safety MCU Demos•

TMS570LS Architecture: Memory Map, Clocking, Exceptions•

Embedded Flash Memory tools: nowECC, nowFlash, Application Programmer Interface (API)

•

Real Time Interrupt (RTI)•

Vectored Interrupt Manager (VIM)•

Direct Memory Access (DMA)•

General-purpose I/O (GIO)•

Programmable Timer Unit with Transfer Unit (NHET/HTU)–

Lab 2: Using NHET as GIO•

Multi-Buffered Serial Peripheral Interface (MibSPI)•

Controller Area Network (DCAN)•

FlexRay

Interface with Transfer Unit (ERAY/FTU)•

Local Interconnect Network (LIN) / Serial Communication Interface (SCI)–

Lab 3: PC to SCI Communication•

External Memory Interface (EMIF) / Parameter Overlay (POM)•

Multi-buffered Analog-to-Digital Converter (MibADC)•

Support Structure: Web, Forum, WIKI

3

TMS570LS: Introduction and Roadmap

4

TI Embedded Processing PortfolioMicrocontrollers

32-bit Real-time

C2000

Fixed & Floating Point

Up to 300 MHz

Flash

32 KB to 512 KB

PWM, ADC, CAN, SPI, I2C

Motor Control, Digital Power,

Lighting

$1.50 to $20.00

32-bit M3 ARM

Stellaris-M3

Industry Std

Low Power

<100 MHz

Flash

Up to 512 KB

USB, ENET, ADC, PWM, CAN

Host Control

$1.00 to $7.00

16-bit

MSP430

Ultra-low Power

Up to 25 MHz

Flash

1 KB to 256 KB

Analog I/O, ADC

LCD, USB, RF

Measurement,

Sensing, General Purpose

$0.49 to $9.00

ARM Core Offerings

DSP

C55x, C64x+C647x

Leadership DSP Performance

24,000 MMACS

Up to 3 MB

L2 Cache

1G EMAC, SRIO,

DDR2, PCI-66

Comm, WiMAX, Industrial/

Medical Imaging

$4.00 to $99+

32-bitARM+

Applications Processors / DSP

Software, Tools & BSPs

32-bitARM+DSP

ARM9/Cortex-A8plus C64x+

Industry-Std Core + DSP for Signal Proc.

4800 MMACs/1.07 DMIPS/MHz

MMU, Cache

VPSS, USB, EMAC, MMC

Lin/Win O/S +

Video, Imag, MM

$12.00 to $65.00

32-bitR4F ARM

TMS570

Floating Point

Up to 220 MHz

FlashUp to 3 MB

USB, ENET, ADC, PWM, CAN

Safety SIL3 Control

$8.00

to $20.00

ARM9ARM Cortex-A8

Industry-Std Core,

High-Perf

GPP

Accelerators

MMU

USB, LCD,

MMC, EMAC

Linux/WinCE User Apps

$8.00 to $35.00

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Airbag

ABS/ESC

Traditional Auto Safety

Growing Transportation

Railway

AeroSpace

Off Road Equipment

Marine Engine

Growing Auto Market

Chassis Domain

HEV/EV

Steering

TMS570: MCU for Transportation

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TMS570 Setting the Standard for Safety-Critical Automotive & Transportation Applications

ARM Cortex-R4F with floating point allows development of complex real-time control algorithms

Safety architecture specifically developed to simplify SIL3 / ASIL D system implementations

Proven scalability, integration, support and broad automotive portfolio get customers to market fast

Safety Architecture

System Approach

Real-Time Control

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TMSx70 Family Roadmap

Broad and Scalable for Transportation Applications

Samples available   NOW

2011

2012

Sampling

Development

Concept

LS2x SeriesLS2x Seriesoption

LS3x SeriesLS3x Series

MC4x SeriesMC4x Series

Lower Cost Roadmap

Lockstep or Multicore

Dual R4Fover 225MHz on R4up to 4MB Flash; 512kB RAMTMS 3Q13

Performan

ce / M

emory / Features

EMAC option

option

EMAC option

option

Lockstep dual R4Fup to 160MHz/250 DMIPS up to 2MB Flash; 160kB RAMTMS 4Q10

Lockstep dual R4Fup to 180MHz/ up to 3MB Flash; 256kB RAMTMS 3Q12

LS1x SeriesLS1x Seriesoption

TMS470MTMS470M

up to 80MHz/96 DMIPS up to 640 kB

Flash; up to 128KB E2emuup to 64kB RAMTMS 4Q10

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TMS570LS Development Tools

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MCU development support

Software Development Support

IDE (Compiler/Linker/Debugger)•

TI Code Composer Studio, iSYSTEM

WINIDEA, Lauterbach

TRACE32, ARM RealView, etc…AutoSAR 3.0

•

MCAL and RTE available from VectorFlexRay™ Drivers

•

Available from Elektrobit

and TTTech

Automotive

Hardware Emulation Tools

TMS570 supports “Standard ARM” Coresight™ debug components •

ETM with up to 32b external bus

and internal FIFO for improved throughput

JTAG debug and trace solutions:•

iSYSTEM, Lauterbach, Sophia, Spectrum DigitalTMS570 Evaluation Modules (EVMs) with integrated JTAG

Prototyping Tools

TMS570 provides high bandwidth interfaces for bypass and calibration •

Vector VX1000 provides up to 3MB/sec using RTP/DMMAuto-code Generation

•

Mathworks

Real Time Workshop, ETAS ASCETBypass proccessing and calibration

•

Vector VX1000/CANape

EVM

CCStudio

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Development Kits

•

TMDX570LS20SMDK–

$695–

Full Featured TMS570 Microcontroller Development Kit

•

TMDX570LS20SUSB–

$79–

Low Cost TMS570 Evaluation Kit

•

Software Included in Each Kit:–

CCStudio

v4.1 IDE•

Includes C/C++ Compiler/Linker/Debugger

–

HalCoGen

Peripheral Driver Generation Tool–

Flash programming integrated into CCS–

HET GUI/Simulator/Assembler–

Demo Project/Code Examples

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Microcontroller Development Kit (MDK)

•

CPU Card–

Connects to COMM Board –

On Board XDS100v2 emulation via USB–

Trace Connectors–

Access to Peripheral Pins

•

COMM Board–

Light & Temperature Sensors–

Sensor Interfaces–

FlexRay/CAN/LIN Transceivers–

Color Touch Screen TFT

•

DEV Kit–

$695 USD (CPU + COMM Board)–

Orderable Part #TMDX570LS20SMDK–

CCS 4.1 SW IDE included–

Power Supply

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Microcontroller USB Kit

•

Main Features–

USB Powered–

On Board USB XDS100v2 JTAG Debug –

On Board SCI to PC Serial Communication

–

Access to Select Signal Pin Test Points–

LEDs, Temp Sensor, Light Sensor and CAN transceiver

–

144 QFP Packaged CPU

•

$79 USD (CPU + COMM Board)–

Orderable Part #TMDX570LS20SUSB–

CCS 4.1 SW IDE included–

Power Supply

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Code Composer Studio v4.1

•

Based on Eclipse industry standard for embedded debug tools

–

Modern window environment–

Advanced source code editor–

Scalable multi-core/processor environment

–

Program and Debug Application via JTAG

–

Test Automation via Scripting

•

Low cost tools enable developers to easily evaluate and start development

–

Develop with CCS for <$100

•

TMS570 Debug Features–

6 Hardware Breakpoints–

Unlimited Software Breakpoints

–

Integrated Flash Programming

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Code Composer Studio Components: Fully Integrated, Easy to Use Development Tools

Memory Window

Watch Window

Disassembly Window

Target Connection

Source & object files

File dependencies

Compiler, assembler & linker build options

Menus or Icons

Help

CPU Window

Source Code View

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Features•

User Input on High Abstraction Level–

Graphical-based code generation–

Easy configuration–

Quick start for new projects •

Generates C Source Code –

ANSI Conforming–

Clear, structured, coding style–

Customizable code for user maintenance

•

Supported Peripherals–

System Module–

RTI–

GIO–

SCI/LIN–

CAN–

SPI–

ADC–

Timer Co-processor (nHET)•

Interactive Help System–

Describes tool features and functions

–

Provides detailed dependency graphs

–

Provides useful example code–

Tool tip help available•

Hierarchical project code viewing

HalCoGen: Hardware Abstraction Layer Code Generator

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Instruction drag and drop

Code paletteEdit mode

Internal Registers & Memory

Helps Customers Not Familiar With High End Timer Module to Program the Timer with a Graphical Interface

HET GUI / Simulator

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Select pins for waveform

Pins

Clocks

HET GUI w/ SynaptiCAD - Waveform Display

Allows for input waveform generation

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Tools Roadmap

External Tools:•

IDE’s•

Lauterbach, iSystems, IAR, Keil

/ ARM, Hitex•

Compiler•

IAR, ARM, GCC, …•

Emulator•

Spectrum Digital, Lauterbach, iSystems, IAR, Keil, Blackhawk, Segger, Signum

Systems, …•

Operating System•

ETAS, Vector, Sciopta, Wittenstein, Micrium, …•

AutoSAR•

Vector, ElectroBit•

Trace / Calibration•

Lauterbach, iSystems, Vector, ETAS, Sophia Systems•

Production Flash Programming•

BP Microsystems, Data-IO•

Rapid Prototyping•

Matlab/Simulink, dSpace

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Safety Features on TMS570LS Microcontrollers

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Exida Has Certified TMS570LS20216S SIL3 Capable

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Rationale of TI Safety Concept

•

“Safe Island”

approach

•

Region of device common to all safety functions is heavily protected by hardware diagnostic measures

–

CPU–

CPU Interrupts–

System control of power, reset, clock–

OS critical IP: DMA, OS timer

•

Once a known safe region can be guaranteed, logic in this region can be used to provide diagnostic coverage on other regions

•

This partition has shown to give strong safety metrics while minimizing impact of safety on system BOM cost

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Safety Features Overview

•

Dual Core Lockstep -

Cycle by Cycle CPU Fail Safe Detection

•

CPU Self Test Controller requires little S/W overhead

•

ECC for Flash / RAM Evaluated inside the Cortex R4F

•

Parity on all Peripheral, DMA and Interrupt controller RAMS

•

Memory BIST on all RAMS allows fast memory test at startup

•

On-Chip Clock and Voltage Monitoring •

Error Signaling Module w/ External Error Pin

•

CRC, IO Loop Back, ADC Self Test, …•

3 domains identified:–

Not safety critical functions (black)–

Core functionality common to all Safety Instrumented Functions (red)

–

Peripheral functionality specific to specific Safety Instrumented Functions (blue)

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1oo1D Dual Core Safety Concept

•

Unique design to reduce common cause failures (βIC)

–

Second CPU mirrored and rotated

–

Minimum distance 100µm between CPUs

–

Cycle delayed lockstep–

Guard ring per CPU–

Duplicated clock tree per CPU

•

CPU Compare Module–

Self-test capability–

Self-test error injection/error forcing

–

Output error injection

Output + Control

Cycle Delay

> 100um

Dedicated Power Ring

Cycle DelayCCM

CompareError

Input + Control

SelfTest

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STC STC DBISTCNTRL

CPU1

ROM

Clock controller

ESM

PCR

Test controller

CPU_nRESET

misr_in1

ERR

DBISTCNTRL CPU2

CCM

misr_in2

ROMinterface FSM

Clock cntrl

STC BYPASS/ATE Interface

REG Block&

CompareBlock

VBUSPinterface

•

Provides High Diagnostic Coverage •

Significantly Lowers S/W and Runtime Overhead •

No SW BIST (Built In Self Test) Code overhead in Flash•

Simple to configure and start BIST via register

CPU Self Test Controller (STC/LBIST)

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Flash / RAM ECC Protection

Cortex-R4F

Flash RAM

•

ECC evaluated in the Cortex R4F CPU–

Single Bit Error Correction and Double Bit Error Detection–

ECC evaluated in parallel to processing data/instructions–

No latency or performance impact–

Protects Busses from CPU to Flash and RAM

4 ECC Bits32 Data Bits

32 Data Bits

64 Inst.

8 ECC

ECC Logic

8 Stage Pipeline

Error

64 Data

8 ECC

4 ECC Bits

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Programmable Memory BIST (PBIST)

•

All on-chip RAMS can be tested

•

Run at startup

•

Multiple Memory Test Algorithms

•

Detects multiple failure modes

PBISTController

Data Logger

Extblock

Cfgblock

VBUS I/f

Tester I/fRAMData path/

CollarsTo / FromMemories(RAMgroups)

ROMblock

ROM I/f

Functional Read/Write Datapath

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Safety Aspects of Network Interfaces

•

Networked peripherals (FlexRay, DCAN, and SCI/LIN) are considered grey-

channel / black-channel communications

•

In such communications application level protocols (time redundancy, CRC in data packet, etc.) are necessary

•

When such assumption is made, the Dangerous Undetected Failure from the network is effectively not measurable (<0.001 Failure In Time (FIT))

•

Detailed fault data available upon request

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Error Signaling Module (ESM)

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ESM Features

•

ESM functions–

Up to 96 error channels, divided into 3 different groups•

32 channels with configurable output for interrupt and error behavior

•

32 channels with predefined output for interrupt and error behavior•

32 channels with predefined output for error behavior–

Error pin to signal severe device failure–

Configurable timebase

for error signal–

Error forcing capability for self test

•

ESM hardware–

Indicates severe device failure at an external pin (nERROR)–

Hardware assistance for prioritizing error sources

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Additional Safety Features

•

Supply monitor (VMON)–

Asserts reset if core or I/O supply exceeds defined min/max thresholds

•

Clock monitoring–

Oscillator monitor•

Detects failure if oscillator frequency exceeds defined min/max thresholds

•

Selectable hardware response on oscillator fail–

PLL slip detector•

Indicates PLL slip if phase lock is lost•

Selectable hardware response on PLL slip•

Internal backup ‘low power oscillator’

(LPO) clock source –

External clock prescaler•

Allows external monitoring of CPU clock frequency

•

Dedicated Memory Protection Units for each bus master

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LAB1: TMS570LS Safety Features Demo

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Lab1: TMS570 Safety MCU Demos