tms320f2812 digital i/0

Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt Ltd.

Digital Signal Controller TMS320F2812

Chapter 3 : F28x –Digital I/O


C281x Block Diagram

32x32 bit32x32 bit

MultiplierMultiplier

32x32 bit32x32 bit

MultiplierMultiplier

SectoredSectored

FlashFlash

SectoredSectored

FlashFlash

A(18-0)A(18-0)

D(15-0)D(15-0)

Program BusProgram Bus

Data BusData Bus

RAMRAMRAMRAM

BootBoot

ROMROM

BootBoot

ROMROM

2222

32-bit32-bit

AuxiliaryAuxiliary

RegistersRegisters

32-bit32-bit

AuxiliaryAuxiliary

RegistersRegisters

33

32 bit 32 bit

Timers Timers

33

32 bit 32 bit

Timers Timers RealtimeRealtime

JTAGJTAG

RealtimeRealtime

JTAGJTAG CPUCPU

Register BusRegister Bus

R-M-WR-M-W

AtomicAtomic

ALUALU

R-M-WR-M-W

AtomicAtomic

ALUALU

PIE PIE Interrupt Interrupt ManagerManager

3232

3232

3232

EventEventManager AManager A

EventEventManager AManager A

EventEventManager BManager B

EventEventManager BManager B

12-bit ADC12-bit ADC12-bit ADC12-bit ADC

WatchdogWatchdogWatchdogWatchdog

McBSPMcBSPMcBSPMcBSP

CAN2.0BCAN2.0BCAN2.0BCAN2.0B

SCI-ASCI-ASCI-ASCI-A

SCI-BSCI-BSCI-BSCI-B

SPISPISPISPI

GPIOGPIOGPIOGPIO


TMS320F2812 Memory MapMO SARAM (1K)MO SARAM (1K)

M1 SARAM (1K)M1 SARAM (1K)

LO SARAM (4K)LO SARAM (4K)

L1 SARAM (4K)L1 SARAM (4K)

HO SARAM (8K)HO SARAM (8K)

Boot ROM (4K)Boot ROM (4K)MP/MC=0MP/MC=0

BROM vector (32)BROM vector (32)MP/MC=0 ENPIE=0MP/MC=0 ENPIE=0

OTP (2K)OTP (2K)

FLASH (128K)FLASH (128K)

reserved

reserved

reservedPF 0 (2K)PF 0 (2K)

reserved

reservedPF 1 (4K)PF 1 (4K)reservedPF 2 (4K)PF 2 (4K)

reservedPIE vectorPIE vector

(256)(256)ENPIE=1ENPIE=1 XINT Zone 0 (8K)

XINT Zone 1 (8K)

XINT Zone 2 (0.5M)XINT Zone 6 (1M)

XINT Zone 7 (16K)MP/MC=1

XINT Vector-RAM (32)MP/MC=1 ENPIE=0

reserved

reserved

reserved

Data | ProgramData | Program

00 000000 0000

00 040000 0400

00 080000 080000 0D0000 0D00

00 100000 100000 600000 600000 700000 700000 800000 8000

00 900000 9000

00 A00000 A0003D 78003D 7800

3D 80003D 8000

3F 80003F 8000

3F A0003F A0003F F0003F F000

3F FFC03F FFC0

3F C0003F C000

20 000020 000010 000010 000008 000008 0000

00 400000 400000 200000 2000

Data | ProgramData | Program

128-Bit Password128-Bit Password

CSM: LO, L1CSM: LO, L1

OTP, FLASHOTP, FLASH


C28x GPIO Register StructureGPIO A Mux ControlGPIO A Mux ControlRegister (GPAMUX)Register (GPAMUX)

GPIO A Direction ControlGPIO A Direction ControlRegister (GPADIR)Register (GPADIR)

GP

IO A

GP

IO A

GPIO B Mux ControlGPIO B Mux ControlRegister (GPBMUX)Register (GPBMUX)

GPIO B Direction ControlGPIO B Direction ControlRegister (GPBDIR)Register (GPBDIR)

GP

IO B

GP

IO B

GPIO D Mux ControlGPIO D Mux ControlRegister (GPDMUX)Register (GPDMUX)

GPIO D Direction ControlGPIO D Direction ControlRegister (GPDDIR)Register (GPDDIR)

GP

IO D

GP

IO D

GPIO E Mux ControlGPIO E Mux ControlRegister (GPEMUX)Register (GPEMUX)

GPIO E Direction ControlGPIO E Direction ControlRegister (GPEDIR)Register (GPEDIR)

GP

IO E

GP

IO E

GPIO F Mux ControlGPIO F Mux ControlRegister (GPFMUX)Register (GPFMUX)

GPIO F Direction ControlGPIO F Direction ControlRegister (GPFDIR)Register (GPFDIR)

GP

IO F

GP

IO F

GPIO G Mux ControlGPIO G Mux ControlRegister (GPGMUX)Register (GPGMUX)

GPIO G Direction ControlGPIO G Direction ControlRegister (GPGDIR)Register (GPGDIR)

GP

IO G

GP

IO G

Internal Bus

Internal Bus

GPIO A, B, D, E include Input Qualification featureGPIO A, B, D, E include Input Qualification feature


GPIO AGPIOA0 / PWM1GPIOA1 / PWM2GPIOA2 / PWM3GPIOA3 / PWM4GPIOA4 / PWM5GPIOA5 / PWM6GPIOA6 / T1PWM_T1CMPGPIOA7 / T2PWM_T2CMPGPIOA8 / CAP1_QEP1GPIOA9 / CAP2_QEP2GPIOA10 / CAP3_QEPI1GPIOA11 / TDIRAGPIOA12 / TCLKINAGPIOA13 / C1TRIPGPIOA14 / C2TRIPGPIOA15 / C3TRIP

GPIO BGPIOB0 / PWM7GPIOB1 / PWM8GPIOB2 / PWM9GPIOB3 / PWM10GPIOB4 / PWM11GPIOB5 / PWM12GPIOB6 / T3PWM_T3CMPGPIOB7 / T4PWM_T4CMPGPIOB8 / CAP4_QEP3GPIOB9 / CAP5_QEP4GPIOB10 / CAP6_QEPI2GPIOB11 / TDIRBGPIOB12 / TCLKINBGPIOB13 / C4TRIPGPIOB14 / C5TRIPGPIOB15 / C6TRIP

GPIO DGPIOD0 / T1CTRIP_PDPINTAGPIOD1 / T2CTRIP / EVASOCGPIOD5 / T3CTRIP_PDPINTBGPIOD6 / T4CTRIP / EVBSOC

GPIO EGPIOE0 / XINT1_XBIOGPIOE1 / XINT2_ADCSOCGPIOE2 / XNMI_XINT13

GPIO FGPIOF0 / SPISIMOAGPIOF1 / SPISOMIAGPIOF2 / SPICLKAGPIOF3 / SPISTEAGPIOF4 / SCITXDAGPIOF5 / SCIRXDAGPIOF6 / CANTXAGPIOF7 / CANRXAGPIOF8 / MCLKXAGPIOF9 / MCLKRAGPIOF10 / MFSXAGPIOF11 / MFSRAGPIOF12 / MDXAGPIOF13 / MDRAGPIOF14 / XF

GPIO GGPIOG4 / SCITXDBGPIOG5 / SCIRXDB

C28x GPIO Pin Assignment

Note: GPIO are pin functions at reset

GPIO A, B, D, E includeInput Qualification feature


C28x GPIO Functional Block Diagram

•• • 10 MUX Control Bit

0 = I/O Function1 = Primary Function

Pin

PrimaryPeripheralFunction

I/O DATBit (R/W) In

Out

•

I/O DIR Bit0 = Input

1 = Output GPxMUX

GPxDIR

GPxDAT

GPxSETGPxCLEAR

GPxTOGGLE

QUALPRDreserved7 - 07 - 015 - 815 - 8

GPxQUALGPxQUAL

00h no qualification (SYNC to SYSCLKOUT)01h QUALPRD = SYSCLKOUT/202h QUALPRD = SYSCLKOUT/4

FFh QUALPRD = SYSCLKOUT/510

............

......

Some digital I/O andperipheral I/O inputsignals include an Input Qualificationfeature


C28x GPIO MUX/DIR RegistersAddress Register Name

70C0h GPAMUX GPIO A Mux Control Register

70C1h GPADIR GPIO A Direction Control Register

70C2h GPAQUAL GPIO A Input Qualification Control Register

70C4h GPBMUX GPIO B Mux Control Register

70C5h GPBDIR GPIO B Direction Control Register

70C6h GPBQUAL GPIO B Input Qualification Control Register

70CCh GPDMUX GPIO D Mux Control Register

70CDh GPDDIR GPIO D Direction Control Register

70CEh GPDQUAL GPIO D Input Qualification Control Register

70D0h GPEMUX GPIO E Mux Control Register

70D1h GPEDIR GPIO E Direction Control Register

70D2h GPEQUAL GPIO E Input Qualification Control Register

70D4h GPFMUX GPIO F Mux Control Register

70D5h GPFDIR GPIO F Direction Control Register

70D8h GPGMUX GPIO G Mux Control Register

70D9h GPGDIR GPIO G Direction Control Register


Address Register Name70E0h GPADAT GPIO A Data Register70E1h GPASET GPIO A Set Register70E2h GPACLEAR GPIO A Clear Register70E3h GPATOGGLE GPIO A Toggle Register70E4h GPBDAT GPIO B Data Register70E5h GPBSET GPIO B Set Register70E6h GPBCLEAR GPIO B Clear Register70E7h GPBTOGGLE GPIO B Toggle Register70ECh GPDDAT GPIO D Data Register70EDh GPDSET GPIO D Set Register70EEh GPDCLEAR GPIO D Clear Register70EFh GPDTOGGLE GPIO D Toggle Register70F0h GPEDAT GPIO E Data Register70F1h GPESET GPIO E Set Register70F2h GPECLEAR GPIO E Clear Register70F3h GPETOGGLE GPIO E Toggle Register70F4h GPFDAT GPIO F Data Register70F5h GPFSET GPIO F Set Register70F6h GPFCLEAR GPIO F Clear Register70F7h GPFTOGGLE GPIO F Toggle Register70F8h GPGDAT GPIO G Data Register70F9h GPGSET GPIO G Set Register70FAh GPGCLEAR GPIO G Clear Register70FBh GPGTOGGLE GPIO G Toggle Register

C28x GPIO Data Registers


C28x Oscillator / PLL Clock ModulePLLCR @ 7021h

DIV3 DIV2 DIV1 DIV0 Clock Frequency (CLKIN) 0 0 0 0 OSCCLK x 1 / 2 (no PLL) 0 0 0 1 OSCCLK x 1 / 2 0 0 1 0 OSCCLK x 2 / 2 0 0 1 1 OSCCLK x 3 / 2 0 1 0 0 OSCCLK x 4 / 2 0 1 0 1 OSCCLK x 5 / 2 0 1 1 0 OSCCLK x 6 / 2 0 1 1 1 OSCCLK x 7 / 2 1 0 0 0 OSCCLK x 8 / 2 1 0 0 1 OSCCLK x 9 / 2 1 0 1 0 OSCCLK x 10 / 2

PLLCRbits 15:4reserved

crystal

PLLClock Module4-bit PLL Select

X1 /CLKIN

X2

XT

AL

OS

C

WatchdogModule

/2PLLCLK

OSCCLK•

C28xCore

CLKIN

MU

X

XF_XPLLDIS

1

0SYSCLKOUT

HISPCP LOSPCP

HSPCLK LSPCLK

• •


Peripheral Clock Control RegisterPCLKCR @ 701Ch

Module Enable Clock Bit0 = disable1 = enable

00

reservedreserved

11223344556677EVA

ENCLKEVB

ENCLKreserved

ADCENCLK

reservedreserved

HECCAENCLK

SPIAENCLK

SCIBENCLK

8899101011111212131314141515

reservedSCIA

ENCLKMA

ENCLKreservedreserved

HSPCLK

LSPCLK


High / Low – Speed Peripheral Clock Pre-scale Registers

HISPCP @ 701Ah / LOSPCP @ 701Bh01215 - 3

HSPCLK0HSPCLK1HSPCLK2reserved

01215 - 3

LSPCLK0LSPCLK1LSPCLK2reserved

H/LSPCLK2 H/LSPCLK1 H/LSPCLK0 Peripheral Clock Frequency 0 0 0 SYSCLKOUT / 1 0 0 1 SYSCLKOUT / 2 (default HISPCP)

0 1 0 SYSCLKOUT / 4 (default LOSPCP)

0 1 1 SYSCLKOUT / 6 1 0 0 SYSCLKOUT / 8 1 0 1 SYSCLKOUT / 10 1 1 0 SYSCLKOUT / 12 1 1 1 SYSCLKOUT / 14


Watchdog Timer

• Resets the C28x if the CPU crashes– Watchdog counter runs independent of CPU– If counter overflows, reset or interrupt is triggered– CPU must write correct data key sequence to reset the counter before

overflow

• Watchdog must be serviced (or disabled) within ~4,3ms after reset (30 MHz external clock)

• This translates into 6.3 million instructions!


Watchdog Timer Module6 - BitFree -RunningCounter

CLR/2/4/8/16/32/64OSCCLK

SystemReset

101100011010001

000

111110

•

•

•

•

8 - Bit WatchdogCounter

CLR

One-CycleDelay

WatchdogReset KeyRegister

55 + AADetector

•

Good Key

Bad Key

1 0 1• •

••//3

3

WDCR . 2 - 0

WDCR . 6

WDPS

WDDIS

WDCR . 7WDFLAG

WDCNTR . 7 - 0

WDKEY . 7 - 0

WDCR . 5 - 3 WDCHK 2-0

Bad WDCR Key

/512

OutputPulse

WDRST

WDINTSCSR .1

WDENINT

•

• •

SCSR . 0WDOVERRIDE


Watchdog Timer Control Register WDCR @ 7029h

WDFLAG WDDIS

7 6 5 4 3 2 1 0

WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0WDCHK2

Logic Check Bits

Write as 101 or reset immediately triggered

WD PrescaleSelection Bits

Watchdog Disable Bit(Functions only if WD OVERRIDE

bit in SCSR is equal to 1)

reserved

15 - 8

WD Flag BitGets set when the WD causes a reset

• Writing a 1 clears this bit• Writing a 0 has no effect


Resetting the Watchdog WDKEY @ 7025h

• Allowable write values:55h - counter enabled for reset on next AAh writeAAh - counter set to zero if reset enabled

• Writing any other value immediately triggers a CPU reset

• Watchdog should not be serviced solely in an ISR– If main code crashes, but interrupt continues to execute, the watchdog will

not catch the crash– Could put the 55h WDKEY in the main code, and the AAh WDKEY in an ISR;

this catches main code crashes and also ISR crashes

reserved D7

7 6 5 4 3 2 1 0

D6 D5 D4 D3 D2 D1 D0

15 - 8


WDKEY Write Results

SequentialStep

123456789

1011

Value Writtento WDKEY

AAhAAh55h55h55hAAhAAh55hAAh55h23h

Result

No actionNo actionWD counter enabled for reset on next AAh writeWD counter enabled for reset on next AAh writeWD counter enabled for reset on next AAh writeWD counter is resetNo actionWD counter enabled for reset on next AAh writeWD counter is resetWD counter enabled for reset on next AAh writeCPU reset triggered due to improper write value


System Control and Status RegisterSCSR @ 7022h

WD Override (protect bit)After RESET - bit gives user ability to disable WD by setting WDDIS bit=1 in WDCR• clear only bit and defaults to 1 after reset0 = protects WD from being disabled by s/w• bit cannot be set to 1 by s/w (clear-only by writing 1)1 = (default value) allows WD to be disabled using WDDIS bit in WDCR• once cleared, bit cannot set to 1 by s/w

01215 - 3

WDOVERRIDE

WDENINTWDINTSreserved

WD Enable InterruptWD Interrupt Status(read only)

0 = active1 = not active

0 = WD generates a DSP reset1 = WD generates a WDINT interrupt


Low Power Modes

Low PowerMode

CPU LogicClock

PeripheralLogic Clock

WatchdogClock

PLL /OSC

Normal Run

IDLE

STANDBY

HALT

on

off

off

off

on

on

off

off

on

on

on

off

on

on

on

off


Low Power Mode Control Register 0LPMCR0 @ 701Eh

017 - 215 - 8

LPM0LPM1QUALSTDBYreserved

Low Power Mode Entering1. Set LPM bits2. Enable desired exit interrupt(s)3. Execute IDLE instruction4. The Power down sequence of the hardware depends on LP mode

Low Power Mode Selection

00 = Idle01 = Standby1x = Halt

Qualify before wakingfrom STANDBY mode

000000 = 2 OSCCLKs000001 = 3 OSCCLKs

111111 = 65 OSCCLKS

.. .. ..


Low Power Mode Control Register 1LPMCR1 @ 701Fh

Wake device from STANDBY mode

0 = disable1 = enable

0

WDINT

SCIRXB C2TRIPC5TRIP

T3CTRIP

1234567

89101112131415

XINT1XNMIT2CTRIP T1CTRIP

C3TRIP

T4CTRIP

C4TRIP

C1TRIP

C6TRIPSCIRXACANRXA


IDLE

STANDBY

HALT

RESET

yes

yes

yes

Externalor

Wake upInterrupts

yes

yes

no

yes

no

no

ExitInterrupt

Low PowerMode

EnabledPeripheralInterrupts

Note: External or Wake up include XINT1, PDPINT, TxCTRIP, CxTRIP NMI, CAN, SPI, SCI, WD

Low Power Mode Exit


• Use the 8 LED‘s connected to GPIO- outputs B0-B7 to show a ‚running light‘ moving from left to right and reverse

• Use a software delay loop to generate the pause interval

Lab : Digital Output on Port B0...B7

Project - Files : :1. C - source file: “Lab2.c”2. Register Definition File: “DSP281x_GlobalVariableDefs.c3. Linker Command File :

EzDSP_RAM_lnk.cmd4. Runtime Library “rts2800_ml.lib


Registers to be used in LAB 2 : • Initialise DSP:

• Watchdog - Timer - Control : WDCR• PLL Clock Register : PLLCR• High Speed Clock Pre-scaler : HISPCP• Low Speed Clock Pre-scaler : LOSPCP • Peripheral Clock Control Reg. : PCLKCR• System Control and Status Reg. : SCSR

• Access to LED‘s (B0...B7):• GPB Multiplex Register : GPBMUX• GPB Direction Register : GPBDIR• GPB Qualification Register : GPBQUAL• GPB Data Register : GPBDAT


Register Definition File ‘DSP281x_GlobalVariableDefs.c’

• This File defines global variables for all memory mapped peripherals.

• The file uses predefined structures ( see ..\include ) and defines instances , e.g. “GpioDataRegs” :

#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile");volatile struct GPIO_DATA_REGS GpioDataRegs;

or “GpioMuxRegsFile” : #pragma DATA_SECTION(GpioMuxRegs,"GpioMuxRegsFile");

volatile struct GPIO_MUX_REGS GpioMuxRegs;

• The structures consist of all the registers, that are part of that group , e.g. : GpioDataRegs.GPBDAT


• For each register exists a union to make a 16bit-access (“all”) or a bit-access (“bit”) , e.g. :

GpioDataRegs.GPBDAT.bit.GPOIB4 = ....GpioDataRegs.GPBDAT.all = ....

• The name of the DATA_SECTION ( ”GpioDataRegsFile” ) is used by the linker command file to connect the section’s variable ( ”GpioDataRegs”) to a physical memory address.

• The master header -file ‘DSP281x_Device.h’ includes all the predefined structures for all peripherals of this DSP.

• All that needs to be done is : (1) make ‘DSP281x_GlobalVariableDefs.c’ part of your project (2) include ‘DSP281x_Device.h’ in your main C file.


Lab Exercise Modify the C -source - code :

• switch 2 LED’s on ( B7 and B0 )

• let the ‘light’ move one step to the centre of the LED-bar ( B6 and B1 switched on )

• continue the move until the ‘lights’ touch each other

• ‘move’ the in the opposite direction

B7 and B0 = on

B6 and B1 = on

B5 and B2 = on

B4 and B3 = on


Lab : Digital Input (GPIO B15..B8)

• 8 DIP-Switches connected to GPIO-Port B ( B15...B8)• 8 LED‘s connected to B7...B0• read the switches and show their status on the LED’s

Aim :

Project - Files :1. C - source file: “Lab3.c”2. Register Definition File:

“DSP28_GlobalVariableDefs.c3. Linker Command File :

EzDSP_RAM_lnk.cmd4. Runtime Library “rts2800_ml.lib


Lab “Knight - Rider” plus frequency control :

modify Lab 2 : • read the input switches ( B15-B8 )• modify the frequency of the ‘running light’ (B7-B0) subject to the status of the input switches, e.g. between

10sec and 0.01 sec per step of the LED-sequence

enable the watchdog timer !• Verify that , ones your program is in the main loop, the watchdog

causes a reset periodically.


Serve the watchdog :

• do not disable the watchdog timer !

• Inside the main-loop execute the watchdog-reset instructions (WDKEY) to prevent the watchdog timer from overflow.

• Place the software-delay in a function and experiment with different delay period’s. What is the period when the watchdog-timer does reset the DSP ?


Lab Add start/stop control:

• use Lab 2 to start:

• GPIO-D1 and D6 are connected to two push-buttons. If they are pushed, the input level reads 0, if released 1.

• Use D1 to start the LED “Knight-rider” and D6 to halt it. If D1 is pushed again the sequence should continue again.

• To do so, you also need to add the instructions to initialise GPIO-D

tms320f2812 digital i/0

Education

direction control gpio

name70c0hgpamux gpio

mux control bit0

data register 70e1hgpasetgpio

set register 70e2hgpacleargpio

f f000mpmc

f c000

b auxiliary 32x32