tiva c series tm4c129cncpdt microcontroller data sheet … · 2020. 12. 13. · 11.4.2...

Tiva™ TM4C129CNCPDT Microcontroller

DATA SHEET

Copyr ight © 2007-2014Texas Instruments Incorporated

DS-TM4C129CNCPDT-15863.2743SPMS437B

TEXAS INSTRUMENTS-PRODUCTION DATA

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June 18, 20142Texas Instruments-Production Data

http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

Table of ContentsRevision History ............................................................................................................................. 46About This Document .................................................................................................................... 49Audience .............................................................................................................................................. 49About This Manual ................................................................................................................................ 49Related Documents ............................................................................................................................... 49Documentation Conventions .................................................................................................................. 50

1 Architectural Overview .......................................................................................... 521.1 Tiva™ C Series Overview .............................................................................................. 521.2 TM4C129CNCPDT Microcontroller Overview .................................................................. 531.3 TM4C129CNCPDT Microcontroller Features ................................................................... 561.3.1 ARM Cortex-M4F Processor Core .................................................................................. 561.3.2 On-Chip Memory ........................................................................................................... 581.3.3 External Peripheral Interface ......................................................................................... 601.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 621.3.5 Advanced Encryption Standard (AES) Accelerator .......................................................... 621.3.6 Data Encryption Standard (DES) Accelerator ................................................................. 631.3.7 Secure Hash Algorithm / Message Digest Algorithm (SHA/MD5) ..................................... 631.3.8 Serial Communications Peripherals ................................................................................ 641.3.9 System Integration ........................................................................................................ 691.3.10 Advanced Motion Control ............................................................................................... 751.3.11 Analog .......................................................................................................................... 771.3.12 JTAG and ARM Serial Wire Debug ................................................................................ 791.3.13 Packaging and Temperature .......................................................................................... 801.4 TM4C129CNCPDT Microcontroller Hardware Details ...................................................... 801.5 Kits .............................................................................................................................. 801.6 Support Information ....................................................................................................... 80

2 The Cortex-M4F Processor ................................................................................... 812.1 Block Diagram .............................................................................................................. 822.2 Overview ...................................................................................................................... 832.2.1 System-Level Interface .................................................................................................. 832.2.2 Integrated Configurable Debug ...................................................................................... 832.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 842.2.4 Cortex-M4F System Component Details ......................................................................... 842.3 Programming Model ...................................................................................................... 852.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 852.3.2 Stacks .......................................................................................................................... 862.3.3 Register Map ................................................................................................................ 862.3.4 Register Descriptions .................................................................................................... 882.3.5 Exceptions and Interrupts ............................................................................................ 1042.3.6 Data Types ................................................................................................................. 1042.4 Memory Model ............................................................................................................ 1042.4.1 Memory Regions, Types and Attributes ......................................................................... 1072.4.2 Memory System Ordering of Memory Accesses ............................................................ 1082.4.3 Behavior of Memory Accesses ..................................................................................... 1082.4.4 Software Ordering of Memory Accesses ....................................................................... 109

3June 18, 2014Texas Instruments-Production Data


2.4.5 Bit-Banding ................................................................................................................. 1102.4.6 Data Storage .............................................................................................................. 1122.4.7 Synchronization Primitives ........................................................................................... 1132.5 Exception Model ......................................................................................................... 1142.5.1 Exception States ......................................................................................................... 1152.5.2 Exception Types .......................................................................................................... 1152.5.3 Exception Handlers ..................................................................................................... 1202.5.4 Vector Table ................................................................................................................ 1202.5.5 Exception Priorities ...................................................................................................... 1212.5.6 Interrupt Priority Grouping ............................................................................................ 1222.5.7 Exception Entry and Return ......................................................................................... 1222.6 Fault Handling ............................................................................................................. 1252.6.1 Fault Types ................................................................................................................. 1262.6.2 Fault Escalation and Hard Faults .................................................................................. 1262.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1272.6.4 Lockup ....................................................................................................................... 1272.7 Power Management .................................................................................................... 1282.7.1 Entering Sleep Modes ................................................................................................. 1282.7.2 Wake Up from Sleep Mode .......................................................................................... 1282.8 Instruction Set Summary .............................................................................................. 129

3 Cortex-M4 Peripherals ......................................................................................... 1363.1 Functional Description ................................................................................................. 1363.1.1 System Timer (SysTick) ............................................................................................... 1373.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1383.1.3 System Control Block (SCB) ........................................................................................ 1393.1.4 Memory Protection Unit (MPU) ..................................................................................... 1393.1.5 Floating-Point Unit (FPU) ............................................................................................. 1443.2 Register Map .............................................................................................................. 1483.3 System Timer (SysTick) Register Descriptions .............................................................. 1513.4 NVIC Register Descriptions .......................................................................................... 1553.5 System Control Block (SCB) Register Descriptions ........................................................ 1653.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 1943.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 203

4 JTAG Interface ...................................................................................................... 2094.1 Block Diagram ............................................................................................................ 2104.2 Signal Description ....................................................................................................... 2104.3 Functional Description ................................................................................................. 2114.3.1 JTAG Interface Pins ..................................................................................................... 2114.3.2 JTAG TAP Controller ................................................................................................... 2134.3.3 Shift Registers ............................................................................................................ 2144.3.4 Operational Considerations .......................................................................................... 2144.4 Initialization and Configuration ..................................................................................... 2174.5 Register Descriptions .................................................................................................. 2174.5.1 Instruction Register (IR) ............................................................................................... 2184.5.2 Data Registers ............................................................................................................ 219

5 System Control ..................................................................................................... 2225.1 Signal Description ....................................................................................................... 2225.2 Functional Description ................................................................................................. 222


Table of Contents

5.2.1 Device Identification .................................................................................................... 2225.2.2 Reset Control .............................................................................................................. 2235.2.3 Non-Maskable Interrupt ............................................................................................... 2305.2.4 Power Control ............................................................................................................. 2315.2.5 Clock Control .............................................................................................................. 2325.2.6 System Control ........................................................................................................... 2405.3 Initialization and Configuration ..................................................................................... 2475.4 Register Map .............................................................................................................. 2485.5 System Control Register Descriptions (System Control Offset) ....................................... 2555.6 Cryptographic System Control Register Description (CCM Offset) .................................. 507

6 Processor Support and Exception Module ........................................................ 5096.1 Functional Description ................................................................................................. 5096.2 Register Map .............................................................................................................. 5096.3 Register Descriptions .................................................................................................. 509

7 Hibernation Module .............................................................................................. 5177.1 Block Diagram ............................................................................................................ 5197.2 Signal Description ....................................................................................................... 5197.3 Functional Description ................................................................................................. 5207.3.1 Register Access Timing ............................................................................................... 5217.3.2 Hibernation Clock Source ............................................................................................ 5217.3.3 System Implementation ............................................................................................... 5247.3.4 Battery Management ................................................................................................... 5257.3.5 Real-Time Clock .......................................................................................................... 5257.3.6 Tamper ....................................................................................................................... 5287.3.7 Battery-Backed Memory .............................................................................................. 5317.3.8 Power Control Using HIB ............................................................................................. 5317.3.9 Power Control Using VDD3ON Mode ........................................................................... 5327.3.10 Initiating Hibernate ...................................................................................................... 5327.3.11 Waking from Hibernate ................................................................................................ 5327.3.12 Arbitrary Power Removal ............................................................................................. 5337.3.13 Interrupts and Status ................................................................................................... 5347.4 Initialization and Configuration ..................................................................................... 5347.4.1 Initialization ................................................................................................................. 5347.4.2 RTC Match Functionality (No Hibernation) .................................................................... 5357.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 5357.4.4 External Wake-Up from Hibernation .............................................................................. 5367.4.5 RTC or External Wake-Up from Hibernation .................................................................. 5377.4.6 Tamper Initialization ..................................................................................................... 5377.5 Register Map .............................................................................................................. 5377.6 Register Descriptions .................................................................................................. 539

8 Internal Memory ................................................................................................... 5868.1 Block Diagram ............................................................................................................ 5868.2 Functional Description ................................................................................................. 5888.2.1 SRAM ........................................................................................................................ 5888.2.2 ROM .......................................................................................................................... 5888.2.3 Flash Memory ............................................................................................................. 5908.2.4 EEPROM .................................................................................................................... 6018.2.5 Bus Matrix Memory Accesses ...................................................................................... 607



8.3 Register Map .............................................................................................................. 6078.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 6108.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 6368.6 Memory Register Descriptions (System Control Offset) .................................................. 653

9 Micro Direct Memory Access (μDMA) ................................................................ 6649.1 Block Diagram ............................................................................................................ 6659.2 Functional Description ................................................................................................. 6659.2.1 Channel Assignments .................................................................................................. 6669.2.2 Priority ........................................................................................................................ 6679.2.3 Arbitration Size ............................................................................................................ 6689.2.4 Request Types ............................................................................................................ 6689.2.5 Channel Configuration ................................................................................................. 6699.2.6 Transfer Modes ........................................................................................................... 6719.2.7 Transfer Size and Increment ........................................................................................ 6799.2.8 Peripheral Interface ..................................................................................................... 6799.2.9 Software Request ........................................................................................................ 6809.2.10 Interrupts and Errors .................................................................................................... 6809.3 Initialization and Configuration ..................................................................................... 6809.3.1 Module Initialization ..................................................................................................... 6809.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 6819.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 6829.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 6849.3.5 Configuring Channel Assignments ................................................................................ 6879.4 Register Map .............................................................................................................. 6879.5 μDMA Channel Control Structure ................................................................................. 6889.6 μDMA Register Descriptions ........................................................................................ 695

10 General-Purpose Input/Outputs (GPIOs) ........................................................... 72810.1 Signal Description ....................................................................................................... 72910.2 Pad Capabilities .......................................................................................................... 73210.3 Functional Description ................................................................................................. 73310.3.1 Data Control ............................................................................................................... 73510.3.2 Interrupt Control .......................................................................................................... 73710.3.3 Mode Control .............................................................................................................. 73810.3.4 Commit Control ........................................................................................................... 73910.3.5 Pad Control ................................................................................................................. 73910.3.6 Identification ............................................................................................................... 74010.4 Initialization and Configuration ..................................................................................... 74010.5 Register Map .............................................................................................................. 74210.6 Register Descriptions .................................................................................................. 745

11 External Peripheral Interface (EPI) ..................................................................... 80211.1 EPI Block Diagram ...................................................................................................... 80311.2 Signal Description ....................................................................................................... 80411.3 Functional Description ................................................................................................. 80511.3.1 Master Access to EPI .................................................................................................. 80611.3.2 Non-Blocking Reads .................................................................................................... 80611.3.3 DMA Operation ........................................................................................................... 80711.4 Initialization and Configuration ..................................................................................... 80811.4.1 EPI Interface Options .................................................................................................. 809


Table of Contents

11.4.2 SDRAM Mode ............................................................................................................. 80911.4.3 Host Bus Mode ........................................................................................................... 81311.4.4 General-Purpose Mode ............................................................................................... 83411.5 Register Map .............................................................................................................. 84111.6 Register Descriptions .................................................................................................. 843

12 Cyclical Redundancy Check (CRC) .................................................................... 93312.1 Functional Description ................................................................................................. 93312.1.1 CRC Support .............................................................................................................. 93312.2 Initialization and Configuration ..................................................................................... 93512.2.1 CRC Initialization and Configuration ............................................................................. 93512.3 Register Map .............................................................................................................. 93612.4 CRC Module Register Descriptions .............................................................................. 936

13 Advance Encryption Standard Accelerator (AES) ............................................ 94213.1 AES Overview ............................................................................................................. 94213.2 AES Functional Description .......................................................................................... 94213.2.1 AES Block Diagram ..................................................................................................... 94313.2.2 AES Algorithm ............................................................................................................ 94613.2.3 AES Operating Modes ................................................................................................. 94713.2.4 AES Software Reset .................................................................................................... 95513.2.5 Power Management .................................................................................................... 95513.2.6 Hardware Requests ..................................................................................................... 95513.3 AES Performance Information ...................................................................................... 95613.4 AES Module Programming Guide ................................................................................. 95813.4.1 AES Low - Level Programming Models ......................................................................... 95813.5 Register Map .............................................................................................................. 96313.6 AES Register Descriptions ........................................................................................... 96513.7 AES µDMA Interrupt Register Descriptions (CCM Offset) ............................................... 987

14 Data Encryption Standard Accelerator (DES) ................................................... 99414.1 DES Functional Description ......................................................................................... 99414.2 DES Block Diagram ..................................................................................................... 99514.2.1 µDMA Control ............................................................................................................. 99514.2.2 Interrupt Control .......................................................................................................... 99614.2.3 Register Interface ........................................................................................................ 99614.2.4 DES Engine ................................................................................................................ 99614.3 Software Reset ........................................................................................................... 99714.4 DES Supported Modes of Operation ............................................................................. 99714.4.1 ECB Feedback Mode .................................................................................................. 99714.5 DES Module Programming Guide -Low Level Programming Models ............................... 99914.5.1 Surrounding Modules Global Initialization ...................................................................... 99914.5.2 Operational Modes Configuration ............................................................................... 100014.5.3 DES Events Servicing ................................................................................................ 100214.6 Register Map ............................................................................................................ 100314.7 DES Register Description .......................................................................................... 100414.8 DES µDMA Interrupt Register Descriptions (CCM Offset) ............................................. 1018

15 SHA/MD5 Accelerator ........................................................................................ 102315.1 SHA/MD5 Functional Description ................................................................................ 102315.1.1 SHA/MD5 Block Diagram ........................................................................................... 1023



15.1.2 Power Management .................................................................................................. 102515.1.3 Reset Management ................................................................................................... 102515.1.4 µDMA and Interrupt Requests .................................................................................... 102515.1.5 Operation Description ................................................................................................ 102615.1.6 SHA/MD5 Performance Information ............................................................................ 103215.1.7 SHA/MD5 Programming Guide ................................................................................... 103315.2 SHA/MD5 Register Map ............................................................................................. 103715.3 SHA/MD5 Register Descriptions ................................................................................. 103915.4 SHA/MD5 µDMA Control Register Descriptions (Encryption Control Offset) ................... 1053

16 General-Purpose Timers .................................................................................... 105816.1 Block Diagram ........................................................................................................... 105916.2 Signal Description ..................................................................................................... 106016.3 Functional Description ............................................................................................... 106116.3.1 GPTM Reset Conditions ............................................................................................ 106216.3.2 Timer Clock Source ................................................................................................... 106216.3.3 Timer Modes ............................................................................................................. 106216.3.4 Wait-for-Trigger Mode ................................................................................................ 107116.3.5 Synchronizing GP Timer Blocks .................................................................................. 107216.3.6 DMA Operation ......................................................................................................... 107316.3.7 ADC Operation .......................................................................................................... 107316.3.8 Accessing Concatenated 16/32-Bit GPTM Register Values .......................................... 107316.4 Initialization and Configuration .................................................................................... 107416.4.1 One-Shot/Periodic Timer Mode .................................................................................. 107416.4.2 Real-Time Clock (RTC) Mode ..................................................................................... 107516.4.3 Input Edge-Count Mode ............................................................................................. 107516.4.4 Input Edge Time Mode ............................................................................................... 107616.4.5 PWM Mode ............................................................................................................... 107616.5 Register Map ............................................................................................................ 107716.6 Register Descriptions ................................................................................................. 1078

17 Watchdog Timers ............................................................................................... 113117.1 Block Diagram ........................................................................................................... 113217.2 Functional Description ............................................................................................... 113217.2.1 Register Access Timing ............................................................................................. 113317.3 Initialization and Configuration .................................................................................... 113317.4 Register Map ............................................................................................................ 113317.5 Register Descriptions ................................................................................................. 1134

18 Analog-to-Digital Converter (ADC) ................................................................... 115618.1 Block Diagram ........................................................................................................... 115718.2 Signal Description ..................................................................................................... 115818.3 Functional Description ............................................................................................... 115918.3.1 Sample Sequencers .................................................................................................. 115918.3.2 Module Control .......................................................................................................... 116018.3.3 Hardware Sample Averaging Circuit ........................................................................... 116518.3.4 Analog-to-Digital Converter ........................................................................................ 116618.3.5 Differential Sampling .................................................................................................. 116818.3.6 Internal Temperature Sensor ...................................................................................... 117018.3.7 Digital Comparator Unit .............................................................................................. 117118.4 Initialization and Configuration .................................................................................... 1175


Table of Contents

18.4.1 Module Initialization ................................................................................................... 117518.4.2 Sample Sequencer Configuration ............................................................................... 117618.5 Register Map ............................................................................................................ 117618.6 Register Descriptions ................................................................................................. 1179

19 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... 126419.1 Block Diagram ........................................................................................................... 126519.2 Signal Description ..................................................................................................... 126519.3 Functional Description ............................................................................................... 126719.3.1 Transmit/Receive Logic .............................................................................................. 126719.3.2 Baud-Rate Generation ............................................................................................... 126819.3.3 Data Transmission ..................................................................................................... 126919.3.4 Serial IR (SIR) ........................................................................................................... 126919.3.5 ISO 7816 Support ...................................................................................................... 127019.3.6 Modem Handshake Support ....................................................................................... 127119.3.7 9-Bit UART Mode ...................................................................................................... 127219.3.8 FIFO Operation ......................................................................................................... 127219.3.9 Interrupts .................................................................................................................. 127319.3.10 Loopback Operation .................................................................................................. 127419.3.11 DMA Operation ......................................................................................................... 127419.4 Initialization and Configuration .................................................................................... 127519.5 Register Map ............................................................................................................ 127619.6 Register Descriptions ................................................................................................. 1277

20 Quad Synchronous Serial Interface (QSSI) ..................................................... 132920.1 Block Diagram ........................................................................................................... 132920.2 Signal Description ..................................................................................................... 133020.3 Functional Description ............................................................................................... 133220.3.1 Bit Rate Generation ................................................................................................... 133220.3.2 FIFO Operation ......................................................................................................... 133220.3.3 Advanced, Bi- and Quad- SSI Function ....................................................................... 133320.3.4 SSInFSS Function ..................................................................................................... 133420.3.5 High Speed Clock Operation ...................................................................................... 133520.3.6 Interrupts .................................................................................................................. 133520.3.7 Frame Formats ......................................................................................................... 133620.3.8 DMA Operation ......................................................................................................... 134320.4 Initialization and Configuration .................................................................................... 134320.4.1 Enhanced Mode Configuration ................................................................................... 134520.5 Register Map ............................................................................................................ 134620.6 Register Descriptions ................................................................................................. 1347

21 Inter-Integrated Circuit (I2C) Interface .............................................................. 137821.1 Block Diagram ........................................................................................................... 137921.2 Signal Description ..................................................................................................... 138021.3 Functional Description ............................................................................................... 138121.3.1 I2C Bus Functional Overview ...................................................................................... 138121.3.2 Available Speed Modes ............................................................................................. 138721.3.3 Interrupts .................................................................................................................. 138921.3.4 Loopback Operation .................................................................................................. 139021.3.5 FIFO and µDMA Operation ........................................................................................ 139021.3.6 Command Sequence Flow Charts .............................................................................. 1392



21.4 Initialization and Configuration .................................................................................... 140021.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 140021.4.2 Configure the I2C Master to High Speed Mode ............................................................ 140121.5 Register Map ............................................................................................................ 140221.6 Register Descriptions (I2C Master) .............................................................................. 140421.7 Register Descriptions (I2C Slave) ............................................................................... 143321.8 Register Descriptions (I2C Status and Control) ............................................................ 1450

22 Controller Area Network (CAN) Module ........................................................... 145922.1 Block Diagram ........................................................................................................... 146022.2 Signal Description ..................................................................................................... 146022.3 Functional Description ............................................................................................... 146122.3.1 Initialization ............................................................................................................... 146222.3.2 Operation .................................................................................................................. 146222.3.3 Transmitting Message Objects ................................................................................... 146322.3.4 Configuring a Transmit Message Object ...................................................................... 146422.3.5 Updating a Transmit Message Object ......................................................................... 146522.3.6 Accepting Received Message Objects ........................................................................ 146522.3.7 Receiving a Data Frame ............................................................................................ 146622.3.8 Receiving a Remote Frame ........................................................................................ 146622.3.9 Receive/Transmit Priority ........................................................................................... 146622.3.10 Configuring a Receive Message Object ...................................................................... 146722.3.11 Handling of Received Message Objects ...................................................................... 146822.3.12 Handling of Interrupts ................................................................................................ 147022.3.13 Test Mode ................................................................................................................. 147122.3.14 Bit Timing Configuration Error Considerations ............................................................. 147322.3.15 Bit Time and Bit Rate ................................................................................................. 147322.3.16 Calculating the Bit Timing Parameters ........................................................................ 147522.4 Register Map ............................................................................................................ 147822.5 CAN Register Descriptions ......................................................................................... 1479

23 Universal Serial Bus (USB) Controller ............................................................. 151023.1 Block Diagram ........................................................................................................... 151123.2 Signal Description ..................................................................................................... 151123.3 Register Map ............................................................................................................ 1512

24 Analog Comparators .......................................................................................... 151924.1 Block Diagram ........................................................................................................... 152024.2 Signal Description ..................................................................................................... 152024.3 Functional Description ............................................................................................... 152124.3.1 Internal Reference Programming ................................................................................ 152224.4 Initialization and Configuration .................................................................................... 152424.5 Register Map ............................................................................................................ 152524.6 Register Descriptions ................................................................................................. 1525

25 Pulse Width Modulator (PWM) .......................................................................... 153525.1 Block Diagram ........................................................................................................... 153625.2 Signal Description ..................................................................................................... 153825.3 Functional Description ............................................................................................... 153825.3.1 Clock Configuration ................................................................................................... 153825.3.2 PWM Timer ............................................................................................................... 1538


Table of Contents

25.3.3 PWM Comparators .................................................................................................... 153925.3.4 PWM Signal Generator .............................................................................................. 154025.3.5 Dead-Band Generator ............................................................................................... 154125.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 154125.3.7 Synchronization Methods .......................................................................................... 154225.3.8 Fault Conditions ........................................................................................................ 154325.3.9 Output Control Block .................................................................................................. 154425.4 Initialization and Configuration .................................................................................... 154425.5 Register Map ............................................................................................................ 154525.6 Register Descriptions ................................................................................................. 1548

26 Quadrature Encoder Interface (QEI) ................................................................. 161426.1 Block Diagram ........................................................................................................... 161426.2 Signal Description ..................................................................................................... 161626.3 Functional Description ............................................................................................... 161626.4 Initialization and Configuration .................................................................................... 161926.5 Register Map ............................................................................................................ 161926.6 Register Descriptions ................................................................................................. 1620

27 Pin Diagram ........................................................................................................ 163728 Signal Tables ...................................................................................................... 163828.1 Signals by Pin Number .............................................................................................. 163928.2 Signals by Signal Name ............................................................................................. 165128.3 Signals by Function, Except for GPIO ......................................................................... 166328.4 GPIO Pins and Alternate Functions ............................................................................ 167528.5 Possible Pin Assignments for Alternate Functions ....................................................... 167928.6 Connections for Unused Signals ................................................................................. 1684

29 Electrical Characteristics .................................................................................. 168629.1 Maximum Ratings ...................................................................................................... 168629.2 Operating Characteristics ........................................................................................... 168729.3 Recommended Operating Conditions ......................................................................... 168829.3.1 DC Operating Conditions ........................................................................................... 168829.3.2 Recommended GPIO Operating Characteristics .......................................................... 168829.4 Load Conditions ........................................................................................................ 169129.5 JTAG and Boundary Scan .......................................................................................... 169229.6 Power and Brown-Out ............................................................................................... 169429.6.1 VDDA Levels .............................................................................................................. 169429.6.2 VDD Levels ................................................................................................................ 169529.6.3 VDDC Levels .............................................................................................................. 169629.6.4 Response ................................................................................................................. 169729.7 Reset ........................................................................................................................ 169929.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 170229.9 Clocks ...................................................................................................................... 170329.9.1 PLL Specifications ..................................................................................................... 170329.9.2 PIOSC Specifications ................................................................................................ 170529.9.3 Low-Frequency Internal Oscillator Specifications ......................................................... 170529.9.4 Hibernation Clock Source Specifications ..................................................................... 170529.9.5 Main Oscillator Specifications ..................................................................................... 170629.9.6 System Clock Specification with ADC Operation .......................................................... 1710



29.9.7 System Clock Specification with USB Operation .......................................................... 171029.10 Sleep Modes ............................................................................................................. 171129.11 Hibernation Module ................................................................................................... 171329.12 Flash Memory ........................................................................................................... 171529.13 EEPROM .................................................................................................................. 171629.14 Input/Output Pin Characteristics ................................................................................. 171729.14.1 Types of I/O Pins and ESD Protection ......................................................................... 171929.15 External Peripheral Interface (EPI) .............................................................................. 172129.16 Analog-to-Digital Converter (ADC) .............................................................................. 172929.17 Synchronous Serial Interface (SSI) ............................................................................. 173529.18 Inter-Integrated Circuit (I2C) Interface ......................................................................... 173829.19 Universal Serial Bus (USB) Controller ......................................................................... 173929.20 Analog Comparator ................................................................................................... 174129.21 Pulse-Width Modulator (PWM) ................................................................................... 174329.22 Current Consumption ................................................................................................ 1744

A Package Information .......................................................................................... 1748A.1 Orderable Devices ..................................................................................................... 1748A.2 Device Nomenclature ................................................................................................ 1748A.3 Device Markings ........................................................................................................ 1748A.4 Packaging Diagram ................................................................................................... 1750


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List of FiguresFigure 1-1. Tiva™ TM4C129CNCPDT Microcontroller High-Level Block Diagram ...................... 55Figure 2-1. CPU Block Diagram ............................................................................................. 83Figure 2-2. TPIU Block Diagram ............................................................................................ 84Figure 2-3. Cortex-M4F Register Set ...................................................................................... 87Figure 2-4. Bit-Band Mapping .............................................................................................. 112Figure 2-5. Data Storage ..................................................................................................... 113Figure 2-6. Vector Table ...................................................................................................... 121Figure 2-7. Exception Stack Frame ...................................................................................... 124Figure 3-1. SRD Use Example ............................................................................................. 142Figure 3-2. FPU Register Bank ............................................................................................ 145Figure 4-1. JTAG Module Block Diagram .............................................................................. 210Figure 4-2. Test Access Port State Machine ......................................................................... 214Figure 4-3. IDCODE Register Format ................................................................................... 220Figure 4-4. BYPASS Register Format ................................................................................... 220Figure 4-5. Boundary Scan Register Format ......................................................................... 220Figure 5-1. Basic RST Configuration .................................................................................... 226Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 226Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 226Figure 5-4. Power Architecture ............................................................................................ 231Figure 5-5. Main Clock Tree ................................................................................................ 235Figure 5-6. Module Clock Selection ...................................................................................... 243Figure 7-1. Hibernation Module Block Diagram ..................................................................... 519Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 523Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 523Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 524Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 528Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 528Figure 7-7. Tamper Block Diagram ....................................................................................... 528Figure 7-8. Tamper Pad with Glitch Filtering ......................................................................... 529Figure 8-1. Internal Memory Block Diagram .......................................................................... 587Figure 8-2. Flash Memory Configuration ............................................................................... 591Figure 8-3. Single 256-Bit Prefetch Buffer Set ....................................................................... 592Figure 8-4. Four 256-Bit Prefetch Buffer Configuration .......................................................... 592Figure 8-5. Single Cycle Access, 0 Wait States ..................................................................... 593Figure 8-6. Prefetch Fills from Flash ..................................................................................... 594Figure 8-7. Mirror Mode Function ......................................................................................... 595Figure 9-1. μDMA Block Diagram ......................................................................................... 665Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 672Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 674Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 675Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 677Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 678Figure 10-1. Digital I/O Pads ................................................................................................. 734Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 735Figure 10-3. GPIODATA Write Example ................................................................................. 736



Figure 10-4. GPIODATA Read Example ................................................................................. 736Figure 11-1. EPI Block Diagram ............................................................................................. 804Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 811Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 812Figure 11-4. SDRAM Write Cycle ........................................................................................... 813Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11 .......................................................... 823Figure 11-6. iRDY Signal Connection ..................................................................................... 823Figure 11-7. PSRAM Burst Read ........................................................................................... 826Figure 11-8. PSRAM Burst Write ........................................................................................... 826Figure 11-9. Read Delay During Refresh Event ...................................................................... 827Figure 11-10. Write Delay During Refresh Event ....................................................................... 828Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 829Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 832Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 832Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH

= 0, RDHIGH = 0 ............................................................................................... 833Figure 11-15. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or

Quad CSn ......................................................................................................... 833Figure 11-16. Continuous Read Mode Accesses ...................................................................... 833Figure 11-17. Write Followed by Read to External FIFO ............................................................ 834Figure 11-18. Two-Entry FIFO ................................................................................................. 834Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 ............... 837Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 ............... 838Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 ............................................................. 838Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 839Figure 11-23. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 839Figure 11-24. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 839Figure 11-25. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 839Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 840Figure 11-27. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 840Figure 11-28. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 840Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 841Figure 13-1. AES Block Diagram ........................................................................................... 943Figure 13-2. AES - ECB Feedback Mode ............................................................................... 947Figure 13-3. AES - CBC Feedback Mode ............................................................................... 948Figure 13-4. AES Encryption With CTR/ICM Mode .................................................................. 948Figure 13-5. AES - CFB Feedback Mode ............................................................................... 949Figure 13-6. AES - F8 Mode .................................................................................................. 950Figure 13-7. AES - XTS Operation ......................................................................................... 950Figure 13-8. AES - F9 Operation ........................................................................................... 951Figure 13-9. AES - CBC-MAC Authentication Mode ................................................................ 952Figure 13-10. AES - GCM Operation ........................................................................................ 953Figure 13-11. AES - CCM Operation ........................................................................................ 954Figure 13-12. AES Polling Mode .............................................................................................. 961Figure 13-13. AES Interrupt Service ........................................................................................ 963Figure 14-1. DES Block Diagram ........................................................................................... 995Figure 14-2. DES - ECB Feedback Mode ............................................................................... 998Figure 14-3. DES3DES - CBC Feedback Mode ...................................................................... 998


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Figure 14-4. DES3DES-CFB Feedback Mode ........................................................................ 999Figure 14-5. DES Polling Mode ............................................................................................ 1001Figure 14-6. DES Interrupt Service ...................................................................................... 1002Figure 14-7. DES Context Input Event Service ...................................................................... 1003Figure 15-1. SHA/MD5 Module Block Diagram ..................................................................... 1024Figure 15-2. SHA/MD5 Polling Mode .................................................................................... 1035Figure 15-3. SHA/MD5 Interrupt Subroutine ......................................................................... 1037Figure 16-1. GPTM Module Block Diagram ........................................................................... 1059Figure 16-2. Input Edge-Count Mode Example, Counting Down ............................................. 1067Figure 16-3. 16-Bit Input Edge-Time Mode Example ............................................................. 1068Figure 16-4. 16-Bit PWM Mode Example .............................................................................. 1070Figure 16-5. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................. 1070Figure 16-6. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................. 1071Figure 16-7. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................. 1071Figure 16-8. Timer Daisy Chain ........................................................................................... 1072Figure 17-1. WDT Module Block Diagram ............................................................................. 1132Figure 18-1. Implementation of Two ADC Blocks .................................................................. 1157Figure 18-2. ADC Module Block Diagram ............................................................................. 1158Figure 18-3. ADC Sample Phases ....................................................................................... 1163Figure 18-4. Doubling the ADC Sample Rate ........................................................................ 1163Figure 18-5. Skewed Sampling ............................................................................................ 1164Figure 18-6. Sample Averaging Example .............................................................................. 1166Figure 18-7. ADC Input Equivalency .................................................................................... 1167Figure 18-8. ADC Voltage Reference ................................................................................... 1167Figure 18-9. ADC Conversion Result ................................................................................... 1168Figure 18-10. Differential Voltage Representation ................................................................... 1170Figure 18-11. Internal Temperature Sensor Characteristic ....................................................... 1171Figure 18-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) .............................................. 1173Figure 18-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................... 1174Figure 18-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) .............................................. 1175Figure 19-1. UART Module Block Diagram ........................................................................... 1265Figure 19-2. UART Character Frame .................................................................................... 1268Figure 19-3. IrDA Data Modulation ....................................................................................... 1270Figure 20-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support .............................. 1330Figure 20-2. TI Synchronous Serial Frame Format (Single Transfer) ...................................... 1337Figure 20-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................... 1338Figure 20-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ........................ 1339Figure 20-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ................ 1339Figure 20-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ....................................... 1340Figure 20-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............. 1341Figure 20-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ...... 1341Figure 20-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ....................................... 1342Figure 21-1. I2C Block Diagram ........................................................................................... 1379Figure 21-2. I2C Bus Configuration ....................................................................................... 1381Figure 21-3. START and STOP Conditions ........................................................................... 1382Figure 21-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1382Figure 21-5. R/S Bit in First Byte .......................................................................................... 1383Figure 21-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1383



Figure 21-7. High-Speed Data Format .................................................................................. 1389Figure 21-8. Master Single TRANSMIT ................................................................................ 1393Figure 21-9. Master Single RECEIVE ................................................................................... 1394Figure 21-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1395Figure 21-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1396Figure 21-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1397Figure 21-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1398Figure 21-14. Standard High Speed Mode Master Transmit ..................................................... 1399Figure 21-15. Slave Command Sequence .............................................................................. 1400Figure 22-1. CAN Controller Block Diagram .......................................................................... 1460Figure 22-2. CAN Data/Remote Frame ................................................................................. 1461Figure 22-3. Message Objects in a FIFO Buffer .................................................................... 1470Figure 22-4. CAN Bit Time ................................................................................................... 1474Figure 23-1. USB Module Block Diagram ............................................................................. 1511Figure 24-1. Analog Comparator Module Block Diagram ....................................................... 1520Figure 24-2. Structure of Comparator Unit ............................................................................ 1521Figure 24-3. Comparator Internal Reference Structure .......................................................... 1522Figure 25-1. PWM Module Diagram ..................................................................................... 1537Figure 25-2. PWM Generator Block Diagram ........................................................................ 1537Figure 25-3. PWM Count-Down Mode .................................................................................. 1540Figure 25-4. PWM Count-Up/Down Mode ............................................................................. 1540Figure 25-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1541Figure 25-6. PWM Dead-Band Generator ............................................................................. 1541Figure 26-1. QEI Block Diagram .......................................................................................... 1615Figure 26-2. QEI Input Signal Logic ...................................................................................... 1616Figure 26-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1618Figure 27-1. 128-Pin TQFP Package Pin Diagram ................................................................ 1637Figure 29-1. Load Conditions ............................................................................................... 1691Figure 29-2. JTAG Test Clock Input Timing ........................................................................... 1693Figure 29-3. JTAG Test Access Port (TAP) Timing ................................................................ 1693Figure 29-4. Power and Brown-Out Assertions vs VDDA Levels .............................................. 1695Figure 29-5. Power and Brown-Out Assertions vs VDD Levels ................................................ 1696Figure 29-6. POK Assertion vs VDDC ................................................................................... 1697Figure 29-7. POR-BOR VDD Glitch Response ....................................................................... 1697Figure 29-8. POR-BOR VDD Droop Response ...................................................................... 1698Figure 29-9. Digital Power-On Reset Timing ......................................................................... 1699Figure 29-10. Brown-Out Reset Timing .................................................................................. 1700Figure 29-11. External Reset Timing (RST) ............................................................................ 1700Figure 29-12. Software Reset Timing ..................................................................................... 1700Figure 29-13. Watchdog Reset Timing ................................................................................... 1700Figure 29-14. MOSC Failure Reset Timing ............................................................................. 1701Figure 29-15. Hibernation Module Timing ............................................................................... 1714Figure 29-16. ESD Protection ................................................................................................ 1719Figure 29-17. ESD Protection for Non-Power Pins (Except WAKE Signal) ................................ 1720Figure 29-18. SDRAM Initialization and Load Mode Register Timing ........................................ 1722Figure 29-19. SDRAM Read Timing ....................................................................................... 1722Figure 29-20. SDRAM Write Timing ....................................................................................... 1723Figure 29-21. Host-Bus 8/16 Asynchronous Mode Read Timing ............................................... 1724


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Figure 29-22. Host-Bus 8/16 Asynchronous Mode Write Timing ............................................... 1724Figure 29-23. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing .................................... 1725Figure 29-24. Host-Bus 8/16 Mode Asynchronous Muxed Write Timing .................................... 1725Figure 29-25. General-Purpose Mode Read and Write Timing ................................................. 1726Figure 29-26. PSRAM Single Burst Read ............................................................................... 1727Figure 29-27. PSRAM Single Burst Write ............................................................................... 1728Figure 29-28. ADC External Reference Filtering ..................................................................... 1734Figure 29-29. ADC Input Equivalency .................................................................................... 1734Figure 29-30. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing

Measurement .................................................................................................. 1736Figure 29-31. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1736Figure 29-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1737Figure 29-33. I2C Timing ....................................................................................................... 1738Figure 29-34. ULPI Interface Timing Diagram ......................................................................... 1740Figure A-1. Key to Part Numbers ........................................................................................ 1748Figure A-2. TM4C129CNCPDT 128-Pin TQFP Package Diagram ......................................... 1750



List of TablesTable 1. Revision History .................................................................................................. 46Table 2. Documentation Conventions ................................................................................ 50Table 1-1. TM4C129CNCPDT Microcontroller Features ......................................................... 53Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 86Table 2-2. Processor Register Map ....................................................................................... 87Table 2-3. PSR Register Combinations ................................................................................. 93Table 2-4. Memory Map ..................................................................................................... 104Table 2-5. Memory Access Behavior ................................................................................... 108Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 110Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 110Table 2-8. Exception Types ................................................................................................ 116Table 2-9. Interrupts .......................................................................................................... 117Table 2-10. Exception Return Behavior ................................................................................. 125Table 2-11. Faults ............................................................................................................... 126Table 2-12. Fault Status and Fault Address Registers ............................................................ 127Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 129Table 3-1. Core Peripheral Register Regions ....................................................................... 136Table 3-2. Memory Attributes Summary .............................................................................. 140Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 142Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 143Table 3-5. AP Bit Field Encoding ........................................................................................ 143Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 144Table 3-7. QNaN and SNaN Handling ................................................................................. 147Table 3-8. Peripherals Register Map ................................................................................... 148Table 3-9. Interrupt Priority Levels ...................................................................................... 173Table 3-10. Example SIZE Field Values ................................................................................ 201Table 4-1. JTAG_SWD_SWO Signals (128TQFP) ............................................................... 210Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 212Table 4-3. JTAG Instruction Register Commands ................................................................. 218Table 5-1. System Control & Clocks Signals (128TQFP) ...................................................... 222Table 5-2. Reset Sources ................................................................................................... 223Table 5-3. Clock Source Options ........................................................................................ 233Table 5-4. Clock Source State Following POR ..................................................................... 233Table 5-5. System Clock Frequency ................................................................................... 237Table 5-6. System Divisor Factors for fvco=480 MHz ............................................................ 239Table 5-7. Actual PLL Frequency ........................................................................................ 239Table 5-8. Peripheral Memory Power Control ...................................................................... 245Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 245Table 5-10. MOSC Configurations ........................................................................................ 248Table 5-11. System Control Register Map ............................................................................. 249Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 278Table 5-13. MOSC Configurations ........................................................................................ 282Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 301Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 304Table 5-16. Module