tinypowertm i/o flash 8-bit mcu with lcd & eeprom ht69f30a ... · rev. 1.20 6 to e 0 201 rev....

TinyPowerTM I/O Flash 8-Bit MCU with LCD & EEPROM

HT69F30A/HT69F40A/HT69F50A

Revision: V1.20 Date: ��to�e� 0�� 201��to�e� 0�� 201�

Rev. 1.20 2 ��to�e� 0�� 201� Rev. 1.20 3 ��to�e� 0�� 201�

HT69F30A/HT69F40A/HT69F50ATinyPowerTM I/O Flash 8-Bit MCU with LCD & EEPROM


Table of Contents

Features ............................................................................................................ 6CPU Featu�es ......................................................................................................................... 6Pe�iphe�al Featu�es ................................................................................................................. 6

General Description ......................................................................................... 7Selection Table ................................................................................................. 7Block Diagram .................................................................................................. 8Pin Assignment ................................................................................................ 9Pin Description .............................................................................................. 13Absolute Maximum Ratings .......................................................................... 24D.C. Characteristics ....................................................................................... 25A.C. Characteristics ....................................................................................... 28LVD & LVR Electrical Characteristics .......................................................... 29LCD D.C. Characteristics .............................................................................. 30Power-on Reset Characteristics ................................................................... 31System Architecture ...................................................................................... 31

Clo�king and Pipelining ......................................................................................................... 31P�og�am Counte� ................................................................................................................... 32Sta�k ..................................................................................................................................... 33A�ithmeti� and Logi� Unit – ALU ........................................................................................... 33

Flash Program Memory ................................................................................. 34St�u�tu�e ................................................................................................................................ 34Spe�ial Ve�to�s ..................................................................................................................... 3�Look-up Ta�le ........................................................................................................................ 3�Ta�le P�og�am Example ........................................................................................................ 3�In Ci��uit P�og�amming – ICP ............................................................................................... 36�n-Chip De�ug Suppo�t – �CDS ......................................................................................... 37

Data Memory .................................................................................................. 38St�u�tu�e ................................................................................................................................ 3�Gene�al Pu�pose Data Memo�y ............................................................................................ 39Spe�ial Pu�pose Data Memo�y ............................................................................................. 39

Special Function Register Description ........................................................ 43Indi�e�t Add�essing Registe�s – IAR0� IAR1 ......................................................................... 43Memo�y Pointe�s – MP0� MP1 .............................................................................................. 43Bank Pointe� – BP ................................................................................................................. 44A��umulato� – ACC ............................................................................................................... 4�P�og�am Counte� Low Registe� – PCL .................................................................................. 4�Look-up Ta�le Registe�s – TBLP� TBHP� TBLH ..................................................................... 4�Status Registe� – STATUS .................................................................................................... 46

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EEPROM Data Memory .................................................................................. 48EEPR�M Registe�s .............................................................................................................. 4�Reading Data f�om the EEPR�M ......................................................................................... �0W�iting Data to the EEPR�M ................................................................................................ �0W�ite P�ote�tion ..................................................................................................................... �0EEPR�M Inte��upt ................................................................................................................ �0P�og�amming Conside�ations ................................................................................................ �1

Oscillator ........................................................................................................ 52�s�illato� �ve�view ............................................................................................................... �2System Clock Configurations ................................................................................................ �2Exte�nal C�ystal/Ce�ami� �s�illato� – HXT ........................................................................... �3Exte�nal RC �s�illato� – ERC ............................................................................................... �4Inte�nal RC �s�illato� – HIRC ............................................................................................... �4Exte�nal 32.76�kHz C�ystal �s�illato� – LXT ........................................................................ ��LXT �s�illato� Low Powe� Fun�tion ...................................................................................... �6Inte�nal 32kHz �s�illato� – LIRC ........................................................................................... �6Exte�nal Clo�k – EC .............................................................................................................. �6Supplementa�y �s�illato�s .................................................................................................... �6

Operating Modes and System Clocks ......................................................... 57System Clo�k ........................................................................................................................ �7System �pe�ation Modes ...................................................................................................... ��Cont�ol Registe� .................................................................................................................... �9Fast Wake-up ........................................................................................................................ 61�pe�ating Mode Swit�hing .................................................................................................... 61�pe�ating Mode Swit�hing and Wake-up .............................................................................. 62N�RMAL Mode to SL�W Mode Swit�hing ........................................................................... 63SL�W Mode to N�RMAL Mode Swit�hing ........................................................................... 64Ente�ing the SLEEP0 Mode .................................................................................................. 6�Ente�ing the SLEEP1 Mode .................................................................................................. 6�Ente�ing the IDLE0 Mode ...................................................................................................... 6�Ente�ing the IDLE1 Mode ...................................................................................................... 66Stand�y Cu��ent Conside�ations ........................................................................................... 66Wake-up ................................................................................................................................ 67P�og�amming Conside�ations ................................................................................................ 67

Watchdog Timer ............................................................................................. 68Wat�hdog Time� Clo�k Sou��e .............................................................................................. 6�Wat�hdog Time� Cont�ol Registe� ......................................................................................... 6�Wat�hdog Time� �pe�ation ................................................................................................... 69

Reset and Initialisation .................................................................................. 70Reset Fun�tions .................................................................................................................... 71Reset Initial Conditions ......................................................................................................... 74

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Input/Output Ports ......................................................................................... 78I/� Po�t Registe� List ............................................................................................................. 7�Pull-high Resisto�s ................................................................................................................ �1Po�t A Wake-up ..................................................................................................................... �1I/� Po�t Cont�ol Registe�s ..................................................................................................... �1Pin-sha�ed Fun�tions ............................................................................................................ �1I/� Pin St�u�tu�es .................................................................................................................. 92P�og�amming Conside�ations ................................................................................................ 92

Timer Modules – TM ...................................................................................... 93Int�odu�tion ........................................................................................................................... 93TM �pe�ation ........................................................................................................................ 93TM Clo�k Sou��e ................................................................................................................... 94TM Inte��upts ......................................................................................................................... 94TM Exte�nal Pins ................................................................................................................... 94TM Input/�utput Pin Cont�ol Registe�s ................................................................................. 9�P�og�amming Conside�ations .............................................................................................. 101

Compact Type TM – CTM ............................................................................ 102Compa�t TM �pe�ation ....................................................................................................... 102Compa�t Type TM Registe� Des��iption.............................................................................. 103Compa�t Type TM �pe�ating Modes .................................................................................. 107Compa�e Mat�h �utput Mode ............................................................................................. 107Time�/Counte� Mode ............................................................................................................110PWM �utput Mode ...............................................................................................................110

Standard Type TM – STM .............................................................................113Standa�d TM �pe�ation ........................................................................................................113Standa�d Type TM Registe� Des��iption ..............................................................................114Standa�d Type TM �pe�ating Modes .................................................................................. 123Compa�e �utput Mode ........................................................................................................ 123Time�/Counte� Mode ........................................................................................................... 126PWM �utput Mode .............................................................................................................. 126Single Pulse Mode .............................................................................................................. 130Captu�e Input Mode ............................................................................................................ 132

Enhanced Type TM – ETM ........................................................................... 134Enhan�ed TM �pe�ation ..................................................................................................... 134Enhan�ed Type TM Registe� Des��iption ............................................................................ 13�Enhan�ed Type TM �pe�ating Modes................................................................................. 142Compa�e �utput Mode ........................................................................................................ 142Time�/Counte� Mode ........................................................................................................... 147PWM �utput Mode .............................................................................................................. 147Single Pulse �utput Mode .................................................................................................. 1�3Captu�e Input Mode ............................................................................................................ 1��

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Interrupts ...................................................................................................... 158Inte��upt Registe�s ............................................................................................................... 1��Inte��upt �pe�ation .............................................................................................................. 164Exte�nal Inte��upt ................................................................................................................. 166Multi-fun�tion Inte��upt ........................................................................................................ 166Time Base Inte��upt ............................................................................................................. 167EEPR�M Inte��upt .............................................................................................................. 16�LVD Inte��upt ....................................................................................................................... 16�TM Inte��upts ....................................................................................................................... 16�Inte��upt Wake-up Fun�tion ................................................................................................. 169P�og�amming Conside�ations .............................................................................................. 169

Low Voltage Detector – LVD ....................................................................... 170LVD Registe� ....................................................................................................................... 170LVD �pe�ation ..................................................................................................................... 171

LCD Driver .................................................................................................... 172LCD Memo�y ....................................................................................................................... 172LCD Registe� ....................................................................................................................... 174LCD Reset Fun�tion ............................................................................................................ 17�Clo�k Sou��e ....................................................................................................................... 17�LCD D�ive� �utput ............................................................................................................... 17�LCD Voltage Sou��e Biasing ............................................................................................... 176LCD Wavefo�m Timing Diag�am.......................................................................................... 177P�og�amming Conside�ations .............................................................................................. 1�2

Configuration Options ................................................................................. 183Application Circuits ..................................................................................... 184Instruction Set .............................................................................................. 185

Int�odu�tion ......................................................................................................................... 1��Inst�u�tion Timing ................................................................................................................ 1��Moving and T�ansfe��ing Data ............................................................................................. 1��A�ithmeti� �pe�ations .......................................................................................................... 1��Logi�al and Rotate �pe�ations ............................................................................................ 1�6B�an�hes and Cont�ol T�ansfe� ........................................................................................... 1�6Bit �pe�ations ..................................................................................................................... 1�6Ta�le Read �pe�ations ....................................................................................................... 1�6�the� �pe�ations ................................................................................................................. 1�6

Instruction Set Summary ............................................................................ 187Ta�le �onventions ............................................................................................................... 1�7

Instruction Definition ................................................................................... 189Package Information ................................................................................... 198

4�-pin LQFP (7mm×7mm) �utline Dimensions .................................................................. 19964-pin LQFP (7mm×7mm) �utline Dimensions .................................................................. 200�0-pin LQFP (10mm×10mm) �utline Dimensions .............................................................. 201

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Features

CPU Features• Operatingvoltage

♦ fSYS=4MHz:2.2V~5.5V♦ fSYS=8MHz:2.4V~5.5V♦ fSYS=12MHz:2.7V~5.5V♦ fSYS=20MHz:4.5V~5.5V

• Upto0.2μsinstructioncyclewith20MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• Oscillatortypes♦ ExternalCrystal–HXT♦ External32.765kHzCrystal–LXT♦ ExternalRC–ERC♦ ExternalClock–EC♦ InternalRC–HIRC♦ Internal32kHzRC–LIRC

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP

• Fullyintegratedinternal4MHz,8MHzand12MHzoscillatorrequiresnoexternalcomponents

• Allinstructionsexecutedinoneortwoinstructioncycles

• Tablereadinstructions

• 63powerfulinstructions

• Upto8-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:2K×16~8K×16

• DataMemory:128×8~384×8

• EEPROMMemory:64×8~128×8

• WatchdogTimerfunction

• Upto52bidirectionalI/Olines

• LCDdriverfunction

• Multiplepin-sharedexternalinterrupts

• MultipleTimerModulefortimemeasure,inputcapture,comparematchoutput,PWMoutputorsinglepulseoutputfunction

• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals

• Lowvoltageresetfunction

• Lowvoltagedetectfunction

• Widerangeofavailablepackagetypes

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General DescriptionTheHT69Fx0AseriesofdevicesareFlashMemoryLCD type8-bithighperformanceRISCarchitecturemicrocontrollers,designedforapplicationswhichrequireanLCDinterface.OfferinguserstheconvenienceofFlashMemorymulti-programmingfeatures, thesedevicesalsoincludeawiderangeoffunctionsandfeatures.OthermemoryincludesanareaofRAMDataMemory.

Analog features includemultipleandextremely flexibleTimerModulesprovide timing,pulsegenerationandPWMgenerationfunctions.ProtectivefeaturessuchasaninternalWatchdogTimer,LowVoltageResetandLowVoltageDetectorcoupledwithexcellentnoise immunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.

Afullchoiceofinternalandexternaloscillatorfunctionsareprovidedincludingfullyintegratedlowandhighspeedsystemoscillatorswhichrequiresnoexternalcomponentsfortheirimplementation.Theabilitytooperateandswitchdynamicallybetweenarangeofoperatingmodesusingdifferentclocksourcesgivesuserstheabilitytooptimisemicrocontrolleroperationandminimisepowerconsumption.

TheinclusionofflexibleI/Oprogrammingfeatures,Time-Basefunctionsalongwithmanyotherfeaturesensurethatthedeviceswillfindexcellentuseinapplicationssuchasconsumerproducts,handheldinstruments,householdappliances,electronicallycontrolledtoolsandmotordrivinginadditiontomanyothers.

Selection TableMost featuresarecommon toalldevices.Themain featuresdistinguishing themareMemorycapacity,I/Ocount,TMfeatures,stackcapacity,LCDdriverandpackagetypes.Thefollowingtablesummarisesthemainfeaturesofeachdevice.

Part No. Program Memory

Data Memory

Data EEPROM I/O External

InterruptLCD

DriverTimer

ModuleTime Base Stacks Package

HT69F30A 2k×16 12�×� 64×� 39 2 24×42�×3

10-�it CTM×110-�it STM×1 2 4 4�LQFP

HT69F40A 4k×16 2�6×� 12�×� �1 2 36×437×3

10-�it CTM×110-�it STM×110-�it ETM×1

2 � 4�/64LQFP

HT69F�0A �k×16 3�4×� 12�×� 63 2 4�×449×3

10-�it CTM×116-�it STM×110-�it ETM×1

2 � 4�/64/�0LQFP

Note:Asdevicesexistinmorethanonepackageformat,thetablereflectsthesituationforthepackagewiththemostpins.

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Block Diagram

Flash/EEPROMProgramming

Circuitry (ICP)/OCDS

WatchdogTimer

8-bitRISCMCUCore

ResetCircuit

InterruptController

ERC/EC/HXTOscillator

LIRC/LXTOscillator

HIRCOscillator

Stack

EEPROMData

Memory

FlashProgramMemory

RAMData

Memory

TM0 TMn

LowVoltageReset

LowVoltageDetect

TimeBase

I/O LCDDriver TM1

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Pin Assignment

HT69F30A 48 LQFP-A

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37123456789101112

363534333231302928272625

PA6/TP

0_0PA

5/TP1_1

PA4/IN

T0PA

3/TP1_0

PA2/TC

K0/TC

K1

PA0/IN

T1PA

1/TP0_1

PB

1/OS

C2

PB

0/OS

C1

VD

DV

SS

PB

2/XT1

PA7/RESPD0/SEG0/INT1PD1/SEG1/TCK0PD2/SEG2/TCK1PD3/SEG3PD4/SEG4PD5/SEG5PD6/SEG6PD7/SEG7PE0/SEG8PE1/SEG9PE2/SEG10

PB3/XT2VLCDVMAX

V1PC0/V2PC1/C1PC2/C2

COM0COM1COM2

COM3/SEG24PF7/SEG23

PE

3/SE

G11

PE

4/SE

G12

PE

5/SE

G13

PE

6/SE

G14

PE

7/SE

G15

PF0/S

EG

16P

F1/SE

G17

PF2/S

EG

18P

F3/SE

G19

PF4/S

EG

20P

F5/SE

G21

PF6/S

EG

22

HT69F30A 48 LQFP- A

HT69F40A 48 LQFP-A

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37123456789101112

363534333231302928272625

PA6/TP

0_0PA

5/TP2_1

PA4/IN

T0PA

3/TP2_0

PA2/TC

K0/TC

K2

PA0/IN

T1/TCK

1PA

1/TP0_1

PB

1/OS

C2

PB

0/OS

C1

VD

DV

SS

PB

2/XT1

PA7/RESPD0/SEG0/INT1PD1/SEG1/TCK0PD2/SEG2/TCK2PD3/SEG3/TCK1PD4/SEG4/TP1APD5/SEG5/TP1B_0PD6/SEG6/TP1B_1PD7/SEG7/TP1B_2PE0/SEG8PE1/SEG9PE2/SEG10

PB3/XT2VLCDVMAX


COM0COM1COM2

COM3/SEG24PF7/SEG23

PE

3/SE

G11

PE

4/SE

G12

PE

5/SE

G13

PE

6/SE

G14

PE

7/SE

G15

PF0/S

EG

16P

F1/SE

G17

PF2/S

EG

18P

F3/SE

G19

PF4/S

EG

20P

F5/SE

G21

PF6/S

EG

22

HT69F40A 48 LQFP- A

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HT69F40A64 LQFP-A

12345678910111213

20 21 2223 2425 26 2728

6061626364

2930 3132

5253545556575859

141516

434445464748

36373839404142

333435

1718 19

495051PB3/XT2

VLCDVMAX


COM0COM1COM2

COM3/SEG36SEG35SEG34SEG33SEG32

PG7/SEG31

PA7/RESPD0/SEG0/INT1PD1/SEG1/TCK0PD2/SEG2/TCK2PD3/SEG3/TCK1PD4/SEG4/TP1APD5/SEG5/TP1B_0PD6/SEG6/TP1B_1PD7/SEG7/TP1B_2PE0/SEG8PE1/SEG9PE2/SEG10PE3/SEG11PE4/SEG12PE5/SEG13PE6/SEG14

PE

7/SE

G15

PF0/S

EG

16P

F1/SE

G17

PF2/S

EG

18P

F3/SE

G19

PF4/S

EG

20P

F5/SE

G21

PF6/S

EG

22P

F7/SE

G23

PG

0/SE

G24

PG

1/SE

G25

PG

2/SE

G26

PG

3/SE

G27

PG

4/SE

G28

PG

5/SE

G29

PG

6/SE

G30

PA6/TP

0_0PA

5/TP2_1

PA4/IN

T0PA

3/TP2_0

PA2/TC

K0/TC

K2

PA0/IN

T1/TCK

1PA

1/TP0_1

PB

1/OS

C2

PB

7/TP1B

_2P

B6/TP

1B_1

PB

5/TP1B

_0P

B4/TP

1A

PB

0/OS

C1

VD

DV

SS

PB

2/XT1

HT69F40A 64 LQFP- A

HT69F50A 48 LQFP-A

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37123456789101112

363534333231302928272625

PA6/TP

0_0PA

5/TP2_1

PA4/IN

T0PA

3/TP2_0

PA2/TC

K0/TC

K2

PA0/IN

T1/TCK

1PA

1/TP0_1

PB

1/OS

C2

PB

0/OS

C1

VD

DV

SS

PB

2/XT1

PA7/RESPD0/SEG0/INT1PD1/SEG1/TCK0PD2/SEG2/TCK2PD3/SEG3/TCK1PD4/SEG4/TP1APD5/SEG5/TP1B_0PD6/SEG6/TP1B_1PD7/SEG7/TP1B_2PE0/SEG8PE1/SEG9PE2/SEG10

PB3/XT2PLCDVMAX


COM0COM1COM2

COM3/SEG24PF7/SEG23

PE

3/SE

G11

PE

4/SE

G12

PE

5/SE

G13

PE

6/SE

G14

PE

7/SE

G15

PF0/S

EG

16P

F1/SE

G17

PF2/S

EG

18P

F3/SE

G19

PF4/S

EG

20P

F5/SE

G21

PF6/S

EG

22

HT69F50A 48 LQFP- A

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HT69F50A64 LQFP-A

12345678910111213

20 21 2223 2425 26 2728

6061626364

2930 3132

5253545556575859

141516

434445464748

36373839404142

333435

1718 19

495051PB3/XT2

PLCDVMAX


COM0COM1COM2

COM3/SEG36PH3/SEG35PH2/SEG34PH1/SEG33PH0/SEG32PG7/SEG31

PA7/RESPD0/SEG0/INT1PD1/SEG1/TCK0PD2/SEG2/TCK2PD3/SEG3/TCK1PD4/SEG4/TP1APD5/SEG5/TP1B_0PD6/SEG6/TP1B_1PD7/SEG7/TP1B_2PE0/SEG8PE1/SEG9PE2/SEG10PE3/SEG11PE4/SEG12PE5/SEG13PE6/SEG14

PE

7/SE

G15

PF0/S

EG

16P

F1/SE

G17

PF2/S

EG

18P

F3/SE

G19

PF4/S

EG

20P

F5/SE

G21

PF6/S

EG

22P

F7/SE

G23

PG

0/SE

G24

PG

1/SE

G25

PG

2/SE

G26

PG

3/SE

G27

PG

4/SE

G28

PG

5/SE

G29

PG

6/SE

G30

PA6/TP

0_0PA

5/TP2_1

PA4/IN

T0PA

3/TP2_0

PA2/TC

K0/TC

K2

PA0/IN

T1/TCK

1PA

1/TP0_1

PB

1/OS

C2

PB

7/TP1B

_2P

B6/TP

1B_1

PB

5/TP1B

_0P

B4/TP

1A

PB

0/OS

C1

VD

DV

SS

PB

2/XT1

HT69F50A 64 LQFP- A

47464544434241

HT69F50A80 LQFP-A

1234567891011121314151617181920

21 22 23 24 25 26 2728 29 30 31 32 33 3435 36 3738 39 40

80 79 78 77 76 75 7473 72 71 70 69 68 6766 65 6463 62 6160595857565554535251404948

PA6/TP

0_0PA

5/TP2_1

PA4/IN

T0PA

3/TP2_0

PA2/TC

K0/TC

K2

PA0/IN

T1/TCK

1PA

1/TP0_1

PB

1/OS

C2

PB

7/TP1B

_2P

B6/TP

1B_1

PB

5/TP1B

_0P

B4/TP

1A

PB

0/OS

C1

VD

D

PC

3P

C4

PC

5P

C6

VS

SP

B2/X

T1

PA7/RESPD0/SEG0/INT1PD1/SEG1/TCK0PD2/SEG2/TCK2PD3/SEG3/TCK1PD4/SEG4/TP1APD5/SEG5/TP1B_0PD6/SEG6/TP1B_1PD7/SEG7/TP1B_2PE0/SEG8PE1/SEG9PE2/SEG10PE3/SEG11PE4/SEG12PE5/SEG13PE6/SEG14PE7/SEG15PF0/SEG16PF1/SEG17PF2/SEG18

PB3/XT2VLCDVMAX


COM0COM1COM2

COM3/SEG48SEG47SEG46SEG45SEG44SEG43SEG42SEG41SEG40

PH7/SEG39

PF3/S

EG

19P

F4/SE

G20

PF5/S

EG

21P

F6/SE

G22

PF7/S

EG

23P

G0/S

EG

24P

G1/S

EG

25P

G2/S

EG

26P

G3/S

EG

27P

G4/S

EG

28P

G5/S

EG

29P

G6/S

EG

30P

G7/S

EG

31P

H0/S

EG

32P

H1/S

EG

33P

H2/S

EG

34P

H3/S

EG

35P

H4/S

EG

36P

H5/S

EG

37P

H6/S

EG

38

HT69F50A 80 LQFP- A

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47464544434241

HT69V50A80 LQFP-A

1234567891011121314151617181920

21 22 23 24 25 26 2728 29 30 31 32 33 3435 36 3738 39 40

80 79 78 77 76 75 7473 72 71 70 69 68 6766 65 6463 62 6160595857565554535251404948

PA6/TP

0_0PA

5/TP2_1

PA4/IN

T0PA

3/TP2_0

PA2/TC

K0/TC

K2/IC

PC

K/O

CD

SC

KPA

0/INT1/TC

K1/IC

PD

A/O

CD

SD

APA

1/TP0_1

PB

1/OS

C2

PB

7/TP1B

_2P

B6/TP

1B_1

PB

5/TP1B

_0P

B4/TP

1A

PB

0/OS

C1

VD

D

PC

3P

C4

PC

5P

C6

VS

SP

B2/X

T1

PA7/RESPD0/SEG0/INT1PD1/SEG1/TCK0PD2/SEG2/TCK2PD3/SEG3/TCK1PD4/SEG4/TP1APD5/SEG5/TP1B_0PD6/SEG6/TP1B_1PD7/SEG7/TP1B_2PE0/SEG8PE1/SEG9PE2/SEG10PE3/SEG11PE4/SEG12PE5/SEG13PE6/SEG14PE7/SEG15PF0/SEG16PF1/SEG17PF2/SEG18

PB3/XT2VLCDVMAX


COM0COM1COM2

COM3/SEG48SEG47SEG46SEG45SEG44SEG43SEG42SEG41SEG40

PH7/SEG39

PF3/S

EG

19P

F4/SE

G20

PF5/S

EG

21P

F6/SE

G22

PF7/S

EG

23P

G0/S

EG

24P

G1/S

EG

25P

G2/S

EG

26P

G3/S

EG

27P

G4/S

EG

28P

G5/S

EG

29P

G6/S

EG

30P

G7/S

EG

31P

H0/S

EG

32P

H1/S

EG

33P

H2/S

EG

34P

H3/S

EG

35P

H4/S

EG

36P

H5/S

EG

37P

H6/S

EG

38

HT69V50A 80 LQFP- A

Note:1.Ifthepin-sharedpinfunctionshavemultipleoutputssimultaneously,theoutputfunctionisdeterminedbythecorrespondingsoftwarecontrolbitsexceptthefunctionsdeterminedbytheconfigurationoptions.

2.TheHT69V50Adevice is theEVchipof theHT69Fx0Aseriesofdevices.Itsupports the“On-ChipDebug”functionfordebuggingduringdevelopmentusingtheOCDSDAandOCDSCKpinsconnectedtotheHoltekHT-IDEdevelopmenttools.

Rev. 1.20 12 ��to�e� 0�� 201� Rev. 1.20 13 ��to�e� 0�� 201�



Pin Description

HT69F30APad Name Function OPT I/T O/T Description

PA0/INT1/ICPDA/ �CDSDA

PA0PAWUPAPUPAFS

ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up and wake-up

INT1INTEGINTC0SFS

ST — Exte�nal Inte��upt 1

ICPDA — ST CM�S ICP Data/Add�ess�CDSDA — ST CM�S �CDS Data/Add�ess

PA1/TP0_1PA1

PAWUPAPUPAFS


TP0_1 PAFS ST CM�S TM0 I/� pin

PA2/TCK0/TCK1/ ICPCK/�CDSCK

PA2PAWUPAPUPAFS


TCK0 SFS ST — TM0 inputTCK1 SFS ST — TM1 inputICPCK — ST CM�S ICP Clo�k pin

�CDSCK — ST — �CDS Clo�k pin

PA3/TP1_0PA3

PAWUPAPUPAFS



PA4/INT0PA4 PAPU

PAWU ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up and wake-up

INT0 INTEGINTC0 ST — Exte�nal Inte��upt 0

PA�/TP1_1PA�

PAWUPAPUPAFS



PA6/TP0_0PA6

PAWUPAPUPAFS



PA7/RESPA7

PAWUPAPUPAFS


RES C� ST — Reset pin

PB0/�SC1PB0 PBPU ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up

�SC1 C� HXT — HXT/ERC os�illato� pin & EC mode input pin


�SC2 C� — HXT HXT os�illato� pin

PB2/XT1PB2 PBPU ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-upXT1 C� LXT — LXT os�illato� pin

PB3/XT2PB3 PBPU ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-upXT2 C� — LXT LXT os�illato� pin

Rev. 1.20 14 ��to�e� 0�� 201� Rev. 1.20 1� ��to�e� 0�� 201�



Pad Name Function OPT I/T O/T Description

PC0/V2PC0 PCPU

PCFS ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up

V2 PCFS — A� LCD voltage pump

PC1/C1PC1 PCPU


C1 PCFS — A� LCD voltage pump

PC2/C2PC2 PCPU



PD0/SEG0/INT1

PD0 PDPUPDFS ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up

SEG0 PDFS — A� LCD segment output

INT1INTEGINTC0SFS


PD1/SEG1/TCK0PD1 PDPU

PDFS ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up

SEG1 PDFS — A� LCD segment outputTCK0 SFS ST — TM0 input




PD3/SEG3PD3 PDPU



PD4/SEG4PD4 PDPU



PD�/SEG�PD� PDPU


SEG� PDFS — A� LCD segment output

PD6/SEG6PD6 PDPU



PD7/SEG7PD7 PDPU



PE0/SEG�PE0 PEPU

PEFS ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up

SEG� PEFS — A� LCD segment output

PE1/SEG9PE1 PEPU


SEG9 PEFS — A� LCD segment output

PE2/SEG10PE2 PEPU



PE3/SEG11PE3 PEPU



Rev. 1.20 14 ��to�e� 0�� 201� Rev. 1.20 1� ��to�e� 0�� 201�




PE4/SEG12PE4 PEPU



PE�/SEG13PE� PEPU



PE6/SEG14PE6 PEPU



PE7/SEG1�PE7 PEPU


SEG1� PEFS — A� LCD segment output

PF0/SEG16PF0 PFPU

PFFS ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up

SEG16 PFFS — A� LCD segment output

PF1/SEG17PF1 PFPU



PF2/SEG1�PF2 PFPU


SEG1� PFFS — A� LCD segment output

PF3/SEG19PF3 PFPU



PF4/SEG20PF4 PFPU



PF�/SEG21PF� PFPU



PF6/SEG22PF6 PFPU



PF7/SEG23PF7 PFPU


SEG23 PFFS — A� LCD segment outputC�M0~C�M2 C�Mn — — A� LCD �ommon outputs

C�M3/SEG24C�M3 — — A� LCD �ommon outputSEG24 LCDC — A� LCD segment output

V1 V1 — — A� LCD voltage pumpVLCD VLCD — PWR — LCD powe� supplyVMAX VMAX — PWR — IC maximum voltage� �onne�ted to VDD� VLCD o� V1VDD VDD — PWR — Positive Powe� supplyVSS VSS — PWR — Negative Powe� supply. G�ound

Note:I/T:Inputtype; O/T:OutputtypeOPT:Optionalbyconfigurationoption(CO)orregisteroptionPWR:Power; CO:ConfigurationoptionST:SchmittTriggerinput; AO:AnalogoutputCMOS:CMOSoutput; NMOS:NMOSoutputHXT:HighfrequencycrystaloscillatorLXT:Lowfrequencycrystaloscillator

Rev. 1.20 16 ��to�e� 0�� 201� Rev. 1.20 17 ��to�e� 0�� 201�




PA0/INT1/TCK1/ICPDA/�CDSDA

PA0PAWUPAPUPAFS


INT1INTEGINTC0SFS


TCK1 SFS ST — TM1 inputICPDA — ST CM�S ICP Data/Add�ess

�CDSDA — ST CM�S �CDS Data/Add�ess

PA1/TP0_1PA1

PAWUPAPUPAFS



PA2/TCK0/TCK2/ ICPCK/�CDSCK

PA2PAWUPAPUPAFS




PA3/TP2_0PA3

PAWUPAPUPAFS



PA4/INT0PA4 PAPU



PA�/TP2_1PA�

PAWUPAPUPAFS



PA6/TP0_0PA6

PAWUPAPUPAFS



PA7/RESPA7

PAWUPAPUPAFS









PB4/TP1APB1 PBPU

PBFS ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up

TP1A PBFS ST CM�S TM1 I/� pin

Rev. 1.20 16 ��to�e� 0�� 201� Rev. 1.20 17 ��to�e� 0�� 201�




PB�/TP1B_0PB� PBPU


TP1B_0 PBFS ST CM�S TM1 I/� pin

PB6/TP1B_1PB6 PBPU



PB7/TP1B_2PB7 PBPU



PC0/V2PC0 PCPU



PC1/C1PC1 PCPU



PC2/C2PC2 PCPU



PD0/SEG0/INT1

PD0 PDPUPDFS ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up.


INT1INTEGINTC0SFS











PD4/SEG4/TP1A


SEG4 PDFSSFS — A� LCD segment output

TP1A PDFSSFS ST CM�S TM1 I/� pin

PD�/SEG�/TP1B_0

PD� PDPUPDFS ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up

SEG� PDFSSFS — A� LCD segment output

TP1B_0 PDFSSFS ST CM�S TM1 I/� pin

Rev. 1.20 1� ��to�e� 0�� 201� Rev. 1.20 19 ��to�e� 0�� 201�




PD6/SEG6/TP1B_1




PD7/SEG7/TP1B_2




PE0/SEG�PE0 PEPU



PE1/SEG9PE1 PEPU



PE2/SEG10PE2 PEPU



PE3/SEG11PE3 PEPU



PE4/SEG12PE4 PEPU






PE6/SEG14PE6 PEPU



PE7/SEG1�PE7 PEPU



PF0/SEG16PF0 PFPU



PF1/SEG17PF1 PFPU



PF2/SEG1�PF2 PFPU



PF3/SEG19PF3 PFPU



PF4/SEG20PF4 PFPU



Rev. 1.20 1� ��to�e� 0�� 201� Rev. 1.20 19 ��to�e� 0�� 201�







PF6/SEG22PF6 PFPU



PF7/SEG23PF7 PFPU



PG0/SEG24PG0 PGPU

PGFS ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up

SEG24 PGFS — A� LCD segment output

PG1/SEG2�PG1 PGPU


SEG2� PGFS — A� LCD segment output

PG2/SEG26PG2 PGPU



PG3/SEG27PG3 PGPU



PG4/SEG2�PG4 PGPU



PG�/SEG29PG� PGPU



PG6/SEG30PG6 PGPU



PG7/SEG31PG7 PGPU


SEG31 PGFS — A� LCD segment outputSEG32~SEG3� SEGn — — A� LCD segment outputsC�M0~C�M2 C�Mn — — A� LCD �ommon outputs

C�M3/SEG36C�M3 — — A� LCD �ommon outputSEG36 LCDC — A� LCD segment output



Rev. 1.20 20 ��to�e� 0�� 201� Rev. 1.20 21 ��to�e� 0�� 201�




PA0/INT1/TCK1/ICPDA/�CDSDA

PA0PAWUPAPUPAFS


INT1INTEGINTC0SFS


TCK1 SFS ST — TM1 inputICPDA — ST CM�S ICP Data/Add�ess

�CDSDA — ST CM�S �CDS Data/Add�ess

PA1/TP0_1PA1

PAWUPAPUPAFS



PA2/TCK0/TCK2/ICPCK/�CDSCK

PA2PAWUPAPUPAFS




PA3/TP2_0PA3

PAWUPAPUPAFS



PA4/INT0PA4 PAPU



PA�/TP2_1PA�

PAWUPAPUPAFS



PA6/TP0_0PA6

PAWUPAPUPAFS



PA7/RESPA7

PAWUPAPUPAFS









PB4/TP1APB1 PBPU


TP1A PBFS ST CM�S TM1 I/� pin

Rev. 1.20 20 ��to�e� 0�� 201� Rev. 1.20 21 ��to�e� 0�� 201�




PB�/TP1B_0PB� PBPU



PB6/TP1B_1PB6 PBPU



PB7/TP1B_2PB7 PBPU



PC0/V2PC0 PCPU



PC1/C1PC1 PCPU



PC2/C2PC2 PCPU


C2 PCFS — A� LCD voltage pumpPC3~PC6 PCn PCPU ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up

PD0/SEG0/INT1



INT1INTEGINTC0SFS











PD4/SEG4/TP1A



TP1A PDFSSFS ST CM�S TM1 I/� pin

PD�/SEG�/TP1B_0

PD� PDPUPDFS ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up

SEG� PDFSSFS — A� LCD segment output


Rev. 1.20 22 ��to�e� 0�� 201� Rev. 1.20 23 ��to�e� 0�� 201�




PD6/SEG6/TP1B_1




PD7/SEG7/TP1B_2




PE0/SEG�PE0 PEPU



PE1/SEG9PE1 PEPU



PE2/SEG10PE2 PEPU



PE3/SEG11PE3 PEPU



PE4/SEG12PE4 PEPU






PE6/SEG14PE6 PEPU



PE7/SEG1�PE7 PEPU



PF0/SEG16PF0 PFPU



PF1/SEG17PF1 PFPU



PF2/SEG1�PF2 PFPU



PF3/SEG19PF3 PFPU



PF4/SEG20PF4 PFPU



Rev. 1.20 22 ��to�e� 0�� 201� Rev. 1.20 23 ��to�e� 0�� 201�







PF6/SEG22PF6 PFPU



PF7/SEG23PF7 PFPU



PG0/SEG24PG0 PGPU



PG1/SEG2�PG1 PGPU



PG2/SEG26PG2 PGPU



PG3/SEG27PG3 PGPU



PG4/SEG2�PG4 PGPU



PG�/SEG29PG� PGPU



PG6/SEG30PG6 PGPU



PG7/SEG31PG7 PGPU



PH0/SEG32PH0 PHPU

PHFS ST CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up

SEG32 PHFS — A� LCD segment output

PH1/SEG33PH1 PHPU



PH2/SEG34PH2 PHPU



PH3/SEG3�PH3 PHPU


SEG3� PHFS — A� LCD segment output

PH4/SEG36PH4 PHPU



PH�/SEG37PH� PHPU



Rev. 1.20 24 ��to�e� 0�� 201� Rev. 1.20 2� ��to�e� 0�� 201�




PH6/SEG3�PH6 PHPU


SEG3� PHFS — A� LCD segment output

PH7/SEG39PH7 PHPU


SEG39 PHFS — A� LCD segment outputSEG40~SEG47 SEGn — — A� LCD segment outputsC�M0~C�M2 C�Mn — — A� LCD �ommon outputs

C�M3/SEG4�C�M3 — — A� LCD �ommon outputSEG4� LCDC — A� LCD segment output



Absolute Maximum RatingsSupplyVoltage................................................................................................VSS-0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS-0.3VtoVDD+0.3VIOLTotal ....................................................................................................80mATotalPowerDissipation........................................................................................................ 500mWStorageTemperature.................................................................................................. -50°Cto125°COperatingTemperature................................................................................................ -40°Cto85°CIOHTotal ..................................................................................................-80mA

Note:Theseare stress ratingsonly.Stressesexceeding the range specifiedunder“AbsoluteMaximumRatings”maycausesubstantialdamage to thedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthose listed in thespecificationisnot impliedandprolongedexposuretoextremeconditionsmayaffectdevicereliability.

Rev. 1.20 24 ��to�e� 0�� 201� Rev. 1.20 2� ��to�e� 0�� 201�



D.C. CharacteristicsTa=2�°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD1 �pe�ating Voltage (HXT) —

fSYS=4MHz 2.2 — �.� VfSYS=�MHz 2.2 — �.� VfSYS=12MHz 2.7 — �.� VfSYS=16MHz 4.� — �.� V

VDD2 �pe�ating Voltage (ERC) —

fSYS=4MHz 2.2 — �.� VfSYS=�MHz 2.4 — �.� VfSYS=12MHz 2.7 — �.� VfSYS=16MHz 4.� — �.� VfSYS=20MHz 4.� — �.� V

VDD3 �pe�ating Voltage (HIRC) —fSYS=4MHz 2.2 — �.� VfSYS=�MHz 2.2 — �.� VfSYS=12MHz 2.7 — �.� V

IDD1

�pe�ating Cu��ent (HXT� fSYS=fH� fS=fSUB=fRTC o� fLIRC)

3VNo load� fH=4��kHz� WDT ena�le

— 100 1�0 μA�V — 2�0 4�0 μA3V

No load� fH=1MHz� WDT ena�le— 2�0 400 μA

�V — �00 1000 μA3V


�V — 1000 1�00 μA3V

No load� fH=�MHz� WDT ena�le— 0.� 1.� mA

�V — 1.� 3.0 mA3V

No load� fH=12MHz� WDT ena�le— 1.� 2.� mA

�V — 3.0 �.0 mA�V No load� fH=16MHz� WDT ena�le — 4.0 6.0 mA

IDD2

�pe�ating Cu��ent (ERC� fSYS=fH� fS=fSUB=fRTC o� fLIRC)

3VNo load� fH=4��kHz� WDT ena�le

— 66 110 μA�V — 200 300 μA3V


�V — �00 1000 μA3V


�V — 1000 1�00 μA3V


�V — 1.� 3.0 mA3V


�V — 3.0 �.0 mA�V No load� fH=16MHz� WDT ena�le — 4.0 6.0 mA

IDD3

�pe�ating Cu��ent (HIRC �SC� fSYS=fH� fS=fSUB=fRTC o� fLIRC)

3VNo load� fH=4MHz� WDT ena�le

— 420 630 μA�V — 700 1000 μA3V


�V — 1.� 3.0 mA3V


�V — 3.0 �.0 mA

IDD4

�pe�ating Cu��ent (EC� fSYS=fH� fS=fSUB=fRTC o� fLIRC)

3VNo load� fH=4MHz� WDT ena�le

— 330 �00 μA

�V — ��0 �20 μA

Rev. 1.20 26 ��to�e� 0�� 201� Rev. 1.20 27 ��to�e� 0�� 201�





IDD�

�pe�ating Cu��ent (HXT� fSYS=fL� fS=fSUB=fRTC o� fLIRC)

3VNo load� fH=�MHz� fL=fH/2� WDT ena�le

— �00 7�0 μA�V — �00 1200 μA3V

No load� fH=�MHz� fL=fH/4� WDT ena�le— 420 630 μA

�V — 700 1000 μA3V

No load� fH=�MHz� fL=fH/�� WDT ena�le— 400 600 μA

�V — 600 �00 μA3V

No load� fH=�MHz� fL=fH/16� WDT ena�le— 360 �40 μA

�V — �60 700 μA3V

No load� fH=�MHz� fL=fH/32� WDT ena�le— 320 4�0 μA

�V — �20 6�0 μA3V

No load� fH=�MHz� fL=fH/64� WDT ena�le— 2�0 420 μA

�V — 440 600 μA

IDD6


3V No load� fH=4MHz� fL=fH/2� WDT ena�le — 270 400 μA�V No load� fH=4MHz� fL=fH/2� WDT ena�le — �60 �40 μA3V No load� fH=4MHz� fL=fH/4� WDT ena�le — 1�0 270 μA�V No load� fH=4MHz� fL=fH/4� WDT ena�le — 400 600 μA

IDD7


3V No load� fH=12MHz� fL=fH/2� WDT ena�le — 0.9 1.� mA�V No load� fH=12MHz� fL=fH/2� WDT ena�le — 1.� 2.7 mA3V No load� fH=12MHz� fL=fH/4� WDT ena�le — 0.6 1.0 mA�V No load� fH=12MHz� fL=fH/4� WDT ena�le — 0.9 1.4 mA

IDD�

�pe�ating Cu��ent (LXT� fSYS=fL=fRTC� fS=fSUB=fRTC)(HT69F30A� HT69F40A)

3VNo load� WDT ena�le� Q�SC=0

— 10 20 μA�V — 20 3� μA3V

No load� WDT ena�le� Q�SC=1— 10 20 μA

�V — 20 3� μA

IDD�a

�pe�ating Cu��ent (LXT� fSYS=fL=fRTC� fS=fSUB=fRTC)(HT69F�0A)


— 10 20 μA�V — 30 �0 μA3V

No load� WDT ena�le� Q�SC=1— 10 20 μA

�V — 30 �0 μA

IDD9

�pe�ating Cu��ent (LIRC� fSYS=fL=fLIRC� fS=fSUB=fLIRC)(HT69F30A� HT69F40A)

3VNo load� WDT ena�le

— 10 20 μA

�V — 20 3� μA

IDD9a

�pe�ating Cu��ent (LIRC� fSYS=fL=fLIRC� fS=fSUB=fLIRC) (HT69F�0A)

3VNo load� WDT ena�le

— 10 20 μA

�V — 30 �0 μA

IDD10

�pe�ating Cu��ent (LXT o� LIRC� fSYS=fL=fSUB)(HT69F30A� HT69F40A)


— 10 20 μA

�V — 20 3� μA

IDD10a

�pe�ating Cu��ent (LXT o� LIRC� fSYS=fL=fSUB)(HT69F�0A)


— 10 20 μA

�V — 30 �0 μA

ISTB1

Stand�y Cu��ent (Idle1) (HXT� fSYS=fH� fS=fSUB=fRTC o� fLIRC)

3V No load� system HALT� WDT ena�le� fSYS=�MHz� FSYS�N=1

— 0.3 0.� mA

�V — 0.� 0.� mA

ISTB2

Stand�y Cu��ent (Idle0) (HXT� fSYS=off� fS=fSUB=fRTC o� fLIRC)

3V No load� system HALT� WDT ena�le� fSYS=�MHz� LXTLP=1

— 1.� 3.0 μA

�V — 2.� �.0 μA

ISTB3Stand�y Cu��ent (Idle0) (HIRC� fSYS=off� fS=fSUB=fLIRC)

3V No load� system HALT� WDT ena�le� fSYS=�MHz

— 1.� 3.0 μA�V — 2.� �.0 μA

Rev. 1.20 26 ��to�e� 0�� 201� Rev. 1.20 27 ��to�e� 0�� 201�





ISTB4Stand�y Cu��ent (Idle0.) (HIRC� fSYS=off� fS=fSUB=fLIRC)

3V No load� system HALT� WDT ena�le� fSYS=3276�Hz� LXTLP=1

— 1.� 3.0 μA

�V — 2.� �.0 μA

ISTB�Stand�y Cu��ent (Idle0) (LXT� fSYS=off)

3V No load� system HALT� WDT ena�le� fSYS=3276�Hz

— 1.� 3.0 μA�V — 2.� �.0 μA

ISTB6Stand�y Cu��ent (Idle0) (fSYS=fL=fRTC� fS=fSUB=fRTC)


— 1.9 4.0 μA�V — 3.3 7.0 μA

ISTB7Stand�y Cu��ent (Idle) (LIRC� fSYS=off� fS=fSUB=fLIRC)

3V No load� system HALT� WDT ena�le� fSYS=32kHz

— 1.� 3.0 μA�V — 2.� �.0 μA

ISTB�

Stand�y Cu��ent (Sleep0) (HXT� fSYS=off� fS=fSUB=fRTC o� fLIRC)

3V No load� system HALT� WDT disa�le� fSYS=12MHz� LXTLP=1

— 0.1 1 μA

�V — 0.3 2 μA

ISTB9Stand�y Cu��ent (Sleep1) (HXT� fSYS=off� fS=fSUB=fRTC)

3V No load� system HALT� WDT ena�le� fSYS=12MHz

— 1.� 3.0 μA�V — 2.� �.0 μA

ISTB10Stand�y Cu��ent (Sleep1) (HXT� fSYS=off� fS=fSUB=fLIRC)

3V No load� system HALT� WDT ena�le� fSYS=12MHz

— 1.� 3.0 μA�V — 2.� �.0 μA

ISTB11Stand�y Cu��ent (Sleep0) (LXT� fSYS=off� fS=fSUB=fRTC)

3V No load� system HALT� WDT disa�le� fSYS=3276�Hz

— 0.1 1 μA�V — 0.3 2 μA

ISTB12Stand�y Cu��ent (Sleep1) (LXT� fSYS=off� fS=fSUB=fRTC)


— 1.� 3.0 μA�V — 2.� �.0 μA

VIL1

Input Low Voltage fo� PA� PB� PC� PD� PE� PF� TCKn and INTn

�—

0V — 1.�V V

— 0V — 0.2VDD V

VIH1

Input High Voltage fo� PA� PB� PC� PD� PE� PF� TCKn and INTn

�—

3.�V — �V V

— 0.�VDD — VDD V

VIL2 Input Low Voltage (RES) — — 0 — 0.4VDD VVIH2 Input High Voltage (RES) — — 0.9VDD — VDD V

I�L I/� Po�t Sink Cu��ent3V V�L=0.1VDD 4 � — mA�V V�L=0.1VDD 10 20 — mA

I�H I/� Po�t Sou��e Cu��ent3V V�H=0.9VDD -2 -4 — mA�V V�H=0.9VDD -� -10 — mA

RPHPull-high Resistan�e of I/� Po�ts

3V — 20 60 100 kΩ�V — 10 30 �0 kΩ

Rev. 1.20 2� ��to�e� 0�� 201� Rev. 1.20 29 ��to�e� 0�� 201�



A.C. CharacteristicsTa=2�°C


Min. Typ. Max. UnitVDD Condition

fCPU �pe�ating Clo�k —

2.2~�.�V DC — 4 MHz2.4~�.�V DC — � MHz2.7~�.�V DC — 12 MHz4.�~�.�V DC — 16 MHz

fSYS System �lo�k (HXT)

2.2V~�.�V

—

0.4 — 4 MHz2.2V~�.�V 0.4 — � MHz2.7V~�.�V 0.4 — 12 MHz4.�V~�.�V 0.4 — 16 MHz

fHIRC System �lo�k (HIRC)

3V/�V Ta=2�°C -2% 4 +2% MHz3V/�V Ta=2�°C -2% � +2% MHz

�V Ta=2�°C -2% 12 +2% MHz2.2V~3.6V Ta=-40°C~��°C -�% 4 +�% MHz3.0V~�.�V Ta=-40°C~��°C -�% 4 +�% MHz2.2V~3.6V Ta=-40°C~��°C -�% � +�% MHz3.0V~�.�V Ta=-40°C~��°C -�% � +�% MHz3.0V~�.�V Ta=-40°C~��°C -�% 12 +�% MHz

fERC System �lo�k (ERC)

�V Ta=2�°CExte�nal RERC=1�0kΩ -2% 4 +2% MHz

�V Ta=0°C~70°CExte�nal RERC=1�0kΩ -�% 4 +�% MHz

�V Ta=-40°C~��°CExte�nal RERC=1�0kΩ -7% 4 +7% MHz

3.0V~�.�V Ta=-40°C~��°CExte�nal RERC=1�0kΩ -9% 4 +9% MHz

2.2V~�.�V Ta=-40°C~��°CExte�nal RERC=1�0kΩ -12% 4 +12% MHz

fLXT System Clo�k (LXT) — — — 3276� — Hz

fLIRC System Clo�k (LIRC)�V Ta=2�°C -10% 32 +10% kHz

2.2V~�.�V Ta=-40°C~��°C -�0% 32 +60% kHz

tTIMERTCKn and time� �aptu�e Input Pulse Width — — 0.3 — — μs

tRES Exte�nal Reset Low Pulse Width — — 10 — — μstINT Inte��upt Pulse Width — — 10 — — μs

tSST

System Sta�t-up Time� Pe�iod(Wake-up f�om HALT� fSYS off at HALT state, Slow Mode→Normal Mode, Normal Mode→Slow Mode)

—

fSYS=HXT o� LXT(Slow Mode→No�mal Mode(HXT)� No�mal Mode→Slow Mode(LXT))

1024 — — tSYS

fSYS=HXT o� LXT(Wake-up f�om HALT� fSYS off at HALT state)

1024 ─ ─ tSYS

— fSYS=ERC o� HIRC 16 — — tSYS

— fSYS=LIRC o� EC 2 — — tSYS

System Sta�t-up Time� Pe�iod(Wake-up f�om HALT� fSYS on at HALT state)

— — 2 — — tSYS

Rev. 1.20 2� ��to�e� 0�� 201� Rev. 1.20 29 ��to�e� 0�� 201�





tRSTD

System Reset Delay Time(Powe� �n Reset� LVR �eset� LVR S/W �eset (LVRC)� WDT S/W �eset (WDTC))

— — 2� �0 100 ms

System Reset Delay Time(RES �eset� WDT no�mal �eset) — — �.3 16.7 33.3 ms

tBGS VBG tu�n on sta�le time — — 10 — — mstEERD EEPR�M Read Time — — 1 2 4 tSYS

tEEWR EEPR�M W�ite Timet — — 1 2 4 ms

Note:tSYS=1/fSYS

LVD & LVR Electrical CharacteristicsTa=2�°C



VLVR1

Low Voltage Reset Voltage —

LVR Ena�le� 2.1V option

-�%

2.1

+�% VVLVR2 LVR Ena�le� 2.��V option 2.��VLVR3 LVR Ena�le� 3.1�V option 3.1�VLVR4 LVR Ena�le� 3.�V option 3.�VLVD1

Low Voltage Dete�to� Voltage —

LVDEN=1� VLVD=2.0V

-�%

2.0

+�%

VVLVD2 LVDEN=1� VLVD=2.2V 2.2 VVLVD3 LVDEN=1� VLVD=2.4V 2.4 VVLVD4 LVDEN=1� VLVD=2.7V 2.7 VVLVD� LVDEN=1� VLVD=3.0V 3.0 VVLVD6 LVDEN=1� VLVD=3.3V 3.3 VVLVD7 LVDEN=1� VLVD=3.6V 3.6 VVLVD� LVDEN=1� VLVD=4.0V 4.0 V

VBGBandgap �efe�en�e with �uffe� voltage — — -3% 1.2� +3% V

IBG

Additional Powe� Consumption if �andgap �efe�en�e with �uffe� is used

— — — 200 300 μA

ILVRAdditional Powe� Consumption if LVR is used

3VLVR disable→LVR enable

— 10 20 μA�V — 1� 30 μA

ILVDAdditional Powe� Consumption if LVD is used

3V LVD disable→LVD enable(LVR disa�le)

— 10 20 μA�V — 1� 30 μA3V LVD disable→LVD enable

(LVR ena�le)— 1 2 μA

�V — 2 4 μAtLVR Low Voltage Width to Reset — — 120 240 4�0 μstLVD Low Voltage Width to Inte��upt — — 20 4� 90 tLIRC

tLVDS LVD� sta�le time— For LVR enable, LVD off→on 1� — — μs— For LVR disable, LVD off→on 1� — — μs

tSRESET Softwa�e Reset Width to Reset — — 20 4� 90 tLIRC

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LCD D.C. CharacteristicsTa=2�°C

Symbol ParameterTest Condition


ISTB1

Stand�y Cu��ent (Sleep)(fSYS� fWDT off� fS=fSUB=3276� o� 32K RC �SC)

3V No load� system HALT� LCD on�WDT off� C type� VLCD=VDD� 1/2 Bias�

— 2.0 4.0 μA

�V — 3.0 �.0 μA

ISTB2

Stand�y Cu��ent (Sleep)(fSYS� fWDT off� fS=fSUB=3276� o� 32K RC �SC)

3V No load� system HALT� LCD on�WDT off� C type� VLCD=VDD� 1/3 Bias�

— 2.0 4.0 μA

�V — 3.0 �.0 μA

ISTB3

Stand�y Cu��ent (Idle)(fSYS� fWDT off� fS=fSUB=3276� o� 32K RC �SC)

3V No load� system HALT� LCD on�WDT off� R type� VLCD=VDD� 1/2 �ias (IBIAS=7.5μA)

— 13.� 20.0 μA

�V — 22.� 40.0 μA

ISTB4


3V No load� system HALT� LCD on�WDT off� R type� VLCD=VDD� 1/2 �ias (IBIAS=15μA)

— 21 40 μA

�V — 3� 60 μA

ISTB�



— �1 �0 μA

�V — �� 160 μA

ISTB6



— 96 160 μA

�V — 160 320 μA

ISTB7


3V No load� system HALT� LCD on�WDT off� R type� VLCD=VDD� 1/3 �ias (IBIAS=7.5μA)

— 11 20 μA

�V — 1�.3 40 μA

ISTB�



— 16 2� μA

�V — 26.6 �0 μA

ISTB9



— 36 �0 μA

�V — 60 100 μA

ISTB10



— 66 100 μA

�V — 110 200 μA

I�L2LCD Common and Segment Sink Cu��ent

3VV�L=0.1VLCD

210 420 — μA�V 3�0 700 — μA

I�H2LCD Common and Segment Sou��e Cu��ent

3VV�H=0.9VLCD

-�0 -160 — μA�V -1�0 -360 — μA

Rev. 1.20 30 ��to�e� 0�� 201� Rev. 1.20 31 ��to�e� 0�� 201�



Power-on Reset CharacteristicsTa=2�°C



VP�R VDD Sta�t Voltage to Ensu�e Powe�-on Reset — — — — 100 mVRRVDD VDD Raising Rate to Ensu�e Powe�-on Reset — — 0.03� — — V/ms

tP�RMinimum Time fo� VDD Stays at VP�R to Ensu�e Powe�-on Reset — — 1 — — ms

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System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.TherangeofdevicestakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningscheme is implemented insuchaway that instruction fetchingand instructionexecutionareoverlapped,hence instructionsareeffectivelyexecuted inonecycle,with theexceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitectural featuresensure thataminimumofexternalcomponents is required toprovideafunctional I/Ocontrolsystemwithmaximumreliabilityandflexibility.Thismakes thedevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derivedfromeitheraHXT,LXT,HIRC,LIRC,ECorERCoscillator issubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsareeffectivelyexecutedinoneinstructioncycle.TheexceptiontothisareinstructionswherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

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System Clocking and Pipelining

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Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionis executed except for instructions, such as “JMP” or “CALL” that demand a jump to anon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecutinginstructionsrequiringjumpstonon-consecutiveaddressessuchasajumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet, thenext instruction,whichhasalreadybeenfetchedduringthepresent instructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

DeviceProgram Counter

Porgram Counter High Byte Porgram Counter Low ByteHT69F30A PC10~PC�

PCL7~PCL0HT69F40A PC11~PC�HT69F�0A PC12~PC�

Program Counter

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythislowbyteisavailableformanipulation,thejumpsarelimitedtothepresentpageofmemory,thatis256locations.Whensuchprogramjumpsareexecuteditshouldalsobenotedthatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.

Rev. 1.20 32 ��to�e� 0�� 201� Rev. 1.20 33 ��to�e� 0�� 201�



StackThisisaspecialpartofthememorywhichisusedtosavethecontentsoftheProgramCounteronly.Thestackhasmultiplelevelsdependinguponthedeviceandisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.

Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

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Device Stack LevelsHT69F30A 4HT69F40A �HT69F�0A �

Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrementINCA,INC,DECA,DEC

• Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI

Rev. 1.20 34 ��to�e� 0�� 201� Rev. 1.20 3� ��to�e� 0�� 201�



Flash Program MemoryTheProgramMemoryis the locationwhere theusercodeorprogramisstored.For thisdeviceseriestheProgramMemoryisFlashtype,whichmeansitcanbeprogrammedandre-programmeda largenumberof times,allowing theuser theconvenienceofcodemodificationon thesamedevice.Byusingtheappropriateprogrammingtools,theseFlashdevicesofferuserstheflexibilitytoconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityofupto8k×16bits.TheProgramMemoryisaddressedbytheProgramCounterandalsocontainsdata,tableinformationandinterruptentriesinformation.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyseparatetablepointerregisters.

Device CapacityHT69F30A 2K×16HT69F40A 4K×16HT69F�0A �K×16

0000H Reset

Inte��upt Ve�to�

0004H

001CH

07FFH 16 �its

HT69F30A

Reset


16 �its

HT69F40A

0FFFH

Reset


16 �its

HT69F�0A

1FFFH

Program Memory Structure

Rev. 1.20 34 ��to�e� 0�� 201� Rev. 1.20 3� ��to�e� 0�� 201�



Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000His reserved foruseby thedevice reset forprograminitialisation.Afteradevice reset isinitiated,theprogramwilljumptothislocationandbeginexecution.

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

After settingup the tablepointer, the tabledatacanbe retrieved from theProgramMemoryusing the“TABRDC[m]”or“TABRDL[m]” instructions, respectively.Whenthe instruction isexecuted, the lowerorder tablebyte fromtheProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecifiedintheinstruction.ThehigherordertabledatabytefromtheProgramMemorywillbetransferredtotheTBLHspecialregister.Anyunusedbitsinthistransferredhigherorderbytewillbereadas0.

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

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Table Program ExampleTheaccompanyingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthedevice.ThisexampleusesrawtabledatalocatedinthelastpagewhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis“700H”whichreferstothestartaddressofthelastpagewithinthe2KProgramMemoryoftheHT69F30Adevice.Thetablepointerissetupheretohaveaninitialvalueof“06H”.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress“706H”or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthepresentpageifthe“TABRDC[m]”instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRDC[m]”instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Rev. 1.20 36 ��to�e� 0�� 201� Rev. 1.20 37 ��to�e� 0�� 201�



Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2 : :mov a,06h ; initialise table pointer - note that this address ; is referenced to the last page or present pagemov tblp, a : :tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempreg1 ; data at program memory address “706H” transferred to ; to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at program memory address “705H” transferred to ; tempreg2 and TBLH ; in this example the data “1AH” is transferred to ; tempreg1 and data “0FH” to register tempreg2 ; the value “00H” will be transferred to the high byte ; register TBLH : :org 700h ; sets initial address of last pagedc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :

In Circuit Programming – ICPTheprovisionofFlashtypeProgramMemoryprovides theuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.

Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,and thenprogrammingorupgradingtheprogramatalaterstage.Thisenablesproductmanufacturerstoeasilykeeptheirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

Holtek Writer Pins MCU Programming Pins Pin DescriptionICPDA PA0 P�og�amming Se�ial DataICPCK PA2 P�og�amming Clo�kVDD VDD Powe� SupplyVSS VSS G�ound

TheProgramMemorycanbeprogrammedserially in-circuitusing this4-wire interface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditional linefor theclock.Twoadditionallinesarerequiredforthepowersupplyandonelineforthereset.Thetechnicaldetailsregardingthein-circuitprogrammingofthedevicesarebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

Rev. 1.20 36 ��to�e� 0�� 201� Rev. 1.20 37 ��to�e� 0�� 201�



Duringtheprogrammingprocess,takingcontroloftheICPDAandICPCKpinsfordataandclockprogrammingpurposes.Theusermusttheretakecaretoensurethatnootheroutputsareconnectedtothesetwopins.

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Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1korthecapacitanceof*mustbelessthan1nF.

On-Chip Debug Support – OCDSThereisanEVchipnamedHT69V0AwhichisusedtoemulatetheHT69Fx0Aseriesofdevices.TheHT69V50Adevicealsoprovides the“On-ChipDebug”function todebug theHT69Fx0Aseriesofdevicesduringdevelopmentprocess.Thedevices,HT69Fx0AandHT69V50A,arealmostfunctionalcompatibleexcept the“On-ChipDebug”functionandpackage types.UserscanusetheHT69V50Adevice toemulate theHT69Fx0Aseriesofdevicesbehaviorsbyconnecting theOCDSDAandOCDSCKpinstotheHoltekHT-IDEdevelopmenttools.TheOCDSDApinistheOCDSData/Addressinput/outputpinwhiletheOCDSCKpinistheOCDSclockinputpin.Whenusersuse theHT69V50AEVchipfordebugging, thecorrespondingpin functionssharedwiththeOCDSDAandOCDSCKpins in theHT69Fx0Aseriesofdeviceswillhavenoeffect in theHT69V50AEVchip.However,thetwoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedas theFlashMemoryprogrammingpins for ICP.FormoredetailedOCDSinformation, refer to thecorrespondingdocumentnamed“Holteke-Linkfor8-bitMCUOCDSUser’sGuide”.

Holtek e-Link Pins EV Chip Pins Pin Description�CDSDA �CDSDA �n-Chip De�ug Suppo�t Data/Add�ess input/output�CDSCK �CDSCK �n-Chip De�ug Suppo�t Clo�k input

VDD VDD Powe� SupplyGND VSS G�ound

Rev. 1.20 3� ��to�e� 0�� 201� Rev. 1.20 39 ��to�e� 0�� 201�



Data MemoryTheDataMemoryisan8-bitwideRAMinternalmemoryandis the locationwhere temporaryinformationisstored.

Dividedintothreesections,thefirstoftheseisanareaofRAMwherespecialfunctionregistersarelocated.Theseregistershavefixedlocationsandarenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisreservedforgeneralpurposeuse.All locationswithin thisareaarereadandwriteaccessibleunderprogramcontrol.The thirdarea is reservedfor theLCDMemory.ThisspecialareaofDataMemory ismappeddirectlytotheLCDdisplaysodatawrittenintothismemoryareawilldirectlyaffectthedisplayeddata.SwitchingbetweenthedifferentDataMemorybanksisachievedbysettingtheBankPointertothecorrectvalue.

StructureTheDataMemoryissubdividedintoseveralbanks,allofwhichare implemented in8-bitwideRAM.TheDataMemorylocatedinBank0issubdividedintotwosections, theSpecialPurposeDataMemoryandtheGeneralPurposeDataMemory.

Thestartaddressof theDataMemoryforalldevices is theaddress00H.Registerswhicharecommontoallmicrocontrollers,suchasACC,PCL,etc.,havethesameDataMemoryaddress.TheLCDMemoryismappedintoBank1.TheBanks2to3containonlyGeneralPurposeDataMemoryfor thosedeviceswith largerDataMemorycapacities.As theSpecialPurposeDataMemoryregistersaremappedintoallbankareas,theycansubsequentlybeaccessedfromanybanklocation.

Device Capacity Banks

HT69F30A Gene�al Pu�pose: 12�×�LCD Memo�y: 2�

0: �0H~FFH1: �0H~9�H

HT69F40A Gene�al Pu�pose: 2�6×�LCD Memo�y: 37

0: �0H~FFH1: �0H~A4H2: �0H~FFH

HT69F�0A Gene�al Pu�pose: 3�4×�LCD Memo�y: 49

0: �0H~FFH1: �0H~B0H2: �0H~FFH3: �0H~FFH

Rev. 1.20 3� ��to�e� 0�� 201� Rev. 1.20 39 ��to�e� 0�� 201�



Spe�ial Pu�poseData Memo�y

Gene�al Pu�poseData Memo�y

00H

7FH�0H

FFH Bank 0

Bank 3Bank 2

Bank 0

40H in Bank 1

LCD Memo�y in Bank 1

Data Memory Structure

General Purpose Data MemoryAllmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramingforbothreadingandwritingoperations.Byusingthe“SET[m].i”and“CLR[m].i”instructionsindividualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.

Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostof theregistersarebothreadableandwriteablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue“00H”.

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00H IAR001H MP002H IAR103H MP104H0�H ACC06H PCL07H TBLP0�H TBLH09H TBHP0AH STATUS0BH SM�D0CH LVDC0DH INTEG0EH WDTC0FH TBC10H INTC011H INTC112H

19H PAPU1�H PAWU

1BH1AH

1DH1CH

1FH

PAPAC

1EH

HT69F30A Spe�ial Pu�pose Data Memo�y

BP

13H14H MFI01�H MFI116H17H

MFI2

Bank 0� 1

SM�D1LVRC

Unused

PBPUPB

PBCPCPU

PCPCC

PDPUPD

PDCPEPU

PEPEC

PFPUPF

PFC

20H21H22H

29H2�H

2BH2AH

2DH2CH

2FH2EH

23H24H2�H26H27H

30H31H32H

39H3�H

3BH3AH

3DH3CH

3FH3EH

33H34H3�H36H37H

PAFS

PCFSPDFSPEFSPFFS

SFSTM0C0TM0C1TM0DLTM0DHTM0ALTM0AH

40H EEC41H EEA42H EED43H

47H4�H49H4AH4BH4CH4DH4EH

LCDC�FH

Bank 0 Bank 1

TM1C0TM1C1TM1DLTM1DHTM1ALTM1AH

60H61H

7FH

Unused

: Unused� �ead as 00H

Unused

UnusedUnusedUnused

Unused

Unused

UnusedUnusedUnused

Unused

Unused

HT69F30A Special Purpose Data Memory

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19H PAPU1�H PAWU

1BH1AH

1DH1CH

1FH

PAPAC

1EH


BP


MFI2

Bank 0� 1� 2

SM�D1LVRC

Unused

PBPUPB

PBCPCPU

PCPCC

PDPUPD

PDCPEPU

PEPEC

PFPUPF

PFCPGPU

PGPGC

20H21H22H

29H2�H

2BH2AH

2DH2CH

2FH2EH

23H24H2�H26H27H

30H31H32H

39H3�H

3BH3AH

3DH3CH

3FH3EH

33H34H3�H36H37H

PAFSPBFSPCFSPDFSPEFSPFFSPGFS

SFSTM0C0TM0C1TM0DLTM0DHTM0ALTM0AH


TM2C0

47H

TM2C1

4�H

TM1C249H

TM2DL

4AH

TM2DH

4BH

TM2AL

4CH

TM2AH

4DH

TM1BL4EH

TM1BH4FH�0H�1H�2H

LCDC�FH

�3H�4H��H�6H�7H

Bank 0� 2 Bank 1

TM1C0TM1C1

TM1DLTM1DHTM1ALTM1AH

60H61H

7FH

Unused


Unused

UnusedUnusedUnused

Unused

Unused


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19H PAPU1�H PAWU

1BH1AH

1DH1CH

1FH

PAPAC

1EH


BP


MFI2

Bank 0� 1� 2� 3

SM�D1LVRC

Unused

PBPUPB

PBCPCPU

PCPCC

PDPUPD

PDCPEPU

PEPEC

PFPUPF

PFCPGPU

PGPGC

PHPUPH

PHC

20H21H22H

29H2�H

2BH2AH

2DH2CH

2FH2EH

23H24H2�H26H27H

30H31H32H

39H3�H

3BH3AH

3DH3CH

3FH3EH

33H34H3�H36H37H

PAFSPBFSPCFSPDFSPEFSPFFSPGFSPHFSSFS

TM0C0TM0C1TM0DLTM0DHTM0ALTM0AH


TM2C0

47H

TM2C1

4�H

TM1C249H

TM2DL

4AH

TM2DH

4BH

TM2AL

4CH

TM2AH

4DH

TM1BL4EH

TM1BH4FH�0H�1H�2H

LCDC

��H

�FH

�3H�4H��H�6H�7H

Bank 0� 2� 3 Bank 1

TM1C0TM1C1

TM1DLTM1DHTM1ALTM1AH

TM2RP

60H61H

7FH

Unused


Unused

Unused


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Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection;howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedto,istheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.

Indirect Addressing Program Exampledata .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h

start: mov a,04h ; setup size of block mov block,a mova,offsetadres1 ;AccumulatorloadedwithfirstRAMaddress movmp0,a ;setupmemorypointerwithfirstRAMaddress loop: clrIAR0 ;clearthedataataddressdefinedbyMP0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue:Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificRAMaddresses.

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Bank Pointer – BPDependinguponwhichdeviceisused,theDataMemoryisdividedintoseveralbanks.SelectingtherequiredDataMemoryareaisachievedusingtheBankPointer.Bits0~1oftheBankPointerareusedtoselectDataMemoryBanks0~3.

TheDataMemoryisinitialisedtoBank0afterareset,exceptforaWDTtime-outresetinthePowerDownMode,inwhichcase,theDataMemorybankremainsunaffected.ItshouldbenotedthattheSpecialFunctionDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecialFunctionRegisterscanbeaccessedfromwithinanybank.DirectlyaddressingtheDataMemorywillalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.AccessingdatafrombanksotherthanBank0mustbeimplementedusingIndirectaddressing.

AsboththeProgramMemoryandDataMemorysharethesameBankPointerRegister,caremustbetakenduringprogramming.

DeviceBit

7 6 5 4 3 2 1 0HT69F30A — — — — — — — DMBP0HT69F40A — — — — — — DMBP1 DMBP0HT69F�0A — — — — — — DMBP1 DMBP0

BP Register List

BP Register• HT69F30A

Bit 7 6 5 4 3 2 1 0Name — — — — — — — DMBP0R/W — — — — — — — R/WP�R — — — — — — — 0

Bit7~1 Unimplemented,readas"0"Bit0 DMBP0:Datamemorybankpoint

0:Bank01:Bank1

• HT69F40A

Bit 7 6 5 4 3 2 1 0Name — — — — — — DMBP1 DMBP0R/W — — — — — — R/W R/WP�R — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 DMBP1, DMBP0:Datamemorybankpoint

00:Bank001:Bank110:Bank211:Undefined

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• HT69F50A

Bit 7 6 5 4 3 2 1 0Name — — — — — — DMBP1 DMBP0R/W — — — — — — R/W R/WP�R — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 DMBP1, DMBP0:Datamemorybankpoint

00:Bank001:Bank110:Bank211:Bank3

Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuserdefinedregisterandanother, it isnecessary todo thisbypassingthedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers – TBLP, TBHP, TBLHThesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointerandindicates thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

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Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe“CLRWDT”or“HALT”instruction.ThePDFflagisaffectedonlybyexecutingthe“HALT”or“CLRWDT”instructionorduringasystempower-up.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVisset ifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.

• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

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STATUS RegisterBit 7 6 5 4 3 2 1 0

Name — — T� PDF �V Z AC C

R/W — — R R R/W R/W R/W R/W

P�R — — 0 0 x x x x

“x” unknownBit7,6 Unimplemented,readas“0”Bit5 TO:WatchdogTime-Outflag

0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:Byexecutingthe“HALT”instruction

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.

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EEPROM Data MemoryTheEEPROMDataMemorycapacity isup to128×8bits for thisseriesofdevices.Unlike theProgramMemoryandRAMDataMemory, theEEPROMDataMemory isnotdirectlymappedintomemoryspaceandisthereforenotdirectlyaddressableinthesamewayastheothertypesofmemory.ReadandWriteoperationstotheEEPROMarecarriedoutinsinglebyteoperationsusinganaddressanddataregisterinBank0andasinglecontrolregisterinBank1.

Device Capacity AddressHT69F30A 64×� 00H~3FHHT69F40A 12�×� 00H~7FHHT69F�0A 12�×� 00H~7FH

EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregister,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinBank0,theycanbedirectlyaccessedinthesamewasasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,cannotbeaddresseddirectlyandcanonlybereadfromorwritten to indirectlyusing theMP1MemoryPointerandIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40HinBank1,theMP1MemoryPointermustfirstbesettothevalue40HandtheBankPointerregister,BP,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.

EEPROM Register List• HT69F30A

Register Name

Bit

7 6 5 4 3 2 1 0EEA — — EEA� EEA4 EEA3 EEA2 EEA1 EEA0EED EED7 EED6 EED� EED4 EED3 EED2 EED1 EED0EEC — — — — WREN WR RDEN RD

• HT69F40A/HT69F50A

Register Name

Bit

7 6 5 4 3 2 1 0EEA — EEA6 EEA� EEA4 EEA3 EEA2 EEA1 EEA0EED EED7 EED6 EED� EED4 EED3 EED2 EED1 EED0EEC — — — — WREN WR RDEN RD

EEA Register• HT69F30A

Bit 7 6 5 4 3 2 1 0Name — — EEA� EEA4 EEA3 EEA2 EEA1 EEA0R/W — — R/W R/W R/W R/W R/W R/WP�R — — x x x x x x

“x”: unknownBit7~6 Unimplemented,readas"0"Bit5~0 EEA5~EEA0:DataEEPROMaddressbit5~bit0

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Bit 7 6 5 4 3 2 1 0Name — EEA6 EEA� EEA4 EEA3 EEA2 EEA1 EEA0R/W — R/W R/W R/W R/W R/W R/W R/WP�R — x x x x x x x

“x”: unknownBit7 Unimplemented,readas"0"Bit6~0 EEA6~EEA0:DataEEPROMaddressbit6~bit0

EED Register

Bit 7 6 5 4 3 2 1 0Name EED� EED4 EED� EED4 EED3 EED2 EED1 EED0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R x x x x x x x x

“x”: unknownBit7~0 EED7~EED0:DataEEPROMdatabit7~bit0

EEC Register

Bit 7 6 5 4 3 2 1 0Name — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WP�R — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3 WREN:DataEEPROMwriteoperationenable

0:Disable1:Enable

ThisistheDataEEPROMWriteOperationEnablebitwhichmustbesethighbeforeDatatEEPROMwriteoperationsarecarriedout.ClearingthisbittozerowillinhibitDataEEPROMwriteoperations.

Bit2 WR:DataEEPROMwritecontrol0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlbitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENbithasnotfirstbeensethigh.

Bit1 RDEN:DataEEPROMreadoperationenable0:Disable1:Enable

ThisistheDataEEPROMReadOperationEnablebitwhichmustbesethighbeforeDatatEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit0 RD:DataEEPROMreadcontrol0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlbitandwhensethighby theapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENbithasnotfirstbeensethigh.

Note:TheWREN,WR,RDENandRDbitscannotbesetto“1”atthesametimeinoneinstruction.TheWRandRDbitscannotbesetto“1”atthesametime.

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Reading Data from the EEPROMToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbittodeterminewhenthedataisvalidforreading.

Writing Data to the EEPROMTheEEPROMaddressofthedatatobewrittenmustfirstbeplacedintheEEAregisterandthedataplacedintheEEDregister.TowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustfirstbesethightoenablethewritefunction.Afterthis,theWRbitintheEECregistermustbe immediatelysethighto initiateawritecycle.These twoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbeforeimplementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.NotethatsettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusinganinternaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallycleared tozeroby themicrocontroller, informing theuser that thedatahasbeenwritten to theEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainst inadvertentwriteoperation isprovided inseveralways.After thedevice ispowered-on theWriteEnablebit in thecontrol registerwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheBankPointer,BP,willbereset tozero,whichmeansthatDataMemoryBank0willbeselected.AstheEEPROMcontrolregisterislocatedinBank1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwrite interrupt is generatedwhen anEEPROMwrite cycle has ended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbit intherelevantinterruptregister.Howeveras theEEPROMiscontainedwithinaMulti-functionInterrupt, theassociatedmulti-function interruptenablebitmustalsobeset.WhenanEEPROMwritecycleends, theDEFrequestflaganditsassociatedmulti-functioninterruptrequestflagwillbothbeset.If theglobal,EEPROMandMulti-function interrupts areenabledand the stack isnot full, a jump to theassociatedMulti-functionInterruptvectorwill takeplace.When the interrupt isservicedonlytheMulti-functioninterruptflagwillbeautomaticallyreset, theEEPROMinterruptflagmustbemanuallyresetbytheapplicationprogram.MoredetailscanbeobtainedintheInterruptsection.

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Programming ConsiderationsCaremustbe taken thatdata isnot inadvertentlywritten to theEEPROM.ProtectioncanbeenhancedbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrolregisterexist.Althoughcertainlynotnecessary,considerationmightbegivenintheapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.

WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.Theglobal interruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.

Programming Examples

Reading Data from the EEPROM – Polling MothodMOV A,EEPROM_ADRES ;userdefinedaddressMOV EEA,AMOV A,040H ;setupmemorypointerMP1MOV MP1,A ;MP1pointstoEECregisterMOV A,01H ;setupBankPointerMOV BP,ASET IAR1.1 ;setRDENbit,enablereadoperationsSET IAR1.0 ;startReadCycle-setRDbitBACK:SZ IAR1.0 ;checkforreadcycleendJMP BACKCLR IAR1 ;disableEEPROMread/writeCLR BPMOV A,EED ;movereaddatatoregisterMOV READ_DATA,A

Writing Data to the EEPROM – Polling MothodCLR EMIMOV A,EEPROM_ADRES ;userdefinedaddressMOV EEA,AMOV A,EEPROM_DATA ;userdefineddataMOV EED,AMOV A,040H ;setupmemorypointerMP1MOV MP1,A ;MP1pointstoEECregisterMOV A,01H ;setupBankPointerMOV BP,ASET IAR1.3 ;setWRENbit,enablewriteoperationsSET IAR1.2 ;StartWriteCycle-setWRbit-executedimmediately ;aftersetWRENbitSET EMIBACK:SZ IAR1.2 ;checkforwritecycleendJMP BACKCLR IAR1 ;disableEEPROMread/writeCLR BP

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OscillatorVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughacombinationofconfigurationoptionsandregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfor theWatchdogTimerandTimeBaseInterrupts.Externaloscillators requiringsomeexternalcomponentsaswellas fully integrated internaloscillators, requiringnoexternalcomponents,areprovidedtoformawiderangeofbothfastandslowsystemoscillators.Alloscillatoroptionsareselected through theconfigurationoptions.Thehigher frequencyoscillatorsprovidehigherperformancebutcarrywithit thedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillators.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock,thedevicehastheflexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Freq. PinsExte�nal C�ystal HXT 400kHz~16MHz �SC1/�SC2 Exte�nal RC ERC �MHz �SC1Exte�nal Clo�k EC 400kHz~20MHz �SC1Inte�nal High Speed RC HIRC 4� � o� 12MHz — Exte�nal Low Speed C�ystal LXT 32.76�kHz XT1/XT2Inte�nal Low Speed RC LIRC 32kHz —

Oscillator Types

System Clock ConfigurationsTherearefivemethodsofgeneratingthesystemclock, threehighspeedoscillatorsandtwolowspeedoscillators.Thehighspeedoscillatorsareistheexternalcrystal/ceramicoscillator,externalRCnetworkoscillatorandtheinternal4MHz,8MHzor12MHzRCoscillator.Thetwolowspeedoscillatorsare the internal32kHzRCoscillatorand theexternal32.768kHzcrystaloscillator.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

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HXT

HIRCP�es�ale�

fH

LIRC

LXT

High Speed �s�illation (H�SC)

Low Speed �s�illation (L�SC)

fH/2

fH/16

fH/64

fH/�

fH/4

fH/32

High Speed �s�illationConfigu�ation �ption

Low Speed �s�illationConfigu�ation �ption

CKS[2:0]� HLCLK

fSYS

Fast Wake-up f�om SLEEP Mode o� IDLE Mode Cont�ol (fo� HXT only)

÷ � LCD D�ive�

fSYS/4

fSUB

fTB

WDT

Time Base

TBCK

fs

ERC

EC

External Crystal/Ceramic Oscillator – HXTTheExternalCrystal/CeramicSystemOscillator isoneof thehighfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Formostcrystaloscillatorconfigurations, thesimpleconnectionofacrystalacrossOSC1andOSC2willcreatethenecessaryphaseshiftandfeedbackforoscillation,withoutrequiringexternalcapacitors.However,forsomecrystaltypesandfrequencies,toensureoscillation, itmaybenecessarytoaddtwosmallvaluecapacitors,C1andC2.Usingaceramicresonatorwillusuallyrequiretwosmallvaluecapacitors,C1andC2,tobeconnectedasshownforoscillationtooccur.ThevaluesofC1andC2shouldbeselectedinconsultationwiththecrystalorresonatormanufacturer'sspecification.Anadditionalconfigurationoptionmustbesetuptoconfigurethedeviceaccordingtowhethertheoscillatorfrequencyishigh,definedasequaltoorabove1MHz,orlow,whichisdefinedasbelow1MHz.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwithinterconnectinglinesarealllocatedasclosetotheMCUaspossible.

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Crystal/Resonator Oscillator – HXT

Rev. 1.20 �4 ��to�e� 0�� 201� Rev. 1.20 �� to�e� 0�� 201�



Crystal Oscillator C1 and C2 Values

Crystal Frequency C1 C212MHz 0pF 0pF�MHz 0pF 0pF4MHz 0pF 0pF1MHz 100pF 100pF

4��kHz (see Note2) 100pF 100pFNote: 1. C1 and C2 values a�e fo� guidan�e only.

2. XTAL mode configuration option: 455kHz.

Crystal Recommended Capacitor Values

External RC Oscillator – ERCUsing theERCoscillatoronlyrequires thata resistor,withavaluebetween56kΩand2.4MΩ,isconnectedbetweenOSC1andVDD,andacapacitor isconnectedbetweenOSC1andground,providinga lowcostoscillatorconfiguration.It isonly theexternalresistor thatdetermines theoscillationfrequency;theexternalcapacitorhasnoinfluenceoverthefrequencyandisconnectedforstabilitypurposesonly.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internal frequencycompensationcircuitsareused toensure that the influenceof thepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresistance/frequencyreferencepoint,itcanbenotedthatwithanexternal150kΩresistorconnectedandwitha5Vvoltagepowersupplyandtemperatureof25°Cdegrees, theoscillatorwillhaveafrequencyof4MHzwithinatoleranceof2%.HereonlytheOSC1pinisused,whichissharedwithI/OpinPB0,leavingpinPB1freeforuseasanormalI/Opin.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk,itisimportanttolocatethecapacitorandresistorasclosetotheMCUaspossible.

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External RC Oscillator — ERC

Internal RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.TheinternalRCoscillatorhasthreefixedfrequenciesofeither4MHz,8MHzor12MHz.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyofeither3Vor5Vandatatemperatureof25°Cdegrees,thefixedoscillationfrequencyof4MHz,8MHzor12MHzwillhavea tolerancewithin2%.Note that if this internalsystemclockoption isselected,as itrequiresnoexternalpinsforitsoperation,I/OpinsPB0andPB1arefreeforuseasnormalI/Opins.

Rev. 1.20 �4 ��to�e� 0�� 201� Rev. 1.20 �� to�e� 0�� 201�



External 32.768kHz Crystal Oscillator – LXTTheExternal32.768kHzCrystalSystemOscillatorisoneofthelowfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Thisclocksourcehasafixedfrequencyof32.768kHzandrequiresa32.768kHzcrystaltobeconnectedbetweenpinsXT1andXT2.Theexternalresistorandcapacitorcomponentsconnectedtothe32.768kHzcrystalarenecessarytoprovideoscillation.Forapplicationswhereprecise frequenciesareessential, thesecomponentsmayberequiredtoprovidefrequencycompensationduetodifferentcrystalmanufacturingtolerances.Duringpower-upthereisatimedelayassociatedwiththeLXToscillatorwaitingforittostart-up.

WhenthemicrocontrollerenterstheSLEEPorIDLEMode,thesystemclockisswitchedofftostopmicrocontrolleractivityandtoconservepower.However, inmanymicrocontrollerapplicationsitmaybenecessarytokeeptheinternaltimersoperationalevenwhenthemicrocontrolleris intheSLEEPorIDLEMode.Todothis,anotherclock,independentofthesystemclock,mustbeprovided.

However,forsomecrystals,toensureoscillationandaccuratefrequencygeneration,itisnecessarytoaddtwosmallvalueexternalcapacitors,C1andC2.TheexactvaluesofC1andC2shouldbeselected inconsultationwith thecrystalor resonatormanufacturer'sspecification.Theexternalparallelfeedbackresistor,Rp,isrequired.

SomeconfigurationoptionsdetermineiftheXT1/XT2pinsareusedfortheLXToscillatororasI/Opins.

• IftheLXToscillatorisnotusedforanyclocksource,theXT1/XT2pinscanbeusedasnormalI/Opins.

• IftheLXToscillatorisusedforanyclocksource,the32.768kHzcrystalshouldbeconnectedtotheXT1/XT2pins.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwithinterconnectinglinesarealllocatedasclosetotheMCUaspossible.

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External LXT Oscillator

LXT Oscillator C1 and C2 Values

Crystal Frequency C1 C232.76�kHz 10pF 10pF

Note:1. C1 and C2 values a�e fo� guidan�e only.2. RP=�M~10MΩ is recommended.

32.768kHz Crystal Recommended Capacitor Values

Rev. 1.20 �6 ��to�e� 0�� 201� Rev. 1.20 �7 ��to�e� 0�� 201�



LXT Oscillator Low Power FunctionTheLXToscillatorcanfunctioninoneoftwomodes,theQuickStartModeandtheLowPowerMode.ThemodeselectionisexecutedusingtheLXTLPbitintheTBCregister.

LXTLP Bit LXT Mode0 Qui�k Sta�t1 Low-powe�

AfterpowerontheLXTLPbitwillbeautomaticallyclearedtozeroensuringthattheLXToscillatoris in theQuickStartoperatingmode.IntheQuickStartModetheLXToscillatorwillpowerupandstabilisequickly.However,after theLXToscillatorhas fullypoweredup itcanbeplacedintotheLow-powermodebysettingtheLXTLPbithigh.Theoscillatorwillcontinuetorunbutwithreducedcurrentconsumption,asthehighercurrentconsumptionisonlyrequiredduringtheLXToscillatorstart-up.Inpowersensitiveapplications,suchasbatteryapplications,wherepowerconsumptionmustbekepttoaminimum,itisthereforerecommendedthattheapplicationprogramsetstheLXTLPbithighabout2secondsafterpower-on.

Itshouldbenotedthat,nomatterwhatconditiontheLXTLPbit issetto, theLXToscillatorwillalwaysfunctionnormally, theonlydifference is that itwill takemore time tostartup if in theLow-powermode.

Internal 32kHz Oscillator – LIRCTheInternal32kHzSystemOscillator isoneof the lowfrequencyoscillatorchoices,which isselectedviaconfigurationoption.It isafullyintegratedRCoscillatorwithatypicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor its implementation.Device trimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25°Cdegrees,thefixedoscillationfrequencyof32kHzwillhaveatolerancewithin10%.

External Clock – ECThesystemclockcanalsobesuppliedbyanexternallysuppliedclockgivingusersamethodofsynchronizing theirexternalhardware to themicrocontrolleroperation.This is selectedusingaconfigurationoptionandsupplyingtheclockonpinOSC1.PinOSC2shouldbe left floatingif theexternaloscillator isused.Theinternaloscillatorcircuitcontainsafiltercircuit toreducethepossibilityoferraticoperationduetonoiseontheoscillatorpin,howeveras thefiltercircuitconsumesacertainamountofpower,aoscillatorconfigurationoptionexiststoturnthisfilteroff.Notusing the internal filtershouldbeconsidered inpowersensitiveapplicationsandwhere theexternallysuppliedclockisofahighintegrityandsuppliedbyalowimpedancesource.

Supplementary OscillatorsThelowspeedoscillators,inadditiontoprovidingasystemclocksourcearealsousedtoprovideaclocksourcetotwootherdevicefunctions.ThesearetheWatchdogTimer,theLCDdriverandtheTimeBaseInterrupts.

Rev. 1.20 �6 ��to�e� 0�� 201� Rev. 1.20 �7 ��to�e� 0�� 201�



Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcoursevice-versa, lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthesedeviceswithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.

System ClockThedevicehasmanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingconfigurationoptionsandregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequency,fH,orlowfrequency,fSUB,source,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromanHXT,ERCorHIRCoscillator,selectedviaaconfigurationoption.Thelowspeedsystemclocksourcecanbesourcedfromtheclock,fSUB.IffSUB isselectedthenitcanbesourcedbyeithertheLXTorLIRCoscillators,selectedviaaconfigurationoption.Theotherchoice,which isadividedversionof thehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

ThefSUBclockisusedtoprovideasubstituteclockforthemicrocontrollerjustafterawake-uphasoccurredtoenablefasterwake-uptimes.

HXT

HIRCP�es�ale�

fH

LIRC

LXT

High Speed �s�illation (H�SC)

Low Speed �s�illation (L�SC)

fH/2

fH/16

fH/64

fH/�

fH/4

fH/32

High Speed �s�illationConfigu�ation �ption

Low Speed �s�illationConfigu�ation �ption

CKS[2:0]� HLCLK

fSYS

Fast Wake-up f�om SLEEP Mode o� IDLE Mode Cont�ol (fo� HXT only)

÷ � LCD D�ive�

fSYS/4

fSUB

fTB

WDT

Time Base

TBCK

fs

ERC

EC

System Clock Configurations

Note:WhenthesystemclocksourcefSYSisswitchedtofSUBfromfH,thehighspeedoscillationwillstoptoconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.

Rev. 1.20 �� to�e� 0�� 201� Rev. 1.20 �9 ��to�e� 0�� 201�



System Operation ModesThere are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingfourmodes,theSLEEP0,SLEEP1, IDLE0andIDLE1Modeareusedwhen themicrocontrollerCPUisswitchedoff toconservepower.

Operating ModeDescription

CPU fSYS fSUB fS

N�RMAL Mode �n fH~fH/64 �n �nSL�W Mode �n fSUB �n �nIDLE0 Mode �ff �ff �n �nIDLE1 Mode �ff �n �n �nSLEEP0 Mode �ff �ff �ff �ffSLEEP1 Mode �ff �ff �n �n

NORMAL ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbyoneofthehighspeedoscillators.Thismodeoperatesallowing themicrocontroller tooperatenormallywithaclocksourcewillcomefromoneof thehighspeedoscillators,eithertheHXT,ERC,ECorHIRCoscillators.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbitsintheSMODregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLOW ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.Theclocksourceusedwillbefromoneofthelowspeedoscillators,eithertheLXTortheLIRC.Runningthemicrocontrollerinthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.

SLEEP0 ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterislow.IntheSLEEP0modetheCPUwillbestopped,andthefSUBandfSclockswillbestoppedtoo,andtheWatchdogTimerfunctionisdisabled.Inthismode,theLVDENismustsetto"0".IftheLVDENissetto"1",itwon'tentertheSLEEP0Mode.

SLEEP1 ModeTheSLEEP1ModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterislow.IntheSLEEP1modetheCPUwillbestopped.HoweverthefSwillcontinuetooperateiftheLVDENis“1”ortheWatchdogTimerfunctionisenabledasitsclocksourceisfromthefSUB.

IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheSMOD1registerislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutsomeperipheralfunctionswillremainoperationalsuchas theWatchdogTimer,TMsandLCDdriver. In theIDLE0Mode, thesystemoscillatorwillbestoppedwhiletheWatchdogTimerclock,fS,willbeon.

Rev. 1.20 �� to�e� 0�� 201� Rev. 1.20 �9 ��to�e� 0�� 201�



IDLE1 ModeTheIDLE1ModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregister ishighandtheFSYSONbit intheSMOD1register ishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperationalsuchastheWatchdogTimer,TMsandSIM.IntheIDLE1Mode,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1ModetheWatchdogTimerclock,fS,willalsobeon.

Control RegisterAregisterpair,SMODandSMOD1, isusedforoverallcontrolof the internalclockswithinthedevice.

SMOD Register

Bit 7 6 5 4 3 2 1 0Name CKS2 CKS1 CKS0 FSTEN LT� HT� IDLEN HLCLKR/W R/W R/W R/W R/W R R R/W R/WP�R 0 0 0 0 0 0 1 1

Bit7~5 CKS2~CKS0:ThesystemclockselectionwhenHLCLKis"0"000:fSUB(fLXTorfLIRC)001:fSUB(fLXTorfLIRC)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedas thesystemclocksource.InadditiontothesystemclocksourcetheLIRC,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.

Bit4 FSTEN:FastWake-upControl(onlyforHXT)0:Disable1:Enable

This is theFastWake-upControlbitwhichdetermines if the fSUBclocksource isinitiallyusedafterthedevicewakesup.Whenthebitishigh,thefSUBclocksourcecanbeusedasatemporarysystemclocktoprovideafasterwakeuptimeasthefSUBclockisavailable.

Bit3 LTO:Lowspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeedsystemoscillator isstableafterpoweronresetorawake-uphasoccurred.TheflagwillbelowwhenintheSLEEP0Modebutafterawake-uphasoccurred,theflagwillchangetoahighlevelafter1~2clockcyclesiftheLIRCoscillatorisused.

Rev. 1.20 60 ��to�e� 0�� 201� Rev. 1.20 61 ��to�e� 0�� 201�



Bit2 HTO:Highspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstable.Thisflagisclearedto“0”byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafterdevicepower-on.TheflagwillbelowwhenintheSLEEPorIDLE0Modebutafterawake-uphasoccurred,theflagwillchangetoahighlevelafter1024clockcyclesiftheHXToscillatorisused.

bit1 IDLEN:IDLEModecontrol0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.

bit0 HLCLK:Systemclockselection0:fH/2~fH/64orfSUB

1:fH

Thisbit isused toselect if the fHclockor the fH/2~fH/64or fSUBclock isusedasthesystemclock.Whenthebit ishigh thefHclockwillbeselectedandif lowthefH/2~fH/64orfSUBclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefSUBclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.

SMOD1 Register

Bit 7 6 5 4 3 2 1 0Name FSYS�N — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WP�R 0 — — — — x 0 0

"x" unknownBit7 FSYSON:fSYSControlinIDLEMode

0:Disable1:Enable

Bit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

0:Notoccurred1:Occurred

Thisbit isset to1whenaspecificLowVoltageResetsituationoccurs.Thisbitcanonlybeclearedto0bytheapplicationprogram.

Bit1 LRF:LVRControlregistersoftwareresetflag0:Notoccurred1:Occurred

Thisbitissetto1iftheLVRCregistercontainsanynondefinedLVRvoltageregistervalues.Thisineffectactslikeasoftware-resetfunction.Thisbitcanonlybeclearedto0bytheapplicationprogram.

bit0 WRF:WDTControlregistersoftwareresetflag0:Notoccurred1:Occurred

Thisbit isset to1by theWDTControlregistersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.

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Fast Wake-upTominimisepowerconsumptionthedevicecanentertheSLEEPorIDLE0Mode,wherethesystemclocksourcetothedevicewillbestopped.Howeverwhenthedeviceiswokenupagain,itcantakeaconsiderabletimefortheoriginalsystemoscillatortorestart,stabilizeandallownormaloperationtoresume.ToensurethedeviceisupandrunningasfastaspossibleaFastWake-upfunctionisprovided,whichallowsfSUB,namelytheLIRCoscillator,toactasatemporaryclocktofirstdrivethesystemuntiltheoriginalsystemoscillatorhasstabilised.AstheclocksourcefortheFastWake-upfunction is fSUB, theFastWake-upfunction isonlyavailable in theSLEEP1andIDLE0modes.Whenthedevice iswokenupfromtheSLEEP0mode, theFastWake-upfunctionhasnoeffectbecausethefSUBclockisstopped.TheFastWake-upenable/disablefunctioniscontrolledusingtheFSTENbitintheSMODregister.

If theHXToscillator isselectedas theNORMALModesystemclockand if theFastWake-upfunction isenabled, then itwill takeone to twotSUBclockcyclesof theLIRCoscillatorfor thesystemtowake-up.ThesystemwilltheninitiallyrununderthefSUBclocksourceuntil1024HXTclockcycleshaveelapsed,atwhichpointtheHTOflagwillswitchhighandthesystemwillswitchovertooperatingfromtheHXToscillator.

IftheERC/HIRCorEC/LIRCoscillatorisusedasthesystemoscillator,thenitwilltake15~16clockcyclesoftheERC/HIRCoscillatoror1~2clockcyclesoftheLIRCosrillatorrespectivelytowakeupthesystemfromtheSLEEPorIDLE0Mode.TheFastWake-upbit,FSTENwillhavenoeffectinthesecases.

SystemOscillator

FSTENBit

Wake-up Time(SLEEP0 Mode)

Wake-up Time(SLEEP1 Mode)

Wake-up Time(IDLE0 Mode)

Wake-up Time(IDLE1 Mode)

HXT

0 1024 HXT �y�les 1024 HXT �y�les 1~2 HXT �y�les

1 1024 HXT �y�les

1~2 fSUB �y�les(System �uns with fSUB first for 1024 HXT �y�les and then swit�hes ove� to �un with the HXT �lo�k )

1~2 HXT �y�les

ERC x 1�~16 ERC �y�les 1�~16 ERC �y�les 1~2 ERC �y�lesHIRC x 1�~16 HIRC �y�les 1�~16 HIRC �y�les 1~2 HIRC �y�lesEC x 1~2 EC �y�les 1~2 EC �y�les 1~2 EC �y�lesLIRC x 1~2 LIRC �y�les 1~2 LIRC �y�les 1~2 LIRC �y�lesLXT x 1024 LXT �y�les 1024 LXT �y�les 1~2 LXT �y�les

Wake-up Times

NotethatiftheWatchdogTimerisdisabled,whichmeansthatthefSUBclockdrivedfromtheLXTorLIRCoscillator isoff, thentherewillbenoFastWake-upfunctionavailablewhenthedevicewakes-upfromtheSLEEP0Mode.

Operating Mode SwitchingThedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionoftheIDLENbitintheSMODregisterandFSYSONintheSMOD1register.

Rev. 1.20 62 ��to�e� 0�� 201� Rev. 1.20 63 ��to�e� 0�� 201�



WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfSUB.IftheclockisfromthefSUB,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofotherinternalfunctionssuchastheTMsandtheLCDdriver.Theaccompanyingflowchartshowswhathappenswhenthedevicemovesbetweenthevariousoperatingmodes.

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Operating Mode Switching and Wake-upThedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionoftheIDLENbitintheSMODregisterandFSYSONintheWDTCregister.

WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfL.IftheclockisfromthefL,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofotherinternalfunctionssuchastheTMsandtheSIM.Theaccompanyingflowchartshowswhathappenswhenthedevicemovesbetweenthevariousoperatingmodes.

Rev. 1.20 62 ��to�e� 0�� 201� Rev. 1.20 63 ��to�e� 0�� 201�



NORMAL Mode to SLOW Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower,thesystemclockcanswitchtorunintheSLOWModebysettheHLCLKbitto"0"andsettheCKS2~CKS0bitsto"000"or"001"intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLXTor theLIRCoscillatorsandthereforerequires theseoscillatorstobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

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Rev. 1.20 64 ��to�e� 0�� 201� Rev. 1.20 6� ��to�e� 0�� 201�



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SLOW Mode to NORMAL Mode SwitchingInSLOWModethesystemuseseither theLXTorLIRClowspeedsystemoscillator.ToswitchbacktotheNORMALMode,wherethehighspeedsystemoscillatorisused,theHLCLKbitshouldbesetto"1"orHLCLKbitis"0",butCKS2~CKS0issetto"010","011","100","101","110"or"111".Asacertainamountof timewillberequiredfor thehighfrequencyclocktostabilise, thestatusof theHTObit ischecked.Theamountof timerequiredforhighspeedsystemoscillatorstabilizationdependsuponwhichhighspeedsystemoscillatortypeisused.

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Entering the SLEEP0 ModeThereisonlyonewayforthedevicetoentertheSLEEP0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTandLVDbothoff.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandthefSUBclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandstoppedastheWDTisdisabled.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

Entering the SLEEP1 ModeThereisonlyonewayforthedevicetoentertheSLEEP1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTorLVDon.When this instruction isexecutedunder theconditionsdescribedabove, thefollowingwilloccur:

• The systemclockwill be stoppedand the applicationprogramwill stopat the “HALT”instruction,buttheWDTorLVDwillremainwiththeclocksourcecomingfromthefSUBclock.


• TheWDTwillbeclearedandresumecountingastheWDTisenabledanditsclocksourceisselectedtocomefromthefSUBclock.



Entering the IDLE0 ModeThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinSMOD1registerequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• The systemclockwill be stoppedand the applicationprogramwill stopat the “HALT”instruction,butthefSUBclockwillbeon.


• TheWDTwillbeclearedandresumecountingastheWDTclocksourceisderivedfromthefSUBclock.



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Entering the IDLE1 ModeThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinSMOD1registerequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandfSUBclockwillbeonandtheapplicationprogramwillstopatthe“HALT”instruction.


• TheWDTwillbeclearedandresumecountingastheWDTclocksourceisderivedfromthefSUBclock.



Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerifthepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbonbedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuits thatdonotdrawcurrent,suchasotherCMOSinputs.Alsonote thatadditionalstandbycurrentwillalsoberequiredif theconfigurationoptionshaveenabledtheLXTorLIRCoscillator.

IntheIDLE1Modethesystemoscillator ison, if thesystemoscillator isfromthehighspeedsystemoscillator,theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

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Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• Anexternalreset

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

If thesystemiswokenupbyanexternal reset, thedevicewillexperiencea full systemreset,however,ifthedeviceiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Althoughbothof thesewake-upmethodswill initiatearesetoperation, theactualsourceof thewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflag isclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe"HALT"instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.

Programming ConsiderationsTheHXTandLXToscillatorsbothusethesameSSTcounter.Forexample,ifthesystemiswokenupfromtheSLEEP0ModeandboththeHXTandLXToscillatorsneedtostart-upfromanoffstate.TheLXToscillatorusestheSSTcounterafterHXToscillatorhasfinisheditsSSTperiod.

• IfthedeviceiswokenupfromtheSLEEP0ModetotheNORMALMode,thehighspeedsystemoscillatorneedsanSSTperiod.Thedevicewillexecutefirst instructionafterHTOis"1".Atthistime,theLXToscillatormaynotbestableiffSUBisfromLXToscillator.Thesamesituationoccursinthepower-onstate.TheLXToscillator isnotreadyyetwhenthefirst instructionisexecuted.

• If thedeviceiswokenupfromtheSLEEP1ModetoNORMALMode,andthesystemclocksourceisfromHXToscillatorandFSTENis“1”,thesystemclockcanbeswitchedtotheLXTorLIRCoscillatorafterwakeup.

• Thereareperipheralfunctions,suchasWDT,TMsandLCDdriver,forwhichthefSYSisused.IfthesystemclocksourceisswitchedfromfHtofSUB,theclocksourcetotheperipheralfunctionsmentionedabovewillchangeaccordingly.

• Theon/offconditionoffSUBandfSdependsuponwhethertheWDTisenabledordisabledastheWDTclocksourceisselectedfromfSUB.

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Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalclockfS,whichisinturnsuppliedbythefSUBclock.ThefSUBclockcanbesourcedfromeithertheLXTorLIRCoscillatorselectedbyaconfigurationoption.TheLIRCinternaloscillatorhasanapproximatefrequencyof32kHzandthisspecified internalclockperiodcanvarywithVDD, temperatureandprocessvariations.TheLXToscillatorissuppliedbyanexternal32.768kHzcrystal.TheWatchdogTimersourceclockisthensubdividedbyaratioof28 to218 togivelongertimeouts, theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.

Watchdog Timer Control RegisterAsingle register,WDTC,controls the required time-outperiodaswellas theenable/disableoperation.ThisregistercontrolstheoveralloperationoftheWatchdogTimer.

WDTC Register

Bit 7 6 5 4 3 2 1 0Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 1 0 1 0 0 1 1

Bit7~3 WE4~WE0:WDTfunctionenablecontrolIftheWDTconfigurationoptionis“alwaysenable”:10101or01010:EnabledOtherValues:ResetMCU

IftheWDTconfigurationoptionis“applicationprogramenable”:10101:Disabled01010:EnabledOtherValues:ResetMCU

Ifthesebitsarechangedduetoadverseenvironmentalconditions,themicrocontrollerwillbereset.Theresetoperationwillbeactivatedafter2~3LIRCclockcyclesandtheWRFbitintheCTRLregisterwillbesetto1.

Bit2~0 WS2~WS0:SelectWDTTimeoutPeriod000:28/fS

001:210/fS

010:212/fS

011:214/fS

100:215/fS

101:216/fS

110:217/fS

111:218/fS

These threebitsdetermine thedivisionratioof theWatchdogTimersourceclock,whichinturndeterminesthetimeoutperiod.

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SMOD1 Register


“x” unknownBit7 FSYSON:fSYSControlinIDLEMode

Describedelsewhere.Bit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

Describedelsewhere.Bit1 LRF:LVRControlregistersoftwareresetflag

Describedelsewhere.bit0 WRF:WDTControlregistersoftwareresetflag


Thisbit isset to1by theWDTControlregistersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.

Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendless loop, theseclear instructionswillnotbeexecutedinthecorrectmanner, inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.TheWatchdogTimerfunctionisdeterminedusingaconfigurationoption.WithregardtotheWatchdogTimerenable/disablefunction, therearealsofivebits,WE4~WE0,intheWDTCregistertooffertheadditionalenable/disablecontrolandresetcontroloftheWatchdogTimer.IftheWDTfunctionconfigurationoptionisdeterminedthat theWDTfunctionisalwaysenabled, theWE4~WE0bitsstillhaveeffectson theWDTfunction.When theWE4~WE0bitsvalue isequal to01010Bor10101B,theWDTfunctionisenabled.However, if theWE4~WE0bitsarechangedtoanyothervaluesexcept01010Band10101B,whichiscausedbytheenvironmentalnoise, itwillreset themicrocontrollerafter2~3fSUBclockcycles.IftheWDTfunctionconfigurationoptionisdeterminedthattheWDTfunctioniscontrolledbytheWDTCcontrolregisterusingtheapplicationprogram,theWE4~WE0valuescandeterminewhichmodetheWDToperates in.TheWDTfunctionwillbedisabledwhentheWE4~WE0bitsareset toavalueof10101BwhiletheWDTfunctionwillbeenablediftheWE4~WE0bitsareequalto01010B.IftheWE4~WE0bitsaresettoanyothervalues,other than01010Band10101B,itwillreset thedeviceafter2~3fSUBclockcycles.Afterpoweronthesebitswillhaveavalueof01010B.

WDT Function Control WE4~WE0 Bits WDT Function

Appli�ation P�og�am Ena�led

10101B Disa�le

01010B Ena�le

Any othe� value Reset MCU

Always Ena�led01010B o� 10101B Ena�le

Any othe� value Reset MCU

Watchdog Timer Enable/Disable Control

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Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101BwrittenintotheWE4~WE0field,thesecondisusingtheWatchdogTimersoftwareclearinstructionandthethirdisviaaHALTinstruction.

ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle“CLRWDT”instructiontocleartheWDTcontents.

Themaximumtimeoutperiod iswhenthe218divisionratio isselected.Asanexample,witha32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8secondforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.

“CLR WDT”Inst�u�tion

�-stage Divide� WDT P�es�ale�

WE4~WE0 �itsWDTC Registe� Reset MCU

LXT fSfSUB fS/2�

�-to-1 MUX

CLR

WS2~WS0(fS/2� ~ fS/21�)

WDT Time-out(2�/fS ~ 21�/fS)

LIRC

MUX

Low Speed �s�illato� Configu�ation option

Watchdog Timer

Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Inadditiontothepower-onreset,situationsmayarisewhereit isnecessarytoforcefullyapplyaresetconditionwhenthe isrunning.Oneexampleof this iswhereafterpowerhasbeenappliedandtheisalreadyrunning,theRESlineisforcefullypulledlow.Insuchacase,knownasanormaloperationreset,someof the registersremainunchangedallowing the toproceedwithnormaloperationaftertheresetlineisallowedtoreturnhigh.

Another typeofreset iswhentheWatchdogTimeroverflowsandresets the .All typesofresetoperationsresult indifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullreset,similartotheRESresetis implementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

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Reset FunctionsThereare fiveways inwhicha resetcanoccur, througheventsoccurringboth internallyandexternally:

Power-on ResetThemostfundamentalandunavoidableresetistheonethatoccursafterpowerisfirstappliedtothe.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensuresthatcertainotherregistersarepresettoknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

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Power-On Reset Timing Chart

Note:tRSTDispower-ondelay,typicaltime=50ms

RES PinAstheresetpinissharedwithanI/Opin,theresetfunctionmustbeselectedusingaconfigurationoption.AlthoughthehasaninternalRCresetfunction,iftheVDDpowersupplyrisetimeisnotfastenoughordoesnotstabilisequicklyatpower-on, theinternalresetfunctionmaybeincapableofprovidingproperresetoperation.ForthisreasonitisrecommendedthatanexternalRCnetworkisconnectedtotheRESpin,whoseadditionaltimedelaywillensurethattheRESpinremainslowforanextendedperiodtoallowthepowersupplytostabilise.Duringthistimedelay,normaloperationof the willbe inhibited.After theRESlinereachesacertainvoltagevalue, theresetdelaytimetRSTDis invokedtoprovideanextradelaytimeafterwhichthewillbeginnormaloperation.TheabbreviationSSTinthefiguresstandsforSystemStart-upTimer.

FormostapplicationsaresistorconnectedbetweenVDDandtheRESpinandacapacitorconnectedbetweenVSSandtheRESpinwillprovideasuitableexternalresetcircuit.AnywiringconnectedtotheRESpinshouldbekeptasshortaspossibletominimiseanystraynoiseinterference.

ForapplicationsthatoperatewithinanenvironmentwheremorenoiseispresenttheEnhancedResetCircuitshownisrecommended.

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External RES Circuit

Note:*ItisrecommendedthatthiscomponentisaddedforaddedESDprotection.

**It isrecommendedthatthiscomponentisaddedinenvironmentswherepowerlinenoiseissignificant.

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MoreinformationregardingexternalresetcircuitsislocatedinApplicationNoteHA0075EontheHoltekwebsite.

PullingtheRESPinlowusingexternalhardwarewillalsoexecuteadevicereset.Inthiscase,asinthecaseofotherresets,theProgramCounterwillresettozeroandprogramexecutioninitiatedfromthispoint.

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RES Reset Timing ChartNote:tRSTDispower-ondelay,typicaltime=16.7ms

Low Voltage Reset – LVRThemicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.TheLVRfunctionisalwaysenabledwithaspecificLVRvoltage,VLVR.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedeviceinternallyandtheLVRFbitintheSMOD1registerwillalsobesetto1.ForavalidLVRsignal,alowsupplyvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistforatimegreaterthanthatspecifiedbytLVRintheA.C.characteristics.Ifthelowsupplyvoltagestatedoesnotexceedthisvalue,theLVRwillignorethelowsupplyvoltageandwillnotperformaresetfunction.TheactualVLVRvaluecanbeselectedbytheLVSbitsintheLVRCregister. If theLVS7~LVS0bitshaveanyothervalue,whichmayperhapsoccurduetoadverseenvironmentalconditionssuchasnoise, theLVRwillresetthedeviceafter2~3fSUBclockcycles.Whenthishappens,theLRFbitintheSMOD1registerwillbesetto1.Afterpowerontheregisterwillhavethevalueof01010101B.NotethattheLVRfunctionwillbeautomaticallydisabledwhenthedeviceentersthepowerdownmode.

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Note:tRSTDispower-ondelay,typicaltime=50msLow Voltage Reset Timing Chart

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• LVRC Register

Bit 7 6 5 4 3 2 1 0Name LVS7 LVS6 LVS� LVS4 LVS3 LVS2 LVS1 LVS0R/W R/W R/W R/W R/W R/w R/w R/W R/WP�R 0 1 0 1 0 1 0 1

Bit7~0 LVS7~LVS0:LVRvoltageselect01010101:2.1V00110011:2.55V10011001:3.15V10101010:3.8VAnyothervalues:GeneratesMCUreset–registerisresettoPORvalue

Whenanactuallowvoltageconditionoccurs,asspecifiedbyoneofthefourdefinedLVRvoltagevaluesabove,anMCUresetwillbegenerated.Theresetoperationwillbeactivatedafter2~3fSUBclockcycles. In thissituation theregistercontentswillremainthesameaftersucharesetoccurs.Anyregistervalue,otherthanthefourdefinedregistervaluesabove,willalsoresultinthegenerationofanMCUreset.Theresetoperationwillbeactivatedafter2~3fSUBclockcycles.HoweverinthissituationtheregistercontentswillberesettothePORvalue.

• SMOD1 Register


"x" unknownBit7 FSYSON:fSYSControlinIDLEMode

Describedelsewhere.Bit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag


Thisbitissetto1whenaspecificLowVoltageResetsituationconditionoccurs.Thisbitcanonlybeclearedto0bytheapplicationprogram.

Bit1 LRF:LVRControlregistersoftwareresetflag0:Notoccurred1:Occurred

Thisbitissetto1iftheLVRCregistercontainsanynondefinedLVRvoltageregistervalues.Thisineffectactslikeasoftware-resetfunction.Thisbitcanonlybeclearedto0bytheapplicationprogram.

bit0 WRF:WDTControlregistersoftwareresetflagDescribedelsewhere.

Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outResetduringnormaloperation is thesameasahardwareRESpinresetexceptthattheWatchdogtime-outflagTOwillbesetto"1".

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WDT Time-out Reset during Normal Operation Timing Chart

Note:tRSTDispower-ondelay,typicaltime=16.7ms

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Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto"0"andtheTOflagwillbesetto"1".RefertotheA.C.CharacteristicsfortSSTdetails.

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WDT Time-out Reset during SLEEP or IDLE Timing Chart

Note:ThetSSTis15~16clockcyclesifthesystemclocksourceisprovidedbyERCorHIRC.ThetSSTis1024clockforHXTorLXT.ThetSSTis1~2clockforLIRC.

Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF RESET Conditions0 0 Powe�-on �esetu u RES o� LVR �eset du�ing N�RMAL o� SL�W Mode ope�ation1 u WDT time-out �eset du�ing N�RMAL o� SL�W Mode ope�ation1 1 WDT time-out �eset du�ing IDLE o� SLEEP Mode ope�ation

"u"standsforunchanged

Thefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETP�og�am Counte� Reset to ze�oInte��upts All inte��upts will �e disa�ledWDT� Time Base Clea� afte� �eset� WDT �egins �ountingTime� Modules Time� Modules will �e tu�ned offInput/�utput Po�ts I/� po�ts will �e setup as inputsSta�k Pointe� Sta�k Pointe� will point to the top of the sta�k

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectsthemicrocontrollerinternalregisters.

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Register Reset Status Table

Register

HT69F30A

HT69F40A

HT69F50A

Power-on Reset RES or LVR Reset WDT Time-out(Normal Operation)

WDT Time-out(HALT)

IAR0 ● ● ● x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u

MP0 ● ● ● x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u

IAR1 ● ● ● x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u

MP1 ● ● ● x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u

BP ● - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - u

BP ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

ACC ● ● ● x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u

PCL ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TBLP ● ● ● x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u

TBLH ● ● ● x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u

TBHP ● - - - - - x x x - - - - - u u u - - - - - u u u - - - - - u u u

TBHP ● - - - - x x x x - - - - u u u u - - - - u u u u - - - - u u u u

TBHP ● - - - x x x x x - - - u u u u u - - - u u u u u - - - u u u u u

STATUS ● ● ● - - 0 0 x x x x - - u u u u u u - - 1 u u u u u - - 1 1 u u u u

SM�D ● ● ● 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 u u u u u u u u

LVDC ● ● ● - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - u u - u u u

INTEG ● ● ● - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u u

WDTC ● ● ● 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 u u u u u u u u

TBC ● ● ● 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 u u u u u u u u

INTC0 ● ● ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u u

INTC1 ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

SM�D1 ● ● ● 0 - - - - x 0 0 0 - - - - 1 u u 0 - - - - u u u u - - - - u u u

LVRC ● ● ● 0 1 0 1 0 1 0 1 u u u u u u u u 0 1 0 1 0 1 0 1 u u u u u u u u

MFI0 ● - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

MFI0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

MFI1 ● ● ● - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - u u u - u u u

MFI2 ● ● ● - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

PAWU ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PAPU ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PA ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PAC ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PBPU ● - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u

PBPU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PB ● - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u u

PB ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PBC ● - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u u

PBC ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PCPU ● ● - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u u

PCPU ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u u

Rev. 1.20 76 ��to�e� 0�� 201� Rev. 1.20 77 ��to�e� 0�� 201�



Register

HT69F30A

HT69F40A

HT69F50A


WDT Time-out(HALT)

PC ● ● - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - u u u

PC ● - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - u u u u u u u

PCC ● ● - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - u u u

PCC ● - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - u u u u u u u

PDPU ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PD ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PDC ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PEPU ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PE ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PEC ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PFPU ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PF ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PFC ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PGPU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PG ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PGC ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PHPU ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PH ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PHC ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PAFS ● ● ● - 0 0 - 0 - 0 - - 0 0 - 0 - 0 - - 0 0 - 0 - 0 - - u u - u - u -

PBFS ● ● 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u - - - -

PCFS ● ● ● - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u u

PDFS ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PEFS ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PFFS ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PGFS ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PHFS ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

SFS ● - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u u - - - -

SFS ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM0C0 ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM0C1 ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM0DL ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM0DH ● ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM0AL ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM0AH ● ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

EEC ● ● ● - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u

EEA ● - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u u

EEA ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u u

EED ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1C0 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

Rev. 1.20 76 ��to�e� 0�� 201� Rev. 1.20 77 ��to�e� 0�� 201�



Register

HT69F30A

HT69F40A

HT69F50A


WDT Time-out(HALT)

TM1C1 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1DL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1DH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM1AL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1AH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM1C0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1C1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1C2 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1DL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1DH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM1AL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1AH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM1BL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1BH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM2C0 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM2C1 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM2DL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM2DH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM2AL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM2AH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM2C0 ● 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -

TM2C1 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM2DL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM2DH ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM2AL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM2AH ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM2RP ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

LCDC ● ● ● 0 - 0 - 0 0 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 0 0 u - u - u u u u

Note:“-”notimplement“u”means“unchanged”“x”means“unknown”

Rev. 1.20 7� ��to�e� 0�� 201� Rev. 1.20 79 ��to�e� 0�� 201�



Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedeviceprovidesbidirectional input/output lines labeledwithportnamesPA~PH.TheseI/OportsaremappedtotheRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

I/O Port Register List

HT69F30A

Register Name

Bit

7 6 5 4 3 2 1 0PAWU PAWU7 PAWU6 PAWU� PAWU4 PAWU3 PAWU2 PAWU1 PAWU0PAPU PAPU7 PAPU6 PAPU� PAPU4 PAPU3 PAPU2 PAPU1 PAPU0

PA PA7 PA6 PA� PA4 PA3 PA2 PA1 PA0PAC PAC7 PAC6 PAC� PAC4 PAC3 PAC2 PAC1 PAC0

PBPU — — — — PBPU3 PBPU2 PBPU1 PBPU0PB — — — — PB3 PB2 PB1 PB0

PBC — — — — PBC3 PBC2 PBC1 PBC0PCPU — — — — — PCPU2 PCPU1 PCPU0

PC — — — — — PC2 PC1 PC0PCC — — — — — PCC2 PCC1 PCC0

PDPU PDPU7 PDPU6 PDPU� PDPU4 PDPU3 PDPU2 PDPU1 PDPU0PD PD7 PD6 PD� PD4 PD3 PD2 PD1 PD0

PDC PDC7 PDC6 PDC� PDC4 PDC3 PDC2 PDC1 PDC0PEPU PEPU7 PEPU6 PEPU� PEPU4 PEPU3 PEPU2 PEPU1 PEPU0

PE PE7 PE6 PE� PE4 PE3 PE2 PE1 PE0PEC PEC7 PEC6 PEC� PEC4 PEC3 PEC2 PEC1 PEC0

PFPU PFPU7 PFPU6 PFPU� PFPU4 PFPU3 PFPU2 PFPU1 PFPU0PF PF7 PF6 PF� PF4 PF3 PF2 PF1 PF0

PFC PFC7 PFC6 PFC� PFC4 PFC3 PFC2 PFC1 PFC0

Rev. 1.20 7� ��to�e� 0�� 201� Rev. 1.20 79 ��to�e� 0�� 201�



HT69F40A

Register Name

Bit



PBPU PBPU7 PBPU6 PBPU� PBPU4 PBPU3 PBPU2 PBPU1 PBPU0PB PB7 PB6 PB� PB4 PB3 PB2 PB1 PB0

PBC PBC7 PBC6 PBC� PBC4 PBC3 PBC2 PBC1 PBC0PCPU — PCPU6 PCPU� PCPU4 PCPU3 PCPU2 PCPU1 PCPU0

PC — PC6 PC� PC4 PC3 PC2 PC1 PC0PCC — PCC6 PCC4 PCC4 PCC3 PCC2 PCC1 PCC0





PFC PFC7 PFC6 PFC� PFC4 PFC3 PFC2 PFC1 PFC0PGPU PGPU7 PGPU6 PGPU� PGPU4 PGPU3 PGPU2 PGPU1 PGPU0

PG PG7 PG6 PG� PG4 PG3 PG2 PG1 PG0PGC PGC7 PGC6 PGC� PGC4 PGC3 PGC2 PGC1 PGC0

Rev. 1.20 �0 ��to�e� 0�� 201� Rev. 1.20 �1 ��to�e� 0�� 201�



HT69F50A

Register Name

Bit



PBPU PBPU7 PBPU6 PBPU� PBPU4 PBPU3 PBPU2 PBPU1 PBPU0PB PB7 PB6 PB� PB4 PB3 PB2 PB1 PB0

PBC PBC7 PBC6 PBC� PBC4 PBC3 PBC2 PBC1 PBC0PCPU — PCPU6 PCPU� PCPU4 PCPU3 PCPU2 PCPU1 PCPU0

PC — PC6 PC� PC4 PC3 PC2 PC1 PC0PCC — PCC6 PCC4 PCC4 PCC3 PCC2 PCC1 PCC0





PFC PFC7 PFC6 PFC� PFC4 PFC3 PFC2 PFC1 PFC0PGPU PGPU7 PGPU6 PGPU� PGPU4 PGPU3 PGPU2 PGPU1 PGPU0

PG PG7 PG6 PG� PG4 PG3 PG2 PG1 PG0PGC PGC7 PGC6 PGC� PGC4 PGC3 PGC2 PGC1 PGC0

PHPU PHPU7 PHPU6 PHPU� PHPU4 PHPU3 PHPU2 PHPU1 PHPU0PH PH7 PH6 PH� PH4 PH3 PH2 PH1 PH0

PHC PHC7 PHC6 PHC� PHC4 PHC3 PHC2 PHC1 PHC0

“—”Unimplemented,readas“0”PAWUn:PAwake-upfunctioncontrol

0:Disable1:Enable

PAn/PBn/PCn/PDn/PEn/PFn/PGn/PHn:I/ODatabit0:Data01:Data1

PACn/PBCn/PCCn/PDCn/PECn/PFCn/PGCn/PHCn:I/Otypeselection0:Output1:Input

PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn/PGPUn/PHPUn:Pull-highfunctioncontrol0:Disable1:Enable

Rev. 1.20 �0 ��to�e� 0�� 201� Rev. 1.20 �1 ��to�e� 0�� 201�



Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregistersPAPU~PHPU,andare implementedusingweakPMOStransistors.

Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

I/O Port Control RegistersEachPorthas itsowncontrol register,knownasPAC~PHC,whichcontrols the input/outputconfiguration.With thiscontrolregister,eachI/Opinwithorwithoutpull-highresistorscanbereconfigureddynamicallyunder softwarecontrol.For the I/Opin to functionasan input, thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.

However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forthesepins,thechosenfunctionofthemulti-functionI/Opinsisselectedbyaseriesofregitersviatheapplicationprogramcontrol.

Rev. 1.20 �2 ��to�e� 0�� 201� Rev. 1.20 �3 ��to�e� 0�� 201�



Pin-shared Function Selection Register List• HT69F30A

Register Name

Bit

7 6 5 4 3 2 1 0PAFS — PAFS6 PAFS� — PAFS3 — PAFS1 —PCFS — — — — — PCFS2 PCFS1 PCFS0PDFS PDFS7 PDFS6 PDFS� PDFS4 PDFS3 PDFS2 PDFS1 PDFS0PEFS PEFS7 PEFS6 PEFS� PEFS4 PEFS3 PEFS2 PEFS1 PEFS0PFFS PFFS7 PFFS6 PFFS� PFFS4 PFFS3 PFFS2 PFFS1 PFFS0SFS — SFS6 SFS� SFS4 — — — —

• HT69F40A

Register Name

Bit

7 6 5 4 3 2 1 0PAFS — PAFS6 PAFS� — PAFS3 — PAFS1 —PBFS PBFS7 PBFS6 PBFS� PBFS4 — — — —PCFS — — — — — PCFS2 PCFS1 PCFS0PDFS PDFS7 PDFS6 PDFS� PDFS4 PDFS3 PDFS2 PDFS1 PDFS0PEFS PEFS7 PEFS6 PEFS� PEFS4 PEFS3 PEFS2 PEFS1 PEFS0PFFS PFFS7 PFFS6 PFFS� PFFS4 PFFS3 PFFS2 PFFS1 PFFS0PGFS PGS7 PFGFS6 PGFS� PGFS4 PGFS3 PGFS2 PGFS1 PGFS0SFS SFS7 SFS6 SFS� SFS4 SFS3 SFS2 SFS1 SFS0

• HT69F50A

Register Name

Bit

7 6 5 4 3 2 1 0PAFS — PAFS6 PAFS� — PAFS3 — PAFS1 —PBFS PBFS7 PBFS6 PBFS� PBFS4 — — — —PCFS — — — — — PCFS2 PCFS1 PCFS0PDFS PDFS7 PDFS6 PDFS� PDFS4 PDFS3 PDFS2 PDFS1 PDFS0PEFS PEFS7 PEFS6 PEFS� PEFS4 PEFS3 PEFS2 PEFS1 PEFS0PFFS PFFS7 PFFS6 PFFS� PFFS4 PFFS3 PFFS2 PFFS1 PFFS0PGFS PGS7 PGFS6 PGFS� PGFS4 PGFS3 PGFS2 PGFS1 PGFS0PHFS PHS7 PHFS6 PHFS� PHFS4 PHFS3 PHFS2 PHFS1 PHFS0SFS SFS7 SFS6 SFS� SFS4 SFS3 SFS2 SFS1 SFS0

Rev. 1.20 �2 ��to�e� 0�� 201� Rev. 1.20 �3 ��to�e� 0�� 201�



PAFS Register – HT69F30A

Bit 7 6 5 4 3 2 1 0Name — PAFS6 PAFS� — PAFS3 — PAFS1 —R/W — R/W R/W — R/W — R/W —P�R — 0 0 — 0 — 0 —

Bit7 Unimplemented,readas“0”Bit6 PAFS6:PortA6FunctionSelection

0:I/O1:TP0_0

Bit5 PAFS5:PortA5FunctionSelection0:I/O1:TP1_1


0:I/O1:TP1_0


0:I/O1:TP0_1

Bit0 Unimplemented,readas“0”

PAFS Register – HT69F40A/HT69F50A



0:I/O1:TP0_0



0:I/O1:TP2_0


0:I/O1:TP0_1


Rev. 1.20 �4 ��to�e� 0�� 201� Rev. 1.20 �� to�e� 0�� 201�



PBFS Register – HT69F40A/HT69F50A

Bit 7 6 5 4 3 2 1 0Name PBFS7 PBFS6 PBFS� PBFS4 — — — —R/W R/W R/W R/W R/W — — — —P�R 0 0 0 0 — — — —

Bit7 PBFS7:PortB7FunctionSelection0:I/O1:TP1B_2



Bit4 PBFS4:PortB4FunctionSelection0:I/O1:TP1A

Bit3~0 Unimplemented,readas“0”

PCFS Register – HT69F30A/HT69F40A/HT69F50A

Bit 7 6 5 4 3 2 1 0Name — — — — — PCFS2 PCFS1 PCFS0R/W — — — — — R/W R/W R/WP�R — — — — — 0 0 0

Bit7~3 Unimplemented,readas“0”Bit2 PCFS2:PortC2FunctionSelection

0:I/O1:C2

Bit1 PCFS1:PortC1FunctionSelection0:I/O1:C1

Bit0 PCFS0:PortC0FunctionSelection0:I/O1:V2

Rev. 1.20 �4 ��to�e� 0�� 201� Rev. 1.20 �� to�e� 0�� 201�



PDFS Register – HT69F30A

Bit 7 6 5 4 3 2 1 0Name PDFS7 PDFS6 PDFS� PDFS4 PDFS3 PDFS2 PDFS1 PDFS0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 1 1 1 1 1 1 1 1

Bit7 PDFS7:PortD7FunctionSelection0:I/O1:SEG7








Rev. 1.20 �6 ��to�e� 0�� 201� Rev. 1.20 �7 ��to�e� 0�� 201�



PDFS Register – HT69F40A/HT69F50A


Bit7 PDFS7:PortD7FunctionSelection0:I/O1:SEG7orTP1B_2



Bit4 PDFS4:PortD4FunctionSelection0:I/O1:SEG4orTP1A





Rev. 1.20 �6 ��to�e� 0�� 201� Rev. 1.20 �7 ��to�e� 0�� 201�



PEFS Register – HT69F30A/HT69F40A/HT69F50A

Bit 7 6 5 4 3 2 1 0Name PEFS7 PEFS6 PEFS� PEFS4 PEFS3 PEFS2 PEFS1 PEFS0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 1 1 1 1 1 1 1 1

Bit7 PEFS7:PortE7FunctionSelection0:I/O1:SEG15








Rev. 1.20 �� to�e� 0�� 201� Rev. 1.20 �9 ��to�e� 0�� 201�



PFFS Register – HT69F30A/HT69F40A/HT69F50A

Bit 7 6 5 4 3 2 1 0Name PFFS7 PFFS6 PFFS� PFFS4 PFFS3 PFFS2 PFFS1 PFFS0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 1 1 1 1 1 1 1 1

Bit7 PFFS7:PortF7FunctionSelection0:I/O1:SEG23








Rev. 1.20 �� to�e� 0�� 201� Rev. 1.20 �9 ��to�e� 0�� 201�



PGFS Register – HT69F40A/HT69F50A

Bit 7 6 5 4 3 2 1 0Name PGFS7 PGFS6 PGFS� PGFS4 PGFS3 PGFS2 PGFS1 PGFS0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 1 1 1 1 1 1 1 1

Bit7 PGFS7:PortG7FunctionSelection0:I/O1:SEG31








Rev. 1.20 90 ��to�e� 0�� 201� Rev. 1.20 91 ��to�e� 0�� 201�



PHFS Register – HT69F50A

Bit 7 6 5 4 3 2 1 0Name PHFS7 PHFS6 PHFS� PHFS4 PHFS3 PHFS2 PHFS1 PHFS0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 1 1 1 1 1 1 1 1

Bit7 PHFS7:PortH7FunctionSelection0:I/O1:SEG39








SFS Register – HT69F30A

Bit 7 6 5 4 3 2 1 0Name — SFS6 SFS� SFS4 — — — —R/W — R/W R/W R/W — — — —P�R — 0 0 0 — — — —

Bit7 Unimplemented,readas“0”Bit6 SFS6:TCK1SourceSelection

0:PA21:PD2

Bit5 SFS5:TCK0SourceSelection0:PA21:PD1

Bit4 SFS4:INT1SourceSelection0:PA01:PD0


Rev. 1.20 90 ��to�e� 0�� 201� Rev. 1.20 91 ��to�e� 0�� 201�



SFS Register – HT69F40A/HT69F50A

Bit 7 6 5 4 3 2 1 0Name SFS7 SFS6 SFS� SFS4 SFS3 SFS2 SFS1 SFS0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0




Bit4 SFS4:INT1SourceSelection0:PA01:PD0

Bit3 SFS3:PD7SpecialFunctionSelection0:SEG71:TP1B_2



Bit0 SFS0:PD4SpecialFunctionSelection0:SEG41:TP1A

Rev. 1.20 92 ��to�e� 0�� 201� Rev. 1.20 93 ��to�e� 0�� 201�



I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

Programming ConsiderationsWithintheuserprogram,oneof thethingsfirst toconsider isport initialisation.Afterareset,allof theI/Odataandportcontrolregisterswillbeset tohigh.ThismeansthatallI/Opinswillbedefaultedtoaninputstate,thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.If theportcontrolregistersarethenprogrammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregistersarefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbitsintheportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

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Generic Input/Output Structure

Rev. 1.20 92 ��to�e� 0�� 201� Rev. 1.20 93 ��to�e� 0�� 201�



Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasuretime.Toimplement timerelatedfunctionseachdeviceincludesseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshaseithertwoorthreeindividualinterrupts.TheadditionofinputandoutputpinsforeachTMensuresthatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.

ThecommonfeaturesofthedifferentTMtypesaredescribedherewithmoredetailedinformationprovidedintheindividualCompact,StandardandEnhancedTMsections.

IntroductionThedevicescontainfromtwoto threeTMsdependinguponwhichdevice isselectedwitheachTMhavingareferencenameofTM0,TM1,andTM2.EachindividualTMcanbecategorisedasacertain type,namelyCompactTypeTM,StandardTypeTMorEnhancedTypeTM.Althoughsimilar innature, thedifferentTMtypesvary in theirfeaturecomplexity.ThecommonfeaturestoalloftheCompact,StandardandEnhancedTMswillbedescribedinthissection, thedetailedoperationregardingeachoftheTMtypeswillbedescribedinseparatesections.ThemainfeaturesanddifferencesbetweenthethreetypesofTMsaresummarisedintheaccompanyingtable.

TM Function CTM STM ETMTime�/Counte� √ √ √I/P Captu�e — √ √Compa�e Mat�h �utput √ √ √PWM Channels 1 1 2Single Pulse �utput — 1 2PWM Alignment Edge Edge Edge & Cent�ePWM Adjustment Pe�iod & Duty Duty o� Pe�iod Duty o� Pe�iod Duty o� Pe�iod

TM Function Summary

EachdeviceintheseriescontainsaspecificnumberofeitherCompactType,StandardTypeandEnhancedTypeTMunitwhichareshowninthetabletogetherwiththeirindividualreferencename,TM0~TM2.

Device TM0 TM1 TM2HT69F30A 10-�it CTM 10-�it STM —HT69F40A 10-�it CTM 10-�it ETM 10-�it STMHT69F�0A 10-�it CTM 10-�it ETM 16-�it STM

TM Name/Type Reference

TM OperationThethreedifferenttypesofTMofferadiverserangeoffunctions,fromsimpletimingoperationstoPWMsignalgeneration.ThekeytounderstandinghowtheTMoperatesistoseeitintermsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

Rev. 1.20 94 ��to�e� 0�� 201� Rev. 1.20 9� ��to�e� 0�� 201�



TM Clock SourceTheclocksourcewhichdrivesthemaincounterineachTMcanoriginatefromvarioussources.Theselectionof therequiredclocksourceis implementedusingtheTnCK2~TnCK0bits intheTMncontrolregisters.TheclocksourcecanbearatioofeitherthesystemclockfSYSortheinternalhighclockfH,thefSUBclocksourceortheexternalTCKnpin.Notethatsettingthesebitstothevalue101willselectareservedclockinput,ineffectdisconnectingtheTMclocksource.TheTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.

TM InterruptsTheCompactandStandardtypeTMseachhavetwointernalinterrupts,oneforeachoftheinternalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.AstheEnhancedtypeTMhasthreeinternalcomparatorsandcomparatorAorcomparatorBorcomparatorPcomparematchfunctions,itconsequentlyhasthreeinternalinterrupts.WhenaTMinterruptisgenerateditcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.

TM External PinsEachoftheTMs,irrespectiveofwhattype,hasoneTMinputpin,withthelabelTCKn.TheTMinputpin,isessentiallyaclocksourcefortheTMandisselectedusingtheTnCK2~TnCK0bitsintheTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThisexternalTMinputpinissharedwithotherfunctionsbutwillbeconnectedtotheinternalTMifselectedusingtheTnCK2~TnCK0bits.TheTMinputpincanbechosentohaveeitherarisingorfallingactiveedge.

TheTMseachhaveoneormoreoutputpinswiththelabelTPn.WhentheTMisintheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalTPnoutputpinisalsothepinwheretheTMgenerates thePWMoutputwaveform.As theTMoutputpinsarepin-sharedwithotherfunction, theTMoutput functionmust firstbesetupusingregisters.Asinglebit inoneof theregistersdeterminesifitsassociatedpinistobeusedasanexternalTMoutputpinorifitistohaveanotherfunction.ThenumberofoutputpinsforeachTMtypeanddeviceisdifferent,thedetailsareprovidedintheaccompanyingtable.

AllTMoutputpinnameshavea“_n”suffix.Pinnamesthatincludea“_1”or“_2”suffixindicatethattheyarefromaTMwithmultipleoutputpins.ThisallowstheTMtogenerateacomplimentaryoutputpair,selectedusingtheI/Oregisterdatabits.

Device CTM STM ETM RegistersHT69F30A TP0_0�TP0_1 TP1_0�TP1_1 — PAFS

HT69F40A TP0_0�TP0_1 TP2_0�TP2_1 TP1A�TP1B_0� TP1B_1� TP1B_2 PAFS� PBFS� PDFS

HT69F�0A TP0_0�TP0_1 TP2_0�TP2_1 TP1A�TP1B_0� TP1B_1� TP1B_2 PAFS� PBFS� PDFS

TM Output Pins

Rev. 1.20 94 ��to�e� 0�� 201� Rev. 1.20 9� ��to�e� 0�� 201�



TM Input/Output Pin Control RegistersSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunction,isimplementedusingoneortworegisters,withasinglebitineachregistercorrespondingtoaTMinput/outputpin.SettingthebithighwillsetupthecorrespondingpinasaTMinput/output, ifresettozerothepinwillretainitsoriginalotherfunction.

TM Input/Output Pin Control Register List• HT69F30A

Register Name

Bit

7 6 5 4 3 2 1 0PAFS — PAFS6 PAFS� — PAFS3 — PAFS1 —SFS — SFS6 SFS� SFS4 — — — —


Register Name

Bit

7 6 5 4 3 2 1 0PAFS — PAFS6 PAFS� — PAFS3 — PAFS1 —PBFS PBFS7 PBFS6 PBFS� PBFS4 — — — —PDFS PDFS7 PDFS6 PDFS� PDFS4 PDFS3 PDFS2 PDFS1 PDFS0SFS SFS7 SFS6 SFS� SFS4 SFS3 SFS2 SFS1 SFS0

PAFS Register – HT69F30A



0:I/O1:TP0_0



0:I/O1:TP1_0


0:I/O1:TP0_1


Rev. 1.20 96 ��to�e� 0�� 201� Rev. 1.20 97 ��to�e� 0�� 201�



PAFS Register – HT69F40A/HT69F50A



0:I/O1:TP0_0



0:I/O1:TP2_0


0:I/O1:TP0_1


PBFS Register – HT69F40A/HT69F50A

Bit 7 6 5 4 3 2 1 0Name PBFS7 PBFS6 PBFS� PBFS4 — — — —R/W R/W R/W R/W R/W — — — —P�R 0 0 0 0 — — — —




Bit4 PBFS4:PortB4FunctionSelection0:I/O1:TP1A


Rev. 1.20 96 ��to�e� 0�� 201� Rev. 1.20 97 ��to�e� 0�� 201�



PDFS Register – HT69F40A/HT69F50A





Bit4 PDFS4:PortD4FunctionSelection0:I/O1:SEG4orTP1A

Bit3~0 PDFS3~PDFS0:PortD3~0FunctionSelectionDescribedelsewhere.

SFS Register – HT69F30A

Bit 7 6 5 4 3 2 1 0Name — SFS6 SFS� SFS4 — — — —R/W — R/W R/W R/W — — — —P�R — 0 0 0 — — — —

Bit7 Unimplemented,readas“0”Bit6 SFS6:TCK1SourceSelection

0:PA21:PD2


Bit4 SFS4:INT1SourceSelectionDescribedelsewhere.


Rev. 1.20 9� ��to�e� 0�� 201� Rev. 1.20 99 ��to�e� 0�� 201�



SFS Register – HT69F40A/HT69F50A

Bit 7 6 5 4 3 2 1 0Name SFS7 SFS6 SFS� SFS4 SFS3 SFS2 SFS1 SFS0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0




Bit4 SFS4:INT1SourceSelectionDescribedelsewhere.




Bit0 SFS0:PD4SpecialFunctionSelection0:SEG41:TP1A

Rev. 1.20 9� ��to�e� 0�� 201� Rev. 1.20 99 ��to�e� 0�� 201�



TM0 (CTM)

0

1

0

1

PA6/TP0_0

PA1/TP0_1

PA2 o� PD1/TCK0

PA6

PA1

0

1

0

1

PAFS6

PAFS3

PA1

PA6

�utput

TCK0 Input

CTM Function Pin Control Block Diagram – HT69F30A/HT69F40A/HT69F50A

TMn (STM)

0

1

0

1

PA3/TPn_0

PA�/TPn_1

PA2 o� PD2/TCKn

PA3

PA�

0

1

0

1

PAFS3

PAFS�

PA�

PA3

PAFS3

PAFS�

Captu�e Input

TCKn Input

�utput

“0”

“0”

1

0

1

0

STM Function Pin Control Block Diagram – HT69F30A (n=1); HT69F40A/HT69F50A (n=2)

Rev. 1.20 100 ��to�e� 0�� 201� Rev. 1.20 101 ��to�e� 0�� 201�



TM1 (ETM)

0

1

0

1

PA0 o� PD3/TCK1

0

1

0

1

CCRB Captu�e Input1

0

1

0

1

0

0

10

1

“0”

PB� o� PD�/TP1B_0

“0”

“0”

TCK1 Input

0

1

PB4� PD4

“0”

CCRB �utput

CCRA Captu�e Input

CCRA �utput PB4 o� PD4/TP1A

PBFS4� PDFS4

1

0

PBFS4� PDFS4

PB�� PD�

PB�� PD�PBFS�� PDFS�

PB6� PD6

PB6� PD6PBFS6� PDFS6

PB7� PD7

PB7� PD7PBFS7� PDFS7

PBFS7� PDFS7

PBFS6� PDFS6

PBFS�� PDFS�

PB6 o� PD6/TP1B_1

PB7 o� PD7/TP1B_2

ETM Function Pin Control Block Diagram – HT69F40A/HT69F50ANote:TheI/OregisterdatabitsshownareusedforTMoutputinversioncontrol.IntheCapture

InputMode,theTMpincontrolregistermustneverenablemorethanoneTMinput.

Rev. 1.20 100 ��to�e� 0�� 201� Rev. 1.20 101 ��to�e� 0�� 201�



Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAandCCRBregisters,beingeither10-bitor16-bit,allhavealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.

AstheCCRAandCCRBregistersareimplementedinthewayshowninthefollowingdiagramandaccessingtheseregisterpairsiscarriedoutinaspecificwaydescribedabove,itisrecommendedtousethe“MOV”instructiontoaccesstheCCRAandCCRBlowbyteregisters,namedTMxALandTMxBL,usingthefollowingaccessprocedures.AccessingtheCCRAorCCRBlowbyteregisterswithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.

Data Bus

�-�it Buffe�

TMxDHTMxDL

TMxBHTMxBL

TMxAHTMxAL

TM Counte� Registe� (Read only)

TM CCRA Registe� (Read/W�ite)

TM CCRB Registe� (Read/W�ite)

Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRBorCCRA♦ Step1.WritedatatoLowByteTMxALorTMxBL

– Notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighByteTMxAHorTMxBH

– Heredataiswrittendirectlytothehighbyteregistersandsimultaneouslydataislatchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRBorCCRA♦ Step1.ReaddatafromtheHighByteTMxDH,TMxAHorTMxBH

– HeredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowByteTMxDL,TMxALorTMxBL– Thisstepreadsdatafromthe8-bitbuffer.

Rev. 1.20 102 ��to�e� 0�� 201� Rev. 1.20 103 ��to�e� 0�� 201�



Compact Type TM – CTMAlthough thesimplest formof the threeTMtypes, theCompactTMtypestill contains threeoperatingmodes,whichareCompareMatchOutput,Timer/EventCounterandPWMOutputmodes.TheCompactTMcanalsobecontrolledwithanexternalinputpinandcandriveoneortwoexternaloutputpins.Thesetwoexternaloutputpinscanbethesamesignalortheinversesignal.

Device TM Type TM Name. TM Input Pin TM Output PinHT69F30AHT69F40AHT69F�0A

10-�it CTM TM0 TCK0 TP0_0� TP0_1

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Compact Type TM Block Diagram (n=0)

Compact TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealso twointernalcomparatorswith thenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPisthreebitswidewhosevalueiscomparedwiththehighestthreebitsinthecounterwhiletheCCRAisthetenbitsandthereforecompareswithallcounterbits.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theTnONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheCompactTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Rev. 1.20 102 ��to�e� 0�� 201� Rev. 1.20 103 ��to�e� 0�� 201�



Compact Type TM Register DescriptionOveralloperationof theCompactTMiscontrolledusingsixregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitCCRAvalue.Theremaining tworegistersarecontrol registerswhichsetup thedifferentoperatingandcontrolmodesaswellasthethreeCCRPbits.

Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0TMnC0 TnPAU TnCK2 TnCK1 TnCK0 Tn�N TnRP2 TnRP1 TnRP0TMnC1 TnM1 TnM0 TnI�1 TnI�0 Tn�C TnP�L TnDPX TnCCLRTMnDL D7 D6 D� D4 D3 D2 D1 D0TMnDH — — — — — — D9 D�TMnAL D7 D6 D� D4 D3 D2 D1 D0TMnAH — — — — — — D9 D�

Compact TM Register List (n=0)

TMnDL RegisterBit 7 6 5 4 3 2 1 0

Name D7 D6 D� D4 D3 D2 D1 D0R/W R R R R R R R RP�R 0 0 0 0 0 0 0 0

Bit7~0 TMnDL:TMnCounterLowByteRegisterbit7~bit0TMn10-bitCounterbit7~bit0

TMnDH RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D�R/W — — — — — — R RP�R — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TMnDH:TMnCounterHighByteRegisterbit1~bit0

TMn10-bitCounterbit9~bit8

TMnAL RegisterBit 7 6 5 4 3 2 1 0

Name D7 D6 D� D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0

Bit7~0 TMnAL:TMnCCRALowByteRegisterbit7~bit0TMn10-bitCCRAbit7~bit0

TMnAH RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D�R/W — — — — — — R/W R/WP�R — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TMnAH:TMnCCRAHighByteRegisterbit1~bit0

TMn10-bitCCRAbit9~bit8

Rev. 1.20 104 ��to�e� 0�� 201� Rev. 1.20 10� ��to�e� 0�� 201�



TMnC0 Register

Bit 7 6 5 4 3 2 1 0Name TnPAU TnCK2 TnCK1 TnCK0 Tn�N TnRP2 TnRP1 TnRP0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0

Bit7 TnPAU:TMnCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 TnCK2~TnCK0:SelectTMnCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:Reserved110:TCKnrisingedgeclock111:TCKnfallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheTM.SelectingtheReservedclockinputwilleffectivelydisabletheinternalcounter.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYS isthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 TnON:TMnCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhen thebitchangesfromhigh to low, the internalcounterwillretainitsresidualvalue.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheTnOCbit,whentheTnONbitchangesfromlowtohigh.

Rev. 1.20 104 ��to�e� 0�� 201� Rev. 1.20 10� ��to�e� 0�� 201�



Bit2~0 TnRP2~TnRP0:TMnCCRP3-bitregister,comparedwiththeTMnCounterbit9~bit7ComparatorPMatchPeriod000:1024TMnclocks001:128TMnclocks010:256TMnclocks011:384TMnclocks100:512TMnclocks101:640TMnclocks110:768TMnclocks111:896TMnclocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter'shighest threebits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theTnCCLRbit isset tozero.SettingtheTnCCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

TMnC1 RegisterBit 7 6 5 4 3 2 1 0

Name TnM1 TnM0 TnI�1 TnI�0 Tn�C TnP�L TnDPX TnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0

Bit7~6 TnM1~TnM0:SelectTMnOperatingMode00:CompareMatchOutputMode01:Undefined10:PWMMode11:Timer/CounterModeThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheTnM1andTnM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 TnIO1~TnIO0:SelectTPn_0,TPn_1outputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:ToggleoutputPWMMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:UndefinedTimer/counterModeunusedThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.

Rev. 1.20 106 ��to�e� 0�� 201� Rev. 1.20 107 ��to�e� 0�� 201�



IntheCompareMatchOutputMode,theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowor totoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheTnOCbit intheTMnC1register.NotethattheoutputlevelrequestedbytheTnIO1andTnIO0bitsmustbedifferentfromtheinitialvaluesetupusingtheTnOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheTnONbitfromlowtohigh.In thePWMMode, theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits. It isnecessarytoonlychangethevaluesof theTnIO1andTnIO0bitsonlyafter theTMnhasbeen switchedoff.UnpredictablePWMoutputswilloccuriftheTnIO1andTnIO0bitsarechangedwhentheTMisrunning.

Bit3 TnOC:TPn_0,TPn_1OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode0:Activelow1:ActivehighThis is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputMode itdetermines the logic levelof theTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesif thePWMsignal isactivehighoractivelow.

Bit2 TnPOL:TPn_0,TPn_1OutputpolarityControl0:Non-invert1:InvertThisbitcontrolsthepolarityoftheTPn_0orTPn_1outputpin.Whenthebit issethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 TnDPX:TMnPWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-periodThisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 TnCCLR:SelectTMnCounterclearcondition0:TMnComparatrorPmatch1:TMnComparatrorAmatchThisbit isused toselect themethodwhichclears thecounter.Remember that theCompactTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheTnCCLRbitisnotusedinthePWMMode.

Rev. 1.20 106 ��to�e� 0�� 201� Rev. 1.20 107 ��to�e� 0�� 201�



Compact Type TM Operating ModesTheCompactTypeTMcanoperateinoneofthreeoperatingmodes,CompareMatchOutputMode,PWMModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheTnM1andTnM0bitsintheTMnC1register.

Compare Match Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1register,shouldbesetto00respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP, theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothTnAFandTnPFinterruptrequestflagsfortheComparatorAandComparatorPrespectively,willbothbegenerated.

IftheTnCCLRbitintheTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theTnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenTnCCLRishighnoTnPFinterruptrequestflagwillbegenerated.IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,value,howeverheretheTnAFinterruptrequestflagwillnotbegenerated.

Asthenameofthemodesuggests,afteracomparisonismade,theTMoutputpinwillchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenanTnAFinterrupt request flagisgeneratedafteracomparematchoccursfromComparatorA.TheTnPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theTnIO1andTnIO0bitsintheTMnC1register.TheTMoutputpincanbeselectedusingtheTnIO1andTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theTnONbitchangesfromlowtohigh,issetupusingtheTnOCbit.NotethatiftheTnIO1andTnIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.20 10� ��to�e� 0�� 201� Rev. 1.20 109 ��to�e� 0�� 201�



Counte� Value

0x3FF

CCRP

CCRA

Tn�N

TnPAU

TnP�L

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM �/P Pin

Time

CCRP=0

CCRP > 0

Counte� ove�flowCCRP > 0Counte� �lea�ed �y CCRP value

Pause

Resume

Stop

Counte� Resta�t

TnCCLR = 0; TnM [1:0] = 00

�utput pin set to initial Level Low if Tn�C=0

�utput Toggle with TnAF flag

Note TnI� [1:0] = 10 A�tive High �utput sele�tHe�e TnI� [1:0] = 11

Toggle �utput sele�t

�utput not affe�ted �y TnAF flag. Remains High until �eset �y Tn�N �it

�utput PinReset to Initial value

�utput �ont�olled �y othe� pin-sha�ed fun�tion

�utput Inve�tswhen TnP�L is high

Compare Match Output Mode – TnCCLR=0

Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.n=0

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Counte� Value

0x3FF

CCRP

CCRA

Tn�N

TnPAU

TnP�L

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM �/P Pin

Time

CCRA=0

CCRA = 0Counte� ove�flowCCRA > 0 Counte� �lea�ed �y CCRA value

Pause

Resume

Stop Counte� Resta�t

TnCCLR = 1; TnM [1:0] = 00

�utput pin set to initial Level Low if Tn�C=0


Note TnI� [1:0] = 10 A�tive High �utput sele�tHe�e TnI� [1:0] = 11





�utput Inve�tswhen TnP�L is high

TnPF not gene�ated

No TnAF flag gene�ated on CCRA ove�flow

�utput does not �hange


Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.TheTnPFflagisnotgeneratedwhenTnCCLR=15.n=0

Rev. 1.20 110 ��to�e� 0�� 201� Rev. 1.20 111 ��to�e� 0�� 201�



Timer/Counter ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignalof fixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.In thePWMmode, theTnCCLRbithasnoeffectonthePWMoperation.Bothof theCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrol thedutycycle.Whichregister isusedtocontroleitherfrequencyordutycycle isdeterminedusing theTnDPXbit in theTMnC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheTnOCbitintheTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

CTM, PWM Mode, Edge-aligned Mode, T0DPX=0CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod 12� 2�6 3�4 �12 640 76� �96 1024Duty CCRA

IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128,

TheCTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

CTM, PWM Mode, Edge-aligned Mode, T0DPX=1CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod CCRADuty 12� 2�6 3�4 �12 640 76� �96 1024

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.

Rev. 1.20 110 ��to�e� 0�� 201� Rev. 1.20 111 ��to�e� 0�� 201�



Counte� Value

CCRP

CCRA

Tn�N

TnPAU

TnP�L

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM �/P Pin(Tn�C=1)

Time

Counte� �lea�ed �y CCRP

Pause Resume Counte� Stop if Tn�N �it low

Counte� Reset when Tn�N �etu�ns high

TnDPX = 0; TnM [1:0] = 10

PWM Duty Cy�le set �y CCRA

PWM �esumes ope�ation

�utput �ont�olled �y othe� pin-sha�ed fun�tion �utput Inve�ts

when TnP�L = 1PWM Pe�iod set �y CCRP


PWM Mode – TnDPX=0

Note:1.HereTnDPX=0--CounterclearedbyCCRP2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=0

Rev. 1.20 112 ��to�e� 0�� 201� Rev. 1.20 113 ��to�e� 0�� 201�



Counte� Value

CCRP

CCRA

Tn�N

TnPAU

TnP�L

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF


Time

Counte� �lea�ed �y CCRA



TnDPX = 1; TnM [1:0] = 10

PWM Duty Cy�le set �y CCRP



when TnP�L = 1PWM Pe�iod set �y CCRA



Note:1.HereTnDPX=1–CounterclearedbyCCRA2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=0

Rev. 1.20 112 ��to�e� 0�� 201� Rev. 1.20 113 ��to�e� 0�� 201�



Standard Type TM – STMTheStandardTypeTMcontains fiveoperatingmodes,which areCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheStandardTMcanalsobecontrolledwithanexternalinputpinandcandriveoneortwoexternaloutputpins.

Device TM Type TM Name. TM Input Pin TM Output PinHT69F30A 10-�it STM TM1 TCK1 TP1_0� TP1_1HT69F40A 10-�it STM TM2 TCK2 TP2_0� TP2_1HT69F�0A 16-�it STM TM2 TCK2 TP2_0� TP2_1

Standard TM OperationTherearetwosizesofStandardTMs,oneis10-bitswideandtheotheris16-bitswide.Atthecoreisa10or16-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.Thesecomparatorswillcompare thevalue in thecounterwithCCRPandCCRAregisters.TheCCRPcomparatoris3or8-bitswidewhosevalueiscomparedthewithhighest3or8bitsinthecounterwhiletheCCRAisthetenorsixteenbitsandthereforecomparesallcounterbits.

Theonlywayofchangingthevalueofthe10or16-bitcounterusingtheapplicationprogram,istoclearthecounterbychangingtheTnONbitfromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheStandardTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

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Standard Type TM Block Diagram (n=1 or 2)

Rev. 1.20 114 ��to�e� 0�� 201� Rev. 1.20 11� ��to�e� 0�� 201�



Standard Type TM Register DescriptionOveralloperationoftheStandardTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10or16-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10or16-bitCCRAvalue.TheremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthethreeoreightCCRPbits.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1�N T1RP2 T1RP1 T1RP0TM1C1 T1M1 T1M0 T1I�1 T1I�0 T1�C T1P�L T1DPX T1CCLRTM1DL D7 D6 D� D4 D3 D2 D1 D0TM1DH — — — — — — D9 D�TM1AL D7 D6 D� D4 D3 D2 D1 D0TM1AH — — — — — — D9 D�

10-bit Standard TM Register List – HT69F30A

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TM2C0 T2PAU T2CK2 T2CK1 T2CK0 T2�N T2RP2 T2RP1 T2RP0TM2C1 T2M1 T2M0 T2I�1 T2I�0 T2�C T2P�L T2DPX T2CCLRTM2DL D7 D6 D� D4 D3 D2 D1 D0TM2DH — — — — — — D9 D�TM2AL D7 D6 D� D4 D3 D2 D1 D0TM2AH — — — — — — D9 D�


Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TM2C0 T2PAU T2CK2 T2CK1 T2CK0 T2�N — — —TM2C1 T2M1 T2M0 T2I�1 T2I�0 T2�C T2P�L T2DPX T2CCLRTM2DL D7 D6 D� D4 D3 D2 D1 D0TM2DH D1� D14 D13 D12 D11 D10 D9 D�TM2AL D7 D6 D� D4 D3 D2 D1 D0TM2AH D1� D14 D13 D12 D11 D10 D9 D�TM2RP D7 D6 D� D4 D3 D2 D1 D0


Rev. 1.20 114 ��to�e� 0�� 201� Rev. 1.20 11� ��to�e� 0�� 201�



10-bit STM Register Definitions – n=1 for HT69F30A and n=2 for HT69F40A• TMnC0 Register

Bit 7 6 5 4 3 2 1 0Name TnPAU TnCK2 TnCK1 TnCK0 Tn�N TnRP2 TnRP1 TnRP0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0

Bit7 TnPAU:TMnCounterPauseControl0:Run1:Pause


Bit6~4 TnCK2, TnCK1, TnCK0:SelectTMnCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:Reserved110:TCKnrisingedgeclock111:TCKnfallingedgeclock

These threebits areused to select theclock source for theTMn.Selecting theReservedclockinputwilleffectivelydisable the internalcounter.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 TnON: TMnCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheTnOCbit,whentheTnONbitchangesfromlowtohigh.

Bit2~0 TnRP2~TnRP0:TMnCCRP3-bitregister,comparedwiththeTMnCounterbit9~bit7ComparatorPMatchPeriod000:1024TMnclocks001:128TMnclocks010:256TMnclocks011:384TMnclocks100:512TMnclocks101:640TMnclocks110:768TMnclocks111:896TMnclocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theTnCCLRbit isset tozero.SettingtheTnCCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

Rev. 1.20 116 ��to�e� 0�� 201� Rev. 1.20 117 ��to�e� 0�� 201�



• TMnC1 Register - 10-bit STM

Bit 7 6 5 4 3 2 1 0Name TnM1 TnM0 TnI�1 TnI�0 Tn�C TnP�L TnDPX TnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0

Bit7~6 TnM1~TnM0:SelectTMnOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheTnM1andTnM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 TnIO1~TnIO0:SelectTPn_0,TPn_1outputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofTPn_0,TPn_101:InputcaptureatfallingedgeofTPn_0,TPn_110:Inputcaptureatfalling/risingedgeofTPn_0,TPn_111:Inputcapturedisabled

Timer/counterModeUnused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode,theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowor totoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheTnOCbit intheTMnC1register.NotethattheoutputlevelrequestedbytheTnIO1andTnIO0bitsmustbedifferentfromtheinitialvaluesetupusingtheTnOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheTnONbitfromlowtohigh.In thePWMMode, theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunction ismodifiedbychanging these twobits. It isnecessary toonlychangethevaluesof theTnIO1andTnIO0bitsonlyafter theTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheTnIO1andTnIO0bitsarechangedwhentheTMisrunning.

Rev. 1.20 116 ��to�e� 0�� 201� Rev. 1.20 117 ��to�e� 0�� 201�



Bit3 TnOC:TPn_0,TPn_1OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode/SinglePulseOutputMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogicleveloftheTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesifthePWMsignalisactivehighoractivelow.

Bit2 TnPOL:TPn_0,TPn_1OutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTPn_0orTPn_1outputpin.Whenthebit issethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 TnDPX:TMnPWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 TnCCLR:SelectTMnCounterclearcondition0:TMnComparatorPmatch1:TMnComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theStandardTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheTnCCLRbitisnotusedinthePWM,SinglePulseorInputCaptureMode.

Rev. 1.20 11� ��to�e� 0�� 201� Rev. 1.20 119 ��to�e� 0�� 201�



• TMnDL Register – 10-bit STM

Bit 7 6 5 4 3 2 1 0Name D7 D6 D� D4 D3 D2 D1 D0R/W R R R R R R R RP�R 0 0 0 0 0 0 0 0

Bit7~0 TMnDL:TMnCounterLowByteRegisterbit7~bit0TMn10-bitCounterbit7~bit0

• TMnDH Register – 10-bit STM

Bit 7 6 5 4 3 2 1 0Name — — — — — — D9 D�R/W — — — — — — R RP�R — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 TMnDH:TMnCounterHighByteRegisterbit1~bit0

TMn10-bitCounterbit9~bit8

• TMnAL Register – 10-bit STM

Bit 7 6 5 4 3 2 1 0Name D7 D6 D� D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0

Bit7~0 TMnAL:TMnCCRALowByteRegisterbit7~bit0TMn10-bitCCRAbit7~bit0

• TMnAH Register – 10-bit STM

Bit 7 6 5 4 3 2 1 0Name — — — — — — D9 D�R/W — — — — — — R/W R/WP�R — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 TMnAH:TMnCCRAHighByteRegisterbit1~bit0

TM110-bitCCRAbit9~bit8

Rev. 1.20 11� ��to�e� 0�� 201� Rev. 1.20 119 ��to�e� 0�� 201�



16-bit STM Register Definitions – HT69F50A• TM2C0 Register

Bit 7 6 5 4 3 2 1 0Name T2PAU T2CK2 T2CK1 T2CK0 T2�N — — —R/W R/W R/W R/W R/W R/W — — —P�R 0 0 0 0 0 — — —

Bit7 T2PAU:TM2CounterPauseControl0:Run1:Pause


Bit6~4 T2CK2, T2CK1, T2CK0:SelectTM2Counterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:Reserved110:TCK2risingedgeclock111:TCK2fallingedgeclock

These threebits areused to select theclock source for theTM2.Selecting theReservedclockinputwilleffectivelydisable the internalcounter.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 T2ON:TM2CounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheT2OCbit,whentheT2ONbitchangesfromlowtohigh.


Rev. 1.20 120 ��to�e� 0�� 201� Rev. 1.20 121 ��to�e� 0�� 201�



• TM2C1 Register – 16-bit STMBit 7 6 5 4 3 2 1 0

Name T2M1 T2M0 T2I�1 T2I�0 T2�C T2P�L T2DPX T2CCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0

Bit7~6 T2M1~T2M0:SelectTM2OperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheT2M1andT2M0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 T2IO1~T2IO0:SelectTP2_0,TP2_1outputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMoutputinactivestate01:PWMoutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofTP2_0,TP2_101:InputcaptureatfallingedgeofTP2_0,TP2_110:Inputcaptureatfalling/risingedgeofTP2_0,TP2_111:Inputcapturedisabled


ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode,theT2IO1andT2IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowor totoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheT2OCbit intheTM2C1register.NotethattheoutputlevelrequestedbytheT2IO1andT2IO0bitsmustbedifferentfromtheinitialvaluesetupusingtheT2OCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheT2ONbitfromlowtohigh.In thePWMMode, theT2IO1andT2IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunction ismodifiedbychanging these twobits. It isnecessary toonlychangethevaluesof theT2IO1andT2IO0bitsonlyafter theTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheT2IO1andT2IO0bitsarechangedwhentheTMisrunning.

Rev. 1.20 120 ��to�e� 0�� 201� Rev. 1.20 121 ��to�e� 0�� 201�



Bit3 T2OC:TP2_0,TP2_1OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh



Bit2 T2POL:TP2_0,TP2_1OutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP2_0orTP2_1outputpin.Whenthebit issethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 T2DPX:TM2PWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 T2CCLR:SelectTM2Counterclearcondition0:TM2ComparatorPmatch1:TM2ComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theStandardTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theT2CCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheT1CCLRbitisnotusedinthePWM,SinglePulseorInputCaptureMode.

Rev. 1.20 122 ��to�e� 0�� 201� Rev. 1.20 123 ��to�e� 0�� 201�



• TM2DL Register – 16-bit STM

Bit 7 6 5 4 3 2 1 0Name D7 D6 D� D4 D3 D2 D1 D0R/W R R R R R R R RP�R 0 0 0 0 0 0 0 0

Bit7~0 TM2DL:TM2CounterLowByteRegisterbit7~bit0TM216-bitCounterbit7~bit0

• TM2DH Register – 16-bit STM

Bit 7 6 5 4 3 2 1 0Name D1� D14 D13 D12 D11 D10 D9 D�R/W R R R R R R R RP�R 0 0 0 0 0 0 0 0

Bit7~0 TM2DH:TM2CounterHighByteRegisterbit7~bit0TM216-bitCounterbit15~bit8

• TM2AL Register – 16-bit STMBit 7 6 5 4 3 2 1 0


Bit7~0 TM2AL:TM2CCRALowByteRegisterbit7~bit0TM216-bitCCRAbit7~bit0

• TM2AH Register – 16-bit STMBit 7 6 5 4 3 2 1 0

Name D1� D14 D13 D12 D11 D10 D9 D�R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0

Bit7~0 TM2AH:TM2CCRAHighByteRegisterbit7~bit0TM216-bitCCRAbit15~bit8

• TM2RP Register – 16-bit STMBit 7 6 5 4 3 2 1 0


Bit7~0 TM2RP:TM2CCRPRegisterbit7~bit0TM2CCRP8-bitregister,comparedwiththeTM2Counterbit15~bit8.ComparatorPMatchPeriod0:65536TM2clocks1~255:256×(1~255)TM2clocks

TheseeightbitsareusedtosetupthevalueontheinternalCCRP8-bitregister,whichare thencomparedwith the internalcounter’shighesteightbits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theT2CCLRbit isset tozero.SettingtheT2CCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighesteightcounterbits, thecomparevaluesexist in256clockcyclemultiples.Clearingalleightbits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

Rev. 1.20 122 ��to�e� 0�� 201� Rev. 1.20 123 ��to�e� 0�� 201�



Standard Type TM Operating ModesTheStandardTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheTnM1andTnM0bitsintheTMnC1register.

Compare Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1register,shouldbesetto00respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP, theotheriswhentheCCRPbitsareallzerowhichallowsthecounter tooverflow.HerebothTnAFandTnPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheTnCCLRbitintheTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theTnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenTnCCLRishighnoTnPFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto"0".

Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenanTnAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheTnPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theTnIO1andTnIO0bitsintheTMnC1register.TheTMoutputpincanbeselectedusingtheTnIO1andTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theTnONbitchangesfromlowtohigh,issetupusingtheTnOCbit.NotethatiftheTnIO1andTnIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.20 124 ��to�e� 0�� 201� Rev. 1.20 12� ��to�e� 0�� 201�



CCRA

CCRP

0x3FF/0xFFFF

Counte� ove�flow

CCRA Int.Flag TnAF

CCRP Int.Flag TnPF

CCRP > 0Counte� �lea�ed �y CCRP value

TM �/P Pin

Tn�N �it

Pause Counte�Reset

�utput Pin set to Initial LevelLow if Tn�C = 0

�utput Togglewith TnAF flag

He�e TnI�1� TnI�0 = 11Toggle �utput Sele�t

Now TnI�1� TnI�0 = 10 A�tive High �utput Sele�t

�utput not affe�ted �yTnAF flag. Remains Highuntil �eset �y Tn�N �it

TnCCLR = 0; TnM[1:0] = 00

TnPAU �it

ResumeStop

Time

CCRP > 0

CCRP = 0

TnP�L �it

�utput PinReset to initial value

�utput inve�tswhen TnP�L is high

�utput �ont�olled�y othe� pin-sha�ed fun�tion

Counte� Value


Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.n=1forHT69F30A;n=2forHT69F40A/HT69F50A

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CCRP

CCRA

0x3FF/0xFFFF

CCRA = 0Counte� ove�flows

CCRP Int.Flag TnPF

CCRA Int.Flag TnAF

CCRA > 0 Counte� �lea�ed �y CCRA value

TM �/P Pin

Tn�N �it

Pause Counte�Reset

�utput PinReset to initial value

�utput Pin set to Initial LevelLow if Tn�C = 0

�utput Togglewith TnAF flag

He�e TnI�1� TnI�0 = 11Toggle �utput Sele�t

Now TnI�1� TnI�0 = 10 A�tive High �utput Sele�t

TnPAU �it

ResumeStop

Time

TnPF notgene�ated

No TnAF flaggene�ated on CCRA ove�flow

�utput doesnot �hange

CCRA = 0

�utput inve�tswhen TnP�L is high

TnP�L �it

TnCCLR = 1; TnM[1:0] = 00

�utput �ont�olled �yothe� pin-sha�ed fun�tion

�utput not affe�ted �yTnAF flag �emains Highuntil �eset �y Tn�N �it

Counte� Value


Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.ATnPFflagisnotgeneratedwhenTnCCLR=15.n=1forHT69F30A;n=2forHT69F40A/HT69F50A

Rev. 1.20 126 ��to�e� 0�� 201� Rev. 1.20 127 ��to�e� 0�� 201�



Timer/Counter ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectivelyandalso theTnIO1andTnIO0bitsshouldbeset to10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible. In thePWMmode, theTnCCLRbithasnoeffectas thePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.WhichregisterisusedtocontroleitherfrequencyordutycycleisdeterminedusingtheTnDPXbitintheTMnC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheTnOCbitintheTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

Rev. 1.20 126 ��to�e� 0�� 201� Rev. 1.20 127 ��to�e� 0�� 201�



10-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod 12� 2�6 3�4 �12 640 76� �96 1024Duty CCRA

IffSYS=16MHz,TMclocksourceselectfSYS/4,CCRP=100bandCCRA=128,

TheSTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%


10-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod CCRADuty 12� 2�6 3�4 �12 640 76� �96 1024

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.

16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0CCRP 1~255 000bPe�iod CCRP×2�6 6��36Duty CCRA

IffSYS=16MHz,TMclocksourceselectfSYS/4,CCRP=2andCCRA=128,

TheSTMPWMoutputfrequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz,duty=128/(2×256)=25%.


16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1CCRP 1~255 000bPe�iod CCRADuty CCRP×2�6 6��36

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbythe(CCRP×256)exceptwhentheCCRPvalueisequalto000b.

Rev. 1.20 12� ��to�e� 0�� 201� Rev. 1.20 129 ��to�e� 0�� 201�



Counte� Value

CCRP

CCRA

Tn�N

TnPAU

TnP�L

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF


Time




TnDPX = 0; TnM [1:0] = 10

PWM Duty Cy�le set �y CCRA



when TnP�L = 1PWM Pe�iod set �y CCRP



Note:1.HereTnDPX=0,CounterclearedbyCCRP2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=1forHT69F30A;n=2forHT69F40A/HT69F50A

Rev. 1.20 12� ��to�e� 0�� 201� Rev. 1.20 129 ��to�e� 0�� 201�



Counte� Value

CCRP

CCRA

Tn�N

TnPAU

TnP�L

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF


Time

Counte� �lea�ed �y CCRA



TnDPX = 1; TnM [1:0] = 10

PWM Duty Cy�le set �y CCRP



when TnP�L = 1PWM Pe�iod set �y CCRA



Note:1.HereTnDPX=1--CounterclearedbyCCRA2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=1forHT69F30A;n=2forHT69F40A/HT69F50A

Rev. 1.20 130 ��to�e� 0�� 201� Rev. 1.20 131 ��to�e� 0�� 201�



Single Pulse ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectivelyandalsotheTnIO1andTnIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheTnONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,theTnONbitcanalsobemadetoautomaticallychangefromlowtohighusingtheexternalTCKnpin,whichwillinturninitiatetheSinglePulseoutput.WhentheTnONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheTnONbit isclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheTnONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaTMinterrupt.Thecountercanonlyberesetback tozerowhentheTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheTnCCLRandTnDPXbitsarenotusedinthisMode.

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Single Pulse Generation

Rev. 1.20 130 ��to�e� 0�� 201� Rev. 1.20 131 ��to�e� 0�� 201�



Counte� Value

CCRP

CCRA

Tn�N

TnPAU

TnP�L

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF


Time

Counte� stopped �y CCRA

PauseResume Counte� Stops

�y softwa�e


TnM [1:0] = 10 ; TnI� [1:0] = 11

Pulse Width set �y CCRA

�utput Inve�tswhen TnP�L = 1

No CCRP Inte��upts gene�ated


TCKn pin

Softwa�e T�igge�

Clea�ed �y CCRA mat�h

TCKn pin T�igge�

Auto. set �y TCKn pin


Softwa�e Clea�

Softwa�e T�igge�Softwa�e

T�igge�

Single Pulse Mode

Note:1.CounterstoppedbyCCRA2.CCRPisnotused3.ThepulsetriggeredbytheTCKnpinorbysettingtheTnONbithigh4.ATCKnpinactiveedgewillautomaticallysettheTnONbithigh5.IntheSinglePulseMode,TnIO[1:0]mustbesetto“11”andcannotbechanged6.n=1forHT69F30A;n=2forHT69F40A/HT69F50A

Rev. 1.20 132 ��to�e� 0�� 201� Rev. 1.20 133 ��to�e� 0�� 201�



Capture Input ModeToselectthismodebitsTnM1andTnM0intheTMnC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheTPn_0orTPn_1pin,whoseactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingtheTnIO1andTnIO0bits in theTMnC1register.Thecounter isstartedwhentheTnONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.

When therequirededge transitionappearson theTPn_0orTPn_1pin thepresentvalue in thecounterwillbelatchedintotheCCRAregistersandaTMinterruptgenerated.IrrespectiveofwhateventsoccurontheTPn_0orTPn_1pinthecounterwillcontinuetofreerununtil theTnONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;in thiswaytheCCRPvaluecanbeusedtocontrol themaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheTnIO1andTnIO0bitscanselecttheactivetriggeredgeontheTPn_0orTPn_1pintobearisingedge,fallingedgeorbothedgetypes.If theTnIO1andTnIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheTPn_0orTPn_1pin,howeveritmustbenotedthatthecounterwillcontinuetorun.

AstheTPn_0orTPn_1pinispinsharedwithotherfunctions,caremustbetakeniftheTMisintheInputCaptureMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.TheTnCCLRandTnDPXbitsarenotusedinthisMode.

Rev. 1.20 132 ��to�e� 0�� 201� Rev. 1.20 133 ��to�e� 0�� 201�



Counte� Value

YY

CCRP

Tn�N

TnPAU

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

CCRA Value

Time


PauseResume

Counte� Reset

TnM [1:0] = 01

TM �aptu�e pin TPn_x

XX

Counte� Stop

TnI� [1:0] Value

XX YY XX YY

A�tive edge A�tive

edgeA�tive edge

00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disa�le Captu�e

Capture Input Mode

Note:1.TnM[1:0]=01andactiveedgesetbytheTnIO[1:0]bits2.ATMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.TnCCLRbitnotused4.Nooutputfunction--TnOCandTnPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero6.n=1forHT69F30A;n=2forHT69F40A/HT69F50A

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Enhanced Type TM – ETMTheEnhancedTypeTMcontains fiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheEnhancedTMcanalsobecontrolledwithanexternalinputpinandcandrivethreeorfourexternaloutputpins.

Device TM Type TM Name. TM Input Pin TM Output PinHT69F30A — — — —HT69F40A HT69F�0A 10-�it ETM TM1 TCK1 TP1A;

TP1B_0� TP1B_1� TP1B_2�

Enhanced TM OperationAtitscoreisa10-bitcount-up/count-downcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Thereare three internalcomparatorswith thenames,ComparatorA,ComparatorBandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwiththeCCRA,CCRBandCCRPregisters.TheCCRPcomparatoris3-bitswidewhosevalueiscomparedwith thehighest3-bits in thecounterwhileCCRAandCCRBare10-bitswideand thereforecomparedwithallcounterbits.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theTnONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheEnhancedTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontroloutputpins.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

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Enhanced Type TM Block Diagram (n=1)

Rev. 1.20 134 ��to�e� 0�� 201� Rev. 1.20 13� ��to�e� 0�� 201�



Enhanced Type TM Register DescriptionOveralloperationoftheEnhancedTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whiletworead/writeregisterpairsexisttostoretheinternal10-bitCCRAandCCRBvalue.TheremainingthreeregistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthethreeCCRPbits.

Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1�N T1RP2 T1RP1 T1RP0

TM1C1 T1AM1 T1AM0 T1AI�1 T1AI�0 T1A�C T1AP�L T1CDN T1CCLR

TM1C2 T1BM1 T1BM0 T1BI�1 T1BI�0 T1B�C T1BP�L T1PWM1 T1PWM0

TM1DL D7 D6 D� D4 D3 D2 D1 D0

TM1DH — — — — — — D9 D�

TM1AL D7 D6 D� D4 D3 D2 D1 D0

TM1AH — — — — — — D9 D�

TM1BL D7 D6 D� D4 D3 D2 D1 D0

TM1BH — — — — — — D9 D�

10-bit Enhanced TM Register List

TM1C0 Register – 10-bit ETM

Bit 7 6 5 4 3 2 1 0Name T1PAU T1CK2 T1CK1 T1CK0 T1�N T1RP2 T1RP1 T1RP0R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0

Bit7 T1PAU:TM1CounterPauseControl0:Run1:Pause


Bit6~4 T1CK2~T1CK0:SelectTM1Counterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:Reserved110:TCK1risingedgeclock111:TCK1fallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheTM.SelectingtheReservedclockinputwilleffectivelydisabletheinternalcounter.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYS isthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Rev. 1.20 136 ��to�e� 0�� 201� Rev. 1.20 137 ��to�e� 0�� 201�



Bit3 T1ON:TM1CounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheT1OCbit,whentheT1ONbitchangesfromlowtohigh.

Bit2~0 T1RP2~T1RP0:TM1CCRP3-bitregister,comparedwiththeTM1Counterbit9~bit7ComparatorPMatchPeriod000:1024TM1clocks001:128TM1clocks010:256TM1clocks011:384TM1clocks100:512TM1clocks101:640TM1clocks110:768TM1clocks111:896TM1clocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounterhighest threebits.The resultof thiscomparisoncanbeselectedtoclear theinternalcounterif theT1CCLRbit isset tozero.SettingtheT1CCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

Rev. 1.20 136 ��to�e� 0�� 201� Rev. 1.20 137 ��to�e� 0�� 201�



TM1C1 Register – 10-bit ETMBit 7 6 5 4 3 2 1 0

Name T1AM1 T1AM0 T1AI�1 T1AI�0 T1A�C T1AP�L T1CDN T1CCLRR/W R/W R/W R/W R/W R/W R/W R R/WP�R 0 0 0 0 0 0 0 0

Bit7~6 T1AM1~T1AM0:SelectTM1CCRAOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremade to theT1AM1andT1AM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 T1AIO1~T1AIO0:SelectTP1AoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMoutputinactivestate01:PWMoutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofTP1A01:InputcaptureatfallingedgeofTP1A10:Inputcaptureatfalling/risingedgeofTP1A11:Inputcapturedisabled


ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode, theT1AIO1andT1AIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheT1AOCbitintheTM1C1register.Notethattheoutputlevel requestedbytheT1AIO1andT1AIO0bitsmustbedifferent fromthe initialvaluesetupusingtheT1AOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheT1ONbitfromlowtohigh.InthePWMMode,theT1AIO1andT1AIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytochangethevaluesoftheT1AIO1andT1AIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheT1AIO1andT1AIO0bitsarechangedwhentheTMisrunning.

Rev. 1.20 13� ��to�e� 0�� 201� Rev. 1.20 139 ��to�e� 0�� 201�



Bit3 T1AOC:TP1AOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh



Bit2 T1APOL:TP1AOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP1Aoutputpin.WhenthebitissethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 T1CDN:TM1Countercountupordownflag0:Countup1:Countdown

Bit0 T1CCLR:SelectTM1Counterclearcondition0:TM1ComparatorPmatch1:TM1ComparatorAmatch

Thisbit isused to select themethodwhichclears the counter.Remember thattheEnhancedTMcontains threecomparators,ComparatorA,ComparatorBandComparatorP,butonlyComparatorAorComparatorPcanbeselectedtocleartheinternalcounter.WiththeT1CCLRbitsethigh, thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheT1CCLRbitisnotusedintheSinglePulseorInputCaptureMode.

Rev. 1.20 13� ��to�e� 0�� 201� Rev. 1.20 139 ��to�e� 0�� 201�



TM1C2 Register – 10-bit ETMBit 7 6 5 4 3 2 1 0

Name T1BM1 T1BM0 T1BI�1 T1BI�0 T1B�C T1BP�L T1PWM1 T1PWM0R/W R/W R/W R/W R/W R/W R/W R R/WP�R 0 0 0 0 0 0 0 0

Bit7~6 T1BM1~T1BM0:SelectTM1CCRBOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/Countermode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremade to theT1BM1andT1BM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 T1BIO1~T1BIO0:SelectTP1B_0,TP1B_1,TP1B_2outputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofTP1B_0,TP1B_1,TP1B_201:InputcaptureatfallingedgeofTP1B_0,TP1B_1,TP1B_210:Inputcaptureatfalling/risingedgeofTP1B_0,TP1B_1,TP1B_211:Inputcapturedisabled


ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode, theT1BIO1andT1BIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheT1BOCbitintheTM1C2register.Notethattheoutputlevel requestedby theT1BIO1andT1BIO0bitsmustbedifferentfromthe initialvaluesetupusingtheT1BOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheT1ONbitfromlowtohigh.InthePWMMode,theT1BIO1andT1BIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits. It isnecessarytoonlychangethevalueof theT1BIO1andT1BIO0bitsonlyafter theTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheT1BIO1andT1BIO0bitsarechangedwhentheTMisrunning.

Rev. 1.20 140 ��to�e� 0�� 201� Rev. 1.20 141 ��to�e� 0�� 201�



Bit3 T1BOC:TP1B_0,TP1B_1,TP1B_2OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh



Bit2 T1BPOL:TP1B_0,TP1B_1,TB1B_2OutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP1B_0,TP1B_1,TP1B_2outputpin.WhenthebitissethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1~0 T1PWM1~T1PWM0:SelectPWMMode00:Edgealigned01:Centrealigned,comparematchoncountup10:Centrealigned,comparematchoncountdown11:Centrealigned,comparematchoncountupordown

TM1DL Register – 10-bit ETMBit 7 6 5 4 3 2 1 0

Name D7 D6 D� D4 D3 D2 D1 D0R/W R R R R R R R RP�R 0 0 0 0 0 0 0 0

Bit7~0 TM1DL:TM1CounterLowByteRegisterbit7~bit0TM110-bitCounterbit7~bit0

TM1DH Register – 10-bit ETMBit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D�R/W — — — — — — R RP�R — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM1DH:TM1CounterHighByteRegisterbit1~bit0

TM110-bitCounterbit9~bit8

Rev. 1.20 140 ��to�e� 0�� 201� Rev. 1.20 141 ��to�e� 0�� 201�



TM1AL Register – 10-bit ETMBit 7 6 5 4 3 2 1 0


Bit7~0 TM1AL:TM1CCRALowByteRegisterbit7~bit0TM110-bitCCRAbit7~bit0

TM1AH Register – 10-bit ETMBit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D�R/W — — — — — — R/W R/WP�R — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM1AH:TM1CCRAHighByteRegisterbit1~bit0

TM110-bitCCRAbit9~bit8

TM1BL Register – 10-bit ETMBit 7 6 5 4 3 2 1 0


Bit7~0 TM1BL:TM1CCRBLowByteRegisterbit7~bit0TM110-bitCCRBbit7~bit0

TM1BH Register – 10-bit ETMBit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D�R/W — — — — — — R/W R/WP�R — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM1BH:TM1CCRBHighByteRegisterbit1~bit0

TM110-bitCCRBbit9~bit8

Rev. 1.20 142 ��to�e� 0�� 201� Rev. 1.20 143 ��to�e� 0�� 201�



Enhanced Type TM Operating ModesTheEnhancedTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheTnAM1andTnAM0bitsintheTMnC1,andtheTnBM1andTnBM0bitsintheTMnC2register.

ETM Operating ModeCCRA Compare Match Output

Mode

CCRA Timer/

Counter Mode

CCRA PWM

Output Mode

CCRASingle Pulse

Output Mode

CCRAInput

Capture Mode

CCRB Compa�e Mat�h �utput Mode √ — — — —

CCRB Time�/Counte� Mode — √ — — —CCRB PWM �utput Mode — — √ — —CCRB Single Pulse �utput Mode — — — √ —

CCRB Input Captu�e Mode — — — — √

“√”: permitted; “—”: not permitt

Compare Output ModeToselect thismode,bitsTnAM1,TnAM0andTnBM1,TnBM0intheTMnC1/TMnC2registersshouldbeallclearedtozero.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP, theother iswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HereboththeTnAFandTnPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheTnCCLRbitintheTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theTnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenTnCCLRishighnoTnPFinterruptrequestflagwillbegenerated.

Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenanTnAForTnBFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorAorComparatorB.TheTnPFinterruptrequest flag,generatedfromacomparematchfromComparatorP,willhavenoeffectontheTMoutputpin.ThewayinwhichtheTMoutputpinchangesstateisdeterminedbytheconditionoftheTnAIO1andTnAIO0bitsintheTMnC1registerforETMCCRA,andtheTnBIO1andTnBIO0bitsintheTMnC2registerforETMCCRB.TheTMoutputpincanbeselectedusingtheTnAIO1,TnAIO0bits(fortheTPnApin)andTnBIO1,TnBIO0bits(fortheTPnB_0,TPnB_1orTPnB_2pins)togohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorAoracomparematchoccursfromComparatorB.TheinitialconditionoftheTMoutputpin,whichissetupaftertheTnONbitchangesfromlowtohigh,issetupusingtheTnAOCorTnBOCbit forTPnAorTPnB_0,TPnB_1,TPnB_2outputpins.Note that if theTnAIO1,TnAIO0andTnBIO1,TnBIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.20 142 ��to�e� 0�� 201� Rev. 1.20 143 ��to�e� 0�� 201�



Counte� Value

0x3FF

CCRP

CCRA

Tn�N

TnPAU

TnAP�L

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TPnA �/P Pin

Time

CCRP=0

CCRP > 0


Pause

Resume

Stop

Counte� Resta�t

TnCCLR = 0; TnAM [1:0] = 00

�utput pin set to initial Level Low if TnA�C=0


Note TnAI� [1:0] = 10 A�tive High �utput sele�tHe�e TnAI� [1:0] = 11





�utput Inve�tswhen TnAP�L is high

ETM CCRA Compare Match Output Mode – TnCCLR=0

Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter2.TheTPnAoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.n=1forHT69F40A/HT69F50A

Rev. 1.20 144 ��to�e� 0�� 201� Rev. 1.20 14� ��to�e� 0�� 201�



Counte� Value

0x3FF

CCRP

CCRB

Tn�N

TnPAU

TnBP�L

CCRP Int. Flag TnPF

CCRB Int. Flag TnBF

TPnB �/P Pin

Time

CCRP=0

CCRP > 0


Pause

Resume

Stop

Counte� Resta�t

TnCCLR = 0; TnBM [1:0] = 00

�utput pin set to initial Level Low if TnB�C=0

�utput Toggle with TnBF flag

Note TnBI� [1:0] = 10 A�tive High �utput sele�tHe�e TnBI� [1:0] = 11


�utput not affe�ted �y TnBF flag. Remains High until �eset �y Tn�N �it



�utput Inve�tswhen TnBP�L is high

ETM CCRB Compare Match Output Mode – TnCCLR=0

Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter2.TheTPnBoutputpiniscontrolledonlybytheTnBFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.n=1forHT69F40A/HT69F50A

Rev. 1.20 144 ��to�e� 0�� 201� Rev. 1.20 14� ��to�e� 0�� 201�



Counte� Value

0x3FF

CCRP

CCRA

Tn�N

TnPAU

TnAP�L

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TPnA �/P Pin

Time

CCRA=0


Pause

Resume


TnCCLR = 1; TnAM [1:0] = 00

�utput pin set to initial Level Low if TnA�C=0


Note TnAI� [1:0] = 10 A�tive High �utput sele�tHe�e TnAI� [1:0] = 11






TnPF not gene�ated


�utput does not �hange

ETM CCRA Compare Match Output Mode – TnCCLR=1

Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter2.TheTPnAoutputpiniscontrolledonlybytheTnAFflag3.TheTPnAoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.TheTnPFflagisnotgeneratedwhenTnCCLR=15.n=1forHT69F40A/HT69F50A

Rev. 1.20 146 ��to�e� 0�� 201� Rev. 1.20 147 ��to�e� 0�� 201�



Counte� Value

0x3FF

CCRB

CCRA

Tn�N

TnPAU

TnBP�L

CCRB Int. Flag TnBF

CCRA Int. Flag TnAF

TPnB �/P Pin

Time

CCRA=0


Pause

Resume


TnCCLR = 1; TnBM [1:0] = 00

�utput pin set to initial Level Low if TnB�C=0

�utput Toggle with TnBF flag

Note TnBI� [1:0] = 10 A�tive High �utput sele�tHe�e TnBI� [1:0] = 11


�utput not affe�ted �y TnBF flag. Remains High until �eset �y Tn�N �it





ETM CCRB Compare Match Output Mode – TnCCLR=1

Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter2.TheTPnBoutputpiniscontrolledonlybytheTnBFflag3.TheTPnBoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.TheTnPFflagisnotgeneratedwhenTnCCLR=15.n=1forHT69F40A/HT69F50A

Rev. 1.20 146 ��to�e� 0�� 201� Rev. 1.20 147 ��to�e� 0�� 201�



Timer/Counter ModeToselectthismode,bitsTnAM1,TnAM0andTnBM1,TnBM0intheTMnC1andTMnC2registersshouldallbesethigh.TheTimer/CounterModeoperates inan identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunctions.

PWM Output ModeToselect thismode, therequiredbitpairs,TnAM1,TnAM0andTnBM1,TnBM0intheTMnC1andTMnC2registersshouldbesetto10respectivelyandalsotheTnAIO1,TnAIO0andTnBIO1,TnBIO0bits shouldbeset to10 respectively.ThePWMfunctionwithin theTMisuseful forapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMmode,theTnCCLRbitisusedtodetermineinwhichwaythePWMperiodiscontrolled.WiththeTnCCLRbitsethigh,thePWMperiodcanbefinelycontrolledusing theCCRAregisters. In thiscase theCCRBregistersareused toset thePWMdutyvalue(forTPnB_xoutputpins).TheCCRPbitsarenotusedandTPnAoutputpinisnotused.ThePWMoutputcanonlybegeneratedontheTPnB_xoutputpins.WiththeTnCCLRbitclearedtozero,thePWMperiodissetusingoneoftheeightvaluesofthethreeCCRPbits, inmultiplesof128.NowbothCCRAandCCRBregisterscanbeusedtosetupdifferentdutycyclevaluestoprovidedualPWMoutputsontheirrelativeTPnAandTPnB_xpins.

TheTnPWM1andTnPWM0bitsdeterminethePWMalignment type,whichcanbeeitheredgeorcentre type. Inedgealignment, the leadingedgeof thePWMsignalswillallbegeneratedconcurrentlywhenthecounter isreset tozero.Withallpowercurrentsswitchingonat thesametime,thismaygiverisetoproblemsinhigherpowerapplications.IncentrealignmentthecentreofthePWMactivesignalswilloccursequentially, thusreducingthelevelofsimultaneouspowerswitchingcurrents.

Interruptflags,oneforeachoftheCCRA,CCRBandCCRP,willbegeneratedwhenacomparematchoccursfromtheComparatorA,ComparatorBorComparatorP.TheTnAOCandTnBOCbitsintheTMnC1andTMnC2registerareusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoTnAIO1,TnAIO0andTnBIO1,TnBIO0bitspairsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnAPOLandTnBPOLbitareusedtoreversethepolarityofthePWMoutputwaveform.

Rev. 1.20 14� ��to�e� 0�� 201� Rev. 1.20 149 ��to�e� 0�� 201�



ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod 12� 2�6 3�4 �12 640 76� �96 1024A Duty CCRAB Duty CCRB

IffSYS=12MHz,TMclocksourceselectfSYS/4,CCRP=100b,CCRA=128andCCRB=256,

TheTPnAPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=5.8594kHz,duty=128/512=25%.

TheTPnB_xPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=5.8594kHz,duty=256/512=50%.

IftheDutyvaluedefinedbyCCRAorCCRBregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1

CCRA 1 2 3 511 512 1021 1022 1023Pe�iod 1 2 3 �11 �12 1021 1022 1023B Duty CCRB

ETM, PWM Mode, Center-aligned Mode, TnCCLR=0

CCRA 001b 010b 011b 100b 101b 110b 111b 000bPe�iod 2�6 �12 76� 1024 12�0 1�36 1792 2046A Duty (CCRA×2)-1B Duty (CCRB×2)-1

ETM, PWM Mode, Center-aligned Mode, TnCCLR=1

CCRA 1 2 3 511 512 1021 1022 1023Pe�iod 2 4 6 1022 1024 2042 2044 2046B Duty (CCRB×2)-1

Rev. 1.20 14� ��to�e� 0�� 201� Rev. 1.20 149 ��to�e� 0�� 201�



Counte� Value

CCRP

CCRA

Tn�N

TnPAU

TnAP�L

CCRA Int. Flag TnAF

CCRB Int. Flag TnBF

TPnA Pin (TnA�C=1)

Time

Counte� Clea�ed �y CCRP

PauseResume Stop Counte�

Resta�t

TnCCLR = 0;TnAM [1:0] = 10� TnBM [1:0] = 10;TnPWM [1:0] = 00




CCRB

CCRP Int. Flag TnPF

TPnB Pin (TnB�C=1)


Duty Cy�le set �y CCRA

Duty Cy�le set �y CCRB

PWM Pe�iod set �y CCRP



ETM PWM Mode – Edge Aligned

Note:1.HereTnCCLR=0thereforeCCRPclearsthecounteranddeterminesthePWMperiod2.TheinternalPWMfunctioncontinuesrunningevenwhenTnAIO[1:0](orTnBIO[1:0])=00or013.CCRAcontrolstheTPnAPWMdutyandCCRBcontrolstheTPnBPWMduty4.n=1forHT69F40A/HT69F50A

Rev. 1.20 1�0 ��to�e� 0�� 201� Rev. 1.20 1�1 ��to�e� 0�� 201�



Counte� Value

CCRA

Tn�N

TnPAU

TnBP�L

CCRB Int. Flag TnBF

Time

Counte� Clea�ed �y CCRA

PauseResume Stop Counte�

Resta�t

TnCCLR = 1; TnBM [1:0] = 10;TnPWM [1:0] = 00

�utput PinReset to Initial value�utput �ont�olled �y

othe� pin-sha�ed fun�tion


CCRB

CCRP Int. Flag TnPF




PWM Pe�iod set �y CCRA

ETM PWM Mode – Edge Aligned

Note:1.HereTnCCLR=1thereforeCCRAclearsthecounteranddeterminesthePWMperiod2.TheinternalPWMfunctioncontinuesrunningevenwhenTnBIO[1:0]=00or013.TheCCRAcontrolstheTPnBPWMperiodandCCRBcontrolstheTPnBPWMduty4.HeretheTMpincontrolregistershouldnotenabletheTPnApinasaTMoutputpin.5.n=1forHT69F40A/HT69F50A

Rev. 1.20 1�0 ��to�e� 0�� 201� Rev. 1.20 1�1 ��to�e� 0�� 201�



Counte� Value

CCRP

CCRA

Tn�N

TnPAU

TnAP�L

CCRA Int. Flag TnAF

CCRB Int. Flag TnBF

TPnA Pin (TnA�C=1)

Time

Pause

ResumeStop

Counte� Resta�t

TnCCLR = 0;TnAM [1:0] = 10� TnBM [1:0] = 10;TnPWM [1:0] = 11


�utput �ont�olled �y �the� pin-sha�ed fun�tion


CCRB

CCRP Int. Flag TnPF





PWM Pe�iod set �y CCRP

ETM PWM Mode – Centre Aligned

Note:1.HereTnCCLR=0thereforeCCRPclearsthecounteranddeterminesthePWMperiod2.TnPWM[1:0]=11thereforethePWMiscentrealigned3.TheinternalPWMfunctioncontinuesrunningevenwhenTnAIO[1:0](orTnBIO[1:0])=00or014.CCRAcontrolstheTPnAPWMdutyandCCRBcontrolstheTPnBPWMduty5.CCRPwillgenerateaninterruptrequestwhenthecounterdecrementstoitszerovalue6.n=1forHT69F40A/HT69F50A

Rev. 1.20 1�2 ��to�e� 0�� 201� Rev. 1.20 1�3 ��to�e� 0�� 201�



Counte� Value

CCRA

Tn�N

TnPAU

TnBP�L

CCRA Int. Flag TnAF

CCRB Int. Flag TnBF

Time

Pause

ResumeStop

Counte� Resta�t

TnCCLR = 1; TnBM [1:0] = 10;TnPWM [1:0] = 11


�utput �ont�olled�y othe� pin-sha�ed fun�tion

CCRB




PWM Pe�iod set �y CCRA


CCRP Int. Flag TnPF

ETM PWM Mode – Centre Aligned

Note:1.HereTnCCLR=1thereforeCCRAclearsthecounteranddeterminesthePWMperiod2.TnPWM[1:0]=11thereforethePWMiscentrealigned3.TheinternalPWMfunctioncontinuesrunningevenwhenTnBIO[1:0]=00or014.CCRAcontrolstheTPnBPWMperiodandCCRBcontrolstheTPnBPWMduty5.CCRPwillgenerateaninterruptrequestwhenthecounterdecrementstoitszerovalue6.n=1forHT69F40A/HT69F50A

Rev. 1.20 1�2 ��to�e� 0�� 201� Rev. 1.20 1�3 ��to�e� 0�� 201�



Single Pulse Output ModeToselectthismode,therequiredbitpairs,TnAM1,TnAM0andTnBM1,TnBM0shouldbesetto10respectivelyandalsothecorrespondingTnAIO1,TnAIO0andTnBIO1,TnBIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.

ThetriggerforthepulseTPnAoutputleadingedgeisalowtohightransitionoftheTnONbit,whichcanbeimplementedusingtheapplicationprogram.ThetriggerforthepulseTPnB_xoutputleadingedge isacomparematchfromComparatorB,whichcanbe implementedusing theapplicationprogram.However in theSinglePulseMode, theTnONbitcanalsobemade toautomaticallychangefromlowtohighusingtheexternalTCKnpin,whichwillinturninitiatetheSinglePulseoutputofTPnA.WhentheTnONbittransitionstoahighlevel, thecounterwillstartrunningandthepulseleadingedgeofTPnAwillbegenerated.TheTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgeofTPnAandTPnB_xwillbegeneratedwhentheTnONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheTnONbitandthusgeneratetheSinglePulseoutputtrailingedgeofTPnAandTPnB_x.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidthofTPnA.The(CCRA-CCRB)valuecanbeusedtocontrolthepulsewidthofTPnB_x.AcomparematchfromComparatorAandComparatorBwillalsogenerateTMinterrupts.ThecountercanonlyberesetbacktozerowhentheTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheTnCCLRbitisalsonotused.

S/W Command SET“Tn�N”

o�TCKn Pin T�ansition

CCRB Leading Edge

CCRA T�ailing Edge

S/W Command CLR“Tn�N”

o�CCRA Compa�e Mat�h

TPnA �utput Pin

TPnB �utput Pin

Pulse Width = (CCRA-CCRB) Value

Pulse Width = CCRA Value

Counte� Value

CCRB

CCRA

0 Time

Tn�N = 1CCRB Compa�e Mat�h

S/W Command CLR“Tn�N”

o�CCRA Compa�e Mat�hCCRB

T�ailing Edge

CCRA Leading Edge

Tn�N �it1 → 0

Tn�N �it1 → 0

Tn�N �it0 → 1

Single Pulse Generation

Rev. 1.20 1�4 ��to�e� 0�� 201� Rev. 1.20 1�� to�e� 0�� 201�



Counte� Value

CCRB

CCRA

Tn�N

TnPAU

TnAP�L

CCRB Int. Flag TnBFCCRA Int. Flag TnAF

TPnA Pin(TnA�C=1)

Time

Counte� stopped �y CCRA

PauseResume Counte� Stops

�y softwa�e


TnAM [1:0] = 10� TnBM [1:0] = 10;TnAI� [1:0] = 11� TnBI� [1:0] = 11

Pulse Width set �y (CCRA-CCRB) �utput Inve�ts

when TnBP�L=1

TCKn pin


Clea�ed �y CCRA mat�h

TCKn pin T�igge�

Auto. set �y TCKn pin


Softwa�e Clea�

Softwa�e T�igge�Softwa�e

T�igge�

TnBP�L

TPnA Pin(TnA�C=0)

TPnB Pin(TnB�C=1)

TPnB Pin(TnB�C=0)

Pulse Width set �y CCRA

�utput Inve�tswhen TnAP�L=1

ETM – Single Pulse Mode

Note:1.CounterstoppedbyCCRA2.CCRPisnotused3.ThepulsetriggeredbytheTCKnpinorbysettingtheTnONbithigh4.ATCKnpinactiveedgewillautomaticallysettheTnONbithigh5.IntheSinglePulseMode,TnAIO[1:0]andTnBIO[1:0]mustbesetto“11”andcannotbechanged6.n=1forHT69F40A/HT69F50A

Rev. 1.20 1�4 ��to�e� 0�� 201� Rev. 1.20 1�� to�e� 0�� 201�



Capture Input ModeToselectthismodebitsTnAM1,TnAM0andTnBM1,TnBM0intheTMnC1andTMnC2registersshouldbeset to01 respectively.Thismodeenablesexternal signals tocaptureandstore thepresentvalueoftheinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheTPnAandTPnB_0,TPnB_1,TPnB_2pins,whoseactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingtheTnAIO1,TnAIO0andTnBIO1,TnBIO0bitsintheTMnC1andTMnC2registers.ThecounterisstartedwhentheTnONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.

WhentherequirededgetransitionappearsontheTPnAandTPnB_0,TPnB_1,TPnB_2pinsthepresentvalueinthecounterwillbelatchedintotheCCRAandCCRBregistersandaTMinterruptgenerated. Irrespectiveofwhateventsoccuron theTPnAandTPnB_0,TPnB_1,TPnB_2pinsthecounterwillcontinuetofreerununtil theTnONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheTnAIO1,TnAIO0andTnBIO1,TnBIO0bitscanselecttheactivetriggeredgeontheTPnAandTPnB_0,TPnB_1,TPnB_2pinstobearisingedge,fallingedgeorbothedgetypes.IftheTnAIO1,TnAIO0andTnBIO1,TnBIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheTPnAandTPnB_0,TPnB_1,TPnB_2pins,howeveritmustbenotedthatthecounterwillcontinuetorun.

AstheTPnAandTPnB_0,TPnB_1,TPnB_2pinsarepinsharedwithotherfunctions,caremustbetakenif theTMisintheCaptureInputMode.Thisisbecauseif thepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.TheTnCCLR,TnAOC,TnBOC,TnAPOLandTnBPOLbitsarenotusedinthismode.

Rev. 1.20 1�6 ��to�e� 0�� 201� Rev. 1.20 1�7 ��to�e� 0�� 201�



Counte� Value

YY

CCRP

Tn�N

TnPAU

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

CCRA Value

Time


PauseResume

Counte� Reset

TnAM [1:0] = 01

TM �aptu�e pin TPnA

XX

Counte� Stop

TnAI� [1:0] Value

XX YY XX YY

A�tive edge A�tive

edgeA�tive edge

00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disa�le Captu�e

ETM CCRA Capture Input Mode

Note:1.TnAM[1:0]=01andactiveedgesetbytheTnAIO[1:0]bits2.TheTMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.TnCCLRbitnotused4.Nooutputfunction--TnAOCandTnAPOLbitsnotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero6.n=1forHT69F40A/HT69F50A

Rev. 1.20 1�6 ��to�e� 0�� 201� Rev. 1.20 1�7 ��to�e� 0�� 201�



CCRP

Counte� ove�flow

CCRP Int.Flag TnPF

CCRB Int.Flag TnBF

Tn�N �it

Pause

Counte�Reset

TnPAU �it

Resume

Stop

YY

XX

CCRBValue XX

TM Captu�e Pin

YY

TnBI�1� TnBI�0Value 00 - Rising edge 01 - Falling edge 11 - Disa�le Captu�e

A�tiveedge

A�tiveedge

XX

10 - Both edges

A�tiveedges

YY

TnBM1� TnBM0 = 01

Time

Counte�Value

ETM CCRB Capture Input Mode

Note:1.TnBM[1:0]=01andactiveedgesetbytheTnBIO[1:0]bits2.TheTMCaptureinputpinactiveedgetransfersthecountervaluetoCCRB3.TnCCLRbitnotused4.Nooutputfunction--TnBOCandTnBPOLbitsnotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero6.n=1forHT69F40A/HT69F50A

Rev. 1.20 1�� to�e� 0�� 201� Rev. 1.20 1�9 ��to�e� 0�� 201�



InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModulerequiresmicrocontrollerattention, theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Thedevicecontainsseveralexternalinterruptandinternalinterruptsfunctions.TheexternalinterruptsaregeneratedbytheactionoftheexternalINT0~INT1pins,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchastheTMs,TimeBaseandLVD.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.Thenumberofregistersdependsuponthedevicechosenbutfall intothreecategories.ThefirstistheINTC0~INTC1registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI2registerswhichsetuptheMulti-functioninterrupts.FinallythereisanINTEGregistertosetuptheexternalinterrupttriggeredgetype.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.

Function Enable Bit Request Flag NotesGlo�al EMI — —INTn Pin INTnE INTnF n=0~1Time Base TBnE TBnF n=0~1Multi-fun�tion MFnE MFnF n=0~2LVD LVE LVF —EEPR�M DEE DEF —

TMTnPE TnPF n=0~2TnAE TnAF n=0~2TnBE TnBF n=1

Interrupt Register Bit Naming Conventions

Rev. 1.20 1�� to�e� 0�� 201� Rev. 1.20 1�9 ��to�e� 0�� 201�



Interrupt Register Contents• HT69F30A

NameBit

7 6 5 4 3 2 1 0INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0INTC0 — TB0F INT1F INT0F TB0E INT1E INT0E EMIINTC1 MF2F MF1F MF0F TB1F MF2E MF1E MF0E TB1EMFI0 — — T0AF T0PF — — T0AE T0PEMFI1 — — T1AF T1PF — — T1AE T1PEMFI2 — — DEF LVF — — DEE LVE


NameBit

7 6 5 4 3 2 1 0INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0INTC0 — TB0F INT1F INT0F TB0E INT1E INT0E EMIINTC1 MF2F MF1F MF0F TB1F MF2E MF1E MF0E TB1EMFI0 T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PEMFI1 — T1BF T1AF T1PF — T1BE T1AE T1PEMFI2 — — DEF LVF — — DEE LVE

INTEG Register

Bit 7 6 5 4 3 2 1 0Name — — — — INT1S1 INT1S0 INT0S1 INT0S0R/W — — — — R/W R/W R/W R/WP�R — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3~2 INT1S1, INT1S0:interruptedgecontrolforINT1pin

00:Disable01:Risingedge10:Fallingedge11:Risingandfallingedges

Bit1~0 INT0S1, INT0S0:interruptedgecontrolforINT0pin00:Disable01:Risingedge10:Fallingedge11:Risingandfallingedge

Rev. 1.20 160 ��to�e� 0�� 201� Rev. 1.20 161 ��to�e� 0�� 201�



INTC0 Register

Bit 7 6 5 4 3 2 1 0Name — TB0F INT1F INT0F TB0E INT1E INT0E EMIR/W — R/W R/W R/W R/W R/W R/W R/WP�R — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6 TB0F:TimeBase0interruptrequestflag

0:Norequest1:Interruptrequest

Bit5 INT1F:INT1interruptrequestflag0:Norequest1:Interruptrequest

Bit4 INT0F:INT0interruptrequestflag0:Norequest1:Interruptrequest

Bit3 TB0E:TimeBase0interruptcontrol0:Disable1:Enable

Bit2 INT1E:INT1interruptcontrol0:Disable1:Enable

Bit1 INT0E:INT0interruptcontrol0:Disable1:Enable

Bit0 EMI:Globalinterruptcontrol0:Disable1:Enable

Rev. 1.20 160 ��to�e� 0�� 201� Rev. 1.20 161 ��to�e� 0�� 201�



INTC1 Register

Bit 7 6 5 4 3 2 1 0Name MF2F MF1F MF0F TB1F MF2E MF1E MF0E TB1ER/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0

Bit7 MF2F:Multi-functioninterrupt2requestflag0:Norequest1:Interruptrequest



Bit4 TB1F:TimeBase1interruptrequestflag0:Norequest1:Interruptrequest

Bit3 MF2E:Multi-functioninterrupt2control0:Disable1:Enable



Bit0 TB1E:TimeBase1interruptcontrol0:Disable1:Enable

MFI0 Register – HT69F30A

Bit 7 6 5 4 3 2 1 0Name — — T0AF T0PF — — T0AE T0PER/W — — R/W R/W — — R/W R/WP�R — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas“0”Bit5 T0AF:TM0ComparatorAmatchinterruptrequestflag


Bit4 T0PF:TM0ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas“0”Bit1 T0AE:TM0ComparatorAmatchinterruptcontrol

0:Disable1:Enable

Bit0 T0PE:TM0ComparatorPmatchinterruptcontrol0:Disable1:Enable

Rev. 1.20 162 ��to�e� 0�� 201� Rev. 1.20 163 ��to�e� 0�� 201�



MFI0 Register – HT69F40A/HT69F50A

Bit 7 6 5 4 3 2 1 0Name T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PER/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 0 0 0 0 0 0

Bit7 T2AF:TM2ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest




Bit3 T2AE:TM2ComparatorAmatchinterruptcontrol0:Disable1:Enable




MFI1 Register – HT69F30A

Bit 7 6 5 4 3 2 1 0Name — — T1AF T1PF — — T1AE T1PER/W — — R/W R/W — — R/W R/WP�R — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas“0”Bit5 T1AF:TM1ComparatorAmatchinterruptrequestflag



Bit3~2 Unimplemented,readas“0”Bit1 T1AE:TM1ComparatorAmatchinterruptcontrol

0:Disable1:Enable


Rev. 1.20 162 ��to�e� 0�� 201� Rev. 1.20 163 ��to�e� 0�� 201�



MFI1 Register – HT69F40A/HT69F50A

Bit 7 6 5 4 3 2 1 0Name — T1BF T1AF T1PF — T1BE T1AE T1PER/W — R/W R/W R/W — R/W R/W R/WP�R — 0 0 0 — 0 0 0

Bit7 Unimplemented,readas“0”Bit6 T1BF:TM1ComparatorBmatchinterruptrequestflag




Bit3 Unimplemented,readas“0”Bit2 T1BE:TM1ComparatorBmatchinterruptcontrol

0:Disable1:Enable



MFI2 Register

Bit 7 6 5 4 3 2 1 0Name — — DEF LVF — — DEE LVER/W — — R/W R/W — — R/W R/WP�R — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas“0”Bit5 DEF:DataEEPROMinterruptrequestflag


Bit4 LVF:LVDinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas“0”Bit1 DEE:DataEEPROMInterruptControl

0:Disable1:Enable

Bit0 LVE:LVDInterruptControl0:Disable1:Enable

Rev. 1.20 164 ��to�e� 0�� 201� Rev. 1.20 16� ��to�e� 0�� 201�



Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparatorP,ComparatorAorComparatorBmatchetc, therelevant interruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha"RETI" ,whichretrieves theoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagramswith theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.

Rev. 1.20 164 ��to�e� 0�� 201� Rev. 1.20 16� ��to�e� 0�� 201�



INT0 Pin

INT1 Pin

INT0F

INT1F

INT0E

INT1E

EMI 04H

EMI 0�H

M. Fun�t. 0 MF0F MF0E

0CH

10H

14H

Time Base 0 TB0F TB0E

1�H

LVD LVF LVE 1CH

Inte��upt Name

Request Flags

Ena�le Bits

Maste� Ena�le Vector

EMI auto disa�led in ISR

P�io�ityHigh

Low

TM1 P T1PF T1PE

TM1 A T1AF T1AE


TM0 P T0PF T0PE

TM0 A T0AF T0AE

Inte��upts �ontained within Multi-Fun�tion Inte��upts

xxE Ena�le Bits

xxF Request Flag� auto �eset in ISR

LegendxxF Request Flag� no auto �eset in ISR

EMI

EMI


EEPR�M DEF DEE

EMI

Time Base 1 TB1F TB1E EMI

EMI

Interrupt Structure – HT69F30A

INT0 Pin

INT1 Pin

INT0F

INT1F

INT0E

INT1E

EMI 04H

EMI 0�H


0CH

10H

14H

Time Base 0 TB0F TB0E

1�H

LVD LVF LVE

1CH

Inte��upt Name

Request Flags

Ena�le Bits

Maste� Ena�le Vector

EMI auto disa�led in ISR

P�io�ityHigh

Low

TM1 P T1PF T1PE

TM1 A T1AF T1AE M. Fun�t. 1 MF1F MF1E

TM0 P T0PF T0PE

TM0 A T0AF T0AE

Inte��upts �ontained within Multi-Fun�tion Inte��upts

xxE Ena�le Bits

xxF Request Flag� auto �eset in ISR

LegendxxF Request Flag� no auto �eset in ISR

EMI

EMI


EEPR�M DEF DEE

EMI

TM2 P T2PF T2PE

TM2 A T2AF T2AE

TM1 B T1BF T1BE

Time Base 1 TB1F TB1E EMI

EMI

Interrupt Structure – HT69F40A/HT69F50A

Rev. 1.20 166 ��to�e� 0�� 201� Rev. 1.20 167 ��to�e� 0�� 201�



External InterruptTheexternal interruptsarecontrolledbysignal transitionsonthepinsINT0~INT1.Anexternalinterruptrequestwill takeplacewhentheexternalinterruptrequestflags,INT0F~INT1F,areset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternalinterruptpins.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveexternalinterruptenablebit,INT0E~INT1E,mustfirstbeset.AdditionallythecorrectinterruptedgetypemustbeselectedusingtheINTEGregistertoenabletheexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinsarepin-sharedwithI/Opins, theycanonlybeconfiguredasexternal interruptpins if theirexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeenset.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestflags,INT0F~INT1F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinswillremainvalidevenifthepinisusedasanexternalinterruptinput.

TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.

Multi-function InterruptWithin thisdevice thereareup to threeMulti-functioninterrupts.Unlike theother independentinterrupts, theseinterruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheTMInterrupts,EEPROMInterruptandLVDinterrupt.

AMulti-functioninterruptrequestwilltakeplacewhenanyoftheMulti-functioninterruptrequestflags,MFnF,areset.TheMulti-function interrupt flagswillbesetwhenanyof their includedfunctionsgeneratean interrupt request flag.Toallow theprogram tobranch to its respectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecalltooneoftheMulti-functioninterruptvectorswilltakeplace.Whentheinterruptisserviced,therelatedMulti-Functionrequestflag,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhentheinterruptisserviced,therequestflagsfromtheoriginalsourceoftheMulti-functioninterrupts, namely theTM Interrupts, EEPROM Interrupt andLVD interruptwill not beautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.

Rev. 1.20 166 ��to�e� 0�� 201� Rev. 1.20 167 ��to�e� 0�� 201�



Time Base InterruptThefunctionoftheTimeBaseInterruptistoprovideregulartimesignalintheformofaninternalinterrupt. It iscontrolledby theoverflowsignal fromits internal timer.When thishappens itsinterruptrequestflag,TBnF,willbeset.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMIandTimeBaseenablebit,TBnE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecall to itsrespectivevector locationwill takeplace.Whentheinterrupt isserviced, theinterruptrequest flag,TBnF,willbeautomaticallyresetand theEMIbitwillbecleared todisableotherinterrupts.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.Itsclocksource,fTB,originatesfromtheinternalclocksourcefSUBorfSYS/4.Andthenpassesthroughadivider, thedivisionratioofwhichisselectedbyprogrammingtheappropriatebits intheTBCregister toobtain longer interruptperiodswhosevalueranges.Theclocksourcewhich in turncontrolstheTimeBaseinterruptperiodisselectedusingabitintheTBCregister.

TBC Register

Bit 7 6 5 4 3 2 1 0Name TB�N TBCK TB11 TB10 LXTLP TB02 TB01 TB00R/W R/W R/W R/W R/W R/W R/W R/W R/WP�R 0 0 1 1 0 1 1 1

Bit7 TBON:TimeBase0andTimeBase1Enable/Disable0:Disable1:Enable

Bit6 TBCK:TBClockfTBSelect0:fSUB

1:fSYS/4Bit5~4 TB11~TB10:TimeBase1Time-outPeriodSelection

00:212/fTB01:213/fTB10:214/fTB11:215/fTB

Bit3 LXTLP:LXTLowPowerControl0:Disable(LXTquickstart-up)1:Enable(LXTlowpowerstart-up)

Bit2~0 TB02~TB00:TimeBase0Time-outPeriod000:28/fTB001:29/fTB010:210/fTB011:211/fTB100:212/fTB101:213/fTB110:214/fTB111:215/fTB

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Time Base Interrupt

Rev. 1.20 16� ��to�e� 0�� 201� Rev. 1.20 169 ��to�e� 0�� 201�



EEPROM InterruptTheEEPROMinterrupt iscontainedwithintheMulti-functionInterrupt.AnEEPROMInterruptrequestwill takeplacewhentheEEPROMInterruptrequestflag,DEF,isset,whichoccurswhenanEEPROMwriteoperationends.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtheEEPROMInterruptenablebit,DEE,andMuti-functioninterruptenablebits,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMwriteoperationends,asubroutinecalltotherespectiveMulti-functionInterruptvector,willtakeplace.WhentheEEPROMInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheDEFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

LVD InterruptTheLowVoltageDetector Interrupt iscontainedwithin theMulti-function Interrupt.AnLVDInterruptrequestwill takeplacewhentheLVDInterruptrequest flag,LVF, isset,whichoccurswhentheLowVoltageDetectorfunctiondetectsalowpowersupplyvoltage.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,LowVoltageInterruptenablebit,LVE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotheMulti-functionInterruptvector,willtakeplace.WhentheLowVoltageInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheLVFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

TM InterruptsTheCompactandStandardTypeTMshavetwointerruptseach,whiletheEnhancedTypeTMhasthreeinterrupts.AlloftheTMinterruptsarecontainedwithintheMulti-functionInterrupts.ForeachoftheCompactandStandardTypeTMstherearetwointerruptrequestflagsTnPFandTnAFandtwoenablebitsTnPEandTnAE.FortheEnhancedTypeTMtherearethreeinterruptrequestflagsTnPF,TnAFandTnBFandthreeenablebitsTnPE,TnAEandTnBE.ATMinterruptrequestwilltakeplacewhenanyoftheTMrequestflagsareset,asituationwhichoccurswhenaTMcomparatorP,AorBmatchsituationhappens.

Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,respectiveTMInterruptenablebit,andrelevantMulti-functionInterruptenablebit,MFnE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecalltotherelevantMulti-functionInterruptvectorlocations,willtakeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.

Rev. 1.20 16� ��to�e� 0�� 201� Rev. 1.20 169 ��to�e� 0�� 201�



Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpins,alowpowersupplyvoltageorcomparatorinputchangemaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremust thereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptserviceroutineisexecuted,asonlytheMulti-functioninterruptrequestflags,MF0F~MF2F,willbeautomaticallycleared, the individualrequestflagfor thefunctionneeds tobeclearedbytheapplicationprogram.

It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

Rev. 1.20 170 ��to�e� 0�� 201� Rev. 1.20 171 ��to�e� 0�� 201�



Low Voltage Detector – LVDEachdevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenabledthedevicetomonitorthepowersupplyvoltage,VDD,andprovideawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.

LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebitsinthisregister,VLVD2~VLVD0,areusedtoselectoneofeightfixedvoltagesbelowwhichalowvoltageconditionwillbedetemined.AlowvoltageconditionisindicatedwhentheLVDObitisset.IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheLVDENbitisusedtocontroltheoverallon/offfunctionofthelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebittozerowillswitchofftheinternallowvoltagedetectorcircuits.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.

LVDC Register

Bit 7 6 5 4 3 2 1 0Name — — LVD� LVDEN — VLVD2 VLVD1 VLVD0R/W — — R R/W — R/W R/W R/WP�R — — 0 0 — 0 0 0

Bit7~6 Unimplemented,readas“0”Bit5 LVDO:LVDOutputFlag

0:NoLowVoltageDetected1:LowVoltageDetected

Bit4 LVDEN:LowVoltageDetectorEnable/Disable0:Disable1:Enable

Bit3 Unimplemented,readas“0”Bit2~0 VLVD2~VLVD0:SelectLVDVoltage

000:2.0V001:2.2V010:2.4V011:2.7V100:3.0V101:3.3V110:3.6V111:4.0V

Rev. 1.20 170 ��to�e� 0�� 201� Rev. 1.20 171 ��to�e� 0�� 201�



LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasarangeofbetween2.0Vand4.0V.Whenthepowersupplyvoltage,VDD,fallsbelowthispre-determinedvalue,theLVDObitwillbesethighindicatinga lowpowersupplyvoltagecondition.TheLowVoltageDetectorfunctionissuppliedbyareferencevoltagewhichwillbeautomaticallyenabled.WhenthedeviceispowereddownthelowvoltagedetectorwillremainactiveiftheLVDENbitishigh.AfterenablingtheLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,atthevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.

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TheLowVoltageDetectoralsohasitsowninterruptwhichiscontainedwithinoneoftheMulti-functioninterrupts,providinganalternativemeansoflowvoltagedetection,inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.WhenthedeviceispowereddowntheLowVoltageDetectorwillremainactiveiftheLVDENbitishigh.Inthiscase,theLVFinterruptrequestflagwillbeset,causinganinterrupttobegeneratedifVDDfallsbelowthepresetLVDvoltage.Thiswillcausethedevicetowake-upfromtheSLEEPorIDLEMode,howeveriftheLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVFflagshouldbefirstsethighbeforethedeviceenterstheSLEEPorIDLEMode.

WhenLVDfunctionisenabled,itisrecommendedtoclearLVDflagfirst,andthenenablesinterruptfunctiontoavoidmistakeaction.

Rev. 1.20 172 ��to�e� 0�� 201� Rev. 1.20 173 ��to�e� 0�� 201�



LCD DriverFor largevolumeapplications,which incorporateanLCDin theirdesign, theuseofacustomdisplayratherthanamoreexpensivecharacterbaseddisplayreducescostssignificantly.However,thecorrespondingCOMandSEGsignalsrequired,whichvaryinbothamplitudeandtime,todrivesuchacustomdisplayrequiremanyspecialconsiderationsforproperLCDoperation tooccur.ThesedevicesallcontainanLCDDriverfunction,whichwiththeirinternalLCDsignalgeneratingcircuitryandvariousoptions,willautomaticallygeneratethesetimeandamplitudevaryingsignalstoprovideameansofdirectdrivingandeasyinterfacingtoarangeofcustomLCDs.

AlldevicesincludeawiderangeofoptionstoenableLCDdisplaysofvarioustypestobedriven.Thetableshowstherangeofoptionsavailableacrossthedevicerange.

Device Duty Bias Bias Type Wave TypeHT69F30A

1/3 o� 1/4 1/2 o� 1/3 R o� C A o� BHT69F40AHT69F�0A

LCD Selections

LCD MemoryAnareaofDataMemoryisespeciallyreservedforusefor theLCDdisplaydata.Thisdataareaisknownas theLCDMemory.Anydatawrittenherewillbeautomaticallyreadbythe internaldisplaydrivercircuits,whichwillinturnautomaticallygeneratethenecessaryLCDdrivingsignals.ThereforeanydatawrittenintothisMemorywillbeimmediatelyreflectedintotheactualdisplayconnectedtothemicrocontroller.

AstheLCDMemoryaddressesoverlapthoseoftheGeneralPurposeDataMemory,itsstoredinitsownindependentBank1area.TheDataMemoryBanktobeusedischosenbyusingtheBankPointer,whichisaspecialfunctionregisterintheDataMemory,withthename,BP.ToaccesstheLCDMemorythereforerequiresfirstthatBank1isselectedbywritingavalueof01HtotheBPregister.Afterthis,thememorycanthenbeaccessedbyusingindirectaddressingthroughtheuseofMemoryPointerMP1.WithBank1selected, thenusingMP1toreadorwrite tothememoryarea,startingwithaddress“80H”forallthedevices,willresultinoperationstotheLCDMemory.DirectlyaddressingtheDisplayMemoryisnotapplicableandwillresult inadataaccess to theBank0GeneralPurposeDataMemory.

TheaccompanyingLCDMemoryMapdiagramsshowshowtheinternalLCDMemoryismappedtotheSegmentsandCommonsofthedisplayforthedevices.LCDMemoryMapsfordeviceswithsmallermemorycapacitiescanbeextrapolatedfromthesediagrams.

Rev. 1.20 172 ��to�e� 0�� 201� Rev. 1.20 173 ��to�e� 0�� 201�



C�

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HT69F30A LCD Memory MapC

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HT69F40A LCD Memory Map

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HT69F50A LCD Memory Map

Rev. 1.20 174 ��to�e� 0�� 201� Rev. 1.20 17� ��to�e� 0�� 201�



LCD RegisterThereisonecontrolregister,namedasLCDC,intheDataMemoryusedtocontrolthevarioussetupfeaturesoftheLCDDriver.

Variousbits inthisregisterscontrolfunctionssuchasLCDwavetype,dutytype,bias type,biasresistorselectionaswellasoverallLCDenableanddisable.TheLCDENbitintheLCDCregister,whichprovidestheoverallLCDenable/disablefunction,willonlybeeffectivewhenthedeviceisintheNOAMRL,SLOWorIDLEMode.IfthedeviceisintheSLEEPModethenthedisplaywillalwaysbedisabled.Bits,RSEL0andRSEL1,intheLCDCregisterselecttheinternalbiasresistorstosupplytheLCDpanelwiththecorrectbiasvoltages.AchoicetobestmatchtheLCDpanelusedintheapplicationcanbeselectedalsotominimisebiascurrent.TheTYPEbitinthesameregisterisusedtoselectwhetherTypeAorTypeBLCDcontrolsignalsareused.

LCDC Register

Bit 7 6 5 4 3 2 1 0Name TYPE — DTYC — BIAS RSEL1 RSEL0 LCDENR/W R/W — R/W — R/W R/W R/W R/WP�R 0 — 0 — 0 0 0 0

Bit7 TYPE:LCDWaveTypeControl0:TypeA1:TypeB

Bit6 Unimplemented,readas“0”Bit5 DTYC:LCDDutyControl

0:1/3duty1:1/4duty

Bit4 Unimplemented,readas“0”Bit3 BIAS:LCDBiasControl

0:1/2bias1:1/3bias

Bit2~1 RSEL1~RSEL0:LCDBiasResistorSelection1/3Bias00:600kΩ01:300kΩ10:100kΩ11:50kΩ

1/2Bias00:400kΩ01:200kΩ10:67kΩ11:34kΩ

Bit0 LCDEN:LCDEnableControl0:Disable1:Enable

IntheNORMAL,SLOWorIDLEmode,theLCDon/offfunctioncanbecontrolledbythisbit.intheSLEEPmode,theLCDfunctionisalwaysoff.

Rev. 1.20 174 ��to�e� 0�� 201� Rev. 1.20 17� ��to�e� 0�� 201�



LCD Reset FunctionTheLCDhasaninternalresetfunctionthat isanORfunctionof theinvertedLCDENbit intheLCDCregisterandtheSleepfunction.WhentheLCDENbitissetto1toenabletheLCDdriverfunctionbeforethedeviceenterstheSLEEPmode,theLCDfunctionwillberesetafterthedeviceenterstheSLEEPmode.ClearingtheLCDENbittozerowillalsoresettheLCDfunction.

LCDEN SLEEP Mode Reset LCD0 �ff √0 �n √1 �ff x1 �n √

LCD Reset Function

Clock SourceTheLCDclocksource is the internalclocksignal, fSUB,dividedby8,usingan internaldividercircuit.ThefSUBinternalclockissuppliedbyeithertheLIRCorLXToscillator,thechoiceofwhichisdeterminedbyaconfigurationoption.ForproperLCDoperation,thisarrangementisprovidedtogenerateanidealLCDclocksourcefrequencyof4kHz.

fSUB Clock Source LCD Clock FrequencyLIRC 4kHzLXT 4kHz

LCD Clock Source

LCD Driver OutputThenumberofCOMandSEGoutputssuppliedbytheLCDdriver,aswellasitsbiasinganddutyselections,aredependentuponhowtheLCDcontrolbitsareprogrammed.TheBiasType,whetherCorRtypeisselectedviaaconfigurationoption.

ThenatureofLiquidCrystalDisplaysrequirethatonlyACvoltagescanbeappliedtotheirpixelsastheapplicationofDCvoltagestoLCDpixelsmaycausepermanentdamage.ForthisreasontherelativecontrastofanLCDdisplayiscontrolledbytheactualRMSvoltageappliedtoeachpixel,whichisequaltotheRMSvalueofthevoltageontheCOMpinminusthevoltageappliedtotheSEGpin.ThisdifferentialRMSvoltagemustbegreater thantheLCDsaturationvoltagefor thepixeltobeonandlessthanthethresholdvoltageforthepixeltobeoff.

Therequirement to limit theDCvoltage tozeroandtocontrolasmanypixelsaspossiblewithaminimumnumberofconnections, requires thatbotha timeandamplitudesignal isgeneratedandappliedto theapplicationLCD.ThesetimeandamplitudevaryingsignalsareautomaticallygeneratedbytheLCDdrivercircuitsinthemicrocontroller.Whatisknownasthedutydeterminesthenumberofcommonlinesused,whicharealsoknownasbackplanesorCOMs.Theduty,whichischosenbyacontrolbittohaveavalueof1/3or1/4andwhichequatestoaCOMnumberof3or4respectively, thereforedefinesthenumberof timedivisionswithineachLCDsignalframe.Twotypesofsignalgenerationarealsoprovided,knownasTypeAandTypeB,therequiredtypeisselectedviatheTYPEbitintheLCDCregister.TypeBofferslowerfrequencysignals,howeverlowerfrequenciesmayintroduceflickeringandinfluencedisplayclarity.

Rev. 1.20 176 ��to�e� 0�� 201� Rev. 1.20 177 ��to�e� 0�� 201�



LCD Voltage Source BiasingThetimeandamplitudevaryingsignalsgeneratedbytheLCDDriverfunctionrequirethegenerationofseveralvoltagelevelsfortheiroperation.ThenumberofvoltagelevelsusedbythesignaldependsuponthevalueoftheBIASbitintheLCDCregister.ThedevicecanhaveeitherRtypeorCtypebiasingselectedviaaconfigurationoption.Selecting theCtypebiasingwillenablean internalchargepumpwhosemultiplierratiocanbeselectedusinganadditionalconfigurationoption.

ForRtypebiasinganexternalLCDvoltagesourcemustbesuppliedonpinVLCDtogeneratetheinternalbiasingvoltages.Thiscouldbe themicrocontrollerpowersupplyorsomeothervoltagesource.For theR type1/2biasselection, threevoltage levelsVSS,VAandVBareutilised.ThevoltageVAisequaltotheexternallysuppliedvoltagesourceappliedtopinVLCD.ThevoltageVBisgeneratedinternallybythemicrocontrollerandwillhaveavalueequaltoVLCD/2.FortheRtype1/3biasselection,fourvoltagelevelsVSS,VA,VBandVCareutilised.ThevoltageVAisequaltoVLCD.ThevoltageVBisequaltoVLCD×2/3whilethevoltageVCisequaltoVLCD×1/3.Inadditiontoselecting1/2or1/3bias,severalvaluesofbiasresistorcanbechosenusingbitsintheLCDCregister.

Differentvaluesof internalbiasresistorscanbeselectedusing theRSEL0andRESEL1bits intheLCDCregister.ThisalongwiththevoltageonpinVLCDwilldeterminethebiascurrent.TheconnectiontotheVMAXpindependsuponthevoltagethatisappliedtotheVLCDpin.IftheVDDvoltageisgreaterthanthevoltageappliedtotheVLCDpinthentheVMAXpinshouldbeconnectedtoVDD,otherwise theVMAXpin shouldbeconnected topinVLCD.Note thatnoexternalcapacitorsorresistorsarerequiredtobeconnectedifRtypebiasingisused.

Condition VMAX connectionVDD > VLCD Conne�t VMAX to VDD�the�wise Conne�t VMAX to VLCD

R Type Bias VMAX Pin Connection

ForCtypebiasinganexternalLCDvoltagesourcemustalsobesuppliedonpinVLCDtogeneratetheinternalbiasingvoltages.TheCtypebiasingschemeusesaninternalchargepumpcircuit,whichinthecaseofthe1/3biasselection,cangeneratevoltageshigherthanwhatissuppliedonVLCD.ThisfeatureisusefulinapplicationswherethemicrocontrollersupplyvoltageislessthanthesupplyvoltagerequiredbytheLCD.AnadditionalchargepumpcapacitormustalsobeconnectedbetweenpinsC1andC2togeneratethenecessaryvoltagelevels.

FortheCtype1/2biasselection,threevoltagelevelsVSS,VAandVBareutilised.ThevoltageVAisgeneratedinternallyandhasavalueofVLCD.ThevoltageVBwillhaveavalueequaltoVA×1/2.FortheCtype1/2biasconfigurationVCisnotused.

FortheCtype1/3biasselection,fourvoltagelevelsVSS,VA,VBandVCareutilised.ThevoltageVAisgeneratedinternallyandhasavalueofVLCD×3/2.ThevoltageVBwillhaveavalueequaltoVA×2/3andVCwillhaveavalueequaltoVA×1/3.TheconnectiontotheVMAXpindependsuponthebiasand thevoltage that isapplied toVLCD.It isextremely important toensure that thesechargepumpgeneratedinternalvoltagesdonotexceedthemaximumVDDvoltageof5.5V.

Biasing Type VMAX Connection

1/3 BiasVDD>VLCD×1.� Conne�t VMAX to VDD�the�wise Conne�t VMAX to V1

1/2 BiasVDD>VLCD Conne�t VMAX to VDD�the�wise Conne�t VMAX to VLCD

C Type Bias VMAX Pin Connection

Rev. 1.20 176 ��to�e� 0�� 201� Rev. 1.20 177 ��to�e� 0�� 201�



LCD Waveform Timing DiagramThe accompanying timing diagrams depict the display driver signals generated by themicrocontrollerforvariousvaluesofdutyandbias.Thehugerangeofvariouspermutationsonlypermitsafewtypestobedisplayedhere.

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LCD Driver Output – Type A- 1/3 Duty, 1/2 BiasNote:For1/2Bias,theVA=VLCD,VB=VLCD×1/2forbothRandCtype.

Rev. 1.20 17� ��to�e� 0�� 201� Rev. 1.20 179 ��to�e� 0�� 201�



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LCD Driver Output – Type A - 1/4 Duty, 1/3 Bias

Note:For1/3Rtypebias,theVA=VLCD,VB=VLCD×2/3andVC=VLCD×1/3.For1/3Ctypebias,theVA=VLCD×1.5,VB=VLCDandVC=VLCD×1/2.

Rev. 1.20 17� ��to�e� 0�� 201� Rev. 1.20 179 ��to�e� 0�� 201�



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LCD Driver Output – Type A- 1/3 Duty, 1/3 Bias

Note:For1/3Rtypebias,theVA=VLCD,VB=VLCD×2/3andVC=VLCD×1/3.For1/3Ctypebias,VA=VLCD×1.5,VB=VLCDandVC=VLCD×1/2.

Rev. 1.20 1�0 ��to�e� 0�� 201� Rev. 1.20 1�1 ��to�e� 0�� 201�



1 Frame

COM0

COM1

COM2

All segments are OFF

COM0 side segments are ON



(other combinations are omitted)

COM0, 1 side segments are ON

Normal Operation Mode

During Reset or LCD Off

COM0, COM1, COM2

All segment outputs

COM0, 2 side segments are ON

VA VBVCVSSVA VBVCVSSVA VBVCVSSVA VBVCVSSVA VBVCVSSVA VBVCVSSVA VBVCVSSVA VBVCVSS

VA VBVCVSSVA VBVCVSS

VA VBVCVSS

VA VBVCVSS

All segments are ON

LCD Driver Output – Type B- 1/3 Duty, 1/3 Bias

Note:For1/3Rtypebias,theVA=VLCD,VB=VLCD×2/3andVC=VLCD×1/3.For1/3Ctypebias,VA=VLCD×3/2,VB=VLCDandVC=VLCD×1/2.

Rev. 1.20 1�0 ��to�e� 0�� 201� Rev. 1.20 1�1 ��to�e� 0�� 201�



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VA VBVCVSS

1 F�ame

VA VBVCVSSVA VBVCVSSVA VBVCVSSVA VBVCVSSVA VBVCVSSVA VBVCVSSVA VBVCVSSVA VBVCVSSVA VBVCVSS

C�M0

C�M1

C�M2

All segments a�e �FF

C�M0 side segments a�e �N

C�M3



(othe� �om�inations a�e omitted)

C�M0� 1 side segments a�e �N


Normal Operation Mode

During Reset or LCD Off

C�M0� C�M1� C�M2� C�M3

All segment outputs

VA VBVCVSSVA VBVCVSS

VA VBVCVSS


VA VBVCVSS


VA VBVCVSS

All segments a�e �N

LCD Driver Output – Type B- 1/4 Duty, 1/3 Bias

Note:For1/3Rtypebias,theVA=VLCD,VB=VLCD×2/3andVC=VLCD×1/3.For1/3Ctypebias,VA=VLCD×3/2,VB=VLCDandVC=VLCD×1/2.

Rev. 1.20 1�2 ��to�e� 0�� 201� Rev. 1.20 1�3 ��to�e� 0�� 201�



Programming ConsiderationsCertainprecautionsmustbe takenwhenprogrammingtheLCD.Oneof these is toensure thattheLCDMemoryisproperlyinitialisedafterthemicrocontrollerispoweredon.LiketheGeneralPurposeDataMemory, thecontentsof theLCDMemoryare inanunknownconditionafterpower-on.AsthecontentsoftheLCDMemorywillbemappedintotheactualdisplay,itisimportanttoinitialisethismemoryareaintoaknownconditionsoonafterapplyingpowertoobtainaproperdisplaypattern.

ConsiderationmustalsobegiventothecapacitiveloadoftheactualLCDusedintheapplication.AstheloadpresentedtothemicrocontrollerbyLCDpixelscanbegenerallymodeledasmainlycapacitiveinnature,itisimportantthatthisisnotexcessive,apointthatisparticularlytrueinthecaseoftheCOMlineswhichmaybeconnectedtomanyLCDpixels.TheaccompanyingdiagramdepictstheequivalentcircuitoftheLCD.

One additional consideration thatmust be taken into account iswhat happenswhen themicrocontrollerenterstheIdleorSlowMode.TheLCDENcontrolbitintheLCDCregisterpermitsthedisplaytobepoweredofftoreducepowerconsumption.Ifthisbit iszero,thedrivingsignalstothedisplaywillcease,producingablankdisplaypatternbutreducinganypowerconsumptionassociatedwiththeLCD.

AfterPower-on,notethatas theLCDENbitwillbeclearedtozero, thedisplayfunctionwillbedisabled.

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LCD Panel Equivalent Circuit

Rev. 1.20 1�2 ��to�e� 0�� 201� Rev. 1.20 1�3 ��to�e� 0�� 201�



Configuration OptionsConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintothedeviceduringtheprogrammingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-IDEsoftwaredevelopment tools.Astheseoptionsareprogrammedintothedeviceusingthehardwareprogrammingtools,once theyareselectedtheycannotbechangedlaterusingtheapplicationprogram.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.

No. Options

1 High Speed System �s�illato� Sele�tion – fH

HXT� ERC� EC o� HIRC

2 HXT Mode Sele�tion1MHz~12MHz o� 4��kHz

3 Low Speed System �s�illato� Sele�tion – fL

LXT o� LIRC

4 HIRC F�equen�y Sele�tion4MHz� �MHz o� 12MHz

� LCD Bias Type Sele�tionR type o� C type

6 LCD Voltage Sele�tionVLCD voltage is 3.0V� 4.�V o� 1.�V

7 TMR/INT Pin Input Filte� Fun�tionEna�le o� Disa�le

� I/� o� Reset pin sele�tionReset pin o� I/� pin

9 Wat�hdog Time� Fun�tionAlways ena�le o� Appli�ation p�og�am ena�le

Note:ThefSUBclocksourceisderivedfromLXTorLIRCselectedbythefLconfigurationoption.

Rev. 1.20 1�4 ��to�e� 0�� 201� Rev. 1.20 1�� to�e� 0�� 201�



Application Circuits

VDD

PA7/RES

VSS

PB0/OSC1

PB1/OSC2

PB2/XT1

PB3/XT2

OSCCircuit

OSCCircuit

LCDPanel

COM[3:0]SEG[47:0]

VLCDVMAX

100KΩ

0.1uF

0.1uF

0.1uF

0.1uF

C1

C2V1

V20.1uF

PA0/INT1/TCK1PA1/TP0_1

PA2/TCK0/TCK2PA3/TP2_0PA4/INT0

PA5/TP2_1PA6/TP0_0

PB4/TP1APB5/TP1B_0PB6/TP1B_1PB7/TP1B_2

PC3~PC6

PD0~PD7

PE0~PE7

PF0~PF7

PG0~PG7

PH0~PH7

VDD

Rev. 1.20 1�4 ��to�e� 0�� 201� Rev. 1.20 1�� to�e� 0�� 201�



Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontrollers,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5µsandbranchorcall instructionswouldbeimplementedwithin1µs.Althoughinstructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe″CLRPCL″or″MOVPCL,A″.Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

Rev. 1.20 1�6 ��to�e� 0�� 201� Rev. 1.20 1�7 ��to�e� 0�� 201�



Logical and Rotate OperationsThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhererotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionortoasubroutineusingtheCALLinstruction.Theydifferinthesensethatinthecaseofasubroutinecall, theprogrammustreturntotheinstructionimmediatelywhenthesubroutinehasbeencarriedout.ThisisdonebyplacingareturninstructionRETinthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.Thereisnorequirementtojumpbacktotheoriginaljumpingoffpointas in thecaseof theCALLinstruction.Onespecialandextremelyusefulsetofbranch instructionsare theconditionalbranches.Hereadecision is firstmaderegarding theconditionofacertaindatamemoryorindividualbits.Dependingupontheconditions,theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.Theseinstructionsarethekeytodecisionmakingandbranchingwithintheprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe″SET[m].i″or″CLR[m].i″instructionsrespectively.Thefeatureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe″HALT″instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

Rev. 1.20 1�6 ��to�e� 0�� 201� Rev. 1.20 1�7 ��to�e� 0�� 201�



Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A�[m] Add Data Memo�y to ACC 1 Z� C� AC� �VADDM A�[m] Add ACC to Data Memo�y 1Note Z� C� AC� �VADD A�x Add immediate data to ACC 1 Z� C� AC� �VADC A�[m] Add Data Memo�y to ACC with Ca��y 1 Z� C� AC� �VADCM A�[m] Add ACC to Data memo�y with Ca��y 1Note Z� C� AC� �VSUB A�x Su�t�a�t immediate data f�om the ACC 1 Z� C� AC� �VSUB A�[m] Su�t�a�t Data Memo�y f�om ACC 1 Z� C� AC� �VSUBM A�[m] Su�t�a�t Data Memo�y f�om ACC with �esult in Data Memo�y 1Note Z� C� AC� �VSBC A�[m] Su�t�a�t Data Memo�y f�om ACC with Ca��y 1 Z� C� AC� �VSBCM A�[m] Su�t�a�t Data Memo�y f�om ACC with Ca��y� �esult in Data Memo�y 1Note Z� C� AC� �VDAA [m] De�imal adjust ACC fo� Addition with �esult in Data Memo�y 1Note CLogic OperationAND A�[m] Logi�al AND Data Memo�y to ACC 1 Z�R A�[m] Logi�al �R Data Memo�y to ACC 1 ZX�R A�[m] Logi�al X�R Data Memo�y to ACC 1 ZANDM A�[m] Logi�al AND ACC to Data Memo�y 1Note Z�RM A�[m] Logi�al �R ACC to Data Memo�y 1Note ZX�RM A�[m] Logi�al X�R ACC to Data Memo�y 1Note ZAND A�x Logi�al AND immediate Data to ACC 1 Z�R A�x Logi�al �R immediate Data to ACC 1 ZX�R A�x Logi�al X�R immediate Data to ACC 1 ZCPL [m] Complement Data Memo�y 1Note ZCPLA [m] Complement Data Memo�y with �esult in ACC 1 ZIncrement & DecrementINCA [m] In��ement Data Memo�y with �esult in ACC 1 ZINC [m] In��ement Data Memo�y 1Note ZDECA [m] De��ement Data Memo�y with �esult in ACC 1 ZDEC [m] De��ement Data Memo�y 1Note ZRotateRRA [m] Rotate Data Memo�y �ight with �esult in ACC 1 NoneRR [m] Rotate Data Memo�y �ight 1Note NoneRRCA [m] Rotate Data Memo�y �ight th�ough Ca��y with �esult in ACC 1 CRRC [m] Rotate Data Memo�y �ight th�ough Ca��y 1Note CRLA [m] Rotate Data Memo�y left with �esult in ACC 1 NoneRL [m] Rotate Data Memo�y left 1Note NoneRLCA [m] Rotate Data Memo�y left th�ough Ca��y with �esult in ACC 1 CRLC [m] Rotate Data Memo�y left th�ough Ca��y 1Note C

Rev. 1.20 1�� to�e� 0�� 201� Rev. 1.20 1�9 ��to�e� 0�� 201�



Mnemonic Description Cycles Flag AffectedData MoveM�V A�[m] Move Data Memo�y to ACC 1 NoneM�V [m]�A Move ACC to Data Memo�y 1Note NoneM�V A�x Move immediate data to ACC 1 NoneBit OperationCLR [m].i Clea� �it of Data Memo�y 1Note NoneSET [m].i Set �it of Data Memo�y 1Note NoneBranch OperationJMP add� Jump un�onditionally 2 NoneSZ [m] Skip if Data Memo�y is ze�o 1Note NoneSZA [m] Skip if Data Memo�y is ze�o with data movement to ACC 1Note NoneSZ [m].i Skip if �it i of Data Memo�y is ze�o 1Note NoneSNZ [m].i Skip if �it i of Data Memo�y is not ze�o 1Note NoneSIZ [m] Skip if in��ement Data Memo�y is ze�o 1Note NoneSDZ [m] Skip if de��ement Data Memo�y is ze�o 1Note NoneSIZA [m] Skip if in��ement Data Memo�y is ze�o with �esult in ACC 1Note NoneSDZA [m] Skip if de��ement Data Memo�y is ze�o with �esult in ACC 1Note NoneCALL add� Su��outine �all 2 NoneRET Retu�n f�om su��outine 2 NoneRET A�x Retu�n f�om su��outine and load immediate data to ACC 2 NoneRETI Retu�n f�om inte��upt 2 NoneTable Read OperationTABRD [m] Read table (specific page) to TBLH and Data Memory 2Note NoneTABRDC [m] Read ta�le (�u��ent page) to TBLH and Data Memo�y 2Note NoneTABRDL [m] Read ta�le (last page) to TBLH and Data Memo�y 2Note NoneMiscellaneousN�P No ope�ation 1 NoneCLR [m] Clea� Data Memo�y 1Note NoneSET [m] Set Data Memo�y 1Note NoneCLR WDT Clea� Wat�hdog Time� 1 T�� PDFCLR WDT1 P�e-�lea� Wat�hdog Time� 1 T�� PDFCLR WDT2 P�e-�lea� Wat�hdog Time� 1 T�� PDFSWAP [m] Swap ni��les of Data Memo�y 1Note NoneSWAPA [m] Swap ni��les of Data Memo�y with �esult in ACC 1 NoneHALT Ente� powe� down mode 1 T�� PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the“CLRWDT1”and“CLRWDT2”instructionstheTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDFflagsareclearedafterboth“CLRWDT1”and“CLRWDT2”instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

Rev. 1.20 1�� to�e� 0�� 201� Rev. 1.20 1�9 ��to�e� 0�� 201�



Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

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CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

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CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

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JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

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RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

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RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

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SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

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SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

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TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

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Package Information

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• PackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)

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48-pin LQFP (7mm×7mm) Outline Dimensions

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SymbolDimensions in inch

Min. Nom. Max.A — 0.3�4 BSC —B — 0.276 BSC —C — 0.3�4 BSC —D — 0.276 BSC —E — 0.020 BSC —F 0.007 0.009 0.011G 0.0�3 0.0�� 0.0�7H — — 0.063 I 0.002 — 0.006 J 0.01� 0.024 0.030 K 0.004 — 0.00� α 0° ― 7°

SymbolDimensions in mm

Min. Nom. Max.A — 9.00 BSC —B — 7.00 BSC —C — 9.00 BSC —D — 7.00 BSC —E — 0.�0 BSC —F 0.17 0.22 0.27G 1.3� 1.40 1.4�H — — 1.60 I 0.0� — 0.1� J 0.4� 0.60 0.7� K 0.09 — 0.20 α 0° ― 7°

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64-pin LQFP (7mm × 7mm) Outline Dimensions

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Min. Nom. Max.A — 0.3�4 BSC —

B — 0.276 BSC —

C — 0.3�4 BSC —

D — 0.276 BSC —

E — 0.016 BSC —

F 0.00� 0.007 0.009

G 0.0�3 0.0�� 0.0�7

H — — 0.063

I 0.002 — 0.006

J 0.01� 0.024 0.030

K 0.004 — 0.00�

α 0° — 7°


Min. Nom. Max.A — 9.0 BSC —

B — 7.0 BSC —

C — 9.0 BSC —

D — 7.0 BSC —

E — 0.4 BSC —

F 0.13 0.1� 0.23

G 1.3� 1.40 1.4�

H — — 1.60

I 0.0� — 0.1�

J 0.4� 0.60 0.7�

K 0.09 — 0.20

α 0° — 7°

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80-pin LQFP (10mm × 10mm) Outline Dimensions

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Min. Nom. Max.A ― 0.472 BSC ―B ― 0.394 BSC ―C ― 0.472 BSC ―D ― 0.394 BSC ―E ― 0.016 BSC ―F 0.007 0.009 0.011G 0.0�3 0.0�� 0.0�7H ― ― 0.063I 0.002 ― 0.006J 0.01� 0.024 0.030K 0.004 ― 0.00�α 0° ― 7°


Min. Nom. Max.A — 12 BSC —B — 10 BSC —C — 12 BSC —D — 10 BSC —E ― 0.4 BSC ―F 0.13 0.1� 0.23G 1.3� 1.4 1.4�H ― ― 1.60I 0.0� — 0.1�J 0.4� 0.60 0.7�K 0.09 ― 0.20α 0° ― 7°

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Copy�ight© 201� �y H�LTEK SEMIC�NDUCT�R INC.The info�mation appea�ing in this Data Sheet is �elieved to �e a��u�ate at the time of pu�li�ation. Howeve�� Holtek assumes no �esponsi�ility a�ising f�om the use of the specifications described. The applications mentioned herein are used solely fo� the pu�pose of illust�ation and Holtek makes no wa��anty o� �ep�esentation that su�h appli�ations will �e suita�le without fu�the� modifi�ation� no� �e�ommends the use of its p�odu�ts fo� appli�ation that may p�esent a �isk to human life due to malfun�tion o� othe�wise. Holtek's p�odu�ts a�e not autho�ized fo� use as ��iti�al �omponents in life suppo�t devi�es o� systems. Holtek �ese�ves the �ight to alte� its products without prior notification. For the most up-to-date information, please visit ou� we� site at http://www.holtek.�om.tw.

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tinypowertm i/o flash 8-bit mcu with lcd & eeprom ht69f30a ... · rev. 1.20 6 to e 0 201 rev....

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