Multiplexing

Presented by-J001,J009,J015,J019

Introduction When the bandwidth of a medium is greater than individual

signals to be transmitted through the channel, a medium can be shared by more than one channel of signals. The process of making the most effective use of the available channel capacity is called Multiplexing.

Multiplexing can also be defined as a technique that allows simultaneous transmission of multiple signals across a single data link.

Types Of Multiplexing

Time Division Multiplexing

Frequency Division

Multiplexing

Wavelength Division

Multiplexing

Time Division Multiplexing When a number of signals with the same frequency is carried

through the medium at different time intervals or time slots then this process is known as TDM.

Research Paper

A Mixed Signal BIST Scheme With Time Division Multiplexing Comparators And Counters

Research done byJeonjin Roh And Jacob A Abraham

Computer Engineering Research CenterThe University Of Texas

BIST-Built In Self Test

Background A low cost and efficient BIST scheme has been proposed for

analog signal circuits. TDM Comparators and Counters are used. The comparator converts response of a circuit under test to a

sequence of ones and zeros by comparing the response to the reference voltages at each time slot using TDM.

Counters are connected to comparators to count the number of ones generated at each time slot.

This scheme can be used to monitor internal nodes in addition to primary output nodes.

Simulation results are presented.

TDM Comparator Design for BIST

Proposed BIST Scheme

Example of a Comparator Design

CMOS Comparator

Example of a Comparator Design(i) When the half cycle φ2 turns on

(ii) When the half cycle φ1 turns on

Implementation of the TDM Comparator

TDM Comparator Clocks for the TDM Comparator

Enhancing Testability

Decision of PASS/FAILOnce the signatures are generated by a BIST circuit, on-chip decision to declare the CUT to be faulty or fault-free is important. Unlike the signatures for digital testing, signatures for analog testing will have specification margins allowing tolerance bands. Fault-free counter values for the TDM comparator will also have allowable variation depending on specifications.

Simple on-chip decision circuit for pass/fail

Previous Researches VS Proposed Scheme

Comparison with Oscillator Built-in Self-Test (OBIST) scheme

Comparison with schemes using Analog-Digital Converter

Advantages of the Proposed Scheme Minimum hardware required Very Flexible Internals nodes can be monitored ADC or Arithmetic unit not required A PASS/FAIL can be designed

EXPERIMENTAL RESULTS

- low pass filter- cut-off frequency of 1.4kHz- All resistors are 10kΩ, C1 and C3 are 0.01μF, and C2 and C3 are 0.02μF- 2048 comparisons (1024 each counter - maximum possible counter value) with reference voltage

-2.4

CONCLUSION An efficient BIST scheme with minimum hardwareoverhead is

proposed for analog and mixed-signal circuit testing

With the TDM technique, we can insert more test points in the circuit with only a simple switch and a counter for each test point

Future research includes an automatic technique to find the optimum number of reference voltages and their respective voltage levels to maximize the fault and yield coverage.

Also, an automatic test point selection algorithm for internal nodes with this scheme will be developed to enhance testability.

References[1] K. Arabi and B. Kaminska, “Oscillation built-in self test(OBIST) scheme for functional and structural testing of analogand mixed-signal integrated circuits,” IEEE ITC, pp.786-795, 1997

[2] M. F. Toner and G. W. Roberts, “A BIST scheme for a SNR,gain tracking and frequency response testing of a sigmadeltaADC,” IEEE Trans. on Circuits and Systems, Vol.42,No.1, pp.1-15, January 1995

[3] C. Y. Pan and K. T. Cheng, “Pseudorandom testing formixed-signal circuits,” IEEE Trans. on Computer-Aided Designof Integrated Circuits and Systems, Vol.16, No.10,pp.1173-1185, October 1997

[4] P. N. Variyam and A. Chatterjee, N. Nagi “Low-cost andefficient digital-compatible BIST for analog circuits usingpulse response sampling,” IEEE VTS, pp.261-266, 1997

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