thermal issues in designing nanometer scale interconnects

Kaustav BanerjeeKaustav Banerjee20th VLSI Multilevel Interconnection Conference, 200320th VLSI Multilevel Interconnection Conference, 2003

Thermal Issues In Designing Nanometer Scale Interconnects

Thermal Issues In Designing Nanometer Scale Interconnects

Kaustav BanerjeeUniversity of California, Santa Barbara

http://www.ece.ucsb.edu/Faculty/Banerjee

State-of-the-Art Seminar

20th VLSI Multilevel Interconnection Conference

Marina Del Rey, California, September 22, 2003


OutlineOutlineIntroduction

Nanometer Scale Interconnect Issues

Micro-scale Interconnect Thermal EffectsCoupling of Self-Heating and ElectromigrationImpact on Interconnect Design

Macro-scale Interconnect Thermal EffectsNon-Uniform Die TemperatureImplications for Signal Integrity and IR-Drop

Impact of Emerging Nanometer Scale IssuesIncreasing Process Variations and LeakageImpact on Junction and Interconnect Temperature




Interconnect Delay BottleneckIntroduction of Cu+Low-k DielectricsInterface Electron ScatteringImpact of Junction Temperature


60 80 100 120 140 160 18010

-2

10-1

100

101

Feature Size (nm)

Del

ay T

ime

(ns)

Optimal Interconnect Delay

Typical Gate Delay

60 80 100 120 140 160 18010

-2

10-1

100

101

Feature Size (nm)

Del

ay T

ime

(ns)

Optimal Interconnect Delay

Typical Gate Delay

IC performance is being dominated by interconnects…..

IC performance is being dominated by interconnects…..

K. Banerjee et al., Proc. IEEE, May 2001.

Global Wires

ITRS 99


Low-k DielectricsLow-k Dielectrics

Old dielectric: SiO2, K = 4.0New dielectric: Silk, K = 2.5

The difference is not even a factor of 2…….Ultimate low-k: air-gap, K=1


Thermal Conductivity of DielectricsThermal Conductivity of Dielectrics

1.0 1.5 2.0 2.5 3.0 3.5 4.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Dielectric Constant (ε)

Ther

mal

Con

duct

ivity

[W

/m·K

]

1.0 1.5 2.0 2.5 3.0 3.5 4.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Dielectric Constant (ε)

Ther

mal

Con

duct

ivity

[W

/m·K

]

Air

HSQ

SiO2

Polyimide

180 nm100 nm 100-130 nm 130 nm

70 nm<50 nm

Im and Banerjee, IEDM 2000.


Cu Resistivity: Effect of ScalingCu Resistivity: Effect of ScalingEffect of Cu diffusion Barrier

Barriers have higher resistivityBarriers can’t be scaled below a

minimum thickness

Problem is worse than anticipated in the ITRS roadmap

Effect of Electron Scatteringe scattering from the surfaceincreases effective resistivity

CMP + NitrideDeposition

Si

Dielectric

Cu

Nitride


Full Chip Thermal AnalysisFull Chip Thermal Analysis

Three Dimensional Heat Conduction Steady State, Uniform Heat

Generation (q), Constant Properties (k)

,0kqT2 =+∇

( Interconnect )

02 =∇ T( Others )

Worst Case Simulation– Uniform jrms for all Metal

Lines ( ITRS ’99 )

Si SubstrateSi Substrate

ILDILD

Cu IMD

ILDILD

InterconnectInterconnect

TDie

q

P/A


Maximum Chip TemperatureMaximum Chip Temperature

Im and Banerjee, IEDM 2000.

0

50

100

150

200

250

180130100705035

Technology Node [nm]

Tem

pera

ture

[°C

]

0.0

0.2

0.4

0.6

0.8

1.0 Power D

ensity [W/m

m2]

Tmax

TDie

0

50

100

150

200

250

0

50

100

150

200

250

180130100705035 180130100705035


Tem

pera

ture

[°C

]

0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.2

0.4

0.6

0.8

1.0 Power D

ensity [W/m

m2]

Tmax

TDie

(FEM Simulation )

50 nm Node

209 °C

126 °C

Global WiresGlobal Wires


Micro-Scale Interconnect Thermal Effects

Micro-Scale Interconnect Thermal Effects


Electrothermal Effects in VLSI Interconnects

Electrothermal Effects in VLSI Interconnects

Inseparable aspect of electrical power distribution and signal transmission Arise due to self-heating (or Joule heating - - I2R) Impact interconnect reliability and design

IBM

20 µm VLSI Metallization


Self-Heating Self-Heating

( ) j2rmsrefmheatingself RITTT θ∆ =−=−

θj is the effective thermal impedance:

effins

insj WLK

t=θ

Weff is the effective metal width to account for quasi-2D heat conduction.

L

Silicon

tins

Metal

insulator

Wm

Kins

Tm

Tref

q

tm


Impact of Scaling Using Low-kImpact of Scaling Using Low-k

DC Conditions

As W decreases SH increases. Low-k increases SH by 10-15%

0

100

200

300

400

500

0 1 2 3

Power [W]

∆T [0 C

] 0.75 µm 1.5 µm 3 µm

Standard Dielectric

0

100

200

300

400

500

0 1 2 3

Power [W]

∆T [0

C]

0.75 µm 1.5 µm 3 µm

Low-K Dielectric

Low-k Increases Thermal EffectsLow-k Increases Thermal Effects

Banerjee et al., IEDM 1996.


Transport of mass in metal interconnects under an applied current densityEM lifetime reliability modeled using Black’s equation given by,

= −

mB

2Tk

QexpjATTF avg

Electromigration ReliabilityElectromigration Reliability

EM stress data gives a technology limit of the current density ( javg ) - - for a required failure rate and a desired lifetime at a reference temperature Tref ( ~ 100 0C)The javg limit does not comprehend self-heating


Coupled equation:

( )( ) effinsrefm

mmmmins

refB

mB20 WKTT

TWtt

TkQexp

TkQexp

jr−

=ρ

Once Tm is calculated, jrms and jpeak can be obtained

Coupled AnalysisCoupled AnalysisUnipolar Case:Unipolar Case:

ton

T

r = ton/Tjpeakjrmsjavg

rj

j2rms

2avg =

Banerjee and Mehrotra, IEEE Circuits and Devices Magazine, pp. 16-32, September 2001.


Coupled AnalysisCoupled AnalysisUnipolar Case: Metal 6, 180 nm node, j0 = 0.6 MA/cm2Unipolar Case: Metal 6, 180 nm node, j0 = 0.6 MA/cm2

10.10.010.0010.0001120

130

140

150

160

170

180

190

200

210

220Tm

jpeakj0/r

r/jrms

Duty Cycle r

Max

imum

allo

we d

j pea

k[M

A/ c

m2 ]

Self-

Co n

s is t

e nt M

etal

Te m

pera

t ur e

Tm

0 C

0.1

1

10

100

1000

10000


Coupled AnalysisCoupled AnalysisBipolar Case:Bipolar Case:

T

T/2j(t)

j+(t)

j-(t)

t

t

t


Coupled AnalysisCoupled Analysis

Bipolar Case: AC ElectromigrationBipolar Case: AC Electromigration

Effective AC value of current density responsible for EM:

jEM bipolar = jACR (Average Current Recovery model)

−== ∫ ∫ −+

T

0

T

0ACRbipolarEM dt)t(jRdt)t(j

T1jj

R is a recovery parameter (R < 1): heuristically accounts for EM void healing under AC stress


Coupled equation for signal lines:

( )( )

effinsrefm

mmmmins2

refBmB20 WK)TT(

TWtt

R1

TkQ

TkQexp

j4r−−

−

=ρ

Coupled AnalysisCoupled AnalysisBipolar Case:Bipolar Case:


Coupled AnalysisCoupled AnalysisUnipolar vs Bipolar:

Metal 6, 180 nm node, j0 = 0.6 MA/cm2, R = 0.5Unipolar vs Bipolar:

Metal 6, 180 nm node, j0 = 0.6 MA/cm2, R = 0.5

10.10.010.0010.0001100 0.1

Duty Cycle r

Max

imum

allo

we d

j rm

s[M

A/ c

m2 ]

1

10

150

200

250

300

350

400

450

Self-

Con

s is t

e nt M

etal

Te m

pera

t ur e

Tm

0 C Tm unipolarjrms unipolar

Tm bipolarjrms bipolar


Current Density Limits: Reliability Based

Current Density Limits: Reliability Based

Impact of Low-k MaterialsImpact of Low-k Materials

Coupled jrms values decrease significantly as low-k materials are introduced

0.0001100

200

300

400

500

600

700

800Se

lf-C

ons i

s te n

t Met

al T

e mpe

rat u

r e T

m0 C

10.10.010.001Duty Cycle r

0.1

Max

imum

allo

we d

j rm

s[M

A/ c

m2 ]

1

10

Kins = 1.05 W/(m-K)Kins = 0.54 W/(m-K)Kins = 0.19 W/(m-K)Kins = 0.12 W/(m-K)Kins = 0.07 W/(m-K)


Thermal effects predominant in semi-global and global interconnects which are:

Away from the Si substrate Long: typically split into buffered segments

Long interconnects can be optimally buffered

Semi-Global and Global WiresSemi-Global and Global Wires

sopt slopt

Current Density Limits: Performance Based

Current Density Limits: Performance Based

jrms (max) occurs close to the repeater output due to the distributed nature of the interconnect


For signal lines reliability design limits satisfied

Performance vs Reliability: LinesPerformance vs Reliability: LinesM

axim

um a

llow

e d j r

ms

[MA

/ cm

2 ]

0.1

10

1

5070100130180Technology Node (nm)

jreliabilityjperformance


Buffers connected to global lines by a series of vias

Vias at the local and semi-global tiers are pitch-matched to the metal lines at these levels

Vias must carry the same current as the global lines

jrms-reliability for vias estimated from experimental self-heating data (Banerjee et al., IRPS 99) and the coupled AC electromigration model

yreliabilitrms

eperformanc-rmsj

IVia Area Minimum

−=

Performance vs Reliability: ViasPerformance vs Reliability: Vias


areaviaspecifiedITRSareaviaMinimumviassizedimumminof# =

0

1

2

3

180 130 100 70 50Technology Node (nm)

Num

ber o

f min

imum

siz

ed v

ias

Metal 1

Metal 2

Via

Performance vs Reliability: ViasPerformance vs Reliability: Vias


Current Continuity Issue: ITRS 2001Current Continuity Issue: ITRS 2001

• Imax (wire) = ITRS Jmax (wire) x A (wire) • Imax (wire) > ITRS Imax (via) for all tiers

0

0.5

1

1.5

2

2.5

150 130 107 90 80 70 65 45 32 22

Via (ITRS)Local WireSemi-Global Wire

I max

[m

A]


Global Wire

Im, Banerjee and Goodson, IEDM 2002.

Via Design and Scaling StrategyVia Design and Scaling Strategy


Thin-Film and Barrier Layer EffectsThin-Film and Barrier Layer Effects

160 120 80 40 01.0

1.2

1.4

1.6

1.8

2.0


Effective Barrier Thin-Film

160 120 80 40 01.0

1.2

1.4

1.6

1.8

2.0



ρ/ ρ

bul

k

160 120 80 40 01.0

1.2

1.4

1.6

1.8

2.0



160 120 80 40 01.0

1.2

1.4

1.6

1.8

2.0



ρ/ ρ

bul

k

160 120 80 40 00.5

0.6

0.7

0.8

0.9

1.0

Technology Node [nm]160 120 80 40 0

0.5

0.6

0.7

0.8

0.9

1.0

Technology Node [nm]α

/ α b

ulk

160 120 80 40 00.5

0.6

0.7

0.8

0.9

1.0

Technology Node [nm]160 120 80 40 0

0.5

0.6

0.7

0.8

0.9

1.0

Technology Node [nm]α

/ α b

ulk

Electron surface scattering becomes dominantJ. C. Anderson, 1966

Local Vias: ITRS


ρ (T)=ρo[1+α (T-To)]

105 oC = Reference temperature for ITRS proposed Imax (via) and Jmax (wire)

Rapid increase beyond 65 nm technology node

160 120 80 40 01

2

3

4

5


105 oC

ITRS Requirementρ[µ

Ω-c

m]

160 120 80 40 01

2

3

4

5


105 oC

ITRS Requirementρ[µ

Ω-c

m]

Electrical Resistivity of Local ViasElectrical Resistivity of Local Vias

2.2 µΩ-cm


Local Via Temperature RiseLocal Via Temperature Rise

160 120 80 40 050

100

150

200

250

300

Avg

. Via

Tem

pera

ture

[o C

]


Imax (Global Wire) Imax (Semi-Global Wire) Imax (Local Wire) Imax (Via)-ITRS

ITRS ref. temp.(105 oC)

(45 nm node)Avg. via temp.

= 197 oC

M2200 oC

M1196 oC

via

3-D FEM Analysis


Evaluation of ITRS Imax (via)Evaluation of ITRS Imax (via)

• ITRS proposed Imax (via) is too aggressive !• Imax (self-consistent) is 9.8 % - 75.8 % smaller than ITRS

proposed Imax (via)

160 120 80 40 00.00.10.20.30.40.5

ITRS Self-Consistent


I max

(via

) [m

A] EM reliability

and Joule heating aware Imax (via)

Fixed local via size (ITRS min. size)


Macro-Scale Interconnect Thermal Effects

Macro-Scale Interconnect Thermal Effects


Non-Uniform Substrate Power MapNon-Uniform Substrate Power Map

Substrate power generation distribution is generally non-uniform

Functional block clock gatingSystem-level power managementNon-uniform distribution of gate sizing and switching activities in different blocks

P1P1 P3P3 P5P5

P2P2P2P2

P4P4


Temp(oC)

Core

Cache 70ºC

120ºC

• Activity & ambient change• Dynamic: 100-1000us

Courtesy of S. Borkar, Intel Corporation.

On-Chip Temperature VariationsOn-Chip Temperature Variations

High-Performance Microprocessor


Non-Uniform Substrate Temperature

Non-Uniform Substrate Temperature

Substrate thermal profile is non-uniformThermal time constant is of the order of msmsSwitching activities in the block level are more importantIntroduces non-uniformity in the global interconnect thermal profile


Interconnect Thermal ProfileInterconnect Thermal Profile

22 2line

line ref2d T (x) = λ T (x) - λ T (x) -θ

dx

λ and θ are constantsf (L, tm ,km ,tins ,kins ,Irms ,RE )

2line2

m

d T Q= -dx k

Q = q1 – q2

L

tins

tmInterconnect

InsulatorVia

Via

Substrate(Tref )

(Tline )

(I2rms.RE )

tinsRT

(Tref )

q1

q2

A. Ajami et al., DAC 2001A. Ajami et al., DAC 2001


D0 is the Elmore delay model at reference temp.

Non-Uniform Temperature-Dependent Delay

Non-Uniform Temperature-Dependent Delay

η η∫ ∫ ∫L L L

d P L 0 0 0 L0 0 xD = R (C +C + c (x)dx)+ r (x)( c ( )d +C )dx

∫ ∫L L

0 0 L 0 0 00 0D = D + (c L+C )ρ β T(x)dx - c ρ β xT(x)dx

L

∆xRd

Cp CL


Clock Net RoutingClock Net Routing

Clock is the most vulnerable signal to the underlying thermal non-uniformity

Have long global segments in the highest metal layersdelay variations affect skew

Clock nets must have near-zero skew among their sinks to guarantee correct functionality of the circuits


H-Tree ClockH-Tree Clock

Balancing loads seen at merging point in H-Tree to have zero-skew at two sides of each branch

1

2

23

3

3

3Having equal load at each sink, the middle point is the branching pointWith non-uniform thermal profile, branching point ( l ) is dependent on the profile

l L-lp q

x1

2 2


Clock Tree Branching PointClock Tree Branching Point

With symmetric non-uniform thermal profile, the branching point is still at l*=L/2Using thermally dependent delay, optimal branching location ( l* ) can be:

∫*l

*

0

β T (x ) d x + l - A = 0

A is constant

l L-lp q

x1

2 2

A. Ajami et al., CICC 2001A. Ajami et al., CICC 2001


Clock SkewClock Skew

9.57911µ=300, σ=700

0.01000µ=1000, σ=400

2.40979.5TH=170, TL=1303.63968.66TH=170, TL=110

2.651021TH=170, TL=130

3.981032TH=170, TL=110

5.421042TH=170, TL=90

7.781210µ=2000, σ=1000

5.24957.5TH=170, TL=90

( )T x ax b= +

H LT TaL−

= Lb T=

( ) bxT x a e−= ⋅

Ha T=1 ln( )HL

TbL T

=

2

2( )2

max( )x

T x T eµ

σ− −

−= ⋅

l=L/2 skew%

l=l*paramsTline(x)


Effects of Non-Uniform Temperature on EDA Flow

Effects of Non-Uniform Temperature on EDA Flow

Interconnect non-uniform thermal profile can affect many EDA flow steps

Optimal layer assignmentBuffer insertion Wire sizingGate sizing

A. Ajami et al., ICCAD 2001A. Ajami et al., ICCAD 2001


Power Network Voltage-dropPower Network Voltage-drop

Voltage-drop is an inseparable aspect of DSM power distribution network (PDN) resistive voltage drop ∆V (on-chip resistance) switching noise, Ldi/dt (off-chip inductance)

Degrades device switching speed and DC noise margins

Can cause functional failure in dynamic logic and timing violation in static logic

10% voltage-drop 8% increase in device propagation delay (0.18µm tech.)


Local Power DistributionLocal Power Distribution

Standard Cell Row(Substrate)

M1M2

CL CL CL

Cdecap Cdecap Cdecap


Global PDN PlanningGlobal PDN Planning

Finding the minimum routing area which satisfies the EM rules

Increased line temperature (Tm) reduces the allowable maximum current (jm) in the global lines

New design rules should be extracted for worst-case temperature in each technology

-1m ref n

m 0B m ref

T -TQj = j (exp( ( ))k T T

A. Ajami et al., ISQED 2002A. Ajami et al., ISQED 2002


Effective Line ResistanceEffective Line Resistance

Barrier thickness affects only the local segments’ resistivity Interconnect temperature affects the global/semi-global

segments’ resistivity

0 thin+Barrier0 0

ρ αR = r ( ) (1+ β ∆T)ρ α

0.7520.820.8670.902(Local)(Local)αα//αα00

0.8030.8580.8950.923(Semi(Semi--global) global) αα//αα00

0.8750.9120.9350.953(Global) (Global) αα//αα00

1.4851.3151.2221.158(Local) (Local) ρρ//ρρ00

1.3341.2221.1581.113(Semi(Semi--global) global) ρρ//ρρ00

1.1861.1251.0901.066(Global)(Global)ρρ//ρρ00

0.070.10.130.18Node (Node (uum)m)


Global/Semi-global PDN Voltage-dropGlobal/Semi-global PDN Voltage-drop Allocation of 5% and 10% of the routing area

for wire-sizing to minimize the voltage-drop:

5

10

15

20

25

30

35

40

0.18 0.13 0.1 0.07Tech. Node (micron)

Tmax, 10%AT=27C , 10%ATmax, 5%AT=27 C, 5%A

Vol

tage

Dro

p [%

]


Full Chip IR-DropFull Chip IR-Drop

0

5

10

15

20

25

0.18 0.13 0.1 0.07

Tech. Node (micron)

N=100+T+SN=100+TN=100N=50+T+SN=50+TN=50

Local worst-case IR-Dropfor 50 and 100 switching cells

5

10

15

20

25

30

35

0.18 0.13 0.1 0.07Tech. No de (m icro n)

N=100+T+SN=100N=50+T+SN=50

Total chip worst-case IR-Drop10% routing, 5% chip area

Vol

tage

Dro

p [%

]

Vol

tage

Dro

p [%

]


Effect of Hot-SpotsEffect of Hot-Spots Non-uniform power consumption results in thermal gradients Voltage-drop increases with the increase in the magnitude of hot-

spot thermal gradient2

2 2lineline sub2

d T (x) = λ T (x) - λ T (x) -θdx

0

5

10

15

2 0

2 5

0 10 2 0 3 0 4 0 50 6 0T h e rm a l G ra id e n t (C )

0 .180 .13

Vol

tage

Dro

p [%

]


SummarySummary Micro-scale thermal effects:

self-heating– increases with low-k, interface electron scattering, and junction temperature

coupled analysis of self-heating and EM is necessary—impacts interconnect design rules

Current continuity, thermal coupling, and chip junction temperature rise affects via design and scaling

ITRS specified Imax (via) and Jmax (wire) are too aggressive for sub-100 nm technologies

Macro-scale thermal effects: On-chip temperature variations: an increasingly important issue non-uniform die temperature affects signal integrity, clock skew,

buffer insertion IR-drop in the power/ground network—strongly affected by global

interconnect thermal profile non-uniformity in die temperature can aversely impact IR-drop

effect Thin-film and barrier effects have major impact on the IR-drop of

local segments


Impact of Emerging Nanometer Scale Issues

Impact of Emerging Nanometer Scale Issues

0

200

400

600

800

1000

1200

1400

25 50 100 150

130nm

100nm

70nm

Nor

mal

ized

leak

age

pow

er

Temperature )( C°

Process variations are increasing for nano-scale CMOS technologies

Sub-threshold leakage increases with variations and junction temperature


Impact of Emerging IssuesImpact of Emerging Issues

ambT

)( jchip TPslope=A function of jT

chipPslope =constant

Desired jT

1jθ 2

jθ

With thermal coupling

jjchipambj TPTT θ⋅+= )(

Without thermal coupling

jchipambj PTT θ⋅+=

)/( WCj °θThermal impedance

Junc

tion

tem

pera

ture

K. Banerjee et al., to appear in IEDM 2003K. Banerjee et al., to appear in IEDM 2003

For leakage dominant technologies the chip power is strongly coupled to the junction temperature ….

Self-consistent junction temperature estimation is needed, which willimpact interconnect temperature….


ReferencesReferencesK. Banerjee and A. Mehrotra, "Global (Interconnect) Warming," IEEE Circuits and Devices Magazine, pp. 16-32, September 2001.S. Im and K. Banerjee, "Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs," Technical Digest IEEE International Electron Devices Meeting (IEDM), 2000, pp. 727-730. S. Im, K. Banerjee and K. E. Goodson, "Via Design and Scaling Strategy for Nanometer Scale Interconnect Technologies," Technical Digest IEEE International Electron Devices Meeting (IEDM), 2002, pp. 587-590.K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, "3-D ICs: A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration," Proceedings of the IEEE, Vol. 89, No. 5, pp. 602-633, May 2001. A. H. Ajami, K. Banerjee, M. Pedram and L. P.P.P van Ginneken, "Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs," 38th ACM Design Automation Conference (DAC), 2001, pp. 567-572.A. H. Ajami, M. Pedram and K. Banerjee, "Effects of Non-Uniform Substrate Temperature on the Clock Signal Integrity in High Performance Designs," IEEE Custom Integrated Circuits Conference (CICC), 2001, pp. 233-236. A. H. Ajami, K. Banerjee and M. Pedram, "Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion," IEEE International Conference on Computer-Aided Design (ICCAD), 2001, pp. 44-48.A. H. Ajami, K. Banerjee, A. Mehrotra and M. Pedram, "Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs," IEEE International Symposium on Quality Electronic Design (ISQED), 2003, pp. 35-40.

thermal issues in designing nanometer scale interconnects

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