design of mixed-signal microsystems in nanometer cmos · design of mixed-signal microsystems in...
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2012 BES Neutron and Photon Detector Workshop
Design of Mixed-Signal Microsystems in Nanometer CMOS
Carl Grace
Lawrence Berkeley National Laboratory
August 2, 2012 DOE BES Neutron and Photon Detector Workshop
2012 BES Neutron and Photon Detector Workshop
Introduction • Common themes in emerging detector requirements:
– Need to capture dynamic processes – More channels, higher speed, lower power/channel, decreased
system footprint, severe cost constraints
• Integrated mixed-signal readout a must • Example: Fast soft X-ray cameras over last 10 years
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Conventional CCD Today (FCCD) Tomorrow
(cp-CCD)
1000X increase in readout channels (for Mpixel square sensor)
Integrated readout required to deal with huge amounts of data
2012 BES Neutron and Photon Detector Workshop
SUBTITLE HERE IF NECESSARY
Why nanometer CMOS?
Nanometer CMOS is an enabling technology for future imaging and particle detection systems
• Increased transistor density – Enables increased channel/pixel count
and new functionality – New, more digital–centric approaches to
design possible
• Vastly improved performance
• Lower power for a given level of functionality
• Cheaper on a functionality basis
SMALLER, FASTER, CHEAPER
Performance Figure of Merit gm/I * ft
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2012 BES Neutron and Photon Detector Workshop
Opportunities and Challenges
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K. Kundert
Mentor Graphics
Design Rules multiplying as processes shrink
Current design techniques inappropriate for system-level mixed-signal ASICs
2012 BES Neutron and Photon Detector Workshop
IC Development Infrastructure
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Software Infrastructure
The days of debugging a chip with an oscilloscope and a function generator are over
• Design entry (schematic and physical layout design)
• Simulation (analog, digital, mixed-mode)
• Synthesis • Automatic Place-and-Route • DRC/LVS verification • FPGA firmware development
environment • Board development suite • Test framework, instrument control • Design-space exploration (MATLAB or
similar)
Required Team Competencies • Transistor-level analog and mixed
-signal design • Digital RTL development • Physical Design and Verification • System-level Validation • Analog/Digital co-simulation • Behavioral Modeling • Project management • Board-level circuit design • FPGA firmware development • Teststand software development • Advanced test execution and debug
Designing a nanometer mixed-signal ASIC requires a competent and experienced team
2012 BES Neutron and Photon Detector Workshop
Platform-Based Design • Most readout systems look broadly
similar • A platform can embody these
commonalities • Individual readout ICs are
instances of the common platform • Dramatic improvements in design
productivity and tractability • Enables small teams to complete
projects that would be impossible using an ad-hoc approach
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A. Sangiovanni Vincentelli, UC Berkeley
Leads directly to improved top-down design methodologies
Sow once Reap many times Each new chip is a platform instance instead of a scratch design
2012 BES Neutron and Photon Detector Workshop
Platform-Based Design • Platform is an integrated system designed for modification and
extensibility • Choose flexible macros for reuse e.g. use Pipelined ADC over SAR • Process, block interfaces, and characteristics standardized
– e.g. 65nm CMOS, pitch matching, electrical interfaces, biasing requirements
• Platform includes set of pin-accurate functional models in Verilog-AMS – Models allow rapid development of platform instances
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Enables digital-centric design approach lower cost and higher performance
Verilog-AMS
Verilog Verilog-A
Verilog-AMS allows full system simulation (analog + digital)
2012 BES Neutron and Photon Detector Workshop
Analog Challenges in Nanometer CMOS
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B. Murmann, Stanford University • Low supply voltage • Low device gain Analog design is hard! • But… cheap and fast transistors • Leverage cheap digital circuits to assist analog circuits
2012 BES Neutron and Photon Detector Workshop
Logic Energy over Time
500nm
180nm
~1000x
350nm
250nm
130nm
90nm 65nm
32nm
B. Murmann, Stanford University
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2012 BES Neutron and Photon Detector Workshop
ADCs versus Logic in 1997/1998
B. Murmann, Stanford University
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2012 BES Neutron and Photon Detector Workshop
ADCs versus Logic in 1997/1998
Digital assistance affordable only for high-resolution ΔΣ
(decimation filtering)
B. Murmann, Stanford University
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2012 BES Neutron and Photon Detector Workshop
ADCs versus Logic in 2012
~100x
~1000x
B. Murmann, Stanford University
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2012 BES Neutron and Photon Detector Workshop
ADCs versus Logic in 2012
~100x
~1000x
Today, it is feasible to use digital signal processing to assist moderate resolution
ADCs
B. Murmann, Stanford University
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2012 BES Neutron and Photon Detector Workshop
Digital-Centric System Design (optical comms)
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Agazzi, et al. 2008 ISSCC
Challenging analog design requires large design team and multiple silicon spins
Digital-centric design has vastly improved system performance, functional on first silicon
Well-understood digital circuits can compensate for analog shortcomings
50X performance improvement due to digital-centric design
K. Kundert
155 Mb/s data rate 10 Gb/s data rate
2012 BES Neutron and Photon Detector Workshop
HIPPO: High-Speed Image Pre-Processor with Oversampling
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16-channel prototype fabricated in 2011
2012 BES Neutron and Photon Detector Workshop
HIPPO Platform in 65nm CMOS
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Front end specific to initial application: Column-Parallel CCD readout for soft X-rays
Back end more general for signal acquisition and data conversion
Functional blocks developed with standard interfaces and Verilog-AMS models to allow accelerated redeployment
2012 BES Neutron and Photon Detector Workshop
Digital-Centric HIPPO Platform Payoff
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Low-accuracy analog system plus digital assistance = high-accuracy mixed-signal system
Result to be presented at NSS 2012
HIPPO ADC designed for good noise performance with relaxed linearity
2012 BES Neutron and Photon Detector Workshop
POM – an instance of the HIPPO platform
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21,600 gas-filled straws. Each straw has dedicated channel of electronics. Example of BES-supported platform development enabling accelerated development of high-performance readout IC for HEP
Mu2e tracker - Fermilab Processor of Muon Decays
Mu2e: experiment to observe neutinoless muon decay
2012 BES Neutron and Photon Detector Workshop
POM Behavioral Simulation (enabled by Platform-Based Design methodology)
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50
100
150
200
18 19 20 21 22 More
Freq
uenc
y
Bin
TDC electron hits (mid-straw)
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10
20
30
40
50
135 136 137 138 139 140 141 142 143 144 145 More
Freq
uenc
y
Bin
TDC electron hits (edge of longest straw)
• Functional circuit blocks modeled with Verilog-AMS • Input straw pulses provided by FNAL using GARFIELD • System-level simulation conducted before detailed design
Spreading due to dispersion in straw model
THIS IS TOP-DOWN DESIGN
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2012 BES Neutron and Photon Detector Workshop
POM Design Reuse
BLOCK REUSE Block Development time reduction
ADC Core structure adapted from silicon-proven HIPPO. Modified to lower power and area.
80%
Shaper Silicon-proven op amp architecture ported from HIPPO.
50%
S2DIFF S2DIFF architecture adapted from Multiplying DAC circuit used in HIPPO ADC.
80%
LVDS Silicon-proven LVDS driver and receiver from HIPPO reused in POM.
100%
Masterbias Silicon-proven current bias generation and distribution block from HIPPO reused in POM.
95%
Configuration Register
Silicon-proven, radiation-tolerant configuration register from HIPPO reused in POM.
95%
Standard Cells Standard cell library used in HIPPO reused in POM. 100%
Pads Pad library used in HIPPO reused in POM. 75% (estimate)
Digital Backend Experience gained in HIPPO synthesis and place-and-route cycle greatly reduced development time.
80%
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2012 BES Neutron and Photon Detector Workshop 21
Design Reuse example Pipelined ADC
HIPPO ADC (2011): 12-bit, 80 MSPS, 50 mW
POM ADC (2012): 8-bit, 65 MSPS, 3 mW
80% shorter development time due to HIPPO platform
2012 BES Neutron and Photon Detector Workshop
The Virtuous Circle of Platform-Based Design
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• Refinements made to POM ADC and improved digital expertise will be directly applied to HIPPO 2, a planned 128-channel readout IC to instrument cp-CCD image sensors.
• Platform-based design allows each project to be used as a springboard to improve the performance and lower the cost of the next project
HIPPO POM HIPPO 2
2012 BES Neutron and Photon Detector Workshop
Platform-Based Design as enabling technology
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POM would have required severe compromises in functionality or performance without Platform-Based Design
Highly leveraged from HIPPO development
2012 BES Neutron and Photon Detector Workshop
Conclusion • Science requirements demand increases in detector
channel count and performance • To meet these needs we need readout ICs that are:
– Platform-Based – Digital Centric – Developed using a top-down methodology
• These are enabling technologies. They represent an industry-proven path to improve the productivity and reach of existing design teams
• Development costs can be spread across projects and application domains for maximum impact
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