the planned but unexpected program sequencer controls program flow and provides the next instruction...

The planned but unexpected

Program Sequencer controls program flow and

provides the next instruction to be executed Interrupt – causing and handling

04/18/23 Program sequencer , Copyright M. Smith, ECE, University of Calgary, Canada

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Tackled today

Program sequencer Linear flow of instruction – previous lecture Jumps – software loops – previous lecture Loops – hardware loops – previous lecture Subroutines – previous lecture

Interrupts and Exceptions Idle – next lecture


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Reset interrupt

When you power-up, how does the processor know what to do?

RESET interrupt


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Over-simplified RESET circuit

Blackfin

BMODE PINS

00 Start at address 0x2000 0000 Flash contains 16-bit instructions01 Use internal BOOT ROM to fetch instructions from 8-bit Flash11 Use internal BOOT ROM to configure and SPI serial ROM

GND

Resistor+5V

Voltage

RESET released

Time

RESET


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Reset code RESET and into USER mode

Don’t have access to all resources and all instructions

Must blast your code into FLASH (VDSP tool)

First instruction P1.H = START; // Point to start of user code P1.L = START; RETI = P1; RTI; // Return from interrupt event (power up)

START: // Place user code here Set up stack, set this, set up that and then

CALL _main;

For information on RESET and then into SUPERVISOR mode see page 3-8 of hardware manual


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Core Timer interrupt -- IVTMR

When a timer interrupt occurs, how does the processor know what to do?

Timer interrupt


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Two cases -- Bit IVTMR not set

There is a global interrupt control register Register is called IMASK

Each possible interrupt is assigned a bit in the IMASK register Core timer interrupt is assigned bit 5 in IMASK 0x20

(Bit IVTMR in figure 4-13.)

If a core timer interrupt occurs because counter reaches zero then TINT is set (page 15-47) BUT if bit 5 in IMASK is zero, THEN NOTHING

HAPPENS – THE TIMER INTERRUPT IS IGNORED, but is still pending


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Two cases -- Bit IVTMR is set

If a core timer interrupt occurs because counter reaches zero then TINT is set (page 15-47)

Now bit 5 in IMASK is set then the interrupt process is started.

Note that the program that is running DOES NOT KNOW WHEN AN INTERRUPT MAY OCCUR Must protect the program from the interrupt Must protect the interrupt from the program Done by safe coding techniques that are discussed in

this class Similar things are needed on other processors.


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Interrupt process -- details

1. A bit in Core interrupt latch register (ILAT page 4.35) is set when interrupt signal rising edge is detected Processor “knows” interrupt happened – and hangs onto the signal, EVEN IF THE INTERRUPT SIGNAL IS ONLY THERE FOR A SHORT TIME

2. System is about to decide what to do based on bits on ILAT and IMASK and interrupt priority level Please wait – your interrupt is important to us!

3. If bit in ILAT and IMASK match and this is the highest priority interrupt then this interrupt is serviced An address is fetched from the Event Vector Table – the first

instruction inside the interrupt service routine Most current instructions in pipeline aborted Return address of first instruction to be executed after the interrupt is

stored (RETI for interrupts) Before the first instruction of ISR starts execution

ILAT bit is cleared and corresponding IPEND bit is set – signifies this is the interrupt that is being serviced now

IPEND[4] is set – this is the NO MORE INTERRUPTS can be handled bit. Gets cleared when RETI address is saved.


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What we need to know

When interrupt occurs, the corresponding bit in ILAT register is set -- automatic

Nothing else happens unless the corresponding bit in IMASK is set How do we make this happen? How are bits set in the IMASK register?

An address is fetched from the event table. This address MUST be the first instruction from our ISR, otherwise the processor crashes. How do we make this happen? How are values put into the event table?


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Two approaches - C++ approach

register_handler(ik_timer, MyISR);with EX_INTERRUPT_HANDLER(MyISR)

register_handler(ik_timer, MyISR);does many things to C++ environment including MyISR starting address into event table

location EVT6 Set IVTMR bit in IMASK is set


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Assembly language approach

#define EVT6_location 0xFFE02018 P0.H = hi(EVT6_location);P0.L = lo(EVT6_location); .extern _MyISR;

P1.H = _MyISR; // handled by linkerP1.L = _MyISR;[P0] = P1; // Event table now set

P1.H = hi(IMASK);P1.L = lo(IMASK);R1 = [P1];R2 = 0x20; // Bit 6R1 = R1 | R2;

[P1] = R1; // Bit 6 is now enabled – core timer interrupts can // occur

Since we are working in a C++ environment in this class – we will USE the register_handler( ) approach and UNDERSTAND the principles of what is happening to the hardware registers


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PF external interrupt

When a PF interrupt occurs, how does the processor know what to do?

PF interrupt


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PF interrupt / Timer interrupt Core timer interrupt (ik_timer) is a “processor core” interrupt – normally

higher priority Only one possible core timer interrupt signal causing an interrupt Controlled by IMASK (Global interrupt mask) Since “core event” -- automatically is cleared when do RTI, and

therefore does not happen again. PF interrupt (ik_ivg12) is an “external system” interrupt – normally lower

priority Currently don’t plan to change SIC_IARx (system interrupt assignment

registers) in this course Up to 16 different PF lines, each of which can cause an interrupt, based

on voltage level (high or low) or on edges (high-to-low or low-to-high) Controlled by IMASK and SIC_MASK (System interrupt mask) Since “system event” – something “magic” must be done so that when

RTI occurs, the ISR is not automatically restarted. My favourite defect is to forget to do this magic thing Easy to detect when this “magic thing” is not done – the processor

hangs and never leaves the ISR routine


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Example code

Look at moving elements from array fooHere[ ] to farAway[ ] using various instruction modes Straight line coding In a loop – please make sure that you

understand the terminology – exam question Software loop – last lecture Hardware loop – last lecture

In a subroutine Via an interrupt – next lecture


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Example code

Each time the PF8 line goes from HIGH to LOW, transfer all the data from array fooHere[ ] to array farAway[ ]

Demonstrate using1. Function

2. Interrupt service routine


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Routine to move arrays

void MoveArrays(long *, long *, long);

void MoveArrays (long *pt1, long *pt2, long num){

for (int count = 0; count < num ; count++) {

*pt1++ = *pt2++;

}


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Move arrays when PF8 line goes Hi-Low – function call approachint main void MoveArrays(long *, long *, long);

SetUpPF8to11ASM(true); for (; ; ) { // Forever loop

void MoveArrays (long *pt1, long *pt2, long num){

quit = ReadPF8to11( ) & 0x1; while (quit == 0) // Wait while low quit = ReadPF8to11( ) & 0x1;

quit = ReadPF8to11( ) & 0x1; while (quit != 0) // Wait while high quit = ReadPF8to11( ) & 0x1;


MoveArrays(fooHere, farAway, 5); *pt1++ = *pt2++;

DoSomethingElse( ); // May not execute }

}


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Move arrays when PF8 line goes Hi-Low – C++ interrupt service routine int main EX_INTERRUPT_HANDLER(MoveArraysISR);

EX_INTERRUPT_HANDLER(MoveArraysISR){

long *pt1 = fooHere; long *pt2 = farAway;

int main(void) {

SetPFInterrupts( PF8 only); EX_REGISTER_HANDLE(MoveArraysISR); register_handler(ik_ivg12, MoveArraysISR);


for (; ; ) { *pt2++ = *pt1++;

DoSomethingElse( ); // ALWAYS EXECUTING // unless ISR takes too long // or happens too often

}

}}


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My approach to developing assembly code ISR – start with function versionLeaf routines are “guaranteed” NOT to call another routine .global _MoveArray void MoveArrays(long *, long *, long);

_MoveArray:

LINK 0; // Permitted since LEAF

P0_pt1 = R0; // Can’t use R0 as pointer

void MoveArrays (long *pt1, long *pt2, long num){ R0 R1 R2


P2_counter = R3; // Can’t use R3 for a

// LSETUP instruction


LSETUP(MA_LSTART, MA_LEND) LC1 = P2; *pt2++ = *pt1++;

MA_LSTART: R0 = [P0++];

MA:LEND: [P1++] = R1;

}

P0 = [FP + 4];

UNLINK

_MoveArray.END: JUMP (P0);


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Identify all registers being usedNo register is volatile inside ISR .global _MoveArray

_MoveArray:



P0 used as pointer 1P1 used as pointer 2


P2_counter = R3; // Can’t use R3 for a

// LSETUP instruction

R0, R1 and R2 not needed as

Can’t pass parameters to ISR

LSETUP(MA_LSTART, MA_LEND) LC1 = P2;


MA:LEND: [P1++] = R1;

LC1, LT1, LB1 are used

P0 = [FP + 4];

UNLINK


Not using RETS Must use


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No register is volatile inside ISRSave all registers – note differences

.global _MoveArrayASM; .global _MoveArrayASM_ISR;

_MoveArrayASM:


_MoveArrayASM_ISR:

[--SP] = ASTAT; [--SP] = FP; [--SP] = (P7:5); // Save P7, P6 and P5

[--SP] = LC1; [--SP] = LT1; [--SP] = LB1;

P0_pt1 = R0; // Parameters passed in

P1_pt2 = R1;

P2_counter = R3;

.extern _fooHere, _farAway; P7.H = _fooHere; P7.L = _fooHere; GLOBAL PARAMETERS

P6.H = _farAway; P6.L = _farAway;

P5 = 5; // Legal?

LSETUP(MA_LSTART, MA_LEND) LC1 = P2; LSETUP(MA_LSTART, MA_LEND) LC1 = P5;


MA:LEND: [P1++] = R0;


MA:LEND: [P1++] = R0;

P0 = [FP + 4];

UNLINK


LB1 = [SP++]; LT1 = [SP++]; LC1 = [SP++]; (P7:5) = [SP++]; FP = [SP++];

ASTAT = [SP++]; RTS; // Other interrupts can now happen


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Code review – watch for RTI and registers used and saved in particular

.global _MoveArrayASM .global _MoveArrayASM_ISR;

_MoveArrayASM:


_MoveArrayASM_ISR:

[--SP] = ASTAT; [--SP] = FP; [--SP] = (P7:5); // Save P7, P6 and P5

[--SP] = LC1; [--SP] = LT1; [--SP] = LB1;


P1_pt2 = R1;

P2_counter = R3;



P5 = 5; // Legal?



MA:LEND: [P1++] = R0;


MA:LEND: [P1++] = R0;

P0 = [FP + 4];

UNLINK


LB1 = [SP++]; LT1 = [SP++]; LC1 = [SP++]; (P7:5) = [SP++]; FP = [SP++];

ASTAT = [SP++]; RTS; // Other interrupts can now happen


24 / 26

Code review – watch for RTI and registers used and saved in particular

.global _MoveArrayASM .global _MoveArrayASM_ISR;

_MoveArrayASM:


_MoveArrayASM_ISR:

[--SP] = ASTAT; [--SP] = FP;

[--SP] = (R7, P7:5); // Save P7, P6 and P5 [--SP] = LC1;

[--SP] = LT1; [--SP] = LB1;


P1_pt2 = R1;

P2_counter = R3;



P5 = 5; // Legal?



MA:LEND: [P1++] = R0;MA_LSTART: R7 = [P7++]; MA:LEND: [P6++] = R7;

P0 = [FP + 4];

UNLINK

_MoveArrayASM.END: JUMP (P0);

LB1 = [SP++]; LT1 = [SP++]; LC1 = [SP++]; (R7, P7:5) = [SP++]; FP = [SP++];

ASTAT = [SP++];

RTI; // Other interrupts can now happen


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Question still unanswered

How do you set up the PF interrupts? What is that “magic” so that once a PF interrupt starts, is

serviced, it will “go away and stop bothering me” Where is that magic placed? Is it needed in C++ or just in assembly code

If two PF interrupts happen at different times, how do you know which one has happened?

Can two PF interrupts happen at the same time? Then what do you do?

What sort of final exam question might be asked? TIMER0, TIMER1, TIMER2 are special pulse-width

modulated timers – they all share one interrupt. ISR in assembly code PF interrupts – can do 16 different choices


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Information taken from Analog Devices On-line Manuals with permission http://www.analog.com/processors/resources/technicalLibrary/manuals/

Information furnished by Analog Devices is believed to be accurate and reliable. However, Analog Devices assumes no responsibility for its use or for any infringement of any patent other rights of any third party which may result from its use. No license is granted by implication or otherwise under any patent or patent right of Analog Devices. Copyright Analog Devices, Inc. All rights reserved.

the planned but unexpected program sequencer controls program flow and provides the next instruction...

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