The NA62 Gigatrackerpresented by A. Kluge

CERN/PH-ESEJune 10, 2010

A. Klugea, G. Aglieri Rinellaa, V. Carassitic , A. Ceccucci, E. Cortina, J. Daguin, G. Dellacasab, M. Fiorinia, S. Garbolinb, P. Jarrona, J. Kaplona, F. Marchettob, E. Martina,d, A. Mapellia,e, G. Mazzab, M. Morela, M. Noya, G. Nüssle, P. Petagna, L. Perktolda, A. Cotta Ramusinoc, P. Riedlera, A. Rivettib, R. Wheadonb

a CERN, Geneva Switzerland, b INFN Torino, Italy, c INFN Ferrara, Italy, d UCL Louvain la Neuve, Belgium, d EPFL Lausanne Switzerland

OutlineNA62, introduction, challengeGigaTracker

specifications, module, beam/data rate

electronics architecturedemonstrator ASICscooling

SummaryA. Kluge

NA62 - Introduction

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Vacuum tank

Mag2 Mag3

Mag4Mag1

GTK1 GTK3

GTK2Cedar

Experimental setup- NA62

selects particleswith 75 GeV/c

seeskaons only

Achromat

250 m

beam: hadrons, only 6% kaons-> only 20% of charged kaon decay in the vacuum tank -> out of which only 10-11 decays are of interest (pion-neutrino-antineutrino)

straw chambers RICH

hit correlation via matching of arrival times – 100 ps

RICH identifies pions

straw chambersmeasure position

GTK seesall particles

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Experimental setup- NA62

100 events of kaon -> pion/neutrino/antineutrinoany deviation from standard model -> new physics

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beam: hadrons, only 6% kaons ->0.06

only 20% of charged kaon decay in the vacuum tank -> 0.20

out of which only 10-11 decays are of interest ->10-11

decay into one pion, one neutrino and one anti-neutrino

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total probability1.2 x 10-13

Experimental setup: GTK specifications

300 µm

300 µm 100 ps time binning of arrival time

800 MHz particle rate

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200 ps per station

Experimental setup: GTK specifications

300 µm

300 µm 100 ps time resolution arrival time

thin, 200µm sensor + 100 µm chip(<0.5% of X0), operated in vacuum

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Beam & detector configuration

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Beam profile60 mm

27 mm

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ASIC covering beam60 mm

27 mm

13.5 mm

4.5-6 mm

12 mm

45 rows times 40 columns per chip = 1800 pixels per chipA. Kluge

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Configuration for beam 27-60

Giga Tracker setup• Sensor&bonds: 0.24% X0

(200 µm Silicon)• RO chip: 0.11% X0

(100 µm Silicon)• Structure: 0.10% X0

(100 µm Carbon or silicon)• Total: 0.45% X0 uniform

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The electronics specification

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General: System Specifications

Number of pixels per chip

1800 = 45 x 40

Size of pixels 300 µm x 300 µmActive area per chip 12 mm x 13.5 mm = 162

mm2

Chip design time resolution

100 ps (rms)

Thickness of sensor 200 µmType of sensor p in nThickness of read-out chip

100 µm

Dynamic input range 5000 – 60000 electronsA. Kluge

General: System Specifications

Design particle rate per chip

130 MHz

Rate of center pixel 140 kHzRate of center column ~ 3.3 MHz or 0.82

MHz/mm2

Average rate per pixel 73 kHzMaximum dead time 1 % (2 % in beam center)Data transfer rate per chip

6 Gbit/s

Total dose in 1 year ~ 105 GyNeutron flux in 100 days 2 x 1014 1 MeV neutron

equivalent cm-2

Material budget/thickness 0.5 % X0 per stationA. Kluge

The ASIC architecture

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Jitter-free pixel signal to TDC in EOC

time-to-digital converter TDC

buffering & read-out processor

amplifier&

discriminator/time-walk-

compensator

reference clock

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Precise clock signal to all pixels

buffering & read-out processor

amplifier&

discriminator/time-walk-

compensator&

buffering&

TDC

reference clock

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TDC per pixel architecture

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The time-to-digital conversionDual slope TDC

TDC Wilkinson (dual slope)

U1

k2k1

tclk tclk

0 1 .. n-1 n

t0 = n tclk k2 / k1

t0

t2t1

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time walk

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Constant fraction discriminator

ta,trailing tb,trailing

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End-of-column architecture

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The time-to-digital conversionDelay locked loop based TDC

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DLL based TDC

DAC1

Pixel cell

TDC

0 1 2 m-2 m-1Clk

= tclk

Phase detector &charge pump

Ref CLK

PD CPUP

DOWNDLL CLK

VCTRL

time walk

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time-over-threshold

t

A

t1t0

A1

t2

t12

tclk

t1clk

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Time-over-threshold

t

A

t1t0

A1

t2

t12

tclk

t1clk

Sb

Demonstrator

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DemonstratorOn-pixel

dual slope TDC with CFD time walk compensation

End-of-columnDLL based TDC with time-over-threshold compensation

2 demonstrator ASICs 45 pixel - folded column with full

frontendcomplete TDC systemreduced read-out and formatting

functionality

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TDC per pixel architecture

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On pixel cell TDC

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Layout – on pixel TDC 130µm

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Efficiency and calibration

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Preliminary pTDC jitter

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Promising test results

EOC column architecture

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45 x 40 pixel final chip

Addr.

Addr.

Addr.

Hit Arbiter Hit Arbiter Hit Arbiter

LVDSH

it Reg1

Addr.

Hit Arbiter

45

4045 45 45 45

Ref CLK320MHz

serializerDLL Digital processing

Hit R

eg2

Hit R

eg1H

it Reg2

Hit R

eg1H

it Reg2

Hit R

eg1H

it Reg2

32

45 x 1 demonstrator

LVDSH

it Reg1

Addr.

Hit Arbiter

45

45

Ref CLK320MHz

serializerDLL Digital processing

Hit R

eg2

32

GTK demonstrator ASIC

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T1, T2 versus input charge

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T1 jitter over input charge

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2.4 fC most probable charge

40 – 55 ps

TDC differential/integral non-linearity

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jitter on TDC 7 ps

Full chain T1 jitter over input charge @ 0.7 fC threshold

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55 ps for full chain

full chain:preamplifierdiscriminatortransmission lineTDCread-out

Full chain T1 rms jitter over pixel

position

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no degradation because of long distancebetween pixel and TDC

GTK cooling & electro-mechanical integration

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Giga Tracker setup• Sensor&bonds: 0.24% X0

(200 µm Silicon)• RO chip: 0.11% X0

(100 µm Silicon)• Structure: 0.10% X0

(100 µm Carbon fiber)• Total: 0.45% X0 uniform

Readout chip (12 x 20 mm), power < 3.2W per chip(2 W/cm2)

Vaccuum Radiation max. Temperature: 5 degree C,

aiming for -20 degree CA. Kluge

Cooling systems under investigation

• carbon plate, conductive cooling

• micro channels

• convective cooling in a vessel

µ channel cooling

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Micro channel cooling

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Si: 31 x 31 x 1 mm3

surface roughness 160 nm134 parallel channels:l = 20 mm, w = 67 µm, h = 680 µm, separation 92 µm

255 W/cm2

Production principle

Micro channels etched in Si waferCover wafer is bonded to channelsWafers thinned in beam area Mapelli, Nüssle

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Nanoport assemblies N-333

µchannel fabrication at EPFL-CMI (Center of MicroNanoTechnologies cmi.epfl,ch)

Silicon – Pyrex bonding

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Cooling testsIR camera

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IN

OUT

IN

OUT

cooling vessel for the GTK

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Cooling vessel

HEAT

FLU

X

COO

LIN

G PL

ATE

PCB

VESSEL FRAME

VESSEL WALL

DETECTOR

ELECTRICALCONNECTIONS

Vittore Carassiti - INFN FE

COOLING VESSEL

THE COOLING VESSEL @ 1,5 bar

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Electro-mechanic integration

Top view

Bottom view

GTK assembly carrier

Vessel & carrier board outside view

M.Morel

Next steps

Bump bonding of sensor assemblyQualification of sensor assembly in

laser/beam testConverge on one architectureDesign of full pixel matrixIn parallel electro-mechanical/cooling

integration studiesInstallation end 2012A. Kluge

Summary300 x 300 µm2, 100 ps pixel detector for

NA62 GigaTrackerSpecifications challenging, demanding

integration, material budget, cooling and time stamping

Demonstrator ASIC has shown very good results

EOC - 55 ps full electronics chain jitterIntegration design is advanced

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