na62 gigatracker working group meeting integration and gtk-carrier pcb design april 9, 2013 michel...

NA62 GigaTracKer Working Group meeting

Integration and GTK-carrier PCB design

April 9, 2013

Michel Morel

2April 9, 2013 Giga Tracker Working Group meeting M. Morel

Outline

• Integration of the GTK carrier in vessels

• CAEN 3009K low voltage power supply tests

• Simulations on GTK carrier 1. Q3D extractor2. Power Distribution Network3. Designer tool

• Conclusion

• Next steps

Giga Tracker Working Group meeting M. Morel 3April 9, 2013


Integration of the GTK carrier in GTK3 mockup


CAEN 3009K low voltage power supply


CAEN 3009K

• First module delivered in February• 12 channels• Sense wires• 0.5V to 2V• 9A


Noisy channels: 4 and 7

No flag: channel #9


Active LoadFilter

EMIreceiver

Current probe

PatchPanel

Test setup and instruments

CAEN3009

Easy crate


15m of 0.5mm²twisted cable (non shielded)Current: 280mAVoltage: 1.2VVoltage drop in the cable: 700mV

VDDA conducted noise emissions

Quasi-peak

Average

1µA= 0 dBµA so 30dBµA=31.62µA


GTK carrier simulations using Ansys™ software


P1 P2

T1 T2

GND1

GND2

Glue:8µ

4350B:167µ

4350B:167µ

4350B:100µ

P1-P2Width=130µSpace=100µ

Coverlay:12+12µ

T1-T2Width=100µSpace=90µ

Coverlay:glue= 3 + cl= 12µLess glue on top of wires

Q3D extractor


0.00 2.00 4.00 6.00 8.00 10.00Freq [GHz]

99.00

99.50

100.00

100.50

101.00

101.50

102.00

102.50

103.00

ma

g(Z

0(P

air

1:d

f,Pa

ir1

:df)

)

2DExtractorDesign1XY Plot 17 ANSOFT

Curve Info

mag(Z0(Pair1:df,Pair1:df))Setup3 : Sw eep1

Microstrip line (real shape) with glue + coverlay

W= 130µS= 100µCoverlay: 12µGlue: from 3 to 12µSubstrat: Rogers 4350B


0.00 2.00 4.00 6.00 8.00 10.00Freq [GHz]

99.50

100.00

100.50

101.00

101.50

102.00

102.50

103.00

103.50

ma

g(Z

0(P

air

2:d

f,Pa

ir2

:df)

)

2DExtractorDesign1XY Plot 16 ANSOFT

Curve Info

mag(Z0(Pair2:df,Pair2:df))Setup3 : Sw eep1

Striplines (real shape)

W= 100µS= 90µSubstrat: Rogers 4350B


TEST_PULSE, RESET_GLOBAL and RESET_COARSE_FRAME_COUNT signals


CLK_DLL and CLK_dig


TDCpix chip symbol


Strip lines are routed in inner layer (yellow traces)Microstrip lines are routed on TOP layer (green traces)


The Power Distribution Network


Voltage drops on 1.2V Dig and 1.2V Analog planes

The goal of PDN is to keep a low impedance from the chip to the Power Supplies


Voltage sources: 1.2V Dig and 1.2V Analog

GND

1.2VDD

1.2VDDA

VDD_S+

VDDA_S+


Sinks on the TDCpix20130320 chip

VDD_dig: 940mA/13 bonds ~ 75mA (from 45 to 102mA / GND from 42 to 105mA)VDD_TDC: 567mA/9 bonds ~65mA (from 53 to 77mA / GND from 54 to 78mA)VDD_SLVS: 50mA/5 bonds ~10mAVDD_PLL: 88mA/ 2 bonds ~44mAVDD serial0_1: 150mA/ 6 bonds ~25mAVDD serial2_3: 150mA/6 bonds ~25mAVDD temp: 1mA / 1 bond ~1mA


1.166V: 34mV

1.188V: 12mV

1.2VDD

1.2VDDA

GND

Voltage drops on 1.2V Dig and 1.2V Analog


Voltage drops in the bonding wires

1.166V

1.152V

14mV VDD

1..188V

1.185V

3mV on VDDA 3~7mV on GND


Current density in the power planes and bonding wires


1.192E8 A/m² = 119.2µA/µ²4.45E-5 A/m²4.856E7 A/m²183µA/µ²

Current density in the bonding wires


Impedance response of VDDA4 and VDD4 on TDCpix U5 (bare Board)

0.01 0.10 1.00 10.00Freq [GHz]

0.10

1.00

10.00

100.00

200.00

Ma

g(Z

(U5

_U

5_

VD

D4

_G

rou

p_

U5

_G

ND

_G

rou

p,U

5_

U5

_V

DD

4_

Gro

up

_U

5_

GN

D_

Gro

up

))

test4_PSSYZ Sweep 2 Z Plot 2 ANSOFT

Curve Info

Mag(Z(U5_U5_VDD4_Group_U5_GND_Group,U5_U5_VDD4_Group_U5_GND_Group))SYZ Sw eep 2

0.01 0.10 1.00 10.00Freq [GHz]

0.10

1.00

10.00

100.00

test4_PSXY Plot 14 ANSOFT

Curve Info

mag(Z(U5_U5_VDDA4_Group_U5_GND_Group,U5_U5_VDDA4_Group_U5_GND_Group))SYZ Sw eep 2

[email protected]

[email protected]


20mm sensorTDCpix

GTK carrier

Restrained space on top layer due to signals connectivity.Inaccessible area on bottom side due the cooling plate dimensions.

Cooling plate

GTK carrier cross section


Designer tool


Serial_out43 Diff S parameters

Input reflection(S11)

Transfer response (S21)


0.00 2.50 5.00 7.50 10.00 12.50 15.00 17.50 20.00__InitialTime [ns]

-2.50

0.00

2.50

5.00

7.50

10.00

12.50

Initi

alIm

pu

lse

Re

spo

nse

<a

mip

rob

e3

8>

[gv]

Circuit1XY Plot 12

m1 m2

4.17nS

Curve Info

InitialImpulseResponse<amiprobe38>AMIAnalysis

Name X Y

m1 2.0100 -0.0133

m2 6.1800 0.0309

Stub to stub reflection at 2*tpd

Impulse response


1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00__InitialTime [ns]

150.00

200.00

250.00

300.00

350.00

400.00

450.00

500.00

550.00

600.00

Ris

e<

am

ipro

be

38

.eye

_p

rob

e>

[mV

]

Circuit1XY Plot 15Curve Info

Rise<amiprobe38.eye_probe>VerifEyeAnalysis

1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00__InitialTime [ns]

150.00

200.00

250.00

300.00

350.00

400.00

450.00

500.00

550.00

600.00

Fa

ll<a

mip

rob

e3

8.e

ye_

pro

be

> [m

V]


Fall<amiprobe38.eye_probe>VerifEyeAnalysis

Rise time

Fall time

-800.00 -600.00 -400.00 -200.00 0.00 200.00 400.00 600.00__Amplitude [mV]

1.00E-021

1.00E-020

1.00E-019

1.00E-018

1.00E-017

1.00E-016

1.00E-015

1.00E-014

1.00E-013

1.00E-012

1.00E-011

1.00E-010

1.00E-009

1.00E-008

1.00E-007

1.00E-006

1.00E-005

1.00E-004

1.00E-003

1.00E-002

1.00E-001

1.00E+000

am

ipro

be

38

.eye

_p

rob

e


amiprobe38.eye_probeVerifEyeAnalysis

Voltage Bathtub

Quick Eye Analysis


• The GTK carrier could be integrate in the GTK3 without modification of the board.

• Tests on the 3009K module brought to the fore problems on few channels

• Simulations of the GTK carrier show the feasibility of the board

Conclusion


Next steps

• Integrate the new GTK carrier with the flange in the vessel.

• Continue the tests on the 3009K power supply as soon it will be back.

• Continue the simulations of the GTK carrier (decoupling and filtering)

• Test the functionality of the miniPOD at low signal rate.


Spare slides


15m of 2.5mm²twisted cable (non shielded)Current: 280mAVoltage: 1.2VVoltage drop in the cable: 100mV

VDDA conducted noise emissions


15m of 2.5mm²Current: 2AVoltage: 1.2VCable unrolledVoltage drop in the cable: 520mV

VDD conducted noise emissions


SNAP12 (TYCO) MiniPOD (AVAGO)

Cost: ~ 400$ ~ 200€ and 287€ + ribbon cable 85$

Max Signal rate:Min:

12 x 3.125 Gbps1 Gbps

12 x 10.31 Gbps1.25 Gbps

AC coupling: 100nF recommended 33pF Embedded in Tx

Surface: 810mm² 410mm²

Fiber: Up to 200m @3.125Gbps Up to 100m @ 10Gbps*

Optical interface: Standard MPO/MPT ribbon fiber connector

- 1x12 ribbon cable connector- Round cable

Test with 300m MM OK with OM3 OK with OM3

Power consumption: 1.5W 2W

Power supplies: VCC33:450mA VCC25: 450mA, VCC33: 500mA

EQ setting (8 possibilities)

SNAP12 versus MiniPOD

https://edms.cern.ch/file/1184765/1/NA62_MiniPOD_test_report_v4_CSoos.pdf*

https://edms.cern.ch/file/1184765/1/NA62_MiniPOD_test_report_v4_CSoos.pdf




Current density in the bonding wires

na62 gigatracker working group meeting integration and gtk-carrier pcb design april 9, 2013 michel...

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