the intel microprocessors chapter 2 the microprocessor and its architecture instructor ： dr. yu...

The Intel MicroprocessorsThe Intel Microprocessors

Chapter 2Chapter 2The Microprocessor and its ArchitectureThe Microprocessor and its Architecture

InstructorInstructor ：： Dr. Yu YoulingDr. Yu Youling

OutlineOutline

• Internal Microprocessor ArchitectureInternal Microprocessor Architecture

• Real Model Memory AddressingReal Model Memory Addressing

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The CPUThe CPU

• The Central Processing Unit (CPU) is a fundamental The Central Processing Unit (CPU) is a fundamental component of a PC system (No CPU component of a PC system (No CPU No Computer)No Computer)

• Basically it is a complex microprocessor whose main Basically it is a complex microprocessor whose main task is to process data stored in an external memory task is to process data stored in an external memory (RAM) according to instructions also stored within that (RAM) according to instructions also stored within that external memoryexternal memory

• Additionally, however, CPUs also generally contain some Additionally, however, CPUs also generally contain some special fast internal storage memory, called registersspecial fast internal storage memory, called registers

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The CPU ComponentsThe CPU Components

• Basic ComponentsBasic Components– Registers & FlagsRegisters & Flags– Arithmetic Logic UnitsArithmetic Logic Units– Shifters / RotatorsShifters / Rotators– Address Decoding ModulesAddress Decoding Modules

• Advanced ComponentsAdvanced Components– Math. Co-processorsMath. Co-processors– Data & Program PipelinesData & Program Pipelines– CachesCaches– Micro-code instruction decoders.Micro-code instruction decoders.– Multimedia Extension Processors. (MMX)Multimedia Extension Processors. (MMX)– Etc.Etc.

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RegistersRegisters

• Registers can be used by a programmer/user like a Registers can be used by a programmer/user like a ‘scratch pad’ to carry out calculations or other tasks ‘scratch pad’ to carry out calculations or other tasks performed within the CPUperformed within the CPU

• All of the 8086 family of CPUs have 14, 16-bit registers All of the 8086 family of CPUs have 14, 16-bit registers that are commonly used and are at the disposal of the that are commonly used and are at the disposal of the useruser

• Starting with the 80386, Intel also added a new set of 32-Starting with the 80386, Intel also added a new set of 32-bit registers and instructions to the CPUbit registers and instructions to the CPU

• For this course, however, we are only going to focus on For this course, however, we are only going to focus on what Intel refer to as the what Intel refer to as the Real Mode operationReal Mode operation of the of the CPUCPU

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Real Mode Memory AddressingReal Mode Memory Addressing

• The special mode called Real Mode switches any 8086 The special mode called Real Mode switches any 8086 family CPU into an 8086 compatibility mode (even family CPU into an 8086 compatibility mode (even Pentium IVs have this mode implemented)Pentium IVs have this mode implemented)

• In this mode the user is allowed access only to 14 basic In this mode the user is allowed access only to 14 basic 16-bit registers, 1Mb of RAM and 64 Kb of I/O space 16-bit registers, 1Mb of RAM and 64 Kb of I/O space

• Once this area has been mastered, the basic skills and Once this area has been mastered, the basic skills and knowledge required to master the more advanced CPUs knowledge required to master the more advanced CPUs like the 80386, 80486, Pentiums, Pentium IIs with MMX, like the 80386, 80486, Pentiums, Pentium IIs with MMX, etc. will have been developedetc. will have been developed

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1MB RAM1MB RAM

• In real mode, 8086 family CPUs are able to access a In real mode, 8086 family CPUs are able to access a total of 1 MB of RAMtotal of 1 MB of RAM

• Conceptually this can be thought of as a contiguous Conceptually this can be thought of as a contiguous block from 00000h block from 00000h FFFFFh FFFFFh

• In practice, however, this memory is segmented into In practice, however, this memory is segmented into 64Kb blocks, i.e. blocks from 0000h 64Kb blocks, i.e. blocks from 0000h FFFFhFFFFh

• This was done to maintain compatibility with Intel’s early This was done to maintain compatibility with Intel’s early 8085 processors, which had only 16 address lines 8085 processors, which had only 16 address lines providing access to 64 Kb of memory (216 = 64K)providing access to 64 Kb of memory (216 = 64K)

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General Purpose RegistersGeneral Purpose Registers

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• General Purpose Register General Purpose Register – for arithmetic calculations, temporary data storage, data for arithmetic calculations, temporary data storage, data

transfer, etctransfer, etc– EAX: Accumulator: Referenced as EAX, AX, AL or AH.EAX: Accumulator: Referenced as EAX, AX, AL or AH.

• The most commonly used registerThe most commonly used register

• Used by string instructions (STOSB, STOSW, etc.) to hold the data being Used by string instructions (STOSB, STOSW, etc.) to hold the data being transferredtransferred

• Used by I/O instructions (IN, OUT) to hold the data being transferredUsed by I/O instructions (IN, OUT) to hold the data being transferred

• Used by multiply (MUL) and divide (DIV) to contain the data before the Used by multiply (MUL) and divide (DIV) to contain the data before the instruction and the result afterinstruction and the result after

• Used by string instructions and BIOS to hold the ASCII and Used by string instructions and BIOS to hold the ASCII and ATTRIBUTE values when writing to the screen in text modeATTRIBUTE values when writing to the screen in text mode

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• General Purpose Register General Purpose Register – EBX: Base Index:EBX: Base Index:

• Used by several addressing mode instructions to hold the base of a Used by several addressing mode instructions to hold the base of a block of data to be manipulated.block of data to be manipulated.

• A block usually contains some related data, e.g. a message to print in A block usually contains some related data, e.g. a message to print in ASCIIASCII

– ECX: Count:ECX: Count:• Used by instructions such as REP and LOOP as a counter, e.g if CX = Used by instructions such as REP and LOOP as a counter, e.g if CX =

10 then the LOOP instruction will loop 10 times decreasing CX until 10 then the LOOP instruction will loop 10 times decreasing CX until it reaches zeroit reaches zero

• Also used by the Shift (SHR, SHL) and Rotate (ROR, ROL) Also used by the Shift (SHR, SHL) and Rotate (ROR, ROL) instructions to indicate how many bits to shift or rotateinstructions to indicate how many bits to shift or rotate

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• General Purpose Register General Purpose Register

– EDX: Data:EDX: Data:

• Used by I/O (IN, OUT) instructions to hold the address of the port Used by I/O (IN, OUT) instructions to hold the address of the port being accessedbeing accessed

• Used by the Multiply (MUL) and Divide (DIV) instructions to hold the Used by the Multiply (MUL) and Divide (DIV) instructions to hold the result of 32-bit data manipulationsresult of 32-bit data manipulations

• Also used by BIOS to set up cursor positionsAlso used by BIOS to set up cursor positions

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• ESP: Stack Pointer:ESP: Stack Pointer:– Used by the stack, call and return instructions.Used by the stack, call and return instructions.

• EBP: Base Pointer:EBP: Base Pointer:– Holds the base pointer for memory data transfers.Holds the base pointer for memory data transfers.

• EDI: Destination Index:EDI: Destination Index:– Holds the base destination pointer for string instructions.Holds the base destination pointer for string instructions.

• ESI: Source Index:ESI: Source Index:– Holds the base source pointer for string instructions.Holds the base source pointer for string instructions.

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• EIP: Instruction Pointer:EIP: Instruction Pointer:– register that points to the register that points to the next instruction next instruction to be executed in the RAMto be executed in the RAM

– If a 2 byte instruction is currently being executed at 0100, then IP = If a 2 byte instruction is currently being executed at 0100, then IP = 01020102

– IP has a range from 0000 (0000 decimal) to FFFF (65535 decimal)IP has a range from 0000 (0000 decimal) to FFFF (65535 decimal)

– This means that the CPU can only access up to 64K bytes of This means that the CPU can only access up to 64K bytes of instructions using the IP register aloneinstructions using the IP register alone

– Always works in conjunction with the CS register to generate a Always works in conjunction with the CS register to generate a physical addressphysical address

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• EIP: Instruction Pointer:EIP: Instruction Pointer:– Certain program instructions may alter it in order to cause execution Certain program instructions may alter it in order to cause execution

of a different section of codeof a different section of code– Jump instructions alter IP to point to a new instruction to jump to Jump instructions alter IP to point to a new instruction to jump to

nextnext– Call instructions also alter IP to indicate a new location to start Call instructions also alter IP to indicate a new location to start

executing from, but the current value of IP is saved to allow a return executing from, but the current value of IP is saved to allow a return to the current next instructionto the current next instruction

– Interrupts alter this register, setting it to point to the location of the Interrupts alter this register, setting it to point to the location of the relevant ISR coderelevant ISR code

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Special Purpose RegistersSpecial Purpose Registers

• EFLAGS:EFLAGS:

– Store the state of various conditions in the microprocessor.Store the state of various conditions in the microprocessor.

– The rightmost 5 flag bits and overflow change after many of the The rightmost 5 flag bits and overflow change after many of the arithmetic and logic instructions execute. Data transfer and arithmetic and logic instructions execute. Data transfer and program control instructions never change the flags.program control instructions never change the flags.

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Flag bitsFlag bits

• C (Carry):C (Carry):– Holds the carry out after addition or the borrow after subtraction.Holds the carry out after addition or the borrow after subtraction.

– Also indicates error conditions.Also indicates error conditions.

• P (Parity):P (Parity):– 0 for odd number of bits (0 for odd number of bits ( 奇数奇数 ) and 1 for even() and 1 for even( 偶数偶数 ).).

– Obsolete feature of the 80x86.Obsolete feature of the 80x86.

• A (Auxiliary Carry):A (Auxiliary Carry):– Highly specialized flag used by DAA and DAS instructions after BCD Highly specialized flag used by DAA and DAS instructions after BCD

addition or subtraction.addition or subtraction.

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Flag bitsFlag bits

• Z (Zero):Z (Zero):– 1 if the result of an arithmetic or logic instruction is 0.1 if the result of an arithmetic or logic instruction is 0.

• S (Sign):S (Sign):– 1 if the sign of the result of an arithmetic or logic instruction is 1 if the sign of the result of an arithmetic or logic instruction is

negative.negative.

• T (Trap):T (Trap):– Trap enable. The microprocessor interrupts the flow of Trap enable. The microprocessor interrupts the flow of

instructions on conditions indicated by the debug and control instructions on conditions indicated by the debug and control registers.registers.

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Flag bitsFlag bits

• I (Interrupt):I (Interrupt):– Controls the operation of the INTR (Interrupt request) pin. If 1, Controls the operation of the INTR (Interrupt request) pin. If 1,

interrupts are enabled. Set by interrupts are enabled. Set by STI and CLI instructions.STI and CLI instructions.

• D (Direction):D (Direction):– Selects with increment or decrement mode for the DI and/or SI Selects with increment or decrement mode for the DI and/or SI

registers during string instructions. If 1, registers are registers during string instructions. If 1, registers are automatically decremented. Set by automatically decremented. Set by STD and CLD instructions.STD and CLD instructions.

• O (Overflow):O (Overflow):– Set for addition and subtraction instructions.Set for addition and subtraction instructions.

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Flag bitsFlag bits

• 80286 and up:80286 and up:

– IOPL (I/O privilege level):IOPL (I/O privilege level):

• It holds the privilege level at which your code must It holds the privilege level at which your code must be running in order to execute any I/O-related be running in order to execute any I/O-related instructions. 00 is the highest.instructions. 00 is the highest.

– NT (Nested Task):NT (Nested Task):

• Set when one system task has invoked another Set when one system task has invoked another through a CALL instruction in protected mode.through a CALL instruction in protected mode.

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Flag bitsFlag bits

• 80386 and up:80386 and up:– RF (Resume):RF (Resume):

• Used in debugging.Used in debugging.– VM (Virtual Mode):VM (Virtual Mode):

• When 0, the CPU can operate in Protected mode, When 0, the CPU can operate in Protected mode, Virtual 8086 mode or Real mode.Virtual 8086 mode or Real mode.

• When set, the CPU is converted to a high speed 8086. When set, the CPU is converted to a high speed 8086. This bit has enormous impact.This bit has enormous impact.

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Flag bitsFlag bits

• 80486SX and up:80486SX and up:– AC (Alignment Check):AC (Alignment Check):

• Specialized instruction for the 80486SX.Specialized instruction for the 80486SX.• Pentium and up:Pentium and up:

– VIF (Virtual Interrupt Flag):VIF (Virtual Interrupt Flag):

• Copy of the interrupt flag bit.Copy of the interrupt flag bit.– VIP (Virtual Interrupt Pending):VIP (Virtual Interrupt Pending):

• Provides information about a virtual mode interrupt.Provides information about a virtual mode interrupt.– ID (Identification):ID (Identification):

• Supports the CPUID instruction, which provides version number Supports the CPUID instruction, which provides version number and manufacturer information about the microprocessor.and manufacturer information about the microprocessor.

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Segment RegistersSegment Registers

• CS (Code Segment):CS (Code Segment):– In real mode, this specifies the start of a 64KB memory segment.In real mode, this specifies the start of a 64KB memory segment.– In protected mode, it selects a descriptor.In protected mode, it selects a descriptor.– The code segment is limited to 64KB in the 8086-80286 and 4 GB in the 386 and The code segment is limited to 64KB in the 8086-80286 and 4 GB in the 386 and

above.above.

• DS (Data Segment):DS (Data Segment):– Similar to the CS except this segment holds data.Similar to the CS except this segment holds data.

• ES (Extra Segment):ES (Extra Segment):– Data segment used by some string instructions to hold destination data.Data segment used by some string instructions to hold destination data.

• SS (Stack Segment):SS (Stack Segment):– Similar to the CS except this segment holds the stack.Similar to the CS except this segment holds the stack.– ESP and EBP hold offsets into this segment.ESP and EBP hold offsets into this segment.

• FS and GS: 80386 and up.FS and GS: 80386 and up.– Allows two additional memory segments to be defined.Allows two additional memory segments to be defined.

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• Used because IP is only 16-bits long whereas the total Used because IP is only 16-bits long whereas the total addressable RAM space is addressable RAM space is 222020 = 1M = 2 = 1M = 216+416+4 in size in size

• The actual physical address in RAM is calculated as The actual physical address in RAM is calculated as (SEGMENT * 16) + IP(SEGMENT * 16) + IP, i.e. Segment & Offset , i.e. Segment & Offset

– e.g. if CS = 07A0 and IP = 0100 then the physical address = e.g. if CS = 07A0 and IP = 0100 then the physical address = 07A00 + 0100 = 07B0007A00 + 0100 = 07B00

• NoteNote

– More than one segment pointer combination can point to the More than one segment pointer combination can point to the same physical addresssame physical address

– e.g. 07B00 = 07A0:0100 or 07B0:0000e.g. 07B00 = 07A0:0100 or 07B0:0000

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• Only mode available to the 8086 and 8088.Only mode available to the 8086 and 8088.– Allow the processor to address only the first 1MB of memory.Allow the processor to address only the first 1MB of memory.

– DOS requires real mode.DOS requires real mode.

• Segments and Offsets:Segments and Offsets:– Effective address = Segment address + an offset.Effective address = Segment address + an offset.

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• Segments and Offsets:Segments and Offsets:– Syntax is usually given as seg_addr:offset, e.g. 1000:F000 in the previous Syntax is usually given as seg_addr:offset, e.g. 1000:F000 in the previous

example to specify 1F000H.example to specify 1F000H.

• Default Segment and Offset RegistersDefault Segment and Offset Registers– Implicit combinations of segment registers and offsets are defined for memory Implicit combinations of segment registers and offsets are defined for memory

references.references.– For example, the code segment (CS) is always used with the instruction pointer For example, the code segment (CS) is always used with the instruction pointer

(IP for real mode or EIP for protected mode).(IP for real mode or EIP for protected mode).

• CS:EIPCS:EIP• SS:ESP, SS:EBPSS:ESP, SS:EBP• DS:EAX, DS:EBX, DS:ECX, DS:EDX, DS:EDI, DS:ESI, DS:8-DS:EAX, DS:EBX, DS:ECX, DS:EDX, DS:EDI, DS:ESI, DS:8-

bit_literal, DS:32-bit_literalbit_literal, DS:32-bit_literal• ES:EDIES:EDI• FS and GS have no default.FS and GS have no default.

• It is illegal to place an offset larger than FFFF into the 80386 32-bit It is illegal to place an offset larger than FFFF into the 80386 32-bit registers operating in Real Mode.registers operating in Real Mode.

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• Segments and Offsets:Segments and Offsets:

– Segments can overlap, as shown Segments can overlap, as shown below for the CS and DS.below for the CS and DS.

– Segmented addressing allows Segmented addressing allows relocation of data and code.relocation of data and code.

– OS can assign the segment OS can assign the segment addresses at run time.addresses at run time.

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RelocationRelocation

• Segment and offset addressing allows for easy and Segment and offset addressing allows for easy and efficient relocation of code and data.efficient relocation of code and data.

• To relocate code or data only the segment number To relocate code or data only the segment number needs to be changed. For example, if an instruction needs to be changed. For example, if an instruction appears at offset address 0002 the segment address appears at offset address 0002 the segment address does not matter because if it changes so does the does not matter because if it changes so does the effective address of the instruction.effective address of the instruction.

HomeworkHomework

• 第一部分第一部分– 8,10,13,14,208,10,13,14,20

• 第二部分（任选一，中文，第二部分（任选一，中文， 500500字）字）– 通过互联网，查询并简要写出保护模式的工作原理通过互联网，查询并简要写出保护模式的工作原理– 通过互联网，查询并简要写出分页机制的工作原理通过互联网，查询并简要写出分页机制的工作原理

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the intel microprocessors chapter 2 the microprocessor and its architecture instructor ： dr. yu...

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