the equipment shown hereon may be protected by … · 1 11 : pitch-pitch stylevendor style...

MCU MISCELLANEOUS SIGNALS

PAGE 2 - USB

PAGE 3 - MCU

PAGE 5 - PROGRAMMING PROCESSOR

PAGE 6 - POWER ON RESETPAGE 7 - POWER CIRCUITRYPAGE 8 - ARDUINO CONNECTORPAGE 9 - SDP CONNECTORPAGE 10 - SDRAM LEVEL TRANSLATORSPAGE 11 - SDRAM

SDP-K1 SCHEMATIC

1 11

<User Define><User Define><User Define>

: Pitch-pitch StyleVendor StylePACKAGE : N/A-lead N/A N/A-family

: N/AProduct(s): N/AHW TYPE : Customer Evaluation

no_template

BCodeID1:1

02_049259TBD

-

-

-

-

-

<PTD_ENGINEER>

-

-

-

-

REV

2REVISIONS

1

OWNED OR CONTROLLED BY ANALOG DEVICES.THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTSPURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES.USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER

8

2

67

A

DATE APPROVED

D

B

DESCRIPTION

345

57

OEM PART# HANDLER

6

C

B

8

SOCKET OEMBK/BD SPEC.P.O SPEC.

A

3 14

C

NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, ORTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS

CHECKER

DESIGNER

PTD ENGINEER

TEST ENGINEER

DECIMALS

X.XXX +-0.005X.XX +-0.010

MASTER PROJECT TEMPLATE

TOLERANCES

+-1/32FRACTIONS

+-2SIZE

DDDD

SCHEMATIC

DRAWING NO.

SCALE CODE ID NO.SHEET OF

REV.

DA A

ENV C

L GSE

ODATE

ANGLES

UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES

TESTER TEMPLATE

TEMPLATE ENGINEER

HARDWARE SERVICES

HARDWARE SYSTEMS

COMPONENT ENGINEER

TEST PROCESS

HARDWARE RELEASE

D

KEEP 1UF CAP AS CLOSE AS POSSIBLE TO PIN 9

KEEP 0.1UF CAP AS CLOSE AS POSSIBLE TO PIN 1

USB

RESISTOR FOR RBIAS ON USB3443 NEEDS TO BE KEPT AS CLOSE AS POSSIBLE TO THE DEVICE

2 11

<DESIGN_VIEW>


1:1

B02_049259

<PTD_ENGINEER>

12K

10K

24MEGHZ

0

0.1UF

0.001UF

0.001UF

330

600OHM

0.5A

0.001UF

1UF

2.2UF

100K

100K

26MEGHZ

0.1UF

0.1UFUSB2422-I/MJ

1UF 0.001UF

0.1UF 0.001UF

33

USB3343-CP

8.06K

1UF

0.1UF

0

0 DNI

DNI0

33OHM

33OHM33OHM

33OHM

33OHM33OHM

33OHM33OHM

333333

1UF

1UF

0.1UF

2.2UF

18PF

18PF

1UF

1UF

16VDC

0.033UF

SI2333DDS-T1-GE3

UX60SC-MB-5S8

76.8K

0.33UF

1000PF

C25

C20

C29

C1

R209

R208R207R206

C27

C2

C11

C16

C7

C19

C31

C5

C10

C12

E2R1

R2

C15

C14

C13

C6

C3

C4

C8

C9

C17

C18

F2

R5

R12

Q2

V1

C23

R24

R26

D2 D4

P2

Y1

Y2

R6

R7

R9

R8

R3

U1

U2

CFG_SEL

HUB_XTAIN

HUB_XTALOUT

MAIN_PWR_SUPPLY

USB_VBUS_DETECTUSB_DM

USB_OTG_HS_ULPI_STP

USB_ULPI_RESET

USB_ULPI_DMUSB_ULPI_DP

USB_OTG_HS_ULPI_D0

USB_OTG_HS_ULPI_D2USB_OTG_HS_ULPI_D1

USB_OTG_HS_ULPI_D3



USB_OTG_HS_ULPI_CKUSB_OTG_HS_ULPI_DIRUSB_OTG_HS_ULPI_NXT

USB_VBUS

USB_VBUSMAIN_PWR_SUPPLY

USB_DP

ULPI_REFCLK

+3.3V

+3.3V

+3.3V

+3.3V

HUB_RESET

HUB_XTAIN

PROG_I2C_SCL

NON_REM1CFG_SEL

NON_REM1

USB_PROG_DP

USB_PROG_DMUSB_ULPI_DM

PROG_I2C_SDA

HUB_XTALOUT

USB_DP

USB_ULPI_DP

USB_VBUSUSB_DM

161152

134143

12511610798

21

212

1

3

2

1

2

1

2

154321

G2G1

43

12

4

2 3

1

21

22

PAD

1891

16 20

53

19

42

17

131415

24

117

23

128

6

10

20

915 23

17

16

24

22

21

19

PAD

3

181314

1

12111087654

2

VSS

RBIAS

PLLFILT

XTAIN/CLKIN

XTALOUT/(CLKIN_EN)

USBDP_UPUSBDM_UP

VDD3

3

SUSP_IND/LOCAL_PWR/(NON_REM0)

VBUS_DET

RESET_N SMBCLK/CFG_SEL0SMBDATA/NON_REM1

OCS2_N

PRTPWR2CRFILT

VDD3

3

OCS1_N

PRTPWR1/(BC_EN1)

NC

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2USBDP_DN1/PRT_DIS_P1

USBDM_DN1/PRT_DIS_M1

VDD3

3 PINSGND

PAD

STP

VDD1

8

RESETB

REFCLK/XI

XO

RBIAS

ID

VBUS

VBAT

VDD3

3

DMDP

DATA7DATA6DATA5

VDDI

O

DATA4DATA3DATA2DATA1DATA0

NXT

CLKOUTDIR

VDDOUTGND

OE

IN/OUT

NC

NC

IN/OUT

D

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

AC

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.

2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

MCU

AWAKE

3 11

<DESIGN_VIEW>


1:1

B02_049259

<PTD_ENGINEER>

0.1UF

0.1UF

0

DNI

0.1UF

0

8MEGHZ

DNI

600OHM4.7UF 1UF4.7UF 0.1UF

1UF 0.1UF

0.1UF

33

33

3333

33

3333

33

0

0.1UF 0.1UF 0.1UF

0.1UF 0.1UF 0.1UF 0.1UF

0.1UF

2.2UF 2.2UFDNI

2.2UF 2.2UF

DNI

STM32F469NIH6

STM32F469NIH6

11

10

14

15

333333

2

3

13

14

15

16

17

18

19

20

21

22

23

24

26

27

28

29

30

31

33

33

333333

3333

33

0

1

4

0

5

6

7

8

9

10

11

12

1

2

3

4

5

6

8

9

25

0.1UF

0.1UF

STM32F469NIH6

8.2PF 8.2PF

DNIBLU

10K

10KDNI

33

3333

7

10K

0

DNI

0.1UF 0.1UF 0.1UF

DNI

10K

10K

0

0.1UF

0.1UF

0.1UF

R225

C62

C73

R46

Y3

C54

R33

C75

E3

C69 C71C67 C72

C68 C70

C59

U11

U11

U11

C51

R57

TP2

R45

C74 C76

R47

C77 C78C48 C50 C53 C56

C47 C49 C52 C55 C61 C63

C79

R31

C58 C64

R10

R32

C65

C57

C60

R4

MAIN_PWR_SUPPLY

ARDUINO_ADC_REF

PROCESSOR_VDD_USB

MAIN_PWR_SUPPLY

MAIN_RESET

MAIN_PWR_SUPPLY

PROGRAMMING_PROCESSOR_UART_RX

MAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY VDDA

ARDUINO_ADC_REF

ARDUINO_GPIO6/PWM2

SDP_SPORT_TFS

ARDUINO_GPIO11/PWM5/MOSISDP_SPI_NSS_B

SDP_GPIO6SDP_GPIO5

SDP_GPIO3

SDP_GPIO1

DEBUG_GPIO3

ARDUINO_ADC_IN5ARDUINO_ADC_IN4USB_OTG_HS_ULPI_NXTUSB_OTG_HS_ULPI_DIRARDUINO_ADC_IN3USB_OTG_HS_ULPI_STP

ARDUINO_ADC_IN2USB_OTG_HS_ULPI_CK

ARDUINO_ADC_IN1USB_OTG_HS_ULPI_D0

ARDUINO_ADC_IN0

MAIN_PWR_SUPPLY

VDDA

SDP_SPI_NSS_CSDP_TMR_D

SDRAM_A<15:14>

SDRAM_D<31:0>

SDRAM_A<11:0>

SDP_UART_TXSDP_UART_RXUSB_RESET

F469_SPI_MOSI/QUADSPI_DIO0

SDRAM_NBL0SDRAM_NBL1

SDP_EXT_BOOT

SDRAM_N_RAS

SDRAM_A12SDRAM_A13

DEBUG_GPIO0ARDUINO_GPIO2SDRAM_SDCLKARDUINO_GPIO4ARDUINO_GPIO7ARDUINO_GPIO8DEBUG_GPIO1

SDRAM_N_CAS

SDRAM_SDCKE0SDRAM_SDNE0USB_AVAILABLESDRAM_N_WE

SDRAM_NBL2SDRAM_NBL3

DEBUG_GPIO2

SDP_SPORT_TSCLKARDUINO_GPIO3/PWM0SDP_QUADSPI_DIO3

SDP_SPORT_DT0

SDP_SPORT_RSCLK

SDP_SPORT_RFSSDP_SPORT_DR0

SDP_SPI_NSSSDP_QUADSPI_DIO2

MAIN_PWR_SUPPLY

F469_SPI/QUADSPI_SCK

PROGRAMMING_PROCESSOR_UART_TX

MAIN_PWR_SUPPLY

SDP_TMR_B

SDP_TMR_A

ARDUINO_GPIO0/RX

F469_VIO_CHECK


SDP_SERIAL_INTF469_SPI_MISO/QUADSPI_DIO1

SDP_GPIO7F469_SPI/QUADSPI_NSS_A

ARDUINO_GPIO1/TX

LED_REDLED_ORANGE

USB_OTG_HS_ULPI_D5

USB_OTG_HS_ULPI_D3

BOOT1_CTRL

USB_OTG_HS_ULPI_D1

F469_SWCLKF469_SWDIO

LED_GREEN

SDP_GPIO2

SDP_GPIO4

PROCESSOR_STATUSPROCESSOR_AWAKE

SDP_GPIO0

SDP_I2C_SCL0_SW

SDP_I2C_SDA0_SW

ARDUINO_SCL_SW

F469_SPI_MISO/QUADSPI_DIO1F469_SPI_MOSI/QUADSPI_DIO0

USB_OTG_HS_ULPI_D4

USB_OTG_HS_ULPI_D2

ARDUINO_GPIO5/PWM1

ARDUINO_GPIO10/PWM4/SS

F469_SWO

MAIN_PWR_SUPPLY

BOOT1_CTRL

BOOT0_CTRL

ARDUINO_GPIO9/PWM3

USB_OTG_HS_ULPI_D6

ARDUINO_GPIO13/SCKARDUINO_GPIO12/MISOUSB_OTG_HS_ULPI_D7

ARDUINO_SDA_SW

MAIN_PWR_SUPPLY

G11 G10

2

B12C12D12C11D11C10B11A11L15L14K15N10M10M11L12K13

A6A5A3A2A1B1B2R8N9P9R9

R10R12P11R11

D2E2G2H2J2K3K2K1L3L2L1P8M6N6P6M8

N7M7M13M12N12N11J15J14H14D9C8B8C7B3A4B7

K4J4H4J3P13N13P14N14P15N15M15E12E13D13

E14D14C14C13C3D3D6D4C2E4D5F3E3G3H3G4

L5K12G13

G12

C1

L11E11

L10F11E7K5H5L8L9

J11

E9E8J5F4

K11E10

F5G5L7

H11

R1P1 N1

K9F10F6K6H6K7K8J10

F8F7J6F2K10F9G6

L6H10

M1

E6

H13H12

J13J12

F13F12J1

N3N2P2R2N4P4P3R3

F15E15D15C15B15A15A14A13

R5R4M5

A10A9A8B6B5A7B4

P12R13L13K14R14R15

M2M3M4L4N5P5H15G15G14F14B14B13A12D1

E1F1

E5

G1H1

R6R7P7N8M9M14

B10B9C9D10

D8D7C6C5C4

2

P10

1

1

BANK1

PDR_ON

DSI_DI_NDSI_DI_P

DSI_D0_NDSI_D0_P

DSI_CK_NDSI_CK_P

PK7PK6PK5PK4PK3

PJ15PJ14PJ13PJ12

PJ5PJ4PJ3PJ2PJ1PJ0

PC13_ANIT_TAMPPC12PC11PC10

PC9PC8PC7PC6PC5PC4PC3PC2PC1PC0

BOOT0

NRST

PH1_OSC_OUTPH0_OSC_IN

PC15_OSC32_OUTPC14_OSC32_IN

PB15PB14PB13PB12PB11PB10PB9PB8PB7PB6PB5PB4PB3PB2PB1PB0

PA15PA14PA13PA12PA11PA10PA9PA8PA7PA6PA5PA4PA3PA2PA1PA0_WKUP

BANK3

VCAP2VCAP1

BYPASS_REGVBAT

VREF-VSSA

VSS20VSS19

VSS17VSS15VSS14

VSS13_VSS18VSS12VSS11VSS10

VSS9VSS8VSS7VSS6VSS5VSS4VSS3VSS2VSS1

DSI_VSS

DSI_VCAPDSI_VDD12

VDD_VREGDSI

VREF+VDDA

VDD19VDD18VDD17VDD15VDD14VDD13VDD12VDD11VDD10

VDD_USBVDD8VDD7VDD6VDD5VDD4VDD3VDD2VDD1

BANK2

PI15PI14PI13PI12PI11PI10

PI9PI8_ANTI_TAMP2

PI7PI6PI5PI4PI3PI2PI1PI0

PH15PH14PH13PH12PH11PH10

PH9PH8PH7PH6PH5PH4PH3PH2

PG15PG14PG13PG12PG11PG10

PG9PG8PG7PG6PG5PG4PG3PG2PG1PG0

PF15PF14PF13PF12PF11PF10PF9PF8PF7PF6PF5PF4PF3PF2PF1PF0

PE15PE14PE13PE12PE11PE10PE9PE8PE7PE6PE5PE4PE3PE2PE1PE0

PD15PD14PD13PD12PD11PD10PD9PD8PD7PD6PD5PD4PD3PD2PD1PD0

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

MCU MISCELLANOUS SIGNALS

4 11

<DESIGN_VIEW>


1:1

B02_049259

<PTD_ENGINEER>

ADG819BRTZ

10K

DNI

10KDNI

LG L29K-G2J1-24-Z

10K

0

0.1UF33

LY L29K-H1J2-26-Z

BSH111BKR

10K

10K

3.9K

3.9K

10K

BSH111BKR

10K

LY L29K-H1J2-26-Z

BSH111BKR

LTC4313CDD-3#PBF

DNI

DNI

2.2K

0.1UF

0.1UF10K

2.2K

0.1UF10K

DNI

0

BSH111BKR

10K

0

0.1UF

74LVC1GU04GX,1251MEG

0

DNI

0

DNI

BSH111BKR

10K

0

1MEG

BSH111BKR

LTC4313CDD-3#PBF

0

74LVC1GU04GX,125

LTC4313CDD-3#PBF

LTC4313CDD-3#PBF

0.1UF

2.2K

BSH111BKR

0

BLU

DNI

BLU

DNI

BLU

DNI

BLU10K

33

33

33

10K

2.2K

0.1UF

10K

4.02K

LS L29K-H1J2-1-Z

4.02K

R219

R16

DS5

DS4

DS6

R224

R221

Q16

R222

Q17

R220

Q18

R223

U37

U36

U35

R214

C21

C66

R213

R212

C30

R211

U34

R22

R20

R67

R25

R21

R19

R64

R23

R218R216

R217R215

Q15

C26

R18

U33

C24

U12

R17

Q1

R78 R113

R104 R210

C28

Q5

R120 TP3 TP4 TP13 TP14

R63

R62

R61

R60

R119

Q4

R118 DS3

U39

C118

USB_AVAILABLEMAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY

ARDUINO_SCL_SWARDUINO_SDA_SW

SDP_I2C_SCL0_SW

SDP_I2C_CTRL_INV

F469_SPI_MOSI/QUADSPI_DIO0

F469_SPI/QUADSPI_NSS_A

SDP_SPI_MISO/QUADSPI_DIO1

+5V

+5V

LED_GREEN

SDP_I2C_CTRL_NON_INV

LED_ORANGE

SDP_I2C_CTRL_INV

SDP_I2C_CTRL_NON_INV

ARDUINO_I2C_CTRL_INV

ARDUINO_SDA

+3.3V

ARDUINO_I2C_CTRL_NON_INV

ARDUINO_I2C_CTRL_NON_INV

ARDUINO_I2C_CTRL_INV

SDP_I2C_SDA+3.3V

PROG_I2C_SCL

+3.3V

+3.3V

SDP_I2C_SCL

+3.3V

PROCESSOR_STATUS

ARDUINO_I2C_CTRL

+3.3V

+3.3V

SDP_I2C_CTRL

+5V


MCU_ADJ

F469_VIO_CHECK

+5V

DEBUG_GPIO2DEBUG_GPIO3

SDP_SPI/QUADSPI_NSS_ADEBUG_GPIO0DEBUG_GPIO1

SDP_SPI/QUADSPI_SCK

SDP_SPI_MOSI/QUADSPI_DIO0

F469_SPI_MISO/QUADSPI_DIO1

+3.3V

MAIN_PWR_SUPPLY

LED_RED

USB_VBUS

ARDUINO_SCL

+5V

MAIN_PWR_SUPPLY

SDP_I2C_SDA0_SW

SDP_I2C_SDA0_SWSDP_I2C_SCL0_SW

PROG_I2C_SDA

ARDUINO_SCL_SW

PROG_I2C_SCLPROG_I2C_SDA

ARDUINO_SDA_SW

A C

A C

A C

8

7 62 3

5

4PAD

1

8

7 62 3

5

4PAD

1

8

7 62 3

5

4PAD

1

8

7 62 3

5

4PAD

1

2

1

3

4

5

1 3

2

4

5

1 3

2

2

1

3

2

1

32

1

3

A C

2

6

4

1

3

5

SG

D

SG

D

S1D

VDDS2

GNDIN

SG

D

SG

D

SG

D

SG

D

EPAD

VCC

SDAOUT SDAIN

READY

GND

SCLINSCLOUT

ENABLE

EPAD

VCC

SDAOUT SDAIN

READY

GND

SCLINSCLOUT

ENABLE

EPAD

VCC

SDAOUT SDAIN

READY

GND

SCLINSCLOUT

ENABLE

EPAD

VCC

SDAOUT SDAIN

READY

GND

SCLINSCLOUT

ENABLE

SG

D

VCC

Y

GND

A

NC

VCC

Y

GND

A

NC

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

PROGRAMMING PROCESSOR

5 11

<DESIGN_VIEW>


1:1

B02_049259

<PTD_ENGINEER>

ADG819BRTZ

2.2K

DNI0.1UF

3220-10-0100-00

3220-10-0100-00

100K

2.2K

0.1UF

ADG854BCPZ

0.1UF

0.1UF

18PF 18PF

10K

10K

BSH111BKR

4.02K

LY L29K-H1J2-26-Z

100K

0.1UF

DNI

8MEGHZ

10K

3333

MK20DX128VFM5

1UF1UF

1MEG

DNI

69157-102HLF

100K 100K

2.2UF

100KR14R13

DS1R115

Q3

R116

R11

C116

P8

C111 C115

C108

C117C112

C114

C113

R110R109

P11

P12

U23

R111R108

R105

R112

R114

U38

R107

R106

C109 C110

Y4

U24

HEADER_SWOF469_SWO

TARGET_SWD_SWV

SWD_CTRL

MAIN_PWR_SUPPLY

MBED_TMS

MBED_TDO

MBED_RESET

HEADER_SWDIO F469_SWDIO

F469_SWCLKTARGET_SWD_CLK

MAIN_PWR_SUPPLY

SDP_I2C_CTRL

TARGET_SWD_SWV

MAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY

PROG_I2C_SDAPROG_I2C_SCL

MBED_TMSPROG_USB_RESET

MBED_LED_CTRL

MAIN_PWR_SUPPLY+5V

MAIN_PWR_SUPPLY

MBED_TCLK

MBED_TDOMBED_TDI

MBED_TCLK

MAIN_PWR_SUPPLY

HEADER_SWCLKTARGET_SWD_DATA_IO

HEADER_SWCLK

SWD_CTRL

PROG_RESET

SWD_CTRL

PROGRAMMING_PROCESSOR_UART_RXPROGRAMMING_PROCESSOR_UART_TX

TARGET_SWD_DATA_IO

BOOT0_CTRLMBED_SYS_HWRSTPROGRAMMING_PROCESSOR_UART_RXPROGRAMMING_PROCESSOR_UART_TXMBED_LED_CTRLTARGET_SWD_CLKUSB_AVAILABLE

MAIN_RESET

HEADER_SWO

HEADER_SWDIO

+5V

ARDUINO_I2C_CTRL

USB_PROG_DPUSB_PROG_DM

MBED_TDI

A C

2

1

3

21

10987654321

10987654321

6

79

31

5

4

10

8

2

2

6

4

1

3

5

21

9

82

6 5

71 11

34

19

32

31

30

29

28

27

26

25242322

2120

18171615141312

PAD

10

SG

D

D2IN2S2BS2A

D1

VDD

S1BIN1

S1A

GND

S1D

VDDS2

GNDIN

PAD

PTD7

PTD6/LLWU_P15

PTD5

PTD4/LLWU_P14

PTC7

PTC6/LLWU_P10

PTC5/LLWU_P9

PTC4/LLWU_P8PTC3/LLWU_P7

PTC2PTC1/LLWU_P6

PTB1PTB0/LLWU_P5

RESET_B

PTA19PTA18PTA4/LLWU_P3PTA3PTA2PTA1PTA0

VBAT

EXTAL32XTAL32

VSSA

VDDA

VREGIN VOUT33

USB0_DMUSB0_DP

VSS

VDD

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

POWER ON RESET

6 11

<DESIGN_VIEW>


1:1

B02_049259

<PTD_ENGINEER>

0.1UF

0.1UF

SN74LVC1G08DBVT

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

100K

EVQQ2K03W

10K

ADM6384YKS17D3Z100K

100K

100K

100K

ADM6384YKS29D3Z

95.3K

100K

ADM6384YKS29D3Z

100K

100K

120K

PMV48XP,215

BSH111BKR

AD8613AKSZ

3.9K

100K

SN74LVC1G08DBVT

100K

100K

SN74LVC1G08DBVT

74LVC1G11DW-7

0.1UF

74AUP1G09GW

ADG819BRTZ

ADG819BRTZ

U32

R15

U31

R69

Q10

Q6

U28

R68

U40

C88

U29

R76

R75

C91

C92

U15

C90

C89

U30

R82

R81

R80

R79R77

C87

U41

R74

S1

R70

U10C82

U14C85

R73

C86

R71

C83

U13C84

R72

SDP_RESET_IN

MBED_RESET

MAIN_PWR_SUPPLY

+5V

RESET_BUTTON

USB_RESET

HUB_RESET

MAIN_PWR_SUPPLY

USB_ULPI_RESET

MAIN_PWR_SUPPLY

+5V

POR_3.3VMAIN_PWR_SUPPLY

RESET_BUTTON

MAIN_PWR_SUPPLY

PROG_RESET

MAIN_PWR_SUPPLY

RESET_BUTTON

RESET_BUTTON

MAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY

MBED_SYS_HWRSTMAIN_RESET

MAIN_PWR_SUPPLY

+3.3V

+3.3V

+5V ULPI_VBAT_CHECKPROG_USB_RESET

USB_ULPI_RESET

MCU_ADJ

POR_3.3V

MCU_ADJ

ULPI_VBAT_CHECK

4

5

3

1

2

4

5

3

21

2

1

3

2

1

3

2

5

143

2

6

4

1

3

5

4

5

3

21

4

5

3

21

4

5

2

631

2

6

4

1

3

5

2B1B

2A1A

4231

4231

4231

VCC

Y

GND

A

BVCC

GNDB

YA

SG

D

RESET_NMR_NVCC GND

V+

-IN+IN

V-OUT

S1D

VDDS2

GNDIN

VCC

GNDB

YA

IO

VCC

GNDB

YAVCC

GNDC

YBA

S1D

VDDS2

GNDIN

RESET_NMR_NVCC GND

RESET_NMR_NVCC GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

IO_SUPPLY

VIO_ADJUST

3.3V

1.8V

PWR_GOOD

USB_SUPPLY

+5V_REG

MAIN_SUPPLY

3.5 AMP MAX

VIN

RECOMMENDED VOLTAGE RANGE: 7V -12V

POWER CIRCUITRY

MPU_VDD_USB

SDRAM_ARDUINO_SUPPLY

7 11

<DESIGN_VIEW>


1:1

B02_049259

<PTD_ENGINEER>

1UF

34.8K

1UF

DNI

LG L29K-G2J1-24-Z

PMV48XP,215

ADP1290ACBZ

BSH111BKR ADP7105ACPZ-3.3

1UF

DMP1046UFDB -7DMP1046UFDB -7

RED

RED

DNIADP7105ACPZ

LT8609SIV#PBF

PMEG3030EP,115PJ-037AH

0.1UF

178K

10PF

374K 374K

100K

1UF

ADP7105ACPZ-3.3

BSS138LT1G

DNI

6.8NF

6.8NF

6.8NF

6.8NF

DNI

100K

22UF

DMP1046UFDB -7DMP1046UFDB -7

16.9K

22UF

DMP1046UFDB -7

LTC4417HUF#PBF

100K

4.02K

0

16.9K

BSS138LT1G

1.5A

105K

0

ADP7105ACPZ

34.8K

0DNI

RED

DNI

1UF

5016

1UF

ADP7105ACPZ-3.3

0.1UF

0.1UF

0.1UF0.1UF0.1UF

1MEG

13.7K

6.8UH38.3K

86.6K

1UF

30K

12K

1UF

0

1MEG

1UF

1UF

100K100K

38.3K

1MEG

100K

100K

13.7K

M20-9990345

374K

1UF

86.6K

1UF

RED

DNI

RED

DNI

5016

1UF

86.6K

38.3K

0.1UF

DMP1046UFDB -7

100K

1MEG

100K

453K4.7UF

0

RED

REDDNI

47UF47UF

100K

100K

DNI

DNI

6.8NF

100K

C146

Q8

R191

R87

R91

R86

C95

C94

C93

U16

R92R177

R178

C97 U17

C99 R181

R179

R182

C101

R183

R85

R84

R83

R90

R89

R88

R95

R94

R93

R185

C102 R184

U18

C105

U19

C107

C134 R188

TP7

C135

C139

TP8

C104

U20

C103

U21

C137

C138

R193

C136

C140

R192

U26

R205

TP11

TP9

R197

TP10

R195

P14

C133

R187 C141

R194 R203

L1

R202 C145 C147 C148

R196 R200

R199R198

R204

Q12

Q12

Q14

Q14Q13

Q13

C96 C98 C100

P15 D5

Q9

R189

R190

C143

R201F3

Q7

Q11

U22

DS2R117

TP23TP22

R186C106

TP12

TP6

C142

C144

SDRAM_&_ARDUINO_PWR_SUPPLY

+5V_REG

USB_CONFIG

USB_CONFIG

MAIN_PWR_SUPPLY

MAIN_PWR_SENSE

+3.3V

USB_CONFIGPROCESSOR_VDD_USB

MAIN_PWR_SUPPLY

SEC_PWR_SENSE

SEC_PWR_SENSE

SDP_VIN_UV

MCU_ADJ

SDP_VIN

ARDUINO_VIN

+5V

USB_VBUS_UV

+5V

MAIN_PWR_SENSE

+5V_REG_OV USB_VBUS_OV

USB_VBUS_UV

USB_VBUS

USB_VBUS_OV

+5V

PROCESSOR_AWAKE

+5V_REG

USB_VBUS

+5V_REG_OVSDP_VIN

SDP_VIN_UVSDP_VIN_OV

+5V_REG_UV+5V_REG

+5V

+5V_REG_UV

+5V

IO_PWR_SUPPLY

+5V_CON_USB

+5V

SDP_VIN_OV

SDP_VIN

+5V

+5V_REG USB_VBUS

+5V

+5V_REG

1122

171513

10

24

2

4

6

PAD

23

1

3

5

21

20

19 789

12

18 16 14

C1 C2

A1B1

A2B2

5

3 6 PAD

7

2

4

8 1

5

3 6 PAD

7

2

4

8 1

1

1

5

3 6 PAD

7

2

4

8 1

5

3 6 PAD

7

2

4

8 1

3 6

7

2

4

8 1 1

1

1

12

3

3PA

D2

5

4

6 PAD1

2

1

3PA

D2

5

4

6 PAD1

2

1

6 PAD1

2

1

3PA

D2

5

4

1

2

CA

3

1

2

3

1

2

1 2

3

1

2

3

1

2

11

PAD

13

3 4 8 14 7 17 18 19 20

121

56

16

15

29

10

CA

11

1

1

5

PAD

PAD

VIN

PGEN/UVLOSSGND

SENSE/ADJ

VOUT

PAD

VIN

PGEN/UVLOSSGND

SENSE/ADJ

VOUT

PAD

VIN

PGEN/UVLOSSGND

SENSE/ADJ

VOUT

PAD

VIN

PGEN/UVLOSSGND

SENSE/ADJ

VOUT

GNDENVOUTVINVOUTVIN

PAD

NCNCNCNC

SYNC

TR/SS

GND

FBPG

EN/UVVINVIN

GND NC

SWSW

GND

GND

VCC

RT

SG

D

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

PAD

V1

V2

V3

VS1

G1

VS2

G2

VS3

G3

VOUT

CAS

GND

VALID3_NVALID2_NVALID1_N

OV3UV3

OV2UV2

OV1UV1

HYSSHDN_NEN

BA

PAD

VIN

PGEN/UVLOSSGND

SENSE/ADJ

VOUT

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

89/PWM10/PWM/CS

AIN 6/PWM

GNDGND

A0

--

----

-

-----

RESETIOREF

NC

A3

A5A4

A2A1

-----7

4

2TX + 1RX + 0

5/PWM

SDASCL

1.7 <= AREF <= VDDAAREFGND13/SCK12/MISO11/PWM/MOSI

DIGI0

DIGI1

3/PWM

VIN

5V3.3V

POWER

ANALOG

THE ADC'S PINS A4 AND A5 ARE ONLY USED AS ADC'S THEY DO NOT WORK AS I2C LINES

ARDUINO CONNECTOR

8 11

<DESIGN_VIEW>


1:1

B02_049259

<PTD_ENGINEER>

RED

DNI

2.2K2.2K

PPPC101LFBN-RC

PPPC081LFBN-RC

PPPC081LFBN-RC

PPPC061LFBN-RC

TSW-103-07-F-D

TP5

R66R65

P5

P3

P7

P4

P6

ARDUINO_GPIO7ARDUINO_GPIO6/PWM2ARDUINO_GPIO5/PWM1

ARDUINO_GPIO4ARDUINO_GPIO3/PWM0

ARDUINO_GPIO0/RX

ARDUINO_GPIO8

ARDUINO_ADC_IN2

ARDUINO_ADC_IN5

ARDUINO_ADC_IN3

IO_PWR_SUPPLY

ARDUINO_VIN

ARDUINO_GPIO1/TX

ARDUINO_GPIO9/PWM3ARDUINO_GPIO10/PWM4/SS

ARDUINO_SCLARDUINO_SDA

ARDUINO_GPIO12/MISO

+5V

ARDUINO_GPIO13/SCK

ARDUINO_GPIO11/PWM5/MOSI

MAIN_PWR_SUPPLY

MAIN_RESET

ARDUINO_GPIO11/PWM5/MOSI

ARDUINO_ADC_IN4

ARDUINO_ADC_IN1ARDUINO_ADC_IN0

ARDUINO_GPIO2

ARDUINO_ADC_REF

ARDUINO_GPIO13/SCKARDUINO_GPIO12/MISO

+5V_CON_USBSDRAM_&_ARDUINO_PWR_SUPPLY

MAIN_RESET

1

654321

87654321

87654321

654321

10987654321

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

SPI

CONNECTOR

VIO: USED TO SET I/O VOLTAGE

VIN: USE THIS PIN TO POWER THE SDP-K1 REQUIRES 5V 300MA

HIGH OR LOW BY YOUR BOARD AT POWER UP. FAILURE TO MEET THIS CRITERIA MAY RESULT IN A NON-FUNCTIONAL SYSTEM.

DATA LINE UNLESS PROPERLY ADDRESSED WITH AN ACTIVE LOW CHIP SELECT, YOU MUST ALSO ENSURE THE SPI CLK LINE IS NOT HELD

PARALLELPORT

GENERALINPUT/OUTPUT

I2C

SPORT

AS SPI IS A SHARED BUS, YOU MUST ENSURE THAT ANY SPI DEVICES ON YOUR DAUGHTER BOARD ARE NOT ACTIVELY DRIVING THE MISO

STANDARD

NOT OVERLAP THAT OF THE EI3 BREAK-OUT BOARD.

IS NOT 0X50 OR 0X51. THIS IS TO ENSURE THE I2C ADDRESS RANGE DOES

CARE MUST BE TAKEN TO ENSURE DAUGHTER BOARD I2C EEPROM ADDRESS

WHEN DESIGNING A DAUGHTER BOARD THE ID EEPROM (24LC32) MUST BE ON I2C BUS 0.

SDP CONNECTORTHE SDP CONNECTOR IMPLEMENTS THE EI3 CONNECTOR SPECIFICATION STANDARD. THIS IS A STANDARD FOR USE ACROSS ADI AND CANNOT BE MODIFIED

9 11

<DESIGN_VIEW>


1:1

B02_049259

<PTD_ENGINEER>

DNI

10K

DNI

10K 10K

DNI

10K

DNI

FX8-120P-SV1(92)

2.2K 2.2K

0

100K

R103

R96

R100

R99

R98R97

R101 R102

P10

SDP_SPI_NSS_C

SDP_SPORT_TFS

SDP_SPI_NSS_B

SDP_SPI_NSS

MAIN_PWR_SUPPLY

SDP_I2C_SCLSDP_I2C_SDA

MAIN_PWR_SUPPLY

SDP_SPI/QUADSPI_NSS_A

SDP_EXT_BOOT

SDP_SPORT_TSCLKSDP_SPORT_DT0

SDP_RESET_INSDP_UART_TX

SDP_SPORT_DR0SDP_SPORT_RFS

MAIN_RESET

SDP_UART_RX

SDP_GPIO4SDP_GPIO2

SDP_SPI_MISO/QUADSPI_DIO1SDP_SPI_MOSI/QUADSPI_DIO0

SDP_SPORT_RSCLK

IO_PWR_SUPPLY

SDP_SPI/QUADSPI_SCK

SDP_GPIO1SDP_GPIO3SDP_GPIO5

SDP_GPIO7SDP_TMR_BSDP_TMR_D

SDP_TMR_ASDP_GPIO6

SDP_GPIO0

SDP_SERIAL_INTSDP_QUADSPI_DIO3SDP_QUADSPI_DIO2

+5V_CON_USB

SDP_VIN

116

65

1

5

6259

72497348

87

89

3029 92

9032

88

3191

3837

85

39

8483

3433

82

64

35

41 8042 79

57

60

1002199

26 9527

7 1148 1139 112

10 111110

1213 10814 10715 10616 105

18 10319 10220 101

22

94

24 9725 96

120119

70

68676655

5453

5150

2

7447

764577447843

118117

115

109

104

98

93

86

81

75

69

6358

52

46

40

36

28

23

17

11

6

43

56

71

61

SPI_SEL_A_N

CLKOUT

NCNC

GNDGNDVIO

GNDPAR_D22PAR_D20PAR_D18PAR_D16PAR_D15

GNDPAR_D12PAR_D10

PAR_D8PAR_D6

GNDPAR_D4PAR_D2PAR_D0

PAR_WR_NPAR_INT

GNDPAR_A2PAR_A0

PAR_FS2PAR_CLK

GNDSPORT_RSCLK

SPORT_DR0SPORT_RFSSPORT_TFSSPORT_DT0

SPORT_TSCLKGND

SPI_MOSISPI_MISO

SPI_CLKGND

SDA_0SCL_0GPIO1GPIO3GPIO5

GNDGPIO7

TMR_BTMR_D

NCGND

NCNCNC

WAKE_NSLEEP_N

GNDUART_TXBMODE1RESET_IN_N

UART_RXGNDRESET_OUT_NEEPROM_A0NCNCNCGNDNCNCTMR_CTMR_AGPIO6GNDGPIO4GPIO2GPIO0SCL_1SDA_1GNDSPI_SEL1/SPI_SS_NSPI_SEL_C_NSPI_SEL_B_NGNDSERIAL_INTSPI_D3SPI_D2SPORT_DT1SPORT_DR1SPORT_TDV1SPORT_TDV0GNDPAR_FS1PAR_FS3PAR_A1PAR_A3GNDPAR_CS_NPAR_RD_NPAR_D1PAR_D3PAR_D5GNDPAR_D7PAR_D9PAR_D11PAR_D13PAR_D14GNDPAR_D17PAR_D19PAR_D21PAR_D23GNDUSB_VBUSGNDGNDNCVIN

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

SDRAM LEVEL TRANSLATORS

10 11

<DESIGN_VIEW>


1:1

B02_049259

<PTD_ENGINEER>

10K

10K

10K

1

0.1UF

0.1UF0.1UF0.1UF0.1UF0.1UF

0.1UF

0.1UF0.1UF

0.1UF0.1UF

0.1UF0.1UF

0.1UF0.1UF

74LVC8T245BQ,118

74LVC8T245BQ,118

1

6

5

4

74LVC8T245BQ,118

15

16

10

11

12

13

14

9

1

7

74LVC8T245BQ,118

4

2

74LVC8T245BQ,118

74LVC8T245BQ,11828

22

23

3

31

30

26

29

27

25

24

21

16

19

18

17

20

11

12

13

15

9

8

10

31

30

29

27

26

28

24

25

23

22

21

20

19

17

18

8

0

2

5

6

7

5

4

3

1

0

15

7

8

9

3

11

14

10

0

6

2

6

7

8

9

2

3

11

14

0

15

10

5

0

4

14

74LVC8T245BQ,118

74LVC1GU04GX,125R27

U9

U8

U7

U6

U5

U4

U27

C46

C39C45C44C43C42

C41C40C38

C35C32

C36C33

C37C34

R28

R30

R29

U3

SDRAM_A<11:0>

SDRAM_D<31:0>

MAIN_PWR_SUPPLY

TRNSLT_OE

SDRAM_A_TRNSLT<11:0>


SDRAM_DATA_DIR_CTRL


TRNSLT_OE


SDRAM_N_WE

TRNSLT_OE

MAIN_PWR_SUPPLY

SDRAM_NBL2_TRNSLT

TRNSLT_OE



TRNSLT_OE

SDRAM_&_ARDUINO_PWR_SUPPLY MAIN_PWR_SUPPLY

SDRAM_DATA_DIR_CTRL



MAIN_PWR_SUPPLY

SDRAM_N_RAS_TRNSLTSDRAM_N_CAS_TRNSLT

SDRAM_DATA_DIR_CTRL

SDRAM_DATA_DIR_CTRL

MAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY

MAIN_PWR_SUPPLY

SDRAM_N_WE

SDRAM_SDCKE0SDRAM_SDCLKSDRAM_SDNE0

SDRAM_N_CASSDRAM_N_RAS

MAIN_PWR_SUPPLY


SDRAM_NBL1_TRNSLT

SDRAM_NBL3_TRNSLT

SDRAM_N_WE_TRNSLTSDRAM_SDNE0_TRNSLT

SDRAM_NBL0_TRNSLT

TRNSLT_OE

SDRAM_NBL3SDRAM_NBL2SDRAM_NBL1SDRAM_NBL0

SDRAM_SDCKE0_TRNSLT

TRNSLT_OE

SDRAM_DATA_TRNSLT<31:0>

SDRAM_A<15:14>

MAIN_PWR_SUPPLY

SDRAM_SDCLK_TRNSLT

TRNSLT_OE

MAIN_PWR_SUPPLY

24 23 1

PAD

22

13 12 11

2

1415161718192021

109876543

24 23 1

PAD

22

13 12 11

2

1415161718192021

109876543

24 23 1

PAD

22

13 12 11

2

1415161718192021

109876543

24 23 1

PAD

22

13 12 11

2

1415161718192021

109876543

24231

PAD

22

131211

2

1415161718192021

109876543

24231

PAD

22

131211

2

1415161718192021

109876543

4

5

13

2

24231

PAD

22

131211

2

1415161718192021

109876543

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8

GNDA8A7A6A5A4A3A2A1

DIR

VCCA

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8

GNDA8A7A6A5A4A3A2A1

DIR

VCCA

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8

GNDA8A7A6A5A4A3A2A1

DIR

VCCA

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8

GNDA8A7A6A5A4A3A2A1

DIR

VCCA

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8

GNDA8A7A6A5A4A3A2A1DIR

VCCA

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8


VCCA

VCC

Y

GND

A

NC

PAD

VCCBOE_N

B1B2B3B4B5B6B7B8


VCCA

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

SDRAM

11 11

<DESIGN_VIEW>


1:1

B02_049259

<PTD_ENGINEER>

2

0

1

3

5

6

0

1

2

3

4

5

7

6

9

10

14

15

20

25

26

27

29

31

DNI

DNI0

0

0

3

1

2

4

5

6

7

9

11

DNI

DNI

0

0

0 DNI

0

0

0 DNI

12

14

15

17

18

21

19

20

22

23

26

24

25

27

28

31

30

4

5

9

10

13

14

15

21

24

25

26

27

28

29

30

4

7

8

9

10

11

14

15

1

0

7

8

0 14

15

0

1

3

4

5

6

7

8

9

10

11

DNI

0

14

15

0

0DNI

DNI0

DNI0DNI

0 DNI

0

4

6

DNI

020

DNI

DNI

2

0 3DNIDNI

50 DNI0

00

DNIDNI

0 DNI9

0 DNI

DNI010

11

DNI0

0DNI

DNI0

0 DNIDNI

DNI0DNI0

0

DNI0

8

0 DNI

DNI0

0

0

DNI

0

08

10

0

DNI

DNI

DNIDNI

11DNI

13

17

0 12

DNI

16

0 DNI

DNI

0

0

0

DNI

16

DNI

0 DNI

0 23

13 0

DNI

19

220 DNIDNI

21

0 DNI

18

0

0

24DNI

DNI0DNI

28

30

DNI0DNI

29 0 DNI

DNI

12

31

0

1

6

8

11

16

17

18

23

22

20

19

MT48LC4M32B2B5-6AIT:L

7

2

3

0.1UF 0.1UF 0.1UF

0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

0.1UF 0.1UF 0.1UF 0.1UF

C131C129C127C125C123C121C119

C132C130C128C126C124C122C120

R142

R131

R130

R143

R144R132

R139R128

R127

R140

R141R129

R136R125

R124

R137

R138R126

R134

R133

R135

R121

R122

R123R145

R161

R162

R163

R164

R165

R167

R166

R168

R169

R170

R171

R172

R173

R174

R176

R175

R146

R147

R149

R148

R150

R151

R152

R154

R153

R155

R156

R157

R158

R159

R160

U25

SDRAM_SDNE0_TRNSLT

SDRAM_SDCLK_TRNSLTSDRAM_SDCKE0_TRNSLT

SDRAM_NBL2_TRNSLT


SDRAM_NBL1_TRNSLT

SDRAM_D<31:0>

SDRAM_NBL1

SDRAM_NBL3

SDRAM_NBL0

SDRAM_NBL2

SDRAM_NBL3_TRNSLT

SDRAM_A<15:14>

SDRAM_N_WE

SDRAM_SDCLKSDRAM_SDNE0

SDRAM_N_RASSDRAM_N_CAS

SDRAM_SDCKE0

SDRAM_A<11:0>

SDRAM_NBL0_TRNSLT

SDRAM_SDCKE0_TRNSLTSDRAM_SDCLK_TRNSLTSDRAM_SDNE0_TRNSLTSDRAM_N_WE_TRNSLTSDRAM_N_CAS_TRNSLTSDRAM_N_RAS_TRNSLT



SDRAM_NBL0_TRNSLTSDRAM_NBL1_TRNSLTSDRAM_NBL2_TRNSLTSDRAM_NBL3_TRNSLT



SDRAM_N_RAS_TRNSLTSDRAM_N_CAS_TRNSLTSDRAM_N_WE_TRNSLT





K8

P8P3N1M1L9E9D1C1B8B3R3L3F1A3

P7P2N9M9

L1E1D9C9B7B2R7L7F9A7

J9

K2

K3H7H3E7E3

F2F8K1K9

E2D3D2B1C2A1C3A2A8C7A9C8B9D8D7E8R2N3R1N2P1M2M3L2L8M7M8P9N8R9N7R8

J8

J1J2

K7

H8J7

H9G7J3H2H1G3G2G1F3F7G9G8

DQ2

DQ0VDD

VSS

DQ15

DQ13

DQ4

VSSQ

VDDQ

VSSQ

VDDQ

DQ11

VDDQ

DQ3

DQ1

DQ14

DQ12

VSSQ

VDDQ

DQ5DQ6

DQ9DQ10

VSSQ

VSSQ

DQ7

VDD

VSS

DQ8

VDDQ

DQM0

WE#CAS#

NC

NU

DQM1

RAS#

CS#

BA0

A9

CKECLK

A11

BA1

NCNC

A8A7

A1A0

A10

A6A5A4

VDD

DQM2

A2A3

DQM3

VSS

VSSQ

DQ16

NCNC

DQ31

VDDQ

VDDQ

DQ18DQ17

DQ30DQ29

VSSQ

VDDQ

DQ20

DQ22

DQ25

DQ27

VSSQ

DQ19

VSSQ

VDDQ

VSSQ

VDDQ

DQ28

DQ21

DQ23

VDD

VSS

DQ24

DQ26

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

the equipment shown hereon may be protected by … · 1 11 : pitch-pitch stylevendor style...

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