textbook: digital design, 3rdrd. edition . edition m. …soc.eecs.yuntech.edu.tw/course/digital...
TRANSCRIPT
P-1/702005/5/11
Textbook: Textbook: Digital Design, 3Digital Design, 3rdrd. Edition. EditionM. Morris Mano
Prentice-Hall, Inc.
教 師 : 蘇 慶 龍INSTRUCTOR : CHING-LUNG SU
課程名稱課程名稱: : 數位邏輯設計數位邏輯設計
E-mail: [email protected]
P-2/702005/5/11
Chapter 3Chapter 3GateGate--Level MinimizationLevel Minimization
Chapter 3Chapter 3
P-3/702005/5/11Outline of Chapter 3Outline of Chapter 3
3.1 The Map Method3.2 Four-Variable Map3.3 Five-Variable Map3.4 Product of Sums Simplification3.5 Don’t-Care Conditions3.6 NAND and NOR Implementation3.7 Other Two-Level Implementations3.8 Exclusive-OR Function3.9 Hardware Description Language (HDL)
P-4/702005/5/113.1 3.1 The Map MethodThe Map Method
3.1 The Map Method3.2 Four-Variable Map3.3 Five-Variable Map3.4 Product of Sums Simplification3.5 Don’t-Care Conditions3.6 NAND and NOR Implementation3.7 Other Two-Level Implementations3.8 Exclusive-OR Function3.9 Hardware Description Language (HDL)
P-5/702005/5/11
nn Map Simplification Methods of the Boolean Map Simplification Methods of the Boolean FunctionFunction
3.1 3.1 The Map MethodThe Map Method
Karnaugh Map (K-Map): 1. is a pictorial form of the truth table2. express any Boolean function as a sum of minterms3. presents all possible Boolean function in standard
form4. Simplify a Boolean function in two standard form:
sum of products or product of sums5. the simplest K-map will be implemented the
minimum number of gates
P-6/702005/5/11
nn TwoTwo--Variable KVariable K--MapMap
3.1 3.1 The Map MethodThe Map Method
Karnaugh Map (K-Map) presents the four minterms of a two-variable function as follows
m0 m1
m2 m3
xy xy
xy xy
yx 0
0
x=1
y=1
P-7/702005/5/11
nn Presentation of Functions in a KPresentation of Functions in a K--MapMap
3.1 3.1 The Map MethodThe Map Method
Example: F=xy
1
yx 0
0
x=1
y=1
Example: F = x + y= x’y + xy’+ xy= m1 + m2 + m3
1
1 1
yx 0
0
x=1
y=1
P-8/702005/5/11
nn ThreeThree--Variable KVariable K--MapMap
3.1 3.1 The Map MethodThe Map Method
Karnaugh Map (K-Map) presents the eight mintermsof a three-variable function as follows
m0 m1
m4 m5
yzx 00
0
x=1
y=1
m3 m2
m7 m6
01 11 10
1
Gray-Code(Only one variable changes
between two adjacent position)
z=1
y=0
x=0
z=0z=0
P-9/702005/5/11
nn ThreeThree--Variable KVariable K--Map with Map with MintermsMinterms
3.1 3.1 The Map MethodThe Map Method
m0 m1
m4 m5
m3 m2
m7 m6
xyz xyz
xyz xyz
yzx 00
0
x=1
y=1
xyz xyz
xyz xyz
01 11 10
1
z=1
P-10/702005/5/11
nn ThreeThree--Variable KVariable K--Map with Map with MintermsMinterms
3.1 3.1 The Map MethodThe Map Method
Example for a 3-variable function with its K-map:F(x,y,z) = m2 + m3 + m4 + m5
= Σ(2,3,4,5)= x’y + xy’
1 1
yzx 00
0
x=1
y=1
1 1
01 11 10
1
z=1
y=0
m2+m3
m4+m5
P-11/702005/5/11
nn Simplify a ThreeSimplify a Three--Variable Boolean Variable Boolean Function Using KFunction Using K--MapMap
3.1 3.1 The Map MethodThe Map Method
F(x,y,z) = Σ(3,4,6,7)= yz + z’x
1
yzx 00
0
x=1
y=1
1
1 1
01 11 10
1
z=1
m3+m7
m4+m6
P-12/702005/5/11
nn Simplify a ThreeSimplify a Three--Variable Boolean Variable Boolean Function Using KFunction Using K--MapMap
3.1 3.1 The Map MethodThe Map Method
F(x,y,z) = Σ(0,2,4,6)= z’
1
1
yzx 00
0
x=1
y=1
1
1
01 11 10
1
z=1
(m0+m2)
(m4+m6)+
P-13/702005/5/11
nn KK--Map Simplify for a ThreeMap Simplify for a Three--Variable FunctionVariable Function
3.1 3.1 The Map MethodThe Map Method
1 minterm represents a term of 3 literals2 adjacent squares represents a term of 2 literals4 adjacent squares represents a term of 1 literal8 adjacent squares represents the function = 1
P-14/702005/5/11
nn Simplify a ThreeSimplify a Three--Variable Boolean Variable Boolean Function Using KFunction Using K--MapMap
3.1 3.1 The Map MethodThe Map Method
F(x,y,z) = Σ(0,2,4,5,6)= z’ + xy’
1
1 1
yzx 00
0
x=1
y=1
1
1
01 11 10
1
z=1
m4+m5
m0+m2+m4+m6
P-15/702005/5/11
nn Simplify Boolean Function Using KSimplify Boolean Function Using K--MapMap
3.1 3.1 The Map MethodThe Map Method
F(A,B,C) = A’C + A’B + AB’C + BC= Σ (1,2,3,5,7)= C + A’B
1
1
BCA 00
0
A=1
B=1
1 1
1
01 11 10
1
C=1
A B
C
P-16/702005/5/113.2 3.2 FourFour--Variable MapVariable Map
3.1 The Map Method3.2 Four-Variable Map3.3 Five-Variable Map3.4 Product of Sums Simplification3.5 Don’t-Care Conditions3.6 NAND and NOR Implementation3.7 Other Two-Level Implementations3.8 Exclusive-OR Function3.9 Hardware Description Language (HDL)
P-17/702005/5/113.2 3.2 FourFour--Variable MapVariable Map
nn FourFour--Variable KVariable K--MapMap
Karnaugh Map (K-Map) presents the 16 minterms of a four-variable function as follows
m0 m1
m4 m5
yzwx 00
00
w=1
y=1
m3 m2
m7 m6
01 11 10
01
Gray-Code
z=1
m12 m13
m8 m9
m15 m14
m11 m10
11
10
x=1
Gray-Code
P-18/702005/5/11
nn FourFour--Variable KVariable K--Map with Map with MintermsMinterms
3.2 3.2 FourFour--Variable MapVariable Map
m0 m1
m4 m5
yzwx 00
00
w=1
y=1
m3 m2
m7 m6
01 11 10
01
z=1
m12 m13
m8 m9
m15 m14
m11 m10
11
10
x=1
wxyz
yzwx 00
00
01 11 10
01
wxyz11
10
P-19/702005/5/11
nn KK--Map Simplify for a FourMap Simplify for a Four--Variable FunctionVariable Function
1 minterm represents a term of 4 literals2 adjacent squares represents a term of 3 literals4 adjacent squares represents a term of 2 literals8 adjacent squares represents a term of 1 literal16 adjacent squares represents the function = 1
3.2 3.2 FourFour--Variable MapVariable Map
P-20/702005/5/113.2 3.2 FourFour--Variable MapVariable Map
nn Simplify a FourSimplify a Four--Variable Boolean Variable Boolean Function Using KFunction Using K--MapMap
F(w,x,y,z) = Σ(0,1,2,4,5,6,8,9,12,13,14)= y’ + w’z’ + xz’
1 1
1 1
yzwx 00
00
w=1
y=1
1
1
01 11 10
01
z=1
1 1
1 1
111
10
x=1
y'
z w
xz
P-21/702005/5/113.2 3.2 FourFour--Variable MapVariable Map
nn Simplify a FourSimplify a Four--Variable Boolean Function Using KVariable Boolean Function Using K--MapMap
F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’= B’D’ + B’C’ + A’CD’
1 1
CDAB 00
00
A=1
C=1
1
1
01 11 10
01
D=1
1 1 1
11
10
B=1
B C
A CD
B D
P-22/702005/5/113.2 3.2 FourFour--Variable MapVariable Map
nn Prime Prime Implicants Implicants and Essential Prime and Essential Prime ImplicansImplicans
1. Prime Implicant : A product term containing the maximum possible number of adjacent squares in the K-map
2. Essential Prime Implicant : A prime implicantcontains a minterm that is covered by only one prime implicant
P-23/702005/5/113.2 3.2 FourFour--Variable MapVariable Map
nn Function Simplification Using Prime Function Simplification Using Prime ImplicantImplicantEssential Prime Implicants:BD and B’D’
Prime Implicants:CD, B’C, AD, and AB’
1
1
CDAB 00
00
A
C
1
1
01 11 10
01
D
1
1
1
1
11
10
B
1
1
CDAB 00
00
A
C
1 1
1
01 11 10
01
D
1
1 1
1
1 1
11
10
B
P-24/702005/5/113.2 3.2 FourFour--Variable MapVariable Map
nn Simplify Boolean Function Using KSimplify Boolean Function Using K--MapMap
F = Σ(0,2,3,5,7,8,9,10,11,13,15)= BD+B’D’+CD+AD= BD+B’D’+CD+AB’= BD+B’D’+B’C+AD= BD+B’D’+B’C+AB’
Essential Prime Implicants
P-25/702005/5/113.3 3.3 FiveFive--Variable MapVariable Map
3.1 The Map Method3.2 Four-Variable Map3.3 Five-Variable Map3.4 Product of Sums Simplification3.5 Don’t-Care Conditions3.6 NAND and NOR Implementation3.7 Other Two-Level Implementations3.8 Exclusive-OR Function3.9 Hardware Description Language (HDL)
P-26/702005/5/113.3 3.3 FiveFive--Variable MapVariable Map
nn FiveFive--Variable KVariable K--Map: F(A,B,C,D,E)Map: F(A,B,C,D,E)
m0 m1
m4 m5
DEBC 00
00
B
D
m3 m2
m7 m6
01 11 10
01
E
m12 m13
m8 m9
m15 m14
m11 m10
11
10
C
m16 m17
m20 m21
DEBC 00
00
B
D
m19 m18
m23 m22
01 11 10
01
E
m28 m29
m24 m25
m31 m30
m27 m26
11
10
C
A=0 A=1
P-27/702005/5/113.3 3.3 FiveFive--Variable MapVariable Map
nn The Relationship between the Number of Adjacent The Relationship between the Number of Adjacent Squares and the Number of Literal in the TermSquares and the Number of Literal in the Term
K 2k n=2 n=3 n=4 n=5
0 1 2 3 4 51 2 1 2 3 42 4 0 1 2 33 8 0 1 24 16 0 15 32 0
Number of Literals in aTerm in an n-variable Map
Number ofAdjacent Square
P-28/702005/5/113.3 3.3 FiveFive--Variable MapVariable Map
nn Simplify the 5Simplify the 5--variable Function Using Kvariable Function Using K--MapMapF = Σ(0,2,4,6,9,13,21,23,25,29,31)
= A’B’E’+BD’E+ACE
1
1
DEBC 00
00
B
D
1
1
01 11 10
01
E
1
1
11
10
C1
DEBC 00
00
B
D
1
01 11 10
01
E
1
1
111
10
C
A=0 A=1
BD E
ACE
P-29/702005/5/113.4 3.4 Product of Sums SimplificationProduct of Sums Simplification
3.1 The Map Method3.2 Four-Variable Map3.3 Five-Variable Map3.4 Product of Sums Simplification3.5 Don’t-Care Conditions3.6 NAND and NOR Implementation3.7 Other Two-Level Implementations3.8 Exclusive-OR Function3.9 Hardware Description Language (HDL)
P-30/702005/5/113.4 3.4 Product of Sums SimplificationProduct of Sums Simplification
nn SOP vs. POSSOP vs. POS
1. Review DeMorgen’s Theorem:A Function can be express as SOP or POS
2. Example:
F(x,y,z) = Σ(1,3,6,7)= Π(0,2,4,5)x y z F
0 0 0 0 Π0 0 1 1 Σ0 1 0 0 Π0 1 1 1 Σ1 0 0 0 Π1 0 1 0 Π1 1 0 1 Σ1 1 1 1 Σ
P-31/702005/5/113.4 3.4 Product of Sums SimplificationProduct of Sums Simplification
nn Simplify Function in SOP and POSSimplify Function in SOP and POS
F(A,B,C,D) = Σ(0,1,2,5,8,9,10)= B’D’ + B’C’ + A’C’D
F=(F’)’=(AB+CD+BD’)’= (A’+B’)(C’+D’)(B’+D)
1 1
0 1
CDAB 00
00
A
C
0 1
0 0
01 11 10
01
D
0 0
1 1
0 0
0 1
11
10
B
P-32/702005/5/113.4 3.4 Product of Sums SimplificationProduct of Sums Simplification
nn Gate Implementation in SOP and POSGate Implementation in SOP and POS
F(A,B,C,D) = B’D’ + B’C’ + A’C’D = (A’+B’)(C’+D’)(B’+D)
AB
D
D
FC
BD
CAD
F
P-33/702005/5/113.5 3.5 DonDon’’tt--Care ConditionsCare Conditions
3.1 The Map Method3.2 Four-Variable Map3.3 Five-Variable Map3.4 Product of Sums Simplification3.5 Don’t-Care Conditions3.6 NAND and NOR Implementation3.7 Other Two-Level Implementations3.8 Exclusive-OR Function3.9 Hardware Description Language (HDL)
P-34/702005/5/113.5 3.5 DonDon’’tt--Care ConditionsCare Conditions
nn DonDon’’tt--Care Terms (x): Care Terms (x): A don’t-care term is a combination of variables whose logical value is not
specified. Eg. BCD has 6 don’t-care terms.Decimal BCD0 00001 00012 00103 00114 01005 01016 01107 01118 10009 100110 x11 x12 x13 x14 x15 x
P-35/702005/5/113.5 3.5 DonDon’’t Care Conditionst Care Conditions
nn DonDon’’tt--Care Terms (x): Care Terms (x): A don’t-care term can be assigned 1 or 0 for simplification functions.
F(w,x,y,z) = Σ(1,3,7,11,15)= yz + w’x’ = yz + w’zDon’t-care terms: d = Σ(0,2,5)
x 1
0 x
yzwx 00
00
w
y
1 x
1 0
01 11 10
01
z
0 0
0 0
1 0
1 0
11
10
x
x 1
0 x
yzwx 00
00
w
y
1 x
1 0
01 11 10
01
z
0 0
0 0
1 0
1 0
11
10
x
P-36/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
3.1 The Map Method3.2 Four-Variable Map3.3 Five-Variable Map3.4 Product of Sums Simplification3.5 Don’t-Care Conditions3.6 NAND and NOR Implementation3.7 Other Two-Level Implementations3.8 Exclusive-OR Function3.9 Hardware Description Language (HDL)
P-37/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn NAND and NOR GatesNAND and NOR Gates
1. NAND and NOR gates are easier to fabricate with electronic components.
2. NAND and NOR gates are the basic gates in all IC digital family.
3. The Function implemented in NAND and NOR gates is important.
P-38/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn NAND GatesNAND Gates1. NAND gate is a universal gate2. Any digital system can be implemented with NAND
gates3. Logical Operation using NAND Gates
Inverter
AND
OR
x
xy
x
y
x
xy
(x y ) = x+y
P-39/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn Two Implementations for NAND GatesTwo Implementations for NAND Gates
DeMorgans’ Theorem: (xyz)’ = x’+y’+z’
xyz
(xyz)
xyz
x+y+z
P-40/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn TwoTwo--Level ImplementationLevel Implementation
F= AB + CD = [(AB)’(CD)’]’
AB
CD
F
AB
CD
F
AB
CD
F
P-41/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn Example: TwoExample: Two--Level Implementation with Level Implementation with NAND GatesNAND Gates
F(x,y,z) = Σ(1,2,3,4,5,7)= xy’ + x’y + z
1
1 1
yzx 00
0
x=1
y=1
1 1
1
01 11 10
1
z=1
P-42/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn Example: TwoExample: Two--Level Implementation with Level Implementation with NAND GatesNAND Gates
F(x,y,z) = xy’ + x’y + z
xyxy
z
F
xyxy
z
F
P-43/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn The Procedure for Implementation The Procedure for Implementation Function with 2Function with 2--level NAND Gateslevel NAND Gates
1. Simplify the function and express it in sum of products.2. Draw a NAND gate for each product term of the
expression that has least two literals.The inputs to each NAND gate are the literals of the term. This constitutes a group of first-level gates.
3. Draw a single gate using the AND-invert or invert-OR graphic symbol in the second level, with inputs coming from outputs of first level gates.
4. A term with a single literal requires an inverter in the first level. However, if the single literal is complemented, it can be connected directly to an input of the second level NAND gates.
P-44/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn Multilevel NAND CircuitsMultilevel NAND Circuits
F(A,B,C,D) = A(CD+B) + BC’CDBABC
F
CDBABC
F
P-45/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn Multilevel NAND CircuitsMultilevel NAND CircuitsF(A,B,C,D) = (AB’+ A’B)( C+D’ )
ABABCD
F
ABABCD
F
P-46/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn The Procedure for Converting a Function into The Procedure for Converting a Function into an Allan All--NAND Gate RepresentationNAND Gate Representation
1. Convert all AND gates to NAND gates with AND-invert graphic symbols.
2. Convert all OR gates to NAND gates with invert-OR graphic symbols.
3. Check all the bubbles in the diagram. For every bubble that is not compensated by another small circle along the same line, insert an invert (one-input NAND gate) or complement the input literal.
P-47/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn NOR ImplementationNOR Implementation
1. NOR gate is a universal gate2. Any digital system can be implemented with NOR
gates
Inverter
OR
AND
x
xy
x
y
x
x+y
(x +y ) = xy
P-48/702005/5/11
nn Two Implementations for NOR GatesTwo Implementations for NOR Gates
DeMorgans’ Theorem: (x+y+z)’ = x’y’z’
3.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
xyz
(x+y+z)
xyz
xyz=(x+y+z)
P-49/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn Example: TwoExample: Two--Level Implementation with NOR GatesLevel Implementation with NOR Gates
F = (A+B)(C+D)E
ABCD
E
F
ABCD
E
F
P-50/702005/5/113.6 3.6 NAND and NOR ImplementationNAND and NOR Implementation
nn Multilevel NOR CircuitsMultilevel NOR CircuitsF(A,B,C,D) = (AB’+ A’B)( C+D’ )
ABABCD
F
ABABCD
F
P-51/702005/5/113.7 3.7 Other TwoOther Two--Level ImplementationsLevel Implementations
3.1 The Map Method3.2 Four-Variable Map3.3 Five-Variable Map3.4 Product of Sums Simplification3.5 Don’t-Care Conditions3.6 NAND and NOR Implementation3.7 Other Two-Level Implementations3.8 Exclusive-OR Function3.9 Hardware Description Language (HDL)
P-52/702005/5/113.7 3.7 Other TwoOther Two--Level ImplementationsLevel Implementations
nn Wired LogicWired Logic
F = (AB)’(CD)’ = (AB+CD)’ Wired-AND= (A+B)’+ (C+D)’ = [(A+B)(C+D)]’ Wired-OR
AB
CD
F=(AB+CD) : Wired-AND
AB
CD
F=[(A+B)(C+D)] : Wired-OR
P-53/702005/5/113.7 3.7 Other TwoOther Two--Level ImplementationsLevel Implementations
nn NonNon--degenerate Formsdegenerate Forms
Two-level Function Implementation with1. AND 2. OR 3. NAND 4. NORTherefore, 16 possible combinations.
The 8 non-degenerate combinations are1. AND-OR (3.4) 5. OR-AND (3.4)2. NAND-NAND (3.6) 6. NOR-NOR (3.6)3. NOR-OR 7. NAND-AND4. OR-NAND 8. AND-NOR
P-54/702005/5/113.7 3.7 Other TwoOther Two--Level ImplementationsLevel Implementations
nn ANDAND--OROR--INVERT ImplementationINVERT Implementation
ABCD
E
F
AND-NOR(AND-OR-INVERT)
ABCD
E
F
AND-NOR
ABCD
E
F
NAND-AND
F = (AB+CD+E)’
P-55/702005/5/113.7 3.7 Other TwoOther Two--Level ImplementationsLevel Implementations
nn OROR--ANDAND--INVERT ImplementationINVERT Implementation
F = [(A+B)(C+D)E]’
ABCD
E
F
OR-NAND(OR-AND-INVERT)
ABCD
E
F
OR-NAND
ABCD
E
F
NOR-OR
P-56/702005/5/113.7 3.7 Other TwoOther Two--Level ImplementationsLevel Implementations
nn Implementation with Other TwoImplementation with Other Two--Level FormsLevel Forms
Equivalent Implements Simplify To GetNon-degenerate the F and OutputForm Function in of
(a) (b)
AND-NOR NAND-AND AND-OR-INVERT F
OR-NAND NOR-OR OR-AND-INVERT F
Sum of productsby combining 0's
in the K-map
Product of sum bycombining 1's in the
K-map and thencomplementing
Table 3-3
P-57/702005/5/113.7 3.7 Other TwoOther Two--Level ImplementationsLevel Implementations
nn ExampleExampleImplementation F with the 4 two-level forms in Table 3-3
1 0
0 0
yzx 00
0
x=1
y=1
0 0
0 1
01 11 10
1
z=1
F = x y z + xyzF = x y + xy + z
xyxy
z
F
AND-NOR
xyxy
z
F
NAND-AND
F= (x’y+xy’+z)’
P-58/702005/5/113.7 3.7 Other TwoOther Two--Level ImplementationsLevel Implementations
nn ExampleExampleImplementation F with the 4 two-level forms in Table 3-3
1 0
0 0
yzx 00
0
x=1
y=1
0 0
0 1
01 11 10
1
z=1
F = x y z + xyzF = x y + xy + z
xyz
F
OR-NAND NOR-OR
xyz
xyz
Fxyz
F= [(x+y+z)(x’+y’+z)]’
P-59/702005/5/113.8 3.8 ExclusiveExclusive--OR FunctionOR Function
3.1 The Map Method3.2 Four-Variable Map3.3 Five-Variable Map3.4 Product of Sums Simplification3.5 Don’t-Care Conditions3.6 NAND and NOR Implementation3.7 Other Two-Level Implementations3.8 Exclusive-OR Function3.9 Hardware Description Language (HDL)
P-60/702005/5/113.8 3.8 ExclusiveExclusive--OR FunctionOR Function
nn ExclusiveExclusive--OR (XOR)OR (XOR)
x y+
(x y)+
xy + x y
xy + x y
Exclusive-OR
Exclusive-NOR
x y+Commutative
Associative
y x+=
(x y) z = x (y z) = x y z+ + + + + +
P-61/702005/5/113.8 3.8 ExclusiveExclusive--OR FunctionOR Function
nn ExclusiveExclusive--OR ImplementationsOR Implementations
x
y
x y+
x
y
x y+ : AND-OR-NOT
: NAND Gates
P-62/702005/5/113.8 3.8 ExclusiveExclusive--OR FunctionOR Function
nn Primitive ExclusivePrimitive Exclusive--OR OperationsOR Operations
1. x 0 = x2. x 1 = x3. x x = 04. x x = 15. x y = x y = (x y)
+++++ + +
P-63/702005/5/113.8 3.8 ExclusiveExclusive--OR FunctionOR Function
nn Odd FunctionOdd Function
Function with odd number of input variables is equal to 1
A B C = (AB + A B)C + (AB + A B )C = AB C + A BC + ABC + A B C = Σ (1,2,4,7)
+ +
1
1
yzx 00
0
x=1
y=1
1
1
01 11 10
1
z=1
1
1
yzx 00
0
x=1
y=1
1
1
01 11 10
1
z=1
Odd Function : F = A B C Even Function : F = (A B C)+ + + +
P-64/702005/5/113.8 3.8 ExclusiveExclusive--OR FunctionOR Function
nn Logic ImplementationLogic Implementation
AB
C3 Input Odd
FunctionF:
AB
C3 Input Even
FunctionF:
P-65/702005/5/113.8 3.8 ExclusiveExclusive--OR FunctionOR Function
nn FourFour--Variable ExclusiveVariable Exclusive--OR FunctionOR FunctionA B C D = Σ (1,2,4,7,8,11,13,14)+ + +
1
1
yzwx 00
00
w=1
y=1
1
1
01 11 10
01
z=1
1
1
1
1
11
10
x=1
1
1
yzwx 00
00
w=1
y=1
1
1
01 11 10
01
z=1
1
1
1
1
11
10
x=1
Even FunctionOdd Function
P-66/702005/5/113.8 3.8 ExclusiveExclusive--OR FunctionOR Function
nn Parity Generation and CheckingParity Generation and Checking
1. XOR is used in error-detection and error-correction.2. Parity bits are extra bits with the data to make its
number of 1’s either odd or even.3. The odd/even parity data is transmitted for error
detection.4. The circuit that generates the parity bit in the
transmitter is called a parity generator.5. The circuit that checks the parity in the receiver is
called a parity checker.
P-67/702005/5/113.8 3.8 ExclusiveExclusive--OR FunctionOR Function
nn Parity Data Transmission SystemParity Data Transmission System
Source Data
Parity Generator
n bits
n+1 bitsEven/Odd Data
Data Transmission
Parity Checker
Source Data
n+1 bitsEven/Odd Data
n bits
Parity bits:1 bit
P-68/702005/5/113.8 3.8 ExclusiveExclusive--OR FunctionOR Function
nn EvenEven--ParityParity--Generator Truth TableGenerator Truth Table
Three-Bit Data Parity Bit
x y z P
0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 11 0 1 01 1 0 01 1 1 1
P-69/702005/5/113.8 3.8 ExclusiveExclusive--OR FunctionOR Function
nn Logic Implementation of Parity Generator and CheckerLogic Implementation of Parity Generator and Checker
P = x y zC = x y z P
+ +
xy
z
P
xy
zP
C
Data Transmission+ + +
P-70/702005/5/113.9 3.9 Hardware Description Language (HDL)Hardware Description Language (HDL)
3.1 The Map Method3.2 Four-Variable Map3.3 Five-Variable Map3.4 Product of Sums Simplification3.5 Don’t-Care Conditions3.6 NAND and NOR Implementation3.7 Other Two-Level Implementations3.8 Exclusive-OR Function3.9 Hardware Description Language (HDL)