template - european commission : cordis :...

7th RTD Framework Program

REALITYReliable and Variability tolerant System-on-a-chip Design in More-Moore

Technologies

Contract No 216537

Deliverable D7.9

Final project report

Editor: Miguel MirandaCo-author / Acknowledgement: The REALITY ConsortiumStatus - Version: V1.0Date: 28/10/2010Confidentiality Level: PublicID number: IST-216537-WP7-D7.9

© Copyright by the REALITY Consortium

The REALITY Consortium consists of:

Interuniversity Microelectronics Centre (IMEC vzw) Prime Contractor BelgiumSTMicroelectronics S.R.L. (STM) Contractor ItalyUniversita Di Bologna (UNIBO) Contractor ItalyKatholieke Universiteit Leuven (KUL) Contractor BelgiumARM Limited (ARM) Contractor United KingdomUniversity Of Glasgow (UoG) Contractor United Kingdom

Deliverable D7.4 of 20

1. DisclaimerThe information in this document is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose. The user thereof uses the information at its sole risk and liability.

2. Acknowledgements

The REALITY consortium acknowledges the contributions from the former project coordinators: Peter Lemmens and Tom Tassignon, who were members of the former Project Office Support group of the Nomadic Embedded Systems (NES) division of imec (today discontinued). Such group had no technical focus and it t was fully devoted to support the different NES’s R&D units in the administrative, legal and non-technical reporting tasks of the projects under their management.

Today, both coordinators remain affiliated to imec,. Peter Lemmens was the first REALITY project coordinator for about one year, between January 2008 and September 2008. Peter is still active at the imec office in Taiwan. Tom was with REALITY for about half year, between October 2008 and April 2009 and he is at the time of writing this report on sabbatical leave.

On May 2009, the project coordination activities were transferred to Miguel Miranda who has been the technical leader of the project throughout the whole duration. Miguel was the last project coordinator of REALITY for about 15 months, until its finalization date.

3. Document revision history

Date Version Editor/Contributor Comments28/10/2010 V1.0 Miguel Miranda First & final draft

IST-216537-WP7-D7.7-v1.0.doc© REALITY Consortium


4. PrefaceThe scope and objectives of the REALITY project are :

Development of design techniques, methodologies and methods for real-time guaranteed, energy-efficient, robust and adaptive SoCs, including both digital and analogue macro-blocks“

The Technical Challenges are : To deal with increased static variability and static fault rates of devices and interconnects. To overcome increased time-dependent dynamic variability and dynamic fault rates. To build reliable systems out of unreliable technology while maintaining design productivity. To deploy design techniques that allow technology scalable energy efficient SoC systems

while guaranteeing real-time performance constraints.

Focus Areas of this project are : “Analysis techniques” for exploring the design space, and analysis of the system in terms of

performance, power and reliability of manufactured instances across a wide spectrum of operating conditions.

“Solution techniques” which are design time and/or runtime techniques to mitigate impact of reliability issues of integrated circuits, at component, circuit, architecture and system (application software) design.

The REALITY project has started its activities in January 2008 and is planned to be completed after 30 months. It is led by Dr. Miguel Miranda of IMEC. The Project Coordinator is Dr. Miguel Miranda from IMEC. Five contractors (STM, ARM, KUL, UoG, UNIBO) participate in the project. The total budget is 2.899 k€.



5. AbstractThis report is deliverable D7.9: “Final report”. It provides an executive summary of the project after its 2.5 years lifespan. It summarizes the awareness created by the project outcome and its implications in society. In addition, and to attend the requests expressed by the expert reviewers during the final review meeting, the project also summarizes the main valorisation actions among the different the consortium partners.



6. Table of contents

1. DISCLAIMER................................................................................................................................................2

2. ACKNOWLEDGEMENTS...........................................................................................................................2

3. DOCUMENT REVISION HISTORY..........................................................................................................2

4. PREFACE.......................................................................................................................................................3

5. ABSTRACT....................................................................................................................................................4

6. TABLE OF CONTENTS...............................................................................................................................5

7. EXECUTIVE SUMMARY............................................................................................................................6

8. SUMMARY DESCRIPTION OF THE PROJECT CONTEXT AND OBJECTIVES...........................7

9. DESCRIPTION OF THE MAIN SCIENTIFIC & TECHNICAL RESULTS ACHIEVED..................7

10. POTENTIAL IMPACT.............................................................................................................................9

11. MAIN DISSEMINATION ACTIVITIES AND EXPLOITATION OF RESULTS..........................11

12. PLAN FOR USE AND DISSEMINATION OF FOREGROUND......................................................11

12.1. USE BY INDUSTRIAL PARTNERS IN PROPRIETARY PRODUCTS..........................................11

12.1.1. STMICROELECTRONICS...............................................................................................................11

HYBRID DESIGN FLOW FOR STATISTICAL STATIC TIMING ANALYSIS.................................................................12REALITY: NOT ONLY TECHNICAL ACHIEVEMENTS............................................................................................12

12.1.2. ARM LTD............................................................................................................................................13

VARIABILITY CHARACTERIZATION:....................................................................................................................14IMPORTANCE OF VARIABILITY AWARE DESIGN...................................................................................................15BEYOND THE TECHNICAL DISCUSSIONS...............................................................................................................15

12.1.3. GOLD STANDARD SIMULATIONS LTD.....................................................................................15

13. PROJECT MANAGEMENT..................................................................................................................16

13.1. IMPACT OF DEVIATIONS MATERIALIZED FROM THE PLANNED MILESTONES AND DELIVERABLES ALONG THE PROJECT EXECUTION....................................................................................................................................1613.2. DEVELOPMENT OF THE PROJECT WEBSITE :...........................................................................................1613.3. USE OF FOREGROUND AND DISSEMINATION ACTIVITIES ALONG THE PROJECT:.....................................16

14. Wider Societal Implications.......................................................................................................................16



7. Executive Summary

REALITY has focused on developing industrially relevant innovative design techniques, methods, and flows for the design and analysis of energy-efficient self-adaptive SoCs. The tackled challenges have included benchmarking the impact of the latest 32nm CMOS process manufacturing variability at all abstraction levels, from device to System on a Chip level, while developing approaches to compensate their negative impact in the design of final products. REALITY has resulted in a number of first time conclusions.

For a first time, a full statistical characterization of an ARM926 core has been achieved. ARM cores are the flag-ship of the European embedded computing industry. These are very popular microprocessors found are at the heart of billions of battery operated devices worldwide. There is no doubt that understanding the impact process variations at advanced process technologies in such popular devices will provide key competitive advantage to European design industry. This is indeed the case, especially now that most European semiconductor manufacturing capabilities are being outsourced to companies outside the European Union.

To achieve this, much R&D effort had to be put in place along these two and half years of project to understand its impact from device to system. For the first time, full scale 3D simulation of statistical variability associated with metal gate granularity and the corresponding metal work function variations has been carried out to clarify the magnitude of statistical variability in 32 nm CMOS transistors with high-k/metal gate stack. It has been observed that for these devices the metal granularities can double the variability if the metal grain size becomes comparable to the transistor dimensions. In addition, technology has been developed to simulate the statistical aspects of variability degradation associated with reliability and ageing effects such as Negative and/or Positive Bias Temperature Instability.

Using such popular ARM core, REALITY has provided deep understanding on the way timing, leakage and dynamic power and especially their statistical response under process variability correlate at the product level, both for local (within die) and non-local (above die) variations. The traditional corner analysis has been be benchmarked with innovative statistical analysis techniques. To achieve a high accuracy of the statistical models, complex mathematical methods and algorithms have been carried out within the project.

Using the ARM core as driver, REALITY has confirmed that the SRAM components are responsible for more than the half of the variations on critical path timing. Hence, concluding that Statistical Timing Analysis (SSTA) flows, widely promoted by the Electronic Design Automation Industry, that assume predictable timing response from these components may lead to over-optimistic conclusions. Much focus has been placed by both state-of-the-art and EDA vendors on the logic while the variability challenges remain in the memories themselves. That said, these techniques are simply not sufficient to predict silicon response at design time. For that purpose REALITY has been also first in deploying a holistic statistical characterization flow including memory analysis.

In the context of reliability, life-time prediction for aged circuits must consider process manufacturing variations at and their evolution over time. With a novel flow integrating manufacturing variations and ageing effects for mixed- signal circuits, the REALITY project has been also first developing a CAD environment that allows designers to make more accurate estimations and thus make circuits more energy and cost efficient.

Finally, REALITY has also for first time evaluated the impact of process variation in SW level metrics showing process variability is not only a concern for HW but for SW as well. It has concluded that variability affecting multi-core multimedia platforms makes it hard to guarantee a certain QoS from the running application’s functionality. The speed variations across the cores cause sub-optimal and platform-dependent parallelism. REALITY has developed an approach to compensate this by using a smart allocation of the workload at run-time, hence also at the SW level, and obtaining an improvement of QoS by 20% and energy consumption by 15% while obtaining better platform predictability.



For that purpose, different circuit design techniques for system adaptation have been investigated, among them Adaptive Body Biasing (ABB). REALITY has shown that even though the possible compensation range in speed up due to ABB is significantly reduced compared to the previous node, it remains still available at 32nm. The technique has been validated on the ALU design of the ARM core using specially characterized commercially available libraries.

In summary, REALITY has been a first-of-its kind project that has linked process technology and system design. Efforts invested in REALITY will pay-off in the many years to come as it has been the first public funded R&D effort that has successfully bridged the traditional gap between electronic design and manufacturing, key for future nanoelectronics. REALITY has been able to identify the technical ingredients of the model needed for a scalable eco-system between semiconductor foundries, fab-less/fab-lite design industry and electronic design automation companies.

8. Summary description of the project context and objectives8.1.1. Concept and project objective(s)

Why is this project needed?It is becoming common knowledge that the progress and scaling of CMOS technology is hitting several brick walls. The most obvious is the fact that due to scaling the dimensions of silicon devices are approaching the atomic scale and are hence subject to atomic uncertainties. According to the ITRS roadmap, this is becomes of concern at 45nm, and will become critical at the 22nm technology node and below. It is also well-know that other ‘brick walls’ are likely to impair technology scaling even before this. Lithography resolution, photo resist and electrical field limits (due to power supply voltage fluctuations, thin oxide breakdowns, etc.) are already critical issues for 65nm and 45nm technologies. However, to achieve the predictions of Moore’s Law, whilst increased transistor density is of course important, the next key challenge is to optimally integrate foundations such as process technology into the architecture/micro-architecture and system tool flows. Such integration will drastically reduce development cycle and NRE costs, allowing tighter time-to-market windows, and achieve high yield to compensate for the soaring economic investments necessary to develop the next generation nanometre technology nodes and build their manufacturing facilities. Such a trend will dictate a deep rethinking of system architectures and design methodologies.

This project addresses all the issues above: soon it will not be possible to design systems using current methodologies and techniques and soon, if not already today, we will be confronted with the design reality to realize reliable systems with unequal, variable, and unreliable components.

Technology scaling has traditionally offered advantages to embedded systems in terms of reduced energy consumption and die cost as well as increased performance, without requiring significant additional design effort. Scaling to and past the 32 nm technology node brings a number of problems ‘(“technology gaps’) whose impact on system level design has not yet been evaluated. Random intra-die process variability, reliability degradation mechanisms and their combined impact on the system level parametric quality metrics are prominent issues that will need to be tackled in the next few years.

Figure 1 (a) 3D simulation of 35 nm MOSFET in presence of random dopants and LER.

(b) ST measurements of the potential distribution in a similar device (Fujitsu).



Statistical variability introduced predominantly by discreteness of charge and granularity of matter has become a major limitation to MOSFET scaling and integration [1,2,3]. It already adversely affects the yield and reliability of SRAM [4], causes timing uncertainty in logic circuits [5] and by slowing down the scaling of the supply voltage exacerbates the on-chip power dissipation problems [6]. Figure 1 illustrated the variability 35 introduced by random discrete dopants and line edge roughness in a 35 nm gate length MOSFET.

Progressive scaling of CMOS transistors, as tracked by the International Technology Roadmap for Semiconductors (ITRS) [7] and captured in Moore’s law, has driven the success of the semiconductor industry, delivering larger, faster, cheaper circuits. Silicon technology has now entered the nano-CMOS era with 40 nm MOSFET’s in mass production at the current 90 nm ITRS technology node [8] and sub-10 nm transistors expected at the 22 nm technology node, scheduled for production in 2018. 4 nm transistors have already been demonstrated experimentally [9], highlighting silicon’s potential for scaling beyond the end of the current ITRS.

Figure 2 Technology-design interdependence Challenges facing the semi-conductor industry (G. Declerk [10])

1 G. Declerck, “A Look Into the Future of Nanoelectronics” Proc. Symp. on VLSI Technol., pp. 6-7, 2005.2 K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer,

“High-performance CMOS variability in the 65-nm regime and beyond”, IBM J. Research and Development, Vol. 50, pp.433-449, 2006

3 A. Asenov, A. R. Brown, J. H. Davies, S. Kaya and G. Slavcheva, “Simulation of intrinsic parameter fluctuations in decananometre and nanometer-scale MOSFETs”, IEEE Trans. on Electron Devices, Vol.50, No.9, pp.1837-1852, 2003

4 B.-J. Cheng, S. Roy and A. Asenov, “The impact of random doping effects on CMOS SRAM cell”, Proc. 30th European Solid-State Circuits Conference (ESSCIRC), Leuven, Belgium, pp.219-222, 2004

5 A. Agarwal, K. Chopra, V. Zolotov and D. Blaauw, “Circuit Optimization using Statistical Static Timing Analysis”, Proc. 42nd Design Automation Conference, Anaheim, CA, USA, pp.321-324, 2005

6 T. Scotnicki, “Nano-CMOS & Emerging Technologies–Myths and Hopes”, International Conference on Solid State Devices and Material (SSDM), Yokohama, Japan, pp.2-5, 2006

7 International Technology Roadmap for Semiconductors, Sematech, http://public.itrs.net8 R. Khumakear at al., “An enhanced 90nm High Performance technology with Strong Performance Improvement from Stress

and Mobility Increase through Simple Process Changes” 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp 162-163, 2004

9 Wakabayashi, “Sub 10-nm Planar-Bulk-CMOS Device using Lateral Junction Control”, IEDM Tech. Digest, pp. 989-991, 200310 G. Declerck, “A Look into the Future of Nanoelectronics”, 2005 Symposium on VLSI Technology Digest of Tech. Papers, pp.6-

10, 2005, Keynote talkIST-216537-WP7-D7.7-v1.0.doc

© REALITY Consortium


However, it is widely recognized that variability in device characteristics and the need to introduce novel device architectures represent huge challenges to scaling and integration for present and next generation nano-CMOS transistors and circuits (Figure 2). This will in turn demand revolutionary changes in the way in which future integrated circuits and systems are designed. Strong links must be established between circuit design, system design and fundamental device technology to allow circuits and systems to accommodate the individual behaviour of every transistor on a chip. Design paradigms must change to accommodate this increasing variability. Adjusting for new device architectures and device variability will add significant complexity to the design process, requiring orchestration of a broad spectrum of design tools by geographically distributed teams of device experts, circuit and system designersThese fluctuations stem from the fundamental discreteness of charge and matter and the statistics of small numbers such as random discrete dopants (Figure 3 and Figure 4), line edge roughness and oxide thickness fluctuations [11]. While intrinsic parameter fluctuations and resultant device mismatch have hitherto affected only analogue design, they now challenge the power consumption, yield and reliability of digital circuits [12]. One of the first digital ‘’casualties” is SRAM, which occupies significant real estate in current System On Chip (SoC) devices [13]. Figure 5 illustrates the random dopants induced distribution of static noise margin in an ensemble of SRAM cells of various cell ratios at the transition between the 90 nm and 65 nm technology nodes.

Figure 3 Random discrete dopants in a 35 nm MOSFET from the present 90 nm technology node.

Figure 4 Corresponding variations in the current-voltage characteristics of 200 transistors wit h different dopant distributions

0.08 0.12 0.16 0.200

10

20

Freq

uenc

ySNM (volt)

cell ratio=2 cell ratio=3 cell ratio=4

Figure 5 Corresponding distribution of the static noise margins in 6T SRAM cells

It is expected that there will be no single replacement for conventional MOSFET’s and that disparate device architectures will coexist and compete. This adds to the design challenges associated with increasing device and circuit variability.

What do we wanted to achieve with this project?The objective of this project is to develop design techniques and methodologies for real-time guaranteed, energy-efficient, robust and adaptive SoCs, including both digital and analog macro-blocks. The technological challenges to be tackled are:

(a) how to cope with increased static variability and static fault rates of devices and interconnects; (b) How to cope with increased time-dependent dynamic variability and dynamic fault rates. (c) build reliable systems out of unreliable technology while maintaining design productivity; (d) Deploy design techniques that allow technology scalable energy efficient SoC systems while

guaranteeing real-time performance constraints. In order to tackle these challenges we focus the R&D effort along two main axes:

Analysis techniques for exploring the design space, and analyzing of the system in terms of performance, power and reliability of manufactured instances across a wide spectrum of operating conditions (thermal, noise, age).

Solution techniques (design time and/or runtime techniques) to mitigate impact of reliability issues (seen as time-dependent variability aspects) of integrated circuits, at component, circuit, and architecture and system (application, software) design.

11 A. Asenov, A. R. Brown, J. H. Davies, S. Kaya and G. Slavcheva, “Simulation of Intrinsic Parameter Fluctuations in Decananometre and Nanometre scale MOSFETs”, IEEE Trans. on Electron Devices, Vol.50, No.9, pp.1837-1852, 2003, Invited

12 P.A. Stolk, H.P. Tuinhout, R. Duffy, et al., “CMOS Device Optimisation for Mixed-Signal Technologies”, IEDM Tech Digest, pp.215-218, 2001

13 B. Cheng, S. Roy, G. Roy, F. Adamu-Lema and A. Asenov, “Impact of Intrinsic Parameter Fluctuations in Decanano MOSFETs on Yield and Functionality of SRAM Cells”, Solid-State Electronics, Vol. 49, pp.740-746, 2005



Classical versus variability aware simulationThe technique most often employed to face variability and reliability is to introduce a heuristic slack-based approach to the classic ‘corner’ analysis (also termed guard banding, or worst-case design). More advanced statistical analysis methods might be used instead. Statistical Static Timing Analysis (SSTA) techniques have recently been introduced in industry for the identification of the timing critical paths in standard cell-based circuits and SoCs under process and environmental variations, and for an early estimation of the impact of variability on parametric timing yield during the sign-off verification phase. Major EDA vendors provide commercial tools supporting this trend. SSTA may properly identify and allow the optimization of cell sensitivities with respect to variations, allowing inherently statistical optimization methods instead of worst-case analysis. In this way, it will be possible to increase the design performance without introducing excessive pessimistic margins, thus taking full advantages of technology scaling. 15% performance [14] and 20-30% power reduction [15] at target timing yields are reported in the literature.

Are design solutions doomed to make design flows top-heavy?It is of significant industry concern that design solutions which cope with variability and reliability may heavily impact the design flow and design paradigms. State-of-the-art techniques addressing design uncertainty assume a thorough technology understanding from both the circuit and architecture designer. Redundancy, design for manufacturing, error corrections, timing and power closure, design centering and other optimizations make the old design paradigm based on perfectly reproducible and predictable standard cells totally inadequate. Therefore, designing using advanced nanometre technologies is becoming increasingly expensive, if not impossible, as system complexity further increases. An important objective of this project is therefore to bring the design flow, as seen by the systems designer, back to the era of ‘happy scaling’, where variability was negligible (except in analogue design) and people assumed that chips lived forever unless one was careless enough to hit them with an ESD.

Runtime countermeasures“Better-than-worst-case” circuit design techniques have started emerging. These approaches extend the functionality of components to embed the management of static and dynamic variability, ensuring the correctness of functional behaviour at the price of limited overhead and controlled performance degradation. We propose bottom-up, holistic generalization of this concept, where self-monitoring and run-time adaptation are built-in at multiple levels of the design abstraction hierarchy, and cross-layer cooperation enables an unprecedented level of resiliency of the system to the degradation of the hardware, ensuring local and global optimal better-then-worst case design.

Support to monitoring and adaptation will be provided at the circuit, architectural and OS/middleware level. At the architectural level the component may be a processor, an hardware accelerator, a memory, a cache, the switch of a Network-on-Chip interconnect, etcAt the system level the component may be a kernel stack, a local monitor, a middleware.To enable such approach, a component at each level must include additional functionality to:

monitor its own error rate and/or degradation level indicators and communicate this information to decision layer

provide to the layer control knobs to tune its behaviour with error management actions Implement local or global error management techniques/policies, exploiting error and

degradation indicators information and control knobs of the underlying level. Policies will exploit detailed analysis of error, error sources behaviour across a wide spectrum of operating conditions to implement component self diagnosis and repair.

14 A. Agarwal, K. Chopra, D. Blaauw and V. Zolotov, “Circuit optimization using statistical static timing analysis”, DAC 2005, pp. 321-324

15 M. Mani, A. Devgan and M. Orshansky, “An efficient algorithm for statistical minimization of total power under timing yield constraints”, DAC 2005, pp. 309-314



Degradation level indicators may be temperature, current, noise levels etc. while control knobs may exploit e.g. energy versus speed control knobs, state-loss vs. state preserving shutdown, supply voltage scaling, body bias control, etc.

For instance, at the circuit level, completion detection logic coupled with delayed-clock sampling can ensure increased robustness to speed variations of logic gates [25]. However, significant improvements can be obtained if functional units are augmented with counters of number of delayed completion events that are made available at the architectural level. In fact, an architecture variability manager can monitor the rate of delayed completions of various units and activate a spare to replace a single unit with a very high delayed completion rate. At the same time, the architectural controller may compute a compound delay completion rate and make it available to a software controller, which may communicate to the system clock generator and reduce the frequency in case a max rate threshold is reached. This simple example shows how a cooperative cross-layer variability management strategy can increase system robustness much beyond what is achievable by a single-layer strategy.

9. Description of the main scientific & technical results achieved

Annex 1 of the project, Section B1.2 (Progress beyond the state of the art) lists for each work package, the key performance R&D indicators to be achieved for every project period. These targets are listed in Table 1 below marking with a those that were fully achieved and highlighting with underline font those that were still achieved but required additional attention from the consortium and/or required minor deviations from the original target.

A global view to the Table already indicates that about 90% of the targets were fully achieved within the expected time frame. Only two exceptions are found:

Models fine tuned. Feedback from device measurements incorporated. There has been two CMOS technologies exercised in the project: Low Power (LP) ST 45nm and High-K Metal Gate (HKMG) IBM 32nm:

o ST 45nm LP: feedback from device measurements was incorporated for ST 45nm. Device models resulting from WP1 were calibrated with such measurements that were provided by ST. Deliverable D1.1 demonstrates the good agreement achieved between the generated models and the gathered silicon data measurement.

o IBM 32nm HKMG: 32nm is a very competitive technology. Today, at the completion of the project, first 32nm products start being produced. Early availability of silicon data is a key differentiating know-how between companies. Moreover, many of them that had the possibility to manufacture their own silicon decided to become fab-light or even fab-less within the first year of the project (between 2008 and 2009). That means that these companies have decided to drastically reduce their own silicon manufacturing capabilities or even completely abandoned them, which was the case of ST. That consequently made it harder for ST and the consortium to get access to early silicon data at 32nm, hence not being able to calibrate the models developed in WP1 with device measurements. Still those models were calibrated (Deliverable D1.2) and benchmarked against foundry calibrated data models which are certified to be accurate.

Feedback from benchmarking acknowledged: o The goal for WP2 at the end of the project was to provide methods and techniques

supporting the analysis of the impact process manufacturing variations through each abstraction level in the electronic design flow. WP2 has met all these objectives. However one important feature of the developed techniques is that they should be easily absorbable by the design flows already existing at our industrial partner’s side. Otherwise, the valorisation opportunities for the outcome of the WP would have got severely weakened.



o One of the investigated techniques relates to the deployment of Statistical Static Analysis (SSTA) techniques heavily advocated by top R&D Labs and Universities (e.g., IBM’s T.J. Watson Research Lab, Texas A&M Univ., Michigan State Univ. and others). However, after thorough evaluation of these techniques at the end of the 2nd

reporting period, ST together with the rest of the consortium came to the conclusion that these techniques cannot directly integrate in an industrial design flow. Although, they provide key missing features for the design and manufacturing of process variation aware digital blocks. Indeed they feature unacceptable turn-around-time for chip designers in an industrial environment, who have to satisfy strict time-to-market windows dictated by an increasingly fierce competition, do not want to change the traditional sign-off methodology for timing verification based on classic Static Timing Analysis (STA).

o The infrastructure required to support such SSTA techniques, namely statistical characterization of standard cell libraries, and especially its existing commercial offerings suffered of two issues (Deliverable D2.3):

Lack of accuracy. There are several existing commercial offerings available in the market (i.e. Cadence’s ELC, Synopsys’s NCX, Magma’s Silicon Smart). These are based on sensitivity analysis techniques. All of them have been benchmarked within the project against a Monte Carlo like based reference flow (Deliverable D5.2) leading to the conclusion that they are not capable to match the accuracy level offered by Monte Carlo.

Lack of CPU time efficiency. In the lack of commercially available offerings providing sufficient accuracy, Monte Carlo based techniques remain the only available alternative for statistical library characterization (Deliverable D5.2). However these techniques are heavy in simulation load leading to unacceptable CPU characterization time for realistic standard cell library sizes.

o Based on the inefficiencies of SSTA, at the end of period 2 a decision was made to abandon the deployment of these techniques and to develop new ones based on a hybrid of classical corner analysis and SSTA. The developed hybrid approach is based on a classical corner analysis technique that is now applied as first phase to identify few potentially critical paths of the digital block under variability and only for these gate along such paths, then to apply a full blown Monte Carlo based statistical characterization approach followed by an SSTA.

o However given the late identification of the problem and late implantation of the correction action, the outcome came too late in the project so as to be absorbed by the integration (WP5) and assessment (WP6) work packages. Instead, a local benchmarking of the alternative took place within WP2.

Table 1 Description of the performance / research indicators (almost all project targets have been met



WP After year 1 After year 2 At end of projectWP1 Device variability

Physical modelling and understanding of the variability at 45/32 nm technology nodes (TN). First statistical compact models.

Compact models that accurately capture the variability and the reliability issues at 32 nm.

Models fine tuned. Feedback from device measurements incorporated (only for 45 nm due to the lack of availability of silicon data at 32nm)

WP2Circuit to System Variability

Preliminary version of a RDR std. cell library [32nm].

Flow definition and framework set up for variability characterization.

Correlated variability energy timing flow definition and set up.

Variability characterization of a [32nm] RDR std cell library.

Exploitation of the variability aware modelling flow on the driver application vehicle, including a solution for IP blocks and memories.

Methodology fine tuned.

Feedback from benchmarking acknowledged. (for all portions except for the hybrid corner-SSTA flow)

WP3Mixed design

Description of the variability and reliability analysis methods at circuit level

Demonstration of the developed method on SRAM and analog circuits

Validation of the developed method

WP4Algorithm

Software techniques for flexible data and workload

allocation for migration (the base flexible RTSM support)

Control algorithms for system level reliability and variability management (exploiting of the base RTSM support)

Porting, optimization and tuning for the target evaluation platform of: (a) the flexible RTSM, (b) the control algorithms

WP5Integration

Definition of characterization blocks, macrocells, and system level architecture

Validation and application of methods to macrocells and integration into system

Final system integration, validation feeding into WP6 benchmarking

WP6Benchmarking

Identification of relevant industrial applications and associated requirements and evaluation metrics

Definition of the validation plan

Benchmarking of block level IPs

Benchmarking of system level platform

Evaluation of results and impact according to validation plan criteria

In summary, REALITY as been able to meet all initially planned project objectives as described in its Annex 1. The minor deviations observed have been due to external factors (limited availability of silicon data at 32nm) and/or late identification of valorisation opportunities of the developed techniques.

10. Potential Impact

The scientific impact has been big since with the developed 3D carrier simulation methodology has been possible to accurately predict variability and the degradation of it at device level with TCAD



simulations for new processes bellow the 32nm node. The project has created a strong potential for commercial impact in the CAD industry. It has enabled the creation of variability aware system on chip design flows which are in fact a required extension of the present ones (which are limited to the block level characterization) and the DFM flows which are effective only towards the end of the project at the physical implementation phase. Allowing a realistic estimation of the manufacturing yield already from the system architecture exploration this project can generate considerable economies by helping draw the appropriate design and architecture guidelines for achieving later on the required production yield at the manufacturing stage. The environmental impact has been also evident since it allows more energy efficient circuits and higher yield.

Leaders of several international projects have contacted the REALITY coordinator for access to available public information of the project results.

An example is the recently launched project in the US project named “Variability Expedition” who’s coordinator, Dr. Yuvraj Agarwal, expressed strong interest in REALITY and its project results during the last meoth of September. “Variability Expedition” studies the variability in components used to design Computer Systems, with the eventual goal of building systems that can not only detect this variability but also adapt to it. The project is an NSF funded Expeditions and is a collaborative effort between several US universities, UC San Diego as the primary institution and UCLA, UC Irvine, Stanford, Michigan, UIUC as partner institutions. The project PI is Prof. Rajesh Gupta who is the chair of the CSE department with Prof. Mani Srivastava from UCLA serving as the deputy Director. They just kicked off the project, and the “Variability” site can be found at: http://variability.org/

They found the REALITY project very interesting to say the least, since we were first studying and characterizing the variability, including for ARM chips (32nm and beyond). They expressed their strong interest in project reports or any publications that have resulted from our effort and asked if there was a website with the relevant publications/ technical documents/presentations that have come out of our project.

A second example with wider implications has been the quick reaction from the IEEE Spectrum magazine (Senior Editor Samuel K. Moore) that contacted the coordinator of REALITY for a potential follow-up the form of an article in the cited magazine the same day the end of project REALITY press release was launched. Today such follow-up article has been confirmed by the time of writing this final report.


http://variability.org/


11. Main dissemination activities and exploitation of results

Within the REALITY consortium all partners contribute to a large extend equally to the dissemination of the project results. Extensive details on the dissemination approach and achievements can be found in deliverable reports D8.3 and D8.5

12. Plan for use and dissemination of foreground

IPR, Access rights and licensing have been made explicit and described in an elaborate way in the Consortium Agreement which was signed by all consortium partners.

The objective of defining the exploitation strategy is to identify the results from the project that can be used or exploited by partners. Therefore, an initial analysis has been assessed on the exploitable results. Based on these results, possible exploitation strategies have been defined. Both the academic and industrial partners have been instrumental in using the methodologies and tools developed during the project course. On the one hand, the academic partners have been interested in the results of the project because they can use them in a near future to continue some of their active research lines. On the other hand, the project results have been crucial to asses and improve the design flows and production processes of the industrial partners, since the specific technical area of the project belongs to some of the leading edge business cases of these companies. Finally, the exploitation phase aims to develop and market new design techniques and methods for future SoC’s and to use these results in the design flow of the industrial companies resulting in real-time guaranteed, energy-efficient, robust and self-adaptive SoC’s.

12.1. Use by industrial partners in proprietary productsThe use of the REALITY project results in products has been proven to be useful for the major industrial partners in this project: ARM and ST

The participation of STMicroelectronics and ARM to this project was motivated by both the strong impact of the research activities and topics addressed, which are critical for a leading company like ST and a leader in microprocessor Intellectual Property like ARM, and by the outstanding competence and scientific reputation of the participating scientific partners.

12.1.1. STMicroelectronics.



The major impact from REALITY has been to develop such tools that on the one hand will link process technology and design and on the other hand will address process issues by offering design solutions.

These techniques are simply not sufficient to predict silicon behaviour at design time STMicroelectronics has extensive collaborations and links with many CAD and EDA vendors aimed at fostering and improving the design flows deployed within the company to address increasingly more demanding constraints of sub-nanometer design nodes and very large volumes products. Trough these links ST can stimulate the R&D of those tools and design flow providers to focus on the relevant problems and address new methodologies and technologies such as the ones developed within the REALITY consortium.

Moreover, the design flows and methodologies for statistical timing analysis and variability impact evaluation have been included into the top-down design flow currently used at ST. In particular, the statistical timing analysis tool used in REALITY has been deployed to perform sensitivity-based optimization to reduce the pessimistic design margins that significantly reduce the potential benefits and advantages introduced by technology scaling. The automatic internal standard cell library characterization tool has been extended with the techniques for statistical characterization developed and validated in REALITY, to include the impact of process variations in the characterization of industrial libraries.

Finally, exploiting the variability data and statistical device compact models developed in REALITY, a path ranking based on statistical timing analysis generated during sign-off was provided for a better correlation with at-speed testing and to improve the parametric yield using the statistical optimization methods defined in REALITY.

Hybrid design flow for Statistical Static Timing Analysis

In concrete ST has been especially interest on Statistical analysis solutions for random within-die (WID) variations available which today are quite complex for an effective industrial exploitation. In REALITY we demonstrated that Statistical Static Timing Analysis (SSTA) is a good estimator of random WID variations, but in general, it lacks ease of deployment in an industrial environment, and requires a lot of efforts to characterize the statistical libraries, as it was demonstrated by means of the work carried out in WP2. Moreover, it is also true that chip designers in an industrial environment, who have to satisfy tough turn-around-time requirements, and have to meet strict time-to-market windows dictated by an increasingly fierce competition, do not want to change the traditional sign-off methodology for timing verification based on Deterministic Static Timing Analysis (DSTA). Therefore, it has been necessary to develop a rapidly deployable solution based on existing corner based analysis flows in mixture with a more detailed statistical based one.. Moreover, it has been necessary to define the basic set of process parameters to effectively characterize the standard cell libraries, thus drastically reducing the library statistical characterization runtime These two critical issues were addressed in REALITY at ST, and practical methodologies and design flows based on the research activities carried out in REALITY work packages were developed and are currently exploited at ST.

System level mitigation of process variability impact

From a system design perspective, the technologies developed by REALITY can be key to achieve the goal of meeting the worst case constraints associated to both performance and reliability of complex products; such as the ones designed for advanced consumer multimedia chips. Consider for example the cost associated to worst case design margins in complex multimillion cells designs; the variability analysis flows provided by REALITY for both memories and cores have allowed relaxing of constraints while at the same time the deployment of SW/HW countermeasures have significantly reduced the energy consumption level while guaranteeing or improving the expected quality of service in many cases; as illustrated by the test cases exercised along the project.

Another key aspect from a system architecture standpoint was the ability to predict QoS, Power and to some extent yield for aged conditions and the overall system effects of aging for a specific application or product. The cooperation with the UNIBO team has been key for such successful outcome.



REALITY: not only technical achievementsDuring the project, the partners had the remarkable opportunity to work in close cooperation, to exchange ideas, to discuss about novel design techniques, and to develop new methodologies which are currently exploited by the design teams. Therefore, we believe this project was a unique opportunity to perform advanced and innovative research activities that otherwise would have been quite problematic within a typical industrial environment, and the proper blend of world-class academic theoretical background and industrial expertise allowed achieving outstanding results within the timeframe of the project, thus providing the European industry a significant competitive advantage. Hence, we consider REALITY a highly successful project and we would pursue further research activities and cooperation with all the partners.

12.1.2. ARM Ltd.The impact at the system level of random variations observed on the transistors of the most advanced technologies is quite difficult to analyse. Acquiring a good knowledge on variability issues through the whole development flow and developing an accurate methodology to percolate the variability information from the device level up to the SoC is fundamental to develop the next generation processors. As a consequence the dissemination of the knowledge acquired during the project has been one of the main challenges for the ARM team.

The exploitation of the outcome of the project has happened in three different ways:

1. Transversal team work organisation

To address the specific transversal needs of the project ARM has build up a project team with engineers coming from different horizons:

Device Physical IP System design

A strong synergy between these three fields is becoming mandatory to understand the challenges we will face at each step of development of the next generation nodes. Within the project the team is developing characterisation methods as well as innovative design solutions to address the random variation issues in the designs. The ability to produce useful solutions will validate the transversal team organisation.The team will survive the project and take advantage of this specific organisation to address new challenges we will face in the future technologies.

2. Internal knowledge spreading

The project is the place of a strong cooperation between ARM engineers and well known European researchers. The links drawn are essential for ARM to build a strong knowledge in variability phenomenon, characterization methods and remedial solutions. Workshops and tutorials have been organised at ARM enabling fruitful exchanges between partners and in house engineers. These events were profitable for both parties:

ARM has got through these discussions a deeper understanding of the troubles they will face in the future technologies. This is especially done with the cooperation with University of Glasgow and IMEC who develop a good synergy to forecast the random effect on advanced devices.

We provide our partners with a better understanding of the industry constraints we are facing both in the Physical IP field and in the System level development era. This is outstanding information to lead the frontend researches toward investigations closer to the applications.

This cooperation between universities, research institutes and ARM gives us a strategic understanding of the issues and allow to better target our research efforts by knowing the industrial constraints as well as the fundamental physics issues we will face.



Beyond the knowledge exchange organized with our partners, the engineers involved in the project have build an strong internal know how for ARM. They have been participating to quarterly meetings with their peers inside ARM to internal research teams with information on the result of the project and discuss the interesting way to lead their technical work. To train the development engineers, internal conferences involving engineers from all divisions of the company have been organised within ARM. Technical presentations in these events were also proposed.Finally the knowledge built during the project led the basis of broader publication in conferences or tutorials in order for us to advertise towards our potential customers on our strategic understanding of the issue.

3. Production phase of tools and methodologies developed during the project

ARM was interested by the Variability Aware Methodology developed during the project. As a consequence a demonstration of the methodology on an ARM926 processor was proposed and achieved. The method will therefore be exploited within ARM. The ultimate demonstration of the methodology could be an application on more advanced processors to address the most power demanding applications.The demonstration of the methodology has been a crucial phase which has really opened the door to exploit the method more widely inside the company if we feel it may provide us with a strategic differentiator toward our competitors.

ARM engineers have also developed internal tools to analyse accurately the variability impacts at the physical IP level as well as at the system level. The tools developed are not supposed to compete with any EDA vendor tool but aims at providing the most accurate information on variability for punctual analysis. One the one hand the information of these tools has been exploited either to provide accurate information on some specific designs. On the other hand this tool has been quite useful to validate the accuracy of the commercially available characterization tools since the statistical analysis is supposed to provide a more exact description of the design electrical behaviours then classic methodologies. At the end of the project, the R&D team has provided the development engineers with prototypes. They have had the capability to test the concepts on their own designs and analyse how the tools can be integrate in their production flow

The tools and methodologies investigated within have allowed analysing the impact of the statistical variations. The wanted impact of these tools has been to allow engineers to analyse the robustness of their design, simple or complex, in a reasonable timeframe towards the effects of random variability. As a side effect, the project has provided us with the necessary information to develop more robust systems and efficient resilient systems.What is more, the accurate analysis of random variability has also paved the way to a better understanding of systematic variability. The comparison between the different effects on the new technologies gives a good understanding where to put our development efforts.

From the 65nm node technology developers and designers have started to be confronted to the variability issues due to local and global effects. In concrete ARM designers have started investigations in variability characterization very early but the lack of technology information was a real limitation for a company focused on design. The main issues on our designs have showed up at the 45nm node. A real need for strong cooperation with experts in this field was identified. Early access to the information on future technology nodes is mandatory for a company developing Physical IP.

Variability Characterization:The first idea we can develop when facing a new issue is to try to model it accurately. This is what we have started doing in the REALITY project. At the transistor level there has been a strong development work to assess accurate variability information. The second step is to analyze the variability impact on simple design.



At the time the project started we could see a strong momentum from the EDA companies to put in place variability aware flows. New tool features and new library format appeared: CCS-VA, S-ECSM. Designers needed to understand the interest of these tools. For this we needed to produce the right liberty data incorporating the correct variability information. We also needed to use the tools and evaluate the results. This is what we carried out on simple standard cells. We also developed a validation flow to verify the output of the flows. This was a really strategic work since were able to identify accuracy issues on these new tools and challenge the EDA vendors on their own expertise. A full characterization of a system could be carried out using the VAM flow. This tool is based on Monte Carlo simulations. It is really demanding in term of library characterization since to achieve a good accuracy a large number of runs is required. Each run is one library characterization. The results of the tool are really valuable since it is the only tool to our knowledge providing a real correlation between power, leakage and speed of the system. Even though tools were developed for standard cells characterizations no EDA flow addressed the issue of variability characterization of SRAM array was. It is important to notice that the first area where the variability issues could be clearly identified is the SRAM array functionality. Due to the high number of SRAM cells a memory array acts like a net catching the extreme variability information. Indeed a memory array is limited in term of functionality as well as in term of performance by the worst case cell in the array. This is why a great interest has been raised on SRAM array characterization. In our case the investigations have taken two different forms. First we needed to understand the limits of functionality of designs. This has been answered by investigations on the memory margining. Strong mathematical models have been used to develop accurate statistical descriptions to account for the variability issues.

Secondly ARM wanted to understand the impact of the SRAM variability on a full system. The memory VAM methodology gave us interesting clues on this issue. The methodology based on MC runs as well first provides interesting information of the stand alone memory variability. In addition with the help of the full system VAM we could directly understand how the system behavior is impacted by our memory design.

Importance of variability aware designOn advanced technologies one of the major issues is coming from the exponential leakage. 32nm technologies have already demonstrated very high leakage level and the first figures coming from papers showing latest technology development is very alarming. We might face in the near future a problem when the chip cannot be fully active at the same time otherwise it will simply melt (Android processor shines light on dark silicon - Rick Merritt – EETimes). New techniques will have to cope with these issues.

An ultra-low power SRAM designs do not seem fully suitable for general purpose solutions today, however it paves to way to the low power design that will be needed in “dark silicon” systems as described in the previous article. It is also fully adequate for ultra-low power systems as the one seen on medical devices which is a growing market.

Low voltage and ultra-low voltage designs are also identified as a potential solution for future developments. When reducing the voltage supply a great gain in leakage power will be witnessed but we will hit the variability wall as well. Design techniques to cope with the increasing variability we will face at the 22nm node and below will be mandatory. The design techniques proposed by the partners in this field make these options possible.

Beyond the technical discussionsThe interest of the project goes far beyond the technical conclusions we have drawn during the 2.5 years of the project. The partners had the opportunities to exchange ideas, start cooperation and understand each others’ objectives and issues. It has been a great opportunity to create a network we all would like to keep alive during further exchanges.

12.1.3. Gold Standard Simulations Ltd.



Gold Standard Simulations Ltd., a spin-off from the University of Glasgow, has been set up to help chip designers model how circuits made from variable and unreliable nanoscale transistors will perform.

The company was created by Professor Asen Asenov (shown), who holds the James Watt Chair in Electrical Engineering at the College of Science and Technology at Glasgow University. Professor Asenov is serving the company as CEO.

GSS is offering a world-leading simulation service to chip developers and manufacturers. The company's executives are three PhD graduates: Campbell Millar, Gareth Roy and Dave Reid. Reid is an expert in software development methods and statistical circuit simulation and is the primary developer of the GSS RandomSPICE software and provides compact modeling services within the company. The company will also offer courses in statistical variability on how to design variability-resistant and reliable devices and circuits.

The company, which is based at the university, is subcontracted to provide simulation services for the MODERN (MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems) project – a €26 million (about $33 million) European collaborative research project looking at how to design computer chips.

Professor Asenov is leading the University of Glasgow’s involvement in the project which is worth £1.5 million (about $2.3 million) to the university and comprises 28 European partners.

REALITY has been one of the projects supporting Prof. Asenov’s R&D activities hence also indirectly to the establishment of GSS.

13. Wider Societal Implications

TBD


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