technical university tallinn, estonia 1 2. sissejuhatus teooriasse 1.teooria: boole’i...
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Technical University Tallinn, ESTONIA
1
2. Sissejuhatus teooriasse
1. Teooria: Boole’i differentsiaalvõrrand
2. Teooria: Binaarsed otsustusdiagrammid
Rike
Test
Testi süntees
Diagnostika sõnastik
Testi analüüs – rikete simuleerimine
Stiimul
Digitaal- süsteem Reaktsioon
Diagnoos12
3
4
Technical University Tallinn, ESTONIA
2
Fault Propagation Problem
&
1
Path activation
Fault “Stuck-at-1”
0
Fault activation
Correct signal
Error
1 0
Logic gate
1
Path activation
Fault Stuck-at-0
Fault activation
Correct signal
Error
1 0 x1 x2
x3 = 1 x4 x5 x6 x7
y
0
0
0 F (X)
Logic circuit
Technical University Tallinn, ESTONIA
3
Boolean derivatives
Boolean function:
Y = F(x) = F(x1, x2, … , xn)
Boolean partial derivative:
),...,...(),...,...()(
11 ninii
xxxFxxxFx
XF
),...1,...(),...0,...()(
11 ninii
xxxFxxxFx
XF
Technical University Tallinn, ESTONIA
4
Boolean Derivatives
Useful properties of Boolean derivatives:
These properties allow to simplify the Boolean differential equation
to be solved for generating test pattern for a fault at xi
If F(x) is independent of xi
ii x
XGXF
x
XGXF
)()(
)()(
ii x
XGXF
x
XGXF
)(
)()()(
)( 323241 xxxxxx
41)( xxXF 3232)( xxxxXG
Näide:
ix
XGxx
x
XGXF
)()()(41
2
Technical University Tallinn, ESTONIA
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Boolean derivatives
- if F(x) is independent of xi
- if F(x) depends always on xi
0)(
ix
XF
1)(
ix
XF
Examples:
:)()( 32321 xxxxxXF 0)(
21213
xxxx
x
XF
:)( 21 xxXF 1)(
221
xx
x
XF
),...1,...(),...0,...()(
11 ninii
xxxFxxxFx
XF
Technical University Tallinn, ESTONIA
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Boolean vector derivatives
If multiple faults take place independent of xi
Example:
&
&
1
x1x2
x3x4
),...,,...(),...,,...(),(
)(11 njinji
ji
xxxxFxxxxFxx
XF
43214321 ),,,( xxxxxxxxFy
)(),(
)(3232414141
32
xxxxxxxxxxxx
XF
Technical University Tallinn, ESTONIA
7
Boolean vector derivatives
Calculation of the vector derivatives by Carnaugh maps:
1)(),(
)(3232414141
32
xxxxxxxxxxxx
XF
43214321 ),,,( xxxxxxxxFy x2
x1
1 1
111
11
x3
x4
4321 xxxx
x2
x1
1 1
11
1 11
x3
x4
4321 xxxx
x2
x1
1 1
1
11
11
x3
x4
1
1
1
=
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Boolean vector derivatives
Interpretation of three solutions:
1)(),(
)(3232414141
32
xxxxxxxxxxxx
XF
141 xx
Two paths activated
&
&
1
x1x2
x3x4
yFault
1
1
141 xx
Single path activated
&
&
1
x1x2
x3x4
yFault
1
0
Technical University Tallinn, ESTONIA
9
Derivatives for complex functions
Boolean derivative for a complex function:
i
j
j
k
i
jk
x
F
F
F
x
XXFF
)),((
Additional condition:
03
2
x
x
y
x2
x1x3x44
3
3
1
14 x
x
x
x
x
y
x
y
Example:
Research in ATI© Raimund Ubar
Topological Idea of Test Generation
1
Path activation
Fault Stuck-at-1
Fault activation
Correct signal
Error
0 1 x1 x2
x3 = 0 x4 x5 x6 x7
y
0
0
0 F (X)
10
7654321 )( xxxxxxxy
1
0
0
x1
x2
y
x3
x4 x5
x6 x7
0
11
x1
x2
y
x3
x4 x5
x6 x7
0
10 1
0
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&
&
&
1
&
x1x2
x3x4
y
x11
x21
x12x31
x13
x22x32
x5
x6
x7
x8
Each node in SSBDD represents a signal path:
Mapping Between Circuit and SSBDD
x11y x21
x12 x31 x4
x13x22 x32
0
1
0
1
11
Signal path
Node x11 in SSBDD represents the path (x1, x11, x6, y ) in the circuitThe SAF-0(1) fault at the node x11 represents the SAF faults on the lines x11, x6, y in the circuit fault collapsing32 faults (16 lines) in the circuit 16 faults (8 nodes) in SSBDD
Technical University Tallinn, ESTONIA
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316254142321 ))((( xxxxxxxxxxxxy
1...
)()())((
)()()(
2341
62414233121
5
562414233121
5
xxxx
xxxxxxxxxxx
x
xxxxxxxxxxxx
x
y
x1 x2y
x3 x2 x4
x1 x4
x5
x2 x6
x1 x2
1
0
Test Generation with BD and BDD
BD:BDD:
x1 x2 x3 x4 x5 x6 y
0 1 - 0 D - D
Test pattern:
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Algorithm:1. Determine the activated path to find the fault candidates2. Analyze the detectability of the each candidate fault
(each node represents a subset of real faults)
Fault Analysis with SSBDDs
x11y x21
x12 x31 x4
x13x22 x32
0
1
0
1
13
&
&
&
1
&
x1
x2
x3x4
y
x11
x21
x12
x31
x13
x22x32
0
1
0 001
00
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14
Test Generation with SSBDDs
&
&
&
1
&
x1
x2
x3x4
y
Test generation for:
x11
x21
x12
x31
x13
x22x32
x110
10
1
00
0
0
10
10
0
x11y x21
x12 x31 x4
x13x22 x32
11 1
10
Structural BDD:
x1y x2
x4 x3
x2
Functional BDD:
0
11
10
1
1
x1 x2 x3 x4 y
1 1 0 -
Test pattern:
1 0
Research in ATI© Raimund Ubar
Functional Synthesis of BDDs
Shannon’s Expansion Theorem: 01)()()(
kk xkxk XFxXFxXFy
2432 )( xxxx
43xx
43124321 ))(( xxxxxxxxy
011
)(x
XFx
x1y43 xx x2 1
x3
x4
xky1
)(kx
XF
0)(
kxXF
Using the Theoremfor BDD synthesis:
1
0
x3 x4 1
0
Research in ATI© Raimund Ubar
Functional Synthesis of BDDs
Shannon’s Expansion Theorem: 01)()()(
kk xkxk XFxXFxXFy
43124321 ))(( xxxxxxxxy
x1y x2 1
x3
x4
x3 x4 1
0
x1y
x3
x2 1
x3
x4
0
Research in ATI© Raimund Ubar
BDDs for Logic GatesElementary BDDs:
1
x1
x2
x3
y x1 x2 x3
NOR
1x2
x3
y x1
x1
x2
x3
ORx1
x2
x3
y
x1 x2 x3
& AND
1
0
&
1
1x1
x2
x3
x21
x22y
a
b
SSBDD synthesis:SSBDDs for a given circuit are built by superposition of BDDs for gates
Given circuit:
17
1
0
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Synthesis of SSBDD for a Circuit
&
1
1x1
x2
x3
x21
x22y
a
b
))((& 322211 xxxxbay
a by
a x1
x21
Superposition of BDDs:
Superposition of Boolean functions:
Given circuit:
Compare to
Structurally Synthesized BDD:
b x22
x3
ay x22
x3
b
x3
y x22x1
x21
a 18
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19
Generation of BDDs for
321 xxxy
Logic Operation with BDDs
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Boolean Operations with SSBDDs
20
1
&
&x1
x2
x3
x21
x22
y
a
b
1
&
&x5
x6
x51
x52
c
d
x4
g
e
AND-operation:
y = e g x3
x1
x21
x22
x6
x4
x51
x52
y
OR-operation:
x3
x1
x21
x22y
x6
x4
x51
x52
y = e g
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21
Boolean function: y = x1x2 x3 (x4 x5x6)
1-nodes of a 1-path representa term in the DNF: x3x5x6 = 1
Properties of SSBDDs
x1y x2 #1
#0
x3 x4
x5 x6
y
0-nodes of a 0-path represent a term in the CNF: x1x4x5 = 0
x2 #1
x3
x6
#0
x1
x4
x5
Research in ATI© Raimund Ubar
Boolean Operations with SSBDDs
22
Boolean function:
y = x1x2 x3
y x1 x2
x3
Dual function:
y*
y*= (x1 x2) x3
x1 x3
x2
Inverted dual function:
y * = x1x2 x3
y * x1
x3
x2
Inverted function (DeMorgan):
y = x1x2 x3 = ( x1 x2) x3
y x1 x3
x2
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Transformation Rules for SSBDDs
23
Commutative law:
y = x1 x2= x2 x1
BOOLEAN ALGEBRASSBDD
Idempotent law:Node passing:
y y y = x1 x1 x2 = = x1 x2=
x2x2
x1
x1
x1
x2
Exchange of nodes:
y y
=x1
x2
x2
x1
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24
Properties of SSBDDs
Boolean function:
y = x1x2 x3 (x4 x5x6)
x1y x2 #1
#0
x3 x4
x5 x6
y x1 #1
x3
x5
#0
x2
x4
x6
Exchange of nodes:
y y
=x1
x2
x2
x1
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25
Properties of SSBDDs
Boolean function:
y = x1x2 x3 (x4 x5x6)
x1y x2 #1
#0
x3 x4
x5 x6
Exchange of subgraphs:
y y
=
x3y x4 #1
#0
x1 x2
x5 x6
G1
G2
G2
G1
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Transformation Rules for SSBDDs
26
Absorption law:
BOOLEAN ALGEBRASSBDD
Node passing:
y = x1 x1x2 = x1y y=
x1
x1
x1
x2 x1 x2
Distributive law:y
=y
y = x1x2 x1x3= = x1(x2 x3)
x1
x1
x2
x3
x2
x3
x1
x1
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Transformation of SSBDDs to BDDs
x11y x21
x12 x31 x4
x13x22 x32
SSBDD:
x1y x2
x12 x31 x4
x13x22 x32
x1y x2
x12 x3 x4
x13x22 x32
x1y x2
x4 x3
x2
Optimized BDD:
x1y x2
x4 x3
x2 x3
BDD:
27
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Transformation Rules for SSBDDs
28
Assotiative law:
BOOLEAN ALGEBRASSBDD
y = x1 (x2 x3) = = (x1 x2) x3
Superposition:
y
z
x1
z
x2
x3
y
z=
x1
x2
z
x3
=
y
x2
x3
x1
Research in ATI© Raimund Ubar
Properties of SSBDDsGraph related properties: SSBDD is
planar asyclic traceable (Hamiltonian path) for every internal node there
exists a 1-path and 0-path homogenous
x11y x21
x12 x31
x4
x13x22 x32
0
1
0 0
1
1
1
1
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BDDs for Flip-Flops
30
D
C
q c
q’
D
Elementary BDDs
D Flip-FlopJK Flip-Flop
c
q’
S
R q’
S
J
q
R
C
KK
JS
C
q
R
0
')'(
SR
qcRqScq
c
q’
S
R q’
R
U
RS Flip-Flop
U - unknown value
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31a
a b
c
Y
Fan-out stems
SSBDD4
SSBDD5
SSBDD3
SSBDD2
SSBDD1
A
B
CY1
Y2
D
E
FFR
FFR
FFR
FFR
FFR
C
From circuit to set of SSBDDs
Mapping Between Circuit and SSBDD
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Advantages of SSBDDs
Linear complexity: a circuit is represented as a system of SSBDDs, where each fanout-free region (FFR) is representred by a separate SSBDD
32
One-to-one correspondence between the nodes in SSBDDs and signal paths in the circuit
This allows easily to extend the logic simulation with SSBDDs to simulation of faults on signal paths
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Shared SSBDDs - S3BDD
Extension of superposition procedure beyond the fan-out nodes of the circuit
33
Merging several functions in the same graphs by introducing multiple roots
Superpositioning of FFRs Node of SSBDD signal path up to fan-out stem Input of SSBDD circuit down to primary inputs
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34
18
9 8
21
6 10 16 13
14 11
7
19
15 12 17
3 4 14 11
17
16
20
18
2
5 1 15 12 10
13
S3BDDs and Fault Collapsing
&
&
&
1
1
1
1
1
&
&
&
&
1
1
1
12
34
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Fault collapsing: From 84 faults to 36 faultsFor SSBDD: 50 faults
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35
SSSBDD for 19
Node Path
14 140-19 (3)
11 110-19 (4)
7 7-19 (4)
15 150-170-19 (3)
12 120-141-170-19 (4)
3 3-111-141-170-19 (5)
4 4-111-141-170-19 (5)
14 11
7
19
15 12 17
3 4 14 11
Shared SSBDDs
&
&
&
1
1
1
1
1
&
&
&
&
1
1
1
12
34
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Each node represents different paths (path segments) in the circuit
Research in ATI© Raimund Ubar
Synthesis of S3BDD for a Circuit
Given circuit C17Superposition of BDDs:
G1 X1 11
G1
3
Y1
3
Y1 X1 11
3 X2 213
Y1 X1 11 Y1 X1 X3
3 X2 21
Y1 X1 X3
3 X2 21 2 12
X4
Y1 X1 X3
3 X2 X3
2X41
Each node in the SSMIBDD represents a signal path in the circuit
Testing a node in SSMIBDD means testing a signal path in the circuit
Research in ATI© Raimund Ubar
Synthesis of S3BDD for a Circuit
Given circuit C17
Two-output circuit is represented by a single SSBDD with shared
subgraphs
37
Superposition of BDDs:
G4 X5 2
Y2
G4
3 Y2 3
X5 2
Y1 X1 X3
3 X2 X3
2X4
2
Y2 3
X5
Y2 3
X5
Y1 X1 X3
3 X2 X4
X3
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38
1
1 T13
2
&
13 1
11
&1
1
16
8
&1 & 26
1
12
T3
T2
4
5
6
79
10
14
15
1718
19
20
21
22
23
24
25
Sequentional S3BDDs
1
12
T222 258
T2
&
13 1
11
&1
1
16
8
&1 & 26
T3
4
5
6
1417
18
19
20
21 23
24
9
T3
T3
T2
14
1
1 T1
3
2
7 9
10
15 T1
T1
3 2
T1
T1
9
T2T3
26
9
14
4
T3 1
14 8
8T2
25 nodes,50 stuck-at faults
10 nodes,20 stuck-at faults,
2,5 times less
GAIN: 2,5 times
in logic simulation, 2,5 2 = 6,25 times in fault simulation
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39
G Nodes Signal paths L
GT1
3 3 – 15 – T1 32 2 – 9 – 10 – 15 – T1 5T1 T1 – 7 – 9 – 10 – 15 – T1 6
Structured Interpretation of S3BDDs
3 2
T1
T1
91
1 T1
3
2
7 9
10
15 T1
T1
Each node in the S3BDD represents a signal path in the circuit
S3BDD represents two subcircuits
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40
G Nodes Signal paths LGT2 8 8 – 12 – 25 – T2 4
G26
T2 T2 – 5 – 21 – 23 – 26 59 9 – 11 – 18 – 20 – 21 – 23 – 26 7
14 14 – 17 – 18 – 20 – 21 – 23 – 26 74 4 – 19 – 20 – 21 – 23 – 26 6T3 T3 – 6 – 14 – 16 – 19 – 20 – 21 – 23 – 26 91 1 – 8 – 13 – 14 – 16 – 19 – 20 – 21 – 23 – 26 10
Structured Interpretation of S3BDDs
1
12
T222 258T2
&
13 1
11
&1
1
16
8
&1 & 26
T3
4
5
6
1417
18
19
20
21 23
24
9
T3T3
T2
14
Research in ATI© Raimund Ubar
Optimization (by ordering of nodes): BDDs for a 2-level AND-OR circuit
BDDs and Complexity
2n nodes 22n - 2 nodes
BDD optimization:We start synthesis:•from the most repeated variable
Research in ATI© Raimund Ubar
BDDs for an 8-bit data selector
BDDs and Complexity
Research in ATI© Raimund Ubar
BDDs and Complexity
43
D
C
q c
q’
D
Elementary BDDs
D Flip-FlopJK Flip-Flop
c
q’
S
R q’
S
J
q
R
C
KK
JS
C
q
R
0
')'(
SR
qcRqScq
c
q’
S
R q’
R
U
RS Flip-Flop
U - unknown value
BDD optimization:We start synthesis:• from the most important variable, or•from the most repeated variable