task and funtion in sverilog

8/11/2019 Task and Funtion in Sverilog

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Tasks and Functions in Interface

You can define a task or a function inside an interface pretty much the sameway that you define a task or a function inside a module . Moreover, a task or afunction defined within an interface can be called from anywhere. This impliesthree different possibilities of how a task or function can be defined andcalled .(a) Defining a task or function within an interface and calling it from a module :For example, a task associated with a connection (e.g. to send or receive data) can

be defined within the interface that represents that connection. A module, withoutany implicit knowledge of the connection or the task, can simply call the task to

perform the operation on the connection.This is shown in the example below. Here, the interface intf_AB contains the task send_data() . This task is called by moduleA that sends data through the connection.

interface intf_AB (input bit clk);logic ack;logic ready;logic send;logic [31:0] data;

task send_data (input logic send_signal, input logic [31:0] data_bus);... // actual task definitionendtask

... // rest of the interface definition hereendinterface

module moduleA (interface xyz);

...xyz.send_data(send);...

endmodule

The rest of the definitions for moduleB and top remain unchanged.(b) Defining a task or function for a modport and calling it from a module : Incase a module uses a special modport of an interface, tasks can be imported intothat modport and then the module can call the task in the same way as above. This


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...endinterface

module moduleA(interface xyz);...task xyz.send_data (input logic send_signal,

input logic [31:0] data_bus);... // actual task definitionendtask...// somewhere within the module this task is being calledxyz.send_data(send, mydata);...

endmodule

module top;...moduleA AA (intf_AB.source);...

endmodule

Task and Function are still same as in Verilog 2001, but SystemVerilog adds the ability to declare awithin static tasks and functions, and static variables within automatic tasks and functions

addition1)Capabilities for declaring task and function ports like for module .2)Passing arguments by reference instead of by value3)Passing argument values by name instead of by position4)Default argument values5) Function output and inout ports6)Void function7)Multiple statements in a task or function without requiring a begin...end or fork...join block8)Returning from a task or function before reaching the end of the task or function9)Importing and exporting functions through the Direct Programming Interface (DPI)

Task declration can be as in verilog 1995/2001 or can be declared as in C or C++. InSystemVerilog following rules hold good for any Task declaration.


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#(delay) $display ("@%g Value passed is %d", $time, count);Endtask

Endmodule

Output@6 Value passed is 4

@7 Returning from task

Tasks & Functions - Examples

Examples for Function

(a) Ethernet

(i) Example for Function

// CRC checking calculations: Ethernet packet// Example for class and function call

module CRC1 ;

class crc;rand bit [15:0]length;rand bit [47:0]addr_s; // source addressrand bit[47:0]addr_d; // Destination addressrand byte fcs[4:0]; // frame check sequencerand bit preamble[63:0];rand byte data[10:0];function integer fcs_cal(bit a_fcs_cal) ;integer k;a_fcs_cal = a_fcs_cal ^ addr_s;a_fcs_cal = a_fcs_cal ^ addr_d;a_fcs_cal = a_fcs_cal ^ length;$display("The value of length, source address, destination address %h %h%h",length,addr_s,addr_d);$display("The value of length crc = %h, source address crc = %h,destinationaddress crc = %h",a_fcs_cal,a_fcs_cal,a_fcs_cal);


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for ( k= 0;k < $size(data); k++ ) begina_fcs_cal = a_fcs_cal ^ data[k];$display("The value of data crc %h ",data[k]);$display("The value of CRC = %h ",a_fcs_cal);endreturn a_fcs_cal;endfunctionendclassinitial

begincrc cal;// object of class is definedcal = new() ;cal.randomize();

$display("***********Simulation started**************");$display("Calculation = %h",cal.fcs_cal(9));$display("\n***********Simulation ended**************");endendmodule

Output in VCS

***********Simulation started**************

The value of length, source address, destination address 1e213 33fd69262e70 b2973d5d03e2The value of length crc = 0, source address crc = 0,destination address crc = 0The value of data crc 0cThe value of CRC = 0The value of data crc 8dThe value of CRC = 1The value of data crc c8The value of CRC = 1

The value of data crc 1fThe value of CRC = 0The value of data crc edThe value of CRC = 1The value of data crc 23The value of CRC = 0The value of data crc 99


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The value of CRC = 1The value of data crc 42The value of CRC = 1The value of data crc 8fThe value of CRC = 0The value of data crc f6The value of CRC = 0The value of data crc 15The value of CRC = 1Calculation = 00000001

***********Simulation ended**************

(b) Sonet

(i) Example for Function

//Example of Generating the Parity in Sonet Frames using Function. For evennumber 1's, parity is 0 else 1

module sonet_Parity() ;reg [7:0] data;reg parity_out;integer i;function parity ;input [47:0] data;integer i;

begin parity = 0;for ( i = 0; i < 47; i = i + 1 )

begin parity = parity data[i];endendendfunctioninitial

begin


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parity_out = 0;data = 0;for ( byte i = 0; i < 8; i = i + 1 )

begin#5 data = i;

parity_out = parity (data);$display ("Data = %b, Parity = %b", data, parity_out);end#10 $finish;endendmodule

Output in VCS

Data = 00000000, Parity = 0Data = 00000001, Parity = 1Data = 00000010, Parity = 1Data = 00000011, Parity = 0Data = 00000100, Parity = 1Data = 00000101, Parity = 0Data = 00000110, Parity = 0Data = 00000111, Parity = 1

task and funtion in sverilog

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