synthesizing hdl using leonardospectrum
DESCRIPTION
Synthesizing HDL using LeonardoSpectrumTRANSCRIPT
Synthesizing HDL Using Leonardo
Prepared By:
Eng. Hossam El-Sayed Abdel-Fadeel
2011
Goal
• Illustrate How to Synthesis your design using LeonardoSpectrum Tool.
Outlines
• What is Synthesis?
• Basic synthesis process.
• Synthesis Tool flow.
• Synthesis stages.
• Getting Started with LeonardoSpectrum.
What is Synthesis?• Once the design has been entered, it must be synthesized.
• The process of synthesis involves converting the VHDL source files into a netlist.
• A netlist is simply a list of logical elements (things that combine, change, or store digital signals) and a list of connections describing how these elements are wired together.
• A netlist can be platform independent, that is, it can target any architecture from any vendor. (e.g. Mentor LS tool, Synopsys).
• Many development environments provide additional support tools such as Register Transfer Level (RTL) viewers (graphical representations of the source code) and/or netlist viewers (graphical representation of how the source code will be implemented in fabric).
• The Electronic Design Interchange Format (EDIF) is a more widely accepted format.
Basic synthesis process
Initial HDL description(technology independent)
RTL level
Logic level
Gate level
Final HDL description(technology dependent netlist)
Optimization
Optimization
Optimization
ASIC
PLD
Synthesisdirectives
Synthesis Tool flow
HDL Designer
Synplify Pro Leonardo Spectrum
Design
Synthesis
ImplementationTarget ASIC/FPGA Vendor
VHDL code
Netlist
Bitstream
Synthesis stages
High level synthesis
Technology
independent
Technologydependent
Low level synthesis
Compile Map Place & Route Implement
- Code analysis
- Derivation of main
logic constructions
- Technology
independent
optimization
- Creation of “RTL
View”
- Mapping of extracted logic
structures to device
primitives
- Technology dependent
optimization
- Application of “synthesis
constraints”
-Netlist generation
- Creation of “Technology
View”
- Placement of
generated netlist onto
the device
-Choosing best
interconnect structure
for the placed design
-Application of
“physical constraints”
- Bitstream
generation
- Burning device
Synthesis stages
High level synthesis Low level synthesis
Compile Map Place & Route Implement
Synplify Pro
Leonardo Spectrum
Technology
independent
Technologydependent
Getting Started with
Synthesis Wizard Tutorial• The following screens and four steps give you a tour of the
Synthesis Wizard. The steps ask you to apply example choices and to use defaults.– Step 1:Invoking LeonardoSpectrum
– Step 2: Load the technology library
– Step 3 - Input Files: *.vhd
– Step 4 - Global Constraints: *MHz
– Step 5 - Output File and Finish: *.edf (default)
Step 1:Invoking LeonardoSpectrum
• To start, invoke LeonardoSpectrum with Level 3
Main Window at Startup
Main Window at Startup
Main Window
Synthesis Bar
Toolbar
Device Settings
Step 2: Load the technology library
The Quick Setup Task Flow1. Set Technology
2. Set Working Directory
3. Open Design Files
4. Set Clock
5. Set the Optimization Effort
6. Verify the Name and Destination
7. Activate Place and Route8. “Click”
Step 3: Input Files
Set Working Library
Step 4: Global Constraints
Step 5: Output File and Finish