leonardospectrum users manual

LeonardoSpectrum for AlteraUser’s Manual

Software Version v2001.1

July 2001

Copyright © 2001 Exemplar Logic, Inc., A Mentor Graphics Company. All rights reserved.This document contains information that is proprietary to Exemplar Logic, Inc and may be duplicated inwhole or in part by the original recipient for internal business purposes only, provided that this entire noticeappears in all copies. In accepting this document, the recipient agrees to make every reasonable effort toprevent the unauthorized use of this information.

This document is for information and instruction purposes. Exemplar Logic reserves the right to makechanges in specifications and other information contained in this publication without prior notice, and thereader should, in all cases, consult Exemplar Logic to determine whether any changes have been made.

The terms and conditions governing the sale and licensing of Exemplar Logic products are set forth inwritten agreements between Exemplar Logic and its customers. No representation or other affirmationof fact contained in this publication shall be deemed to be a warranty or give rise to any liability ofExemplar Logic whatsoever.

DISCLAIMER

ALTHOUGH EXEMPLAR LOGIC, INC HAS TESTED THE SOFTWARE AND REVIEWED THEDOCUMENTATION, EXEMPLAR LOGIC, INC MAKES NO WARRANTY OR REPRESENTATION,EITHER EXPRESSED OR IMPLIED, WITH RESPECT TO THIS SOFTWARE AND DOCUMENTATION,ITS QUALITY, PERFORMANCE, MERCHANTABILITY, OR FITNESS FOR A PARTICULARPURPOSE.

EXEMPLAR LOGIC SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, ORCONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS)ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT,EVEN IF EXEMPLAR LOGIC INC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

RESTRICTED RIGHTS LEGEND 03/97

U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirelyat private expense and are commercial computer software provided with restricted rights. Use,duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to therestrictions set forth in the license agreement provided with the software pursuant to DFARS 227.7202-3(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - RestrictedRights clause at FAR 52.227-19, as applicable.

Contractor/manufacturer is:Exemplar Logic Inc.

880 Ridder Park Drive, San Jose, CA 95131web site: http://www.exemplar.com

email: [email protected]

TRADEMARKS

Exemplar Logic™ and its Logo are trademarks of Exemplar Logic, Inc. LeonardoSpectrum™,LeonardoInsight™, TimeCloser™, FlowTabs™, HdlInventor™, SmartScripts™,P&RIntegrator™,DesktopASIC™, XlibCreator™, SynthesisWizard™, and MODGEN™ are trademarks of Exemplar Logic,Inc.; Model Sim/VHDL™, Model Sim™, and V-System/Verilog™ are trademarks of Model Technology,Inc.; Renoir™, Monet™, and PackagedPower™ are trademarks of Mentor Graphics Corporation.Verilog® and Verilog-XL® are registered trademarks of Cadence Design Systems, Inc. All othertrademarks remain the property of their respective owners.

http://www.exemplar.com

Table of Contents

. 1-1

...

...... 1-2

..

..... 1-..... 1-4.... 1-5... 1-8..... 1-9.... 1-9............ 1-9.... 1-10

.. 2-1

..... 2-2... 2-2... 2-5... 2-7

. 3-1

...... 3-3

...... 3-3..... 3-4...

... 3-4

..... 3-6

....... 3-6

..... 3-7

.... 3-9

..... 3-9.. 3-10

TABLE OF CONTENTS

Chapter 1Introducing LeonardoSpectrum..............................................................................................

HDL Languages.................................................................................................................. 1-2Save and Restore Project .................................................................................................HDLInventor.......................................................................................................................... 1-2Tcl Script Sourcing .............................................................................................................. 1-2

Using the Synthesis Wizard.................................................................................................3Understanding the Quick Setup Flow..................................................................................

The Quick Setup Task Flow ..............................................................................................Applying Constraints with FlowTabs ....................................................................................Technology-Specific Synthesis Options..............................................................................Documentation Available Online .........................................................................................

Context-Sensitive Help .....................................................................................................1-9Menu Bar Help..................................................................................................................... 1-9Product Manuals Online ...................................................................................................

PC Hardware and Software Requirements .........................................................................

Chapter 2Preparing for Synthesis...........................................................................................................

Preparing Your Design for Synthesis ..................................................................................Checking Your RTL Coding Style .....................................................................................Rules for Partitioning Your Design ....................................................................................

Creating a Simple Working Directory Structure ...................................................................

Chapter 3Understanding the User Interface...........................................................................................

Understanding the Synthesis Controls ................................................................................Standard Tcl Commands..................................................................................................LeonardoSpectrum Tcl Commands ..................................................................................Setting Tcl Variables .......................................................................................................... 3-4Setting Attributes ................................................................................................................... 3-4Methods for Using Commands With a Tcl Script ..............................................................

Understanding the Tool Setup Environment .......................................................................Setting the Place and Route Executable Pathnames .......................................................Startup Files ........................................................................................................................... 3-6Saving and Restoring a Project .........................................................................................Setting Aliases ....................................................................................................................... 3-9

Invoking the Graphical User Interface..................................................................................The leonardo Command....................................................................................................

The Main Window at Startup................................................................................................Tip of the Day ...................................................................................................................... 3-10

LeonardoSpectrum for Altera User’s Manual, v2001.1d iii

TABLE OF CONTENTS [continued]

Table of Contents

.. 3-12.. 3-13.. 3-203-20.. 3-21

. 3-23

.. 3-23-26.... 3-27.... 3-.. 3-29... 3-29..... 3-

. 4-1

.... 4-2

...

.... 4-3

.... 4-5..... 4-6

... 5-1

.... 5-2

.....

.... 5-2.... 5-3.... 5-4..... 5-6..... 5-6..... 5-7.... 5-7

... 5-10

SynthesisWizard ................................................................................................................. 3-11The Major Elements of the Main Window ............................................................................The Main Window Header ...................................................................................................The Information Window .....................................................................................................

Printing the Content of the Information Window................................................................The HDLInventor Source Code Editor .................................................................................

Templates............................................................................................................................. 3-21Editing Options .................................................................................................................... 3-23Editing Options - Transcript and Filtered Transcript..........................................................More Editing Options ........................................................................................................4Printing the Content of the HDLInventor Window .............................................................

Changing the Default Session Settings ...............................................................................Main Session Settings......................................................................................................27Browser View Options.......................................................................................................Schematic Viewer Options ...............................................................................................Place and Route ................................................................................................................ 3-30

Using the Variable Editor .....................................................................................................31

Chapter 4Loading a Technology Library ................................................................................................

Loading a Technology Library .............................................................................................Technology Mapping............................................................................................................. 4-2

Introduction............................................................................................................................ 4-2Lookup Table Mapping .....................................................................................................

Global Buffers........................................................................................................................... 4-4I/O Mapping.............................................................................................................................. 4-4The Technology FlowTab - FPGA .......................................................................................

Advanced Settings PowerTab - FPGA .............................................................................

Chapter 5Reading Your Design..............................................................................................................

Reading Your Design into Memory......................................................................................Opening Design Files........................................................................................................5-2Reading Custom VHDL Libraries and Packages ..............................................................

Understanding the In-Memory Design Data Model .............................................................Understanding the In-Memory Design Data Structure .........................................................How LeonardoSpectrum Infers and Implements Operators ................................................Understanding Modgen Libraries ........................................................................................Understanding Pre-Optimization .........................................................................................

What is Pre-Optimization?.................................................................................................The Input FlowTab ................................................................................................................. 5-8

The VHDL Input PowerTab ..............................................................................................

LeonardoSpectrum for Altera User’s Manual, v2001.1div


Table of Contents

.. 5-11.. 5-12

.. 6-1

........ 6-3

..... 6-

....... 6-6... 6-9... 6-10.. 6-116-12

.... 6

.. 6-12

.. 6-13

... 6-... 6-18... 6-20... 6-22... 6-24... 6-26.... 6-28... 6-30

.. 7-1

.... 7-2.... 7-2.... 7-5...... 7.. 7-7............ 7-12

The Verilog Input PowerTab ............................................................................................The EDIF Input PowerTab ...............................................................................................

Chapter 6Setting Timing Constraints .....................................................................................................

Setting Timing Constraints ..................................................................................................6-3Setting Global Timing Constraints on Sub-Blocks.............................................................Resets ..................................................................................................................................... 6-4Clocks .................................................................................................................................... 6-4Setting Clock Constraints .................................................................................................4Setting Clock Skew............................................................................................................ 6-5Multiple Synchronous Clocks per Block ............................................................................Setting the Input Arrival Time............................................................................................Setting Output Required Times: .......................................................................................Setting Multicycle Path Constraints: .................................................................................Known Problem with Setting Multicycle Paths...................................................................False Path Constraints:.....................................................................................................-12Constraining Purely Combinational Designs.....................................................................Constraining Mixed Synchronous and Asynchronous Designs.........................................

The Constraints FlowTab.....................................................................................................16The Clock Constraints PowerTab .....................................................................................The Input Signal PowerTab ..............................................................................................The Output Signal PowerTab ...........................................................................................The Internal Signal PowerTab ..........................................................................................The Module PowerTab .....................................................................................................The Path Constraints PowerTab ......................................................................................The Report Constraints PowerTab....................................................................................

Chapter 7Optimizing Your Design ..........................................................................................................

Understanding Global Area Optimization ............................................................................How LeonardoSpectrum Optimizes a Design ...................................................................

Understanding Extended Optimization Effort ......................................................................Managing Hierarchy ............................................................................................................... 7-5

Design Partitioning Hints...................................................................................................-6Implementing Hierarchy in VHDL......................................................................................Flattening Hierarchy ........................................................................................................... 7-7Protecting Hierarchy ........................................................................................................... 7-8

The Optimize FlowTab.........................................................................................................7-9Advanced Optimization PowerTab....................................................................................

LeonardoSpectrum for Altera User’s Manual, v2001.1d v


Table of Contents

... 8-1

........ 8-4..... 8-5.... 8-6... 8-7

.. 9-1

..... 9

. 9-2..... 9-4..

0-1

. 10-2

.. 10-

.. 10-2.. 10-2.. 10... 10-... 10-3.. 10-40-4.. 10-5

10-5. 10-510-5

. 10-510-6.. 10-6.. 10-6.. 10-710-7. 10-7

Chapter 8Saving Your Design.................................................................................................................

The Output FlowTab ............................................................................................................ 8-2The EDIF Out PowerTab ..................................................................................................The SDF Out PowerTab ..................................................................................................The Verilog Out PowerTab ...............................................................................................The VHDL Out PowerTab .................................................................................................

Chapter 9Performing Physical Layout....................................................................................................

The Place & Route Tab........................................................................................................-2The Altera MAX+PLUS II Place & Route Tab....................................................................The Altera Quartus PowerTab .........................................................................................Quartus Integration .............................................................................................................. 9-5

Chapter 10Altera FLEX, ACEX, and MAX Synthesis ............................................................................ 1

The FLEX and ACEX Architecture.......................................................................................Introduction.......................................................................................................................... 10-2Logic Elements (LEs) ........................................................................................................2Input/Output Elements (IOEs) ...........................................................................................Embedded Array Blocks (EABs).......................................................................................

The MAX Architecture .........................................................................................................-2The Altera Synthesis Flow...................................................................................................3

The QuickSetup Flow .......................................................................................................The Advanced (Level 3) Synthesis Flow...........................................................................

Summary of FLEX, ACEX, and MAX Specific Control Variables ....................................... 1User Options that Control Mapping......................................................................................

Device .................................................................................................................................. 10-5Speed.................................................................................................................................... 10-5Map IO Registers (FLEX 10K and ACEX 1K) ...................................................................Max Fanin (MAX only) ......................................................................................................Max PT (MAX only) ...........................................................................................................Max Fanout (FLEX and ACEX).........................................................................................Lock LCells (FLEX and ACEX) .........................................................................................Map Cascades (FLEX and ACEX) ....................................................................................Use the Carry/Sum Primitive .............................................................................................Exclude Gates ..................................................................................................................... 10-6

Assigning Device Pin Numbers to Primary I/Os ...................................................................Mapping to the Logic Element (LE) in FLEX Devices..........................................................

Fanin Limited Optimization................................................................................................

LeonardoSpectrum for Altera User’s Manual, v2001.1dvi


Table of Contents

. 10-810-10. 10-10-110-13

10-160-16

0-2210-281

. 10-29. 10-3010-3010-32

. 10-3310-34

. 10-3610-37

11-1

11-1.... 11-2.. 11-3.. 11-411-411-5. 11-6.. 11-7.. 11-8.. 11-911-10. 11-1111-1211-13

. A-1

.... A-2

Lookup Table (LUT) Mapping ...........................................................................................Managing the Inclusion of Modules .....................................................................................

Understanding LeonardoSpectrum Modgen.....................................................................Mapping Combinatorial Logic to Embedded Array Blocks (EABs)................................. 10Implementing a Pipelined Multiplier ................................................................................. 1

Mapping Memory Elements to FLEX Devices ....................................................................Inferring ROMs from the HDL Code ................................................................................ 1Mapping RAMs to the FLEX 10K Architecture ............................................................... 1Generating Simulation Memory Models with Genmem....................................................LPM Instantiation ..............................................................................................................0-29Genmen Verilog Design ...................................................................................................LeonardoSpectrum for Genmem ......................................................................................

Writing the EDIF Output ......................................................................................................Using FLEX Designs as Input ..............................................................................................

EDIF Input ......................................................................................................................... 10-32FLEX 6000/8000 Devices Supported ..................................................................................FLEX 10K Devices Supported .............................................................................................ACEX Devices Supported ...................................................................................................MAX Family Devices Supported .........................................................................................

Chapter 11Altera APEX Synthesis............................................................................................................

APEX 20K/20KE/20KC Family.............................................................................................Mapping Options ..............................................................................................................11-1LeonardoSpectrum APEX 20K/20KE Mapping.................................................................APEX Technology Support ...............................................................................................APEX ESB (Embedded System Block).............................................................................Directing Quartus to Implement a Design Block in PTERM ..............................................Simulation with Pre-Layout Verification (Optional)...........................................................FSM Encoding (binary, gray, random, onehot, twohot, auto) ............................................

APEX 20K Devices Supported.............................................................................................APEX 20KE Devices Supported ..........................................................................................APEX 20KC Devices Supported ..........................................................................................APEX II Devices Supported .................................................................................................Mercury Devices Supported ................................................................................................Excalibur Mips Devices Supported ......................................................................................Excalibur Arm Devices Supported .......................................................................................

Appendix ASynthesisWizard Tutorial........................................................................................................

SynthesisWizard Tour............................................................................................................ A-1Specifying the Technology Library - Step 1 of 4 ...............................................................

LeonardoSpectrum for Altera User’s Manual, v2001.1d vii


Table of Contents

.... A-

.... A-5... A-7

Input Files, Step 2 of 4......................................................................................................3Global Constraints, Step 3 of 4.........................................................................................Output File, Step 4 of 4......................................................................................................Run........................................................................................................................................ A-8

LeonardoSpectrum for Altera User’s Manual, v2001.1dviii

Table of Contents

.... 1-4.... 1-5

..... 1-7

.... 2-5... 2-6..... 2-6.. 2-7.... 3-3...... 3-6.. 3-10.. 3-12. 3-13.. 3-20... 3-21. 3-24.. 3-253-26.. 3-27. 3-29... 3-30.. 3-31.... 4-5.. 4-6.... 5-85-10. 5-11.. 5-12... 6-3..... 6-4.... 6-5..... 6... 6-6.... 6-7..... 6-7... 6-9.. 6-1.... 6-12.. 6-136-136-146-14.. 6-15. 6-16

LIST OF FIGURES

Figure 1-1. Quick Setup Data Flow Diagram ......................................................................Figure 1-2. Quick Setup Options ........................................................................................Figure 1-3. Setting the Place and Route Tools Path Location ............................................Figure 2-1. Example of Design Partitioning ........................................................................Figure 2-2. Example of Separating Timing Blocks ..............................................................Figure 2-3. Registers Placed at the End of a Block ............................................................Figure 2-4. A Typical Working Directory Structure .............................................................Figure 3-1. Relationship between Commands, Variables, and Attributes...........................Figure 3-2. Setting the Place and Route Executable Pathnames .......................................Figure 3-3. Main Window at Startup ...................................................................................Figure 3-4. Main Window ...................................................................................................Figure 3-5. Part of Main Window Header ............................................................................Figure 3-6. Example of a Simple Report .............................................................................Figure 3-7. Part of Source Code with Popup Message .......................................................Figure 3-8. Example HDLInventor Template and Bookmarks ............................................Figure 3-9. HDL Source Code Example..............................................................................Figure 3-10. HDL Code with Editor Line Number Example ................................................Figure 3-11. Setting Options for the Main Session ............................................................Figure 3-12. Design Browser View Options. .......................................................................Figure 3-13. Setting the Place and Route Tools Path Location ..........................................Figure 3-14. The Variable Editor........................................................................................Figure 4-1. Technology Settings - FPGA ............................................................................Figure 4-2. Advanced Setting PowerTab for Altera FLEX6K .............................................Figure 5-1. The Input FlowTab............................................................................................Figure 5-2. The VHDL Input PowerTab Options..................................................................Figure 5-3. The Verilog Input PowerTab Options................................................................Figure 5-4. EDIF Input PowerTab Options .........................................................................Figure 6-1. Setting Global Timing Constraints on Sub-Blocks............................................Figure 6-2. Clock Constraints .............................................................................................Figure 6-3. Clock Network ..................................................................................................Figure 6-4. Clock Skew ......................................................................................................-6Figure 6-5. Clock Skew Timing ...........................................................................................Figure 6-6. Multiple Synchronous Clocks ...........................................................................Figure 6-7. Synchronous Clocks.........................................................................................Figure 6-8. Input Arrival Time .............................................................................................Figure 6-9. Output Time ......................................................................................................0Figure 6-10. False Path Constraints...................................................................................Figure 6-11. Combinational Design.....................................................................................Figure 6-12. Constraining Designs with Mixed Signals (1 of 3)...........................................Figure 6-13. Constraining Designs with Mixed Signals (2 of 3)...........................................Figure 6-14. Constraining Designs with Mixed Signals (3 of 3)...........................................Figure 6-15. Constraining Sub-Blocks ................................................................................Figure 6-16. The Constraints FlowTab - Global Constraint Options ...................................

LeonardoSpectrum for Altera User’s Manual, v2001.1dix

LIST OF FIGURES [continued]

Table of Contents

.. 6-18.. 6-19.. 6-20.. 6-22.. 6-24.. 6-26... 6-28.. 6-30... 7-3... 7-5... 7-9. 7-12.... 8-2.... 8-4.... 8-5... 8-7. 9-2.... 9-4.. 10-9.. 10-. 11-3. A-2.. A-3. A-4... A-5.. A-6... A-7... A-8A-8

Figure 6-17. The Clock Constraints PowerTab Options......................................................Figure 6-18. Clock Waveform Diagram ..............................................................................Figure 6-19. The Input Signal Constraints PowerTab Options ...........................................Figure 6-20. The Output Signal Constraints PowerTab Options.........................................Figure 6-21. The Internal Signal Constraints PowerTab Options .......................................Figure 6-22. The Module PowerTab Options......................................................................Figure 6-23. The Path Constraints PowerTab Options .......................................................Figure 6-24. The Report Constraints PowerTab Options ....................................................Figure 7-1. A Binary Decision Diagram...............................................................................Figure 7-2. Setting Extended Optimization Effort................................................................Figure 7-3. The Optimize FlowTab Options ........................................................................Figure 7-4. Advanced Optimization PowerTab Options ......................................................Figure 8-1. The Output FlowTab Options ...........................................................................Figure 8-2. EDIF Out PowerTab Options............................................................................Figure 8-3. SDF Out PowerTab Options .............................................................................Figure 8-4. VHDL Out PowerTab Options ..........................................................................Figure 9-1. Altera MAX+PLUSII Physical Tab Options .......................................................Figure 9-2. Altera Quartus PowerTab Options ....................................................................Figure 10-1. Mapped Circuit Schematic..............................................................................Figure 10-2. Output Netlist ..................................................................................................9Figure 11-1. Writing Power/Ground as Undriven Nets ........................................................Figure A-1. Specifying the Technology Library, Step 1of 4 ................................................Figure A-2. Opening the Input Files, Step 2 of 4 ................................................................Figure A-3. Setting the Working Directory ..........................................................................Figure A-4. Set Input File(s) ...............................................................................................Figure A-5. Global Clock, Step 3 of 4.................................................................................Figure A-6. Output File, Step 4 of 4 ....................................................................................Figure A-7. Set Output File ................................................................................................Figure A-8. Screen A-8. Warning - Overwriting Output File.................................................

LeonardoSpectrum for Altera User’s Manual, v2001.1dx

Table of Contents

... 1-11

. 3-22

. 4-3

. 10-110-14

LIST OF TABLES

Table 1-1. System Memory Requirements .........................................................................Table 3-1. Builtin HDL Templates .......................................................................................Table 4-1. LUT Mapping Options for Altera FLEX .............................................................Table 10-1. Modgen Options ..............................................................................................Table 10-2. Effect of Pipelining on Quality of Results ....................................................... 1

LeonardoSpectrum for Altera User’s Manual, v2001.1d xi

LIST OF TABLES [continued]

Table of Contents

LeonardoSpectrum for Altera User’s Manual, v2001.1dxii

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Chapter 1Introducing LeonardoSpectrum

LeonardoSpectrum for Altera is a suite of high level design tools for Complex ProgrammaLogic Devices (CPLDs). LeonardoSpectrum for Altera offers design capture via VHDL andVerilog entry, register-transfer-level logic synthesis, constraint-based optimization, timinganalysis, and encapsulated place-and-route.

The graphical user interface (GUI) is supported on Windows 95/98/2000/NT; and UNIX HPand Sun. The GUI provides the following features:

• Same look and feel for all platforms

• Windows editing, dragging, and dropping features are available

• SynthesisWizard, Quick Setup, and FlowTabs guide you through the design proces

• Embedded, interactive, and filtered windows extend task information

• Quick file changes with right mouse button (RMB)

• Popups and pulldowns are prevalent

• Pertinent information is parsed for quick reading

• Clickable buttons assign tasks

In addition, if you have the LeonardoInsight option, you can cross probe a schematic thatgenerated in Renoir with a schematic generated in LeonardoSpectrum. (2) You can view twhole critical path in one window, even if the path traverses multiple levels of hierarchy. (3You can view fanout and fanin cones of logic from a selected net or instance. (4) When thcritical path viewer is in query mode, detailed timing popup information is displayed for theobjects in the critical path. (5) Query mode provides general popup information for everyschematic. (6) The schematic viewer search utility allows you to search for instance, net, aport; and lists these items for you in a window. (7) The schematic viewer can cross probeRenoir.

LeonardoSpectrum for Altera User’s Manual, v2001.1d 1-1

Introducing LeonardoSpectrum

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HDL Languages

By default you are provided with either the Verilog or VHDL language. You can add eitherVerilog or VHDL as a second language.

Save and Restore Project

Entire design projects can be restored on the same or a different machine. Before you quidesign, you are prompted to save the entire project. Later you can go back and bring up thdiscontinued project; the restored project is complete with your specifications and windowenvironment.

Project Saves and Restores:

• File locations for input files, output files, and current working directory

• Present design information

• Applied constraints, directives, and attributes

• All tab selection information: source technology, designation technology, file type,hierarchy preservation, global constraints, optimization passes, FSM encoding.

HDLInventor

The HDLInventor is an interactive source code editor in LeonardoSpectrum. You can douclick on errors, warnings, and information (red, green, and blue dots) in the information winor click on the name of your input file to bring up the HDLInventor. The HDLInventorinteractively highlights syntax and synthesis construct errors found during synthesis. Youmake your edits in this window and, if required, insert template(s) of HDL code that youfrequently use.

Tcl Script Sourcing

LeonardoSpectrum provides three ways to source your Tcl script. After you create a Tcl scin a standard text editor, you can source your script from LeonardoSpectrum as follows:

• GUI Menu BarFile -> Run Script

• Batch mode from a shell using the syntax:

% spectrum -file <my_Tcl_script>

LeonardoSpectrum for Altera User’s Manual, v2001.1d1-2

Introducing LeonardoSpectrum Using the Synthesis Wizard

ugh

Refer the topicBatch Mode Operationsin theLeonardoSpectrum Reference Manualforcomplete syntx.

Using the Synthesis WizardYou can invoke the Synthisis wizard by clicking on the Wizard’s Hat icon as shown in thefigure below. The SynthesisWizard is designed for the first time users by walking them throthe synthesis flow in four easy steps.

Refer to theSynthesisWizard Tutorialstarting on pageA-1 for more detailed instruction.

Click to invoke the Synthesis Wizard


Understanding the Quick Setup Flow Introducing LeonardoSpectrum

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Understanding the Quick Setup FlowQuick Setup is the default synthesis flow presented to users when LeonardoSpectrum is finvoked. Quick Setup can be used by advanced as well as beginning users as a simple andmeans to achieve good first-pass synthesis results. You specify the target technology, opeinput design files, optionally set the target clock frequency, and verify the name and locatiothe generated output netlist. You click theRun Flow button to run the entire synthesis flow.Optionally, you can have Quick Setup automatically invoke the vendor place and route toogenerate a set of vendor place and route files.

Figure 1-1is a simplified illustration of the data flow in a Quick Setup synthesis run.

Figure 1-1. Quick Setup Data Flow Diagram

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Introducing LeonardoSpectrum Understanding the Quick Setup Flow

The Quick Setup Task Flow

As shown inFigure 1-2, setting up a Quick Setup Flow is fast and straight forward.

Figure 1-2. Quick Setup Options

1. Set the Technology

2. Set Working Directory

4. Set theClock

5. Set the Effort

7. Activate Place and Route

6. Verify the Nameand Destination

8. “Click”

3. Open Design Files

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Understanding the Quick Setup Flow Introducing LeonardoSpectrum

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Selecting a Technology

When you select an FPGA/CPLD technology, LeonardoSpectrum selects a Device, SpeeGrade, and Wire Load table by default. You may override these selections by moving to thTechnology FlowTab and scrolling through the choices in each dialog box.

Setting the Working Directory

The working directory is the directory where LeonardoSpectrum places all generated outpfiles. These files include the output files from the synthesis process as well as the output ffrom the integrated place and route tools. Since the generated files are many in number, igood practice to separate your design source files and Tcl scripts into a separate sub-direAs shown inFigure 1-1, the input source files are kept in a sub-directory namedsrc . If, forexample, your first synthesis run generates the “fastest” possible circuit, you may want toone or more optional runs to evaluate the tradeoffs between speed and area. You can simcopy thesrc sub-directory into a new working directory named “smallest”, for example, andthe new generated files for the next run will be placed there.

Opening the Design Files

LeonardoSpectrum does not read pre-compiled HDL designs from disk. Instead, the sourcare read directly into memory where LeonardoSpectrum builds an EDIF-like in-memorydatabase. The design source files do not have to reside in the specified working directory.may reside in any location and may even reside in more than one location. You simply clicthe Open files button, navigate to and select a source file, then click Open. The file(s) arein the order in which they will be read. For VHDL source files, order is important. If an openfile is out of place in the list, you may drag the file into the correct position with the mousecursor. The files are read from top to bottom.

Reading Custom VHDL Libraries and Packages

Many standard VHDL libraries and packages are built into LeonardoSpectrum and don’t hto be specified in the Open file list. If your design references custom libraries and packagethen you must Open these package source files for reading before your design files are reamethods for doing this are fully discussed in theLeonardoSpectrum HDL Synthesis Manualstarting on page4-4.

Setting the Clock Frequency

This is an optional setting. If you don’t specify a clock frequency, LeonardoSpectrum willoptimize the design to the smallest possible area. If you specify a clock frequency, the smarea design will be optimized, then LeonardoSpectrum will re-optimize the hardware in thecritical paths to try to match or slightly exceed your specified clock frequency. This critical poptimization effort will increase the circuit area, but only in the places necessary to speed udesign.


Introducing LeonardoSpectrum Understanding the Quick Setup Flow

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Setting the Optimization Effort

As shown inFigure 1-2, you can set the optimization effort that LeonardoSpectrum shouldexpend to reach your specified timing constraints. As you move the slider from left to rightLeonardoSpectrum will expend more effort in trying to reach your constraints, often at theexpense of run time.

Verifying the Output File Name and Location

LeonardoSpectrum creates a set of output files. By default, the output netlist name is basethe name of the first file in the Input list. The target pathname is the current working directoand the file type is EDIF (.edf) . You should verify that this output file name, type, and targelocation is acceptable. If not, you can change the information in the Output File dialog box.generated file set includes a technology-mapped structural netlist and a vendor-specificconstraint file. Other files may also be generated, depending on the target technology.

Activating Integrated Place and Route

This is an automated feature for running the selected vendor place and route tools. In ordework, you must first verify that the proper path location is set to the Vendor’s executabledirectory. As shown inFigure 1-3, you can selectTools > Options...from theLeonardoSpectrum Main pulldown menu and click on thePlace & Route Pathstab. The figureshows the typical path location for Altera Quartus tools. (The actual name of the environmvariable may differ between platforms.)

Figure 1-3. Setting the Place and Route Tools Path Location

Running the Flow

You click Run Flow to start the synthesis process and generate a technology-mapped strunetlist. As shown inFigure 1-1, the opened input files are read by LeonardoSpectrum and anmemory EDIF style database is created. This is called the RTL database and the design iscomposed of generic gates and non-mapped (black box) operators. As shown inFigure 1-1, youmay view this in-memory design with an optional design browser and schematic viewer ca

Tools > Options...


Applying Constraints with FlowTabs Introducing LeonardoSpectrum

est

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LeonardoInsight. Next, the in-memory design is mapped to the specified technology andglobally optimized for area. Extended Optimization routines are run, if specified, and the bresults for each module are saved. If a timing constraint is not met at this point, additionalcritical path optimizations are run to try to meet the constraints. As shown inFigure 1-1, theresults are kept in a second in-memory technology-mapped design database. The outputand support files are then automatically generated and written to the working directory. IfAutomated Place and Routeis specified, the P&R tools are run next and the generated P&file set is placed in the working directory.

Applying Constraints with FlowTabsThe FlowTabs are designed for the more advanced users who need access to all the embpower of LeonardoSpectrum. As shown in the figure below, you bring up the FlowTabs byclicking on the “A” icon.

The basic method for using FlowTabs is to first use the Input FlowTab toReadyour design intomemory, then you use the remaining FlowTabs to enter andApply constraints to the in-memorydesign. Finally, you press theRun Flow button to optimize the design and write an outputnetlist. The details for applying constraints with each FlowTab are found in the followingchapters:

• The Technology FlowTab -Loading a Technology Libraryon page4-1.

• The Input FlowTab -Reading Your Designon page5-1.

• The Constraints FlowTab -Setting Timing Constraintson page6-1.

• The Optimize FlowTab -Optimizing Your Designon page7-1.

• The Output FlowTab -Saving Your Designon page8-1.

• The Physical FlowTab -Performing Physical Layouton page9-1.

FlowTabs

Click to Display FlowTabs


Introducing LeonardoSpectrum Technology-Specific Synthesis Options

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Technology-Specific Synthesis OptionsThe options and constraints that you apply to your design may depend on which technololibrary you are using. The more you understand about the target technology, the better yobe able to guide LeonardoSpectrum toward achieving an optimum result. The details for Aspecific technologies can be found in the following chapters:

• UndertandingAltera FLEX Synthesisstarting on page10-1.

• UndertandingAltera MAX Synthesisstarting on page11-1.

• UndertandingAltera APEX Synthesisstarting on page11-1.

Documentation Available Online

Context-Sensitive Help

LeonardoSpectrum has context-sensitive help throughout the GUI. While the FlowTabs aractive, you can pressF1 to open a context-sensitive help or press the help button. The GUIwindow must be selected first to be in current focus when usingF1.

Menu Bar Help

Online help is available in Windows 95 format. You can view frames of help text and grapby moving your cursor to the Main window pulldown menu and selecting:

Help > Help Contents...

You can expand the Table of Contents and select from a variety of topics.

Product Manuals Online

All LeonardoSpectrum product manuals are available for on-screen viewing with the AdobAcrobat Reader after LeonardoSpectrum and the Adobe Acrobat Reader are installed fromLeonardoSpectrum CD-ROM.

Note

The GUI window must be selected first to be in current focus when usingF1.Also, F1 does not work on UNIX.


PC Hardware and Software Requirements Introducing LeonardoSpectrum

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You can view the manuals by selecting the following pulldown menu from the Main menu:

Help > Open Manuals Bookcase

The PDF manuals and the Manuals Bookcase also contain HyperText links that guide yourelated documentation on the Web, provided your web browser is operational and properlconfigured.

PC Hardware and SoftwareRequirements

The following are hardware requirements for LeonardoSpectrum for Altera.

Type of PC

An IBM compatible PC with a Pentium or Pentium-Pro CPU is recommended. A 486 PC isacceptable, but may run slowly.

Operating System

LeonardoSpectrum for Altera requires Windows NT/95/98/2000.

Disk Space

LeonardoSpectrum requires approximately 70 MBytes of disk space for programs and datfiles. Plan for an additional 50 MBytes for your files.


Introducing LeonardoSpectrum PC Hardware and Software Requirements

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System Memory (RAM)

System Memory Requirementsshows the recommended memory for proper operation ofExemplar synthesis tools. The actual requirements may vary; this depends on your designcoding style.

Table 1-1. System Memory Requirements

Design Size

Number of Gates Look Up Tables Flip-Flops RAM, MBytes

up to 15,000 up to 1100 500 64

15,000 to 75,000 1100 to 5000 3000 128

75,000 and up 5000 and up 5000 256

Note

A system running with less than the recommended memory may slowdownto memory swapping.


PC Hardware and Software Requirements Introducing LeonardoSpectrum


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2-2-2-5

2-7

Chapter 2Preparing for Synthesis

You can ensure a smooth synthesis process by first following the templates and recommecoding practices as set forth in theLeonardoSpectrum HDL Synthesis Manual. A summary ofthese recommendations are repeated in this section for convenience.

Preparing Your Design for Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Checking Your RTL Coding Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Rules for Partitioning Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Creating a Simple Working Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


Preparing Your Design for Synthesis Preparing for Synthesis

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Preparing Your Design for Synthesis

Checking Your RTL Coding Style

Synthesizing State Machines

LeonardoSpectrum encodes state machines during the synthesis process. After a designbeen encoded during synthesis, the design cannot be re-encoded later in optimization. Adefined VHDL or Verilog coding style must be followed to allow LeonardoSpectrum to identhe state machine.

RecommendationState machines should be isolated into separate hierarchical blocks. Thspeeds optimization performance and allows for easy modifications to state machine enco

Supported State Machine Styles

Binary - Generates state machines with the fewest possible flip-flops. Binary state machineuseful for area critical designs when timing is not an issue.

Gray - Generates state machines where only one flip-flop changes during each transition.encoded state machines are usually without glitches.

Random - Generates state machines using random state encoding. Random state machinencoding should only be used when all other implementations are not achieving the desireresults. Random state encoding is not recommended.

OneHot - Generates state machines containing one flip-flop for each state. One hot statemachines provide the best performance and shortest clock to out delays. One-hotimplementations are larger than binary.

Twohot - Twohot encoding sets two flip flops high for each state. The twohot encoding requmore flip flops than binary and fewer flip flops than onehot. Twohot encoding may bebeneficial to large FSMs where onehot uses too many flip flops, and binary requires too mdecode logic. Refer also to Chapter 2 in theLeonardoSpectrum HDL Synthesis Manual.

Auto - For auto encoding, LeonardoSpectrum varies the encoding based on bit width. Morspecifically, enumerated types with fewer elements than global integerlower_enum_break areencoded as binary; larger enumerated types are encoded as onehot. Values larger than gintegerupper_enum_break are encoded as binary. Auto encoding allows LeonardoSpectrumassign encoding on a case-by-case basis.

Setting FSM Encoding with VHDL Attributes

To set the encoding for a particular state machine, insert the following statements into youcode.


Preparing for Synthesis Preparing Your Design for Synthesis

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• Declare thetype_encoding_style attribute. Typeencoding_style is: (BINARY,ONEHOT, TWOHOT, GRAY, RANDOM, AUTO); attribute TYPE_ENCODING_STYLE: ONEHOT;

• Declare your state machine enumeration type. Typemy_state_type is:(s0,s1,s2,s3,s4);

• Set thetype_encoding_style of the state.

Type: attribute: TYPE_ENCODING_STYLE of my_state_type is ONEHOT;

Setting FSM Encoding with Verilog Pragmas

To set the encoding for a state machine in Verilog, you should insert the following commetext into your Verilog Model above the state machine model

parameter [3:0] // pragma enum state_parameters onehotidle = 4’b0001,halt = 4’b0010,run = 4’b0100,stop = 4’b1000;reg[3:0] /*pragma enum state_parameters */state;

Note: In the first line of the above code example, the state machine encoding specified isonehot . This is an optional specification that could also be set tobinary , gray , andrandom . Iftheenum pragma is specified and not set to a partition, indicate FSM encoding. The encodidefault isonehot and can be changed with theset encoding command.

Setting FSM Encoding using the Encoding Variable

Alternatively, theencoding variable is used to set state machine encoding. Once this variabset with the Variable Editor (see the Tools pulldown memu), all state machines employ thespecified encoding until anotherset encoding command issued. Set this variable prior toreading in VHDL or Verilog code

VHDL Example

set encoding onehotread uart_control_sm.vhdlset encoding binaryread interface_control_sm.vhdl

Note

VHDL Attributes and Verilog pragmas override the encoding variable



Verilog Example

set encoding binaryread -format verilog control.v

Arguments to the Encoding Variable

Arguments Description

binary Sets state machine encoding to binary

onehot Sets state machine encoding to onehot

twohot Sets state machine encoding to twohot

gray Sets state machine encoding to grey

random Sets state machine encoding to random

auto Sets state machine encoding based onbit width.


Preparing for Synthesis Preparing Your Design for Synthesis

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Rules for Partitioning Your Design

For large designs and team designs, partitioning the design into a hierarchy and maintaininhierarchy throughout the synthesis process has many advantages. The following arerecommended steps when you partition a design into leaf blocks:

1. You should place all logic into hierarchical blocks;glue logic does not exist at any levelthat is not part of a hierarchical block. When you follow this convention, it helps ensthat you receive the correct results from the LeonardoSpectrum timing analysisenvironment.

Figure 2-1. Example of Design Partitioning

2. Gate counts in leaf blocks should be between 10K and 50K gates. Optimizations caperformed on blocks much larger provided the sub-hierarchy falls within this guidel

3. In general, you should limit clocks to one per block. Multi-clock designs are supporhowever, setting constraints becomes more complex.

4. You should group similar logic together, i.e., state machines, data path logic, decodlogic, ROMs. You should pay close attention to blocks that may contain special aredelay optimizations. For example, if you know a particular block is going to containcritical path, you should eliminate any non-critical logic from that block.

5. You should place state machines into separate blocks of hierarchy to speed optimizand provide more control over encoding.

6. As shown inFigure 2-2, you should separate timing critical blocks from non-timingcritical blocks. LeonardoSpectrum performs area and timing optimizations separateBy separating timing critical logic into one block, you can perform aggressive area

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optimizations on a greater percentage of the design, and create a smaller circuit thmeets timing.

Figure 2-2. Example of Separating Timing Blocks

7. As shown inFigure 2-3, you should place registers at the boundaries of hierarchicalblocks. There are two barriers that constrain optimization, hierarchical boundariesregisters. When you are designing with hierarchy, you should place registers eitherfront-end or back-end of the hierarchical boundaries, but not at both front and backTwo barriers are combined into a single barrier. (This minimizes the impact to theoverall results when performing bottom-up optimizations.) If this design practice isfollowed, then preserving hierarchy in a design has no impact on optimization resuand allows for faster CPU run times.

Figure 2-3. Registers Placed at the End of a Block

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R egist ersplaced atthe end ofa bl ock


Preparing for Synthesis Creating a Simple Working Directory Structure

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Creating a Simple Working DirectoryStructure

Theworking directoryis the directory where LeonardoSpectrum places all generated outpufiles. These files include the output files from the synthesis process as well as the output ffrom the integrated place and route tools.Figure 2-4shows a typical working directory structurefor small to medium sized designs.

Figure 2-4. A Typical Working Directory Structure

Only a few generated files are shown in the illustration. Since the generated files can be manumber, it is a good practice to separate your design source files and Tcl scripts into a sepsub-directory. As shown inFigure 2-4, the input source files are kept in a sub-directory name


Creating a Simple Working Directory Structure Preparing for Synthesis

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src . If, for example, your first synthesis run generates the “fastest” possible circuit, you mawant to do one or more optional runs to evaluate the tradeoffs between speed and area. Ysimply copy thesrc sub-directory into a new working directory named “smallest”, for exampand the new generated files for the next run will be placed there.


ork.

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3-4

3-63-63-7

3-9

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20

-21

-21-2123-2324

Chapter 3Understanding the User Interface

This chapter will help you understand how the basic mechanisms of LeonardoSpectrum wIn addition, the elements of the Main window of the Graphical User Interface (GUI) areexplained.

Understanding the Synthesis Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Standard Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .LeonardoSpectrum Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Setting Tcl Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Setting Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Methods for Using Commands With a Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Understanding the Tool Setup Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Startup Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Saving and Restoring a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Setting Aliases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Invoking the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .The leonardo Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The Main Window at Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Tip of the Day . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-SynthesisWizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

The Major Elements of the Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

The Main Window Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

The Information Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-

The HDLInventor Source Code Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

The HDLInventor Source Code Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Editing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-Editing Options - Transcript and Filtered Transcript . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3More Editing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-


Understanding the User Interface

3-27-2729-29-30

-31

Changing the Default Session Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Main Session Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Browser View Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-Schematic Viewer Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Using the Variable Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3


Understanding the User Interface Understanding the Synthesis Controls

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Understanding the Synthesis ControlsThe LeonardoSpectrum Graphical User Interface (GUI) is based on the Tcl language. Wheclick on an item in the GUI, you are executing a Tclcommand, changing the value of a Tclvariable, or setting anattributeon a database object. As shown inFigure 3-1, Standard TclCommands provide a foundation for the command structure. LeonardoSpectrum Tcl commextensions proved the major source of synthesis processing power. This power is directedsetting Tcl variables. Global constraints and directives are communicated to LeonardoSpethrough these variables. A finer level of control is execised when you set attributes on in-memory design objects. In general, a message communicated to LeonardoSpectrum throattribute overrides the global messge communicated by setting a variable.

Figure 3-1. Relationship between Commands, Variables, and Attributes

Standard Tcl Commands

LeonardoSpectrum accepts all standard commands of the Tcl language. Tcl supports comthat include: variable assignment, handling of lists and arrays, sorting, string manipulationarithmetic operations, (if/case/foreach/while) statements, and procedures.

Sets GlobalConstraints/Directives

Provides aFoundation

Overrides a Variableon a Design Object

Adds the Powerof Synthesis


Understanding the Synthesis Controls Understanding the User Interface

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LeonardoSpectrum Tcl Commands

Exemplar Logic has added a number of command extensions to the Tcl language to handsupport the synthesis process. These commands are “built-in” and are executed the samestandard Tcl commands.

Setting Tcl Variables

You can set and unset variables with the Variable Editor from the Tools pulldown menu.Global constraints and directives are communicated by the setting of variables and you cadirect the behavior of LeonardoSpectrum by changing the value of these varaibles.

Setting Attributes

An attribute is information that is attached to (owned by) an object in the LeonardoSpectrumemory design database. Attributes allow users to fine tune the synthesis process. Attributake precedence over variables.

An attribute has a name, a type, a value, and an owner. An attribute’s value typically descricharacteristic about the design object. Many times the information is used tooverridea globalconstraint that is applied to the design as a whole by setting a Tcl variable.

The concept of an attribute in an HDL language is the same. The attribute is a name/valuethat is associated with, (“attached to”, “set on”, or “owned by”) a design object in the designVHDL, the attribute construct may be used to associated a design object with an attributvalue and in Verilog, a//exemplar attribute directive may be use. If these attributes aredeclared in the source files, the HDL attributes are converted to attributes in the in-memordatabase and many time are translated as EDIF properties during an EDIF netlisting oper

Methods for Using Commands With a Tcl Script

After you create a Tcl script with a standard text editor, you can source your Tcl script fromLeonardoSpectrum as follows:

• The GUI Menu Bar File -> Run Script

• The Shell Command Line with a Path to LeonardoSpectrum

Another common method of generating a Tcl script is to manually walk through a synthesisusing the LeonardoSpectrum GUI. As part of the output, LeonardoSpectrum generates a hfile (.his file). You can also save and use afilteredversion of this file which is a version with theoutput comments removed. This is a valid Tcl script and can be used as a driver to repeatsynthesis run automically on the next run. Typically, a user first edits a filtered transcript filadd aclean_all command as the first line to initialize LeonardoSpectrum. It is also commo


Understanding the User Interface Understanding the Synthesis Controls

the

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for a user to add “puts” commands throughtout the script that send progress messages toLeonardoSpectrum Information Widow as the script executes.

GUI Menu Bar File -> Run Script

On the menu bar click onFile -> Run Script. Type in your Tcl script name or click on thebutton and choose a Tcl script file. Your script file runs in the GUI Information window.

Command Line with Path to LeonardoSpectrum

Bring up your PC or UNIX window. In the LeonardoSpectrum install area, locate where$EXEMPLAR points to the location of the software. Type the appropriate argument to souyour Tcl script:

UNIX : $EXEMPLVAR/bin/spectrum -file <my_tcl_script>

PC DVOS: $EXEMPLAR/bin/win32/spectrum -file <my_tcl_script>


Understanding the Tool Setup Environment Understanding the User Interface

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Understanding the Tool SetupEnvironment

Setting the Place and Route Executable Pathnames

Before you can use the automatic place and route features of LeonardoSpectrum Quick SFlowTab, you must set the path to the vendor’s place and route tools executable directoryFigure 3-13illustrates a typical path location for Altera Quartus tools. The name of theenvironment variable may differ between platforms.

Figure 3-2. Setting the Place and Route Executable Pathnames

Startup Files

Theexemplar.ini is the default startup file for LeonardoSpectrum and .by default, it islocated at the pathname$EXEMPLAR/data . You can customize the startup file as useful way tpre-configure LeonardoSpectrum for daily optimizations. Refer to the following example:

exemplar.ini Startup File

# Define common aliases

alias lp list_design -portsalias reportit {report_area; report_delay}

# Set synthesis working directory - Note directory# slashes are UNIX style for all machines including PCs.

set_working_dir "C:/Exemplar/LeoSpec/v1999.1/demo"

Tools > Options...


Understanding the User Interface Understanding the Tool Setup Environment

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# Disable Asynchronous Feedback Loops

set delay_break_loops TRUE

Startup files for UNIX

For a customized startup, you can place theexemplar.ini file in your working directory. Thecommands in the file are automatically executed when LeonardoSpectrum is invoked.

Startup files for Windows

1. Place theexemplar.ini file in a personal or project folder that is not part of theLeonardoSpectrum installation directory structure because all the LeonardoSpectrufiles are deleted and replaced with each new software install.

2. Edit the file$EXEMPLAR/data/exemplar.ini to add the following line to the bottom ofthe file. You must add this line again after each new software install.

Source d:/<pathname to startup file>/exemplar.ini

Saving and Restoring a Project

LeonardoSpectrum has the powerful ability to “checkpoint” a design optimization in progreThe term “checkpoint” refers to the ability to take a snapshot of the state of a project, savethen fully restore that state at a later point in time. The checkpointed state is called aproject.When you save and restore a project, you can avoid redundant runs and increase yourproductivity.

Files Specific to Creating a Project

When you create and save a project, the following new files are added to your workingdirectory. A project consists of the following three files:

.xdb File

The .xdb file is a binary representation of your in-memory design. The XDB format isExemplar Logic’s proprietary format and can only be read by LeonardoSpectrum. If you arLevel 3 user, this file is a “snap shot” of the present state of the synthesized design and caread into memory for future analysis and modification. If you are a Level 2 user, this file issaved when you save the project, but is ignored when you restore the project because the2 flow always re-reads the source files to start the flow.


Understanding the Tool Setup Environment Understanding the User Interface

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.lsp File

The .lsp file stores the GUI settings of your project. This file is an ASCII file. The.lsp filecontains information like input file path, output file path, FlowTab options settings, and windsettings.

.scr File

The .scr file contains several variables that affect the flow of synthesis.

Advantages of Using a Project

There are three main advantages:

1. Power of Check Pointing for Level 3:You can store the design and the designimplementation while you are working on a project. For example, you have optimizeyour design and then decide to quit the tool. If you save the optimized design as a prbefore you quit, then the optimization is not lost. Later, when you restore the projectoptimized design is waiting for you to continue the task with further timing optimizatior generating reports. This checkpoint process proves to be very useful and time sawith large designs.

2. Organizes a design and the synthesis runs in a systematic way:For example, youwant to try your design implementation on two different devices (parts) for your AlteFLEX 6000 technology. Device 1 is EPF6016QC208 and Device 2 is EPF6016QC2In addition, you want to analyze the trade-off between report area and report delayeach of the Altera FLEX 6000 devices. Now you try your design on Device 1 andDevice 2 and then save each as a project:

a. Device 1 - save as project:high_speed .

b. Device 2 - save as project:low_cost .

c. Later, during your team presentation, for example, you can quickly open thehigh_speed.lsp andlow_cost.lsp projects. You then click the Report FlowTabto review the reports for area and delay for the two Altera FLEX 6000 devices.

3. Portable: take your project with you from platform to platform . For example, if youare working on a module on a PC, and would like to continue the task on a UNIXworkstation, then you can!Caution: If you read in your input files, then you mustensure that the files installed at the UNIX workstation are in the same directory strucas the PC.

!Caution

You should avoid editing this file. Editing this file may change the look andfeel of the GUI and also the synthesis run of your design.


Understanding the User Interface Invoking the Graphical User Interface

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Starting a Project

Click File -> for the project related commands.

1. Start a new project and run the flow for this task.

2. Next save this project as:my_new_project.lsp

Note Level 3:You can save a project at any checkpoint during synthesis (for exampafter completing optimization), and then open the project and resume the task at atime.

3. File -> Recent Projects>shows your saved projects. Select your project,my_new_project.lsp from this list; LeonardoSpectrum then loads the project.

Setting Aliases

LeonardoSpectrum allows you to set aliases to rename any LeonardoSpectrum commandexemplar.ini startup file is the most logical place to define commonly used aliases. Forexample:

alias lp list_design -ports

Invoking the Graphical User InterfaceWhen you invoke LeonardoSpectrum with theleonardocommand, the tool comes up with theGraphical User Interface (GUI). When you use thespectrumcommand, the tool comes up witha command line interface and can be driven bybatch mode options.Refer to theLeonardoSpectrum Reference ManualChapter 4 for details.

The leonardo Command

1. When invoking from a Unix shell, type the following:

% $EXEMPLAR/bin/leonardo

2. When invoking from a Windows Command Prompt, type the following:

C:\> leonardo

(Assuming that the PATH variable is set to Exemplar tree ../bin/win32/leonardo.exe

3. Double-click on a Windows Shortcut with a Target set to the following path:


The Main Window at Startup Understanding the User Interface

r

(Exemplar tree).../bin/win32/leonardo.exe

You can customize the leonardo invocation with command switches. Refer to the leonardocommand in Chapter 4 of theLeonardoSpectrum Reference Manual.

The Main Window at StartupAs shown inFigure 3-3, when you invoke LeonardoSpectrum for the first time, the mainwindow is maximized and displays the Tip of the Day.

Figure 3-3. Main Window at Startup

Tip of the Day

The tip of the day is a quick way for new users to get useful information. The tip of the dayopens automatically on the first invocation of LeonardoSpectrum. You can click forwards obackwards to move through the tips.


Understanding the User Interface The Main Window at Startup

. Ifht

SynthesisWizard

The SynthesisWizard consists of four steps that must be completed in the order presentedyou are a first-time user, then the SynthesisWizard is recommended to get you started rigaway. Continue to“SynthesisWizard Tutorial” on page A-1for a description of each step.

The SynthesisWizard is one of three ways to synthesize your design; Quick Setup andFlowTabs are the other two ways.

Note: RMB over the FlowTabs to open this popup:

Allow Docking (rearrange windows and bars as needed)Hide (turn off windows or bars as needed)FlowTabs on left (tabs appear on left side of main window)FlowTabs on top (tabs appear at top of main window, default)Float in Main Window (float FlowTabs in main window)


The Major Elements of the Main Window Understanding the User Interface

The Major Elements of the Main WindowFigure 3-4highlights the features of the main window.

Figure 3-4. Main Window

BannerMenu Bar ToolBarsFlowTabs Information window

Flow Progress PowerTabs Status BarFlowTabs window


Understanding the User Interface The Main Window Header

are

the

The Main Window HeaderFigure 3-5shows a portion of the main window header. The items and icons on the headerdescribed in the following tables:

Figure 3-5. Part of Main Window Header

Clicking the Advanced FlowTab icon and the Quick Setup FlowTab icon toggles betweentwo sets. If you click either of these icons twice, the FlowTabs window closes. Click a thirdtime and the FlowTabs window re-opens.

The choices on theFile pulldown allow you to manage and savefiles.

New (Ctrl+N) File -> Newopens an untitled window for a new file. This windowis for entering your design code.

Open... (Ctrl+O) File -> Open....The Windows Open utility comes up. Filesavailable under Files of type: are:History File (*.his)VHDL Files (*.vhdl;*.vhd;*.hdl)Verilog Files (*.v;*.veri;*.h;*.ver)TCL Files (*.tcl, *.scr)Log Files (*.log)EDIF Files (*.edif;*.edf; *.ed)Report Files (*.sum)HDL Files (*.vhdl; *.vhd; *.hdl; *.v; *.veri; *.h; *.ver)All Files (*.*)

Click for Advanced FlowTabs


The Main Window Header Understanding the User Interface

Save (Ctrl+S) File -> Saveto save any file currently in the Information Window.If this is a new file, you are asked to specify a file name. Saveoverwrites the current active file with new information.

Save As... (Ctrl+A) File -> Save As... to name a new file or rename a file. TheWindows Save As utility opens. You can save as type: HistoryFile (*.his) or All Files (*.*)

Save Command File... Saving the transcripted commands to a *.tcl file can be a goodstarting point to craft a Tcl script. If this is a new file, you will beasked to specify the file name.

Run Script for Tcl File -> Run Script to open Run Script. Refer to theLeonardoSpectrum Reference Manualfor Tcl script information.Click button on Run Script to open the Windows Open utility.Select a Tcl file (*.tcl) or All Files (*.*).

New Project

If you click Yes, the SaveWorkspace As opens withunsaved_project.lsp in theFile name: field.

If you click No, all objectsare cleared from memoryand the system isinitialized.

File -> New Project to add a new project file *.lsp forLeonardoSpectrum. New project defaults to unsaved_project.lspin the File name: field. You are not prompted for a project nameand location. Before starting a new project, a check is made forany unsaved current project. If an unsaved project is found, youare prompted with “Save this workspace before starting a newone?”

Open Project File -> Open Project to bring up the Open utility. Files of type:LeonardoSpectrum Workspaces (Project) (*.lsp) is the default.

Save Project File -> Save Projectto bring up Save Workspace As for Files oftype: LeonardoSpectrum Workspaces (Project) (*.lsp). You canalso write over your current design with new information.

Click to clear memoryand initialize all settings



y

Save Project As File -> Save Project Asto bring up Save Workspace As for Filesof type: LeonardoSpectrum Workspaces (*.lsp). When Save Asopens, the current project name is already selected. You areprompted to confirm project or project file name and location.When you clickOK the entire design is saved to your projectfolder or the default unsaved_project.lsp project folder.Note:v1999.x projects cannot be read by v1998.x unless you set thefollowing variable in v1999.x to v1998.x:xdb_write_version v1998.x

Change WorkingDirectory

File -> Change Working Directory. Use the standard directorynavigator to set up your new Working Directory. The newWorking Directory is saved as part of your design when you doSave or Save As. This working directory is the starting point forall relative pathnames, and will become the default outputdirectory. Specify an absolute (not relative) pathname for yournew working directory. Your current working directory is stilldisplayed on the right side of the status bar.

Recent Files> (notavailable until after firstinvocation)

Path(s) to your recent file(s) after first startup.

Recent Projects> (notavailable until after firstinvocation)

Path(s) to your recent project(s) after first startup.

Exit File -> Exit to exit LeonardoSpectrum. You are prompted toconfirm.

TheEdit menu provides you with a list of Windows editingcommands. The availability of these items depends on the activiton the main window. For example, an active HDLInventor enablesthe editing commands:

Undo (Ctrl+Z) Edit -> Undo to reverse the last action.

Cut (Ctrl+X) Edit -> Cut to remove selected text and place on clipboard.

Copy (Ctrl+C) Edit -> Copy to copy text from clipboard to cursor position.

Paste (Ctrl+V) Edit -> Pasteto paste text from clipboard at cursor position.

Clear (del) Edit -> Clear to delete selected text.

Select All (Ctrl+A) Edit -> SelectAll to select all text.

Find (Ctrl+F) Edit -> Find to find typed text. Search through files for specificdata.



Find Next F3 Edit -> Find Next to find the next occurrence of a word or phrase.

Replace (Ctrl+H) Edit -> Replaceto replace text.

Goto Line Edit -> Goto Line to openGo to line. Enter line number fromdisplayed source code in HDLInventor.

The View pulldown gives you choices to enable or disable thedisplays of:ToolbarStatus BarReport Window

Analysis PulldownThe Analysis pulldown is available when the HDLInventor isactive. Analysis allows you to:Trace to Hierarchy (Cross probe from source code to schematic)Show next (currently unavailable)

The Tools pulldown provides you with the following options:

Design Browser Tools -> Design Browserto display ports, nets, instances,registers, and primitive cells. Refer to theLeonardoInsight UsersManual.

View RTL Schematic(original, unmappeddesign)

Tools -> View RTL Schematic - LeonardoInsight provides youwith a view of your original RTL schematic in the schematicviewer. Refer to theLeonardoInsight Users Manual.Note: Before you can bring up the schematic viewer you musthave an active design.

View Gate-LevelSchematic

Tools -> View Gate-Level Schematic- LeonardoInsight providesyou with a view of your gate level design in the schematic viewer.Refer to theLeonardoInsight Users Manual.Note: Before you can bring up the schematic viewer you musthave an active design.



e

.

Variable Editor Tools -> Variable Editor Refer to page3-31.

Options Tools -> Options... This is you main access to changing the setupsesion defaults for various LeonardoSpectrum windows. See pag3-27for details.

Window pulldown provides you with task bar properties fromWindows to organize and manage several open windows:Arrange AllCascadeTile HorizontalTile VerticalInformation - Read Only (Retrieve Information Window.)

Flows Pulldown Flows pulldown provides you with the following:SynthesisWizard (toggle steps 1 to 4) - Refer toSynthesisWizardTutorial on pageA-1.FlowTabs (toggle between FlowTabs and Command Line)

Help pulldown provides you with:

Help -> Help Contents Opens a series of tabs that are designed around the Windowsproperties. Help has indexes and context-sensitive choices. Helpcan guide you through the entire synthesis process.

Help -> Show ExtendedHelp

This is help text at the top of the SynthesisWizard and FlowTabs

Help -> Purchase currently unavailable

Help -> Tip of the Day Enable or disable Tip of the Day.

Help -> Video Tutorial Open video tutorial.

Help -> View UserManuals

List of available pdf documents.



l
Help -> About Opens a display of the LeonardoSpectrum version number, Leveinformation, and Copyright. Use this information when contactingtechnical support.
Exemplar’s Logo Click on the logo to open your system web browser (for exampleNetscape). The web address is: http://www.exemplar.com

Task Icons The icons can be moved in groups to suit your needs. LMB overan icon to popup a short balloon title. The entire icon title appearsin the status bar.

Show Hide Flow Bar Toggle

A step by step wizard forthe synthesis of yourdesign

Refer to SynthesisWizard in Chapter 12.

Enable Cross Probe Refer to theLeonardoInsight Users Manual.

Design Browser Refer to theLeonardoInsight Users Manual.

View RTL Schematic Refer to theLeonardoInsight Users Manual.

View TechnologySchematic

Refer to theLeonardoInsight Users Manual.

View Critical PathSchematic

Refer to theLeonardoInsight Users Manual.

View the current summaryfile

Opens the review window.



ges.

Interrupt the current run STOP - red, when completed STOP is grayed out.

Editing Icons The editing icons are available when the HDLInventor is active.

Create a new document Same function as File -> New.

Open an existingdocument

Same function as File -> Open.

Save the active document Same function as File -> Save.

Print the active document Print with Windows utilities.

Cut the selection and put iton the clipboard

Same function as Edit -> Cut.

Copy the selection and putit on the clipboard

Same function as Edit -> Copy.

Paste/insert clipboardcontents

Same function as Edit -> Paste.

Undo the last action Same function as Edit -> Undo.

Redo the previous undoneaction

Same function as Edit -> Redo.

Show extended help Show extended help on the SynthesisWizard and FlowTabs pa


The Information Window Understanding the User Interface

ated

The Information WindowThe Information window is used to display the recorded session transcript and any generreports. Green, red, and blue buttons may appear in the left gutter (margin).Greenindicatesinformation,Redindicates an error, andBluesignals a warning. You can double click onbluetobring up the HDLInventor editor for finding and correcting the source of the error.

Figure 3-6. Example of a Simple Report

Pri nt ing t he Contentoft he Inform at ion W indow

Y ou can pr intt hecont entsoft heI nfom ation w indow .Si m ply cl ick t hecur soranyw her ein thew indow ,t hen cl ick t hePrinteri con i n them ain Leonar doSpect rum toolbar .A pr interdi alogbox w i llappeart o hel p you speci fy wherethei nform ation shoul d bepr inted.

1.Check t he f it

2.Check t he t im ing


Understanding the User Interface The HDLInventor Source Code Editor

d,

ted

esor

tellows. For

The HDLInventor Source Code EditorNote: Double click LMB over input file name on Quick Setup or Input FlowTabs to openHDLInventor in the information window.

The HDLInventor is an interactive source code editor. The errors of syntax constructs founduring synthesis are highlighted in distinctive colors. You can easily interpret the color (redgreen, blue) for the type of warning or error. Errors, information, and warnings are annotadirectly to the integrated HDL source code editor, HDLInventor. The source code editor islinked to the transcript in the message and report window. Line numbering identifies the linnumber in the source code. An information message pops up as you move the mouse curover the line number. Refer toFigure 3-7.

Note: Actual line numbers may differ from the examples inFigure 3-7.

Figure 3-7. Part of Source Code with Popup Message

Templates

The HDLInventor includes a list of templates that are predefined RTL templates. You caninstantiate a template directly into your HDL source code. You can also create customtemplates.

Note: LMB over highlighted file in the input window and double click to open HDLInventor.This editor also contains a set of VHDL and Verilog templates that include a macro templalibrary of state machines, counters, ALUs, and technology specific comments. The editor ayou to trace syntax errors directly back to your source code for quick and easy debuggingconvenience,Table 3-1lists the builtin templates.


The HDLInventor Source Code Editor Understanding the User Interface

Table 3-1. Builtin HDL Templates

Template Function

Overall Structure context clauseslibrary units

Architecture Body _architecture_name_entity_name_signal_name

Finite StateMachine

State Machine with Asynch ResetState Machine without Asynch Reset

Full Designs Full Design CounterFull Design flip flopFull Design 3-State Buffer

Statements Case StatementComponent DeclarationComponent Instantiation StatementConcurrent Procedure CallConcurrent Signal AssignmentStatementConditional Signal AssignmentConstant DeclarationEntity DeclarationFor StatementGenerate Statement (for generate)Generate Statement (if generate)If StatementLibrary ClausePackage DeclarationProcedure Call StatementProcess (combinatorial logic)Process (sequential logic)Selected Signal AssignmentStatementSignal DeclarationSignal Assignment StatementSubtypeTypeUSE ClauseWait StatementVariable Declaration StatementVariable Assignment Statement



s:

e

. Use

up:

Editing Options

You can add templates, do edits, and toggle to add or remove bookmarks. Use these step

1. RMB over the HDLInventor to open this popup:

2. Undo, Redo, Cut, Copy, Paste

3. Toggle bookmark

4. Open Report Window

5. View line numbers

6. Insert template> (Refer again to Templates in this section.)

7. Highlight the desired code to apply Windows edit functions.

8. Click line of code for placing bookmark next to line number. Click again to removebookmark. Refer toFigure 3-8.

9. Click View line numbers to toggle line numbers on and off.

10. Click Insert template> to bring up the template list. Click to select and insert list. Thtemplate requires editing. Refer again toTable 3-1.

Editing Options - Transcript and Filtered Transcript

You can toggle to add or remove bookmarks and to turn messages on and off, for examplethese steps:

1. RMB over left margin of either the Transcript or Filtered Transcript to open this pop

2. Toggle Bookmark

3. View Line Numbers

4. Save (Transcript only)

5. Save Filtered Transcript

6. RMB over left margin of the Filtered Transcript to open this popup list:

7. Show Transcript

8. Show Errors



9. Show Warnings

10. Show Information

11. Show Commands

Figure 3-8. Example HDLInventor Template and Bookmarks

More Editing Options

Use these steps to edit your code:

1. Click or double click on a red, green, or blue button. Refer toFigure 3-9.



2. Click to bring up line numbers. Edit source code as needed.

Figure 3-9. HDL Source Code Example

Note: Example lines 449 and 502 inFigure 3-9(“line 449: Warning,...”; line 502: Warning,...”)are highlighted with a blue button. Double click on button 449 with the left mouse button to



on
open the HDLInventor.Figure 3-10shows the lines of code for line number 449. The red buttindicates a warning and the green button indicates information.
Figure 3-10. HDL Code with Editor Line Number Example

Pri nt ing t he Contentoft he HDLInvent orW indow

Y ou can pr intt hecont entsoft heH D LInvent orw i ndow.Si m ply cl ick t hecur soranyw her einthewindow ,t hen cl ick t hePrinteri con i n them ain Leonar doSpect rum toolbar .A pr interdi alogbox w i llappeart o hel p you speci fy wherethewindow inform ation shoul d bepr inted.


Understanding the User Interface Changing the Default Session Settings

Changing the Default Session SettingsYou can change the session settings from theTools > Options...pulldown menu

Main Session Settings

Figure 3-11. Setting Options for the Main Session


Changing the Default Session Settings Understanding the User Interface

not.

ur

lt

ded.

.

Option Description

Run Wizard mode on startup: When you start up, SynthesisWizard doesopen automatically unless you select this boxYou can also set this option on Input File(s).

Automatically save and restore sessionsettings

Settings on all session settings are saved. Yosynthesis setup is saved. Default is selected.

Automatically load previous project(off by default)

When this selection is off, LeonardoSpectrumopens without any project loaded. This defauis identical to File -> Open Project. WhenAutomatically load previous project isselected, LeonardoSpectrum then opens theprevious project, if any.

Automatically save and restore CurrentWorking Directory(on by default)

When you start up LeonardoSpectrum, thecurrent working directory is restored. IfAutomatically save and restore CurrentWorking Directory is off, then a defaultcurrent working directory is available.

Automatically Load Statistics after synthesis: The summary of your synthesis run is loa

Sounds: Music plays when you start up.

Run License Query at startup. Asks if you want to run with Level 1, 2, or 3

Run License Query at startup Disabled if you disableRun license selection next time

Show page help Displays text at top of FlowTabs andPowerTab screens.

Exemplar Variable: Click to open the set EXEMPLAR variablebrowser.

Web Browser Location: UNIX only: Click to open web browserlocation. Invokes your web browser when youclick on a technology logo.


Understanding the User Interface Changing the Default Session Settings

Browser View Options

Figure 3-12. Design Browser View Options.

Schematic Viewer Options

The display options for the schematic viewer are documented in theLeonardoInsight UsersManual.


Changing the Default Session Settings Understanding the User Interface

etup.

Place and Route

Before you can use the automatic place and route features of LeonardoSpectrum Quick SFlowTab, you must set the path to the vendor’s place and route tools executable directoryFigure 3-13illustrates a typical path location for Altera Quartus tools. The name of theenvironment variable may differ between platforms.

Figure 3-13. Setting the Place and Route Tools Path LocationTools > Options...


Understanding the User Interface Using the Variable Editor

Using the Variable EditorYou can change the values of Tcl variable from theTools > Variable Editor... pulldown menu

Figure 3-14. The Variable Editor


Using the Variable Editor Understanding the User Interface

eiables

Option Description

Variable Name: Select from pulldown. These variables are also documented inalphabetical order in the LeonardoSpectrumReference Manual.

Variable Value: Use default FALSE or type in a value.

Variable Type: Use default Boolean or type in a variabletype.

Show Advanced Variables. These are typically uncommonvariables.

When Show Advanced Variables is selected, theadvanced variables appear in the Variable Name:pulldown. For example:apex_wysiwyg_support is an advancedvariable.

Note: The Variable editor allows you to select and add variables without typing. Refer to thLeonardoSpectrum Reference Manual, Variables chapter, for a printed list. Advanced varare not printed in this list.


an

4-2

4-2-2-3

-4

-4

4-54-6

Chapter 4Loading a Technology Library

This chapter provides a brief introduction to the topic of loading a technology library. You cfind more in-depth information about synthesizing for a specific technology in the in thefollowing chapters:

• Altera FLEX Synthesison page10-1

• Altera MAX Synthesison page11-1

• Altera APEX Synthesison page11-1

Loading a Technology Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Technology Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Lookup Table Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Global Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

The Technology FlowTab - FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Advanced Settings PowerTab - FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


Loading a Technology Library Loading a Technology Library

load

ded

ughll I/Og the

Os -

ignedents

ach

Loading a Technology LibraryIn order for LeonardoSpectrum to map your design to a specific technology, you must firsta library for a specific technology. This library includes both the technology-specific celldefinitions and the modgen operator implementations. Both libraries are automatically loawhen you select a technology from the list on the Technology FlowTab.

Technology Mapping

Introduction

This section describes the mapping techniques used in LeonardoSpectrum to mapcombinational and sequential logic. Also, I/O pad assignments and setting constraints throthe constraint file are described. When running LeonardoSpectrum in the default mode, asignals are assigned pads. The pads are selected from the target technology library durintechnology mapping phase. If more than one size of the same pad is available,LeonardoSpectrum chooses the smallest pad size. If the target library contains complex I/I/Os with registers in the I/O cell - then LeonardoSpectrum maps these complex I/Os asrequired.

Each architecture has different constraints on the usage of complex I/Os. For manually assI/Os, you are responsible for the validity of the output design. You can override the assignmdone by LeonardoSpectrum and assign pads manually. This can be done selectively on epad.


Loading a Technology Library Technology Mapping

ions.

s

Lookup Table Mapping

During the optimization process, combinational logic is decomposed to individual logicfunctions. LUT mapping fits these logic functions into a minimal number of LUTs whilemeeting timing requirements. For each of the LUT based technologies, a different LUTmapping is performed. LUT mapping finds an optimal coverage that maps these logic funct

Table 4-1. LUT Mapping Options for Altera FLEX

Advanced Settings On/Off Interactive Command Line Shell Batch Mode

Map Cascades on default default

off set altera_use_cascades false -nocascade

During LUT mapping, Map Cascades controls the mapping of logic to cascade gates forAltera FLEX 6K, 8K, 10K.


Global Buffers Loading a Technology Library

cksgy.

gn.

andd

e

Global BuffersLeonardoSpectrum assigns clock buffers to I/O signals with high-fanouts. This is useful tospeed up clock-to-output timing and input-to-register timing. Also, LeonardoSpectrum chethat assigning a certain clock buffer does not violate any design rule of the target technolo

I/O MappingDuring I/O mapping, LeonardoSpectrum assigns PADs to all I/Os in the top level of a desiLeonardoSpectrum can map input buffers, output buffers, tri-state buffers, bi-directionalbuffers, and complex I/O cells. LeonardoSpectrum also maps global buffers for clock lineshigh fanout input pads. There are several technology independent options on the AdvanceSettings PowerTab which controls I/O pad assignments. These options affect the completdesign, not just individual I/Os.


Loading a Technology Library The Technology FlowTab - FPGA

he

e

l

The Technology FlowTab - FPGALoading the Technology Library is the first step in the synthesis process.

Figure 4-1. Technology Settings - FPGA

Option Description

Part: This is the part number of your target device. LeonardoSpectrum selects tpart number for you or you can select another from the pull down list(v50bg256).

Speed: This the speed grade of your target device. LeonardoSpectrum selects thspeed (process) for you or you can select another from the pull down list .

Wire Load This is the table that will be used for estimated routing delay values. Actuarouting delays will be determined by the place and route tools.

Click to View theAltera W eb Site


The Technology FlowTab - FPGA Loading a Technology Library

Advanced Settings PowerTab - FPGA

Figure 4-2. Advanced Setting PowerTab for Altera FLEX6K

GUI Option Optionon/off

Interactive Command Line Shell Batch Mode Option

Map Cascades on default (true) default (true)

off set flex_use_cascades false -nocascades

Lock LCells on default (false) default (false)

off set dont_lock_lcells true -dont_lock_lcells


Loading a Technology Library The Technology FlowTab - FPGA

e

or

e gates

LEX

ology.

aylits

t

hich

Lock LCells If Lock LCells is not selected, then this directs LeonardoSpectrum not to forcLCell buffers in the output EDIF netlist. You can then use MAX+PLUS II tomap the combinational logic into LCells. FAST is the recommended setting fMAX+PLUS II GLOBAL_PROJECT_SYNTHESIS_STYLE.

Map Cascades By default this option is selected. LeonardoSpectrum then maps to cascadwhere applicable.

Exclude GatesScroll through the Exclude Gates list and highlight the gate(s) as needed. The listed Altera F6K gates are:

Latch, DFFC, FF, DFFP, DFFE, TRI, TRIBUF, CBUF, SCLK, Global, INBUF, OUTBUF,BDBUF,TFF, TFFC, TFFP

The selected gate(s) are excluded from the library when your design is mapped to the technIn addition, excluded gates are not saved as part of a Project.

Max Fanout: Use the Max Fanout field on the GUI to override the default max fanout loadspecified in the library. However, a synthesized netlist with high fanout nets mbe a problem for the place and route tool. The place and route tool usually spthe net arbitrarily. High fanout nets can cause significant delays on wires andbecome unroutable. On a critical path, high fanout nets can cause significandelays in a single net segment and cause the timing constraints to fail.To eliminate the need for splitting of the net by the place and route tool, thesynthesis tool must maintain a reasonable number of fanouts for a net.LeonardoSpectrum tries to maintain reasonable fanout limits for each targettechnology. Default fanout limits are derived from the synthesis library.Note: The LUT buffering and replication is supported for the Altera FLEX6/8/10 and 10KA/KE/KB technologies.General RuleLeonardoSpectrum maintains reasonable fanouts by replicating the driver wresults in net splitting. If replication is not possible, the signal is buffered. Thebuffering of high fanout primary input signals is an example. Buffering thesignal causes the wire to be slower by adding intrinsic delays.User SwitchesOn the interactive command line shell type:set lut_max_fanout <integer>

On specific nets, you can set an attribute to control the max_fanout value:set_attribute -net <net_name> -name lut_max_fanout -value <int>Note: Setting this attribute takes precedence over any global fanoutspecifications.


The Technology FlowTab - FPGA Loading a Technology Library


urce

rate

5-25-25-2

5-3

5-4

. 5-6

5-6

5-75-7

-810-11-12

Chapter 5Reading Your Design

The LeonardoSpectrum in-memory database is created by reading one or more design sofiles into memory. Design files are read in a two-phase process. First, a file isanalyzed(checkedfor proper syntax), thenelaborated(synthesized into an in-memory database composed ofgeneric gates and black box operators). The read command does both analyze and elaboautomatically.

Reading Your Design into Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Opening Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Reading Custom VHDL Libraries and Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Understanding the In-Memory Design Data Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Understanding the In-Memory Design Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

How LeonardoSpectrum Infers and Implements Operators . . . . . . . . . . . . . . . . . . . . . . . . .

Understanding Modgen Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Understanding Pre-Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .What is Pre-Optimization? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The Input FlowTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5The VHDL Input PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-The Verilog Input PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5The EDIF Input PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5


Reading Your Design into Memory Reading Your Design

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Reading Your Design into Memory

Opening Design Files

LeonardoSpectrum does not read pre-compiled HDL designs from disk. Instead, the desigsource files are read directly into memory where LeonardoSpectrum builds an EDIF-like inmemory database. The design source files do not have to reside in a specified working direThey may reside in any location and may even reside in more than one location. You simpclick on the Open files button, navigate to and select a source file, then click Open. The filare listed in the order in which they will be read.

Verilog designs can be read into LeonardoSpectrum in any order. LeonardoSpectrum supauto-top detection which automatically locates the top-level module so no particular file ordrequired as in VHDL.

For VHDL source files, order is important. VHDL files must be read in bottom-up order, i.elower-level blocks must be read before the top level blocks. If an opened file is out of placethe list, you may drag the file into the correct position with the mouse cursor. The files arefrom the top of the list to the bottom.

Reading Custom VHDL Libraries and Packages

Many standard VHDL libraries and packages are build into LeonardoSpectrum and don’t hto be specified in the Open file list. If your design references custom libraries and packagethen you must Open these package source files for reading before your design files are reamethods for doing this are fully discussed in theLeonardoSpectrum HDL Synthesis Manualstarting on page4-4.


Reading Your Design Understanding the In-Memory Design Data Model

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Understanding the In-Memory DesignData Model

The LeonardoSpecturm in-memory design data base is modeled after the EDIF design damodel. All design data is stored in a set of EDIF-type libraries which start at theroot . A librarycontains a list of cells, and a cell contains a list of views. In comparison to VHDL, acell isequivalent to anENTITY and aview is equivalent to anarchitecture . Just as most VHDLentities have only one architecture, most cells have only one view. Views are the basic buiblocks of your design and are equivalent to a schematic sheet. A view can have three typeobjects; ports, nets, and instances. A view is the implementation or contents of a single lehierarchy.

Examples:

• When you read a VHDL description into LeonardoSpectrum, your VHDL entitytranslates to a cell, and the VHDL architecture (contents) translates to a view. Bydefault, the cell is stored in an EDIF-style library calledwork (by default). You canchange the name of this library if you wish.

• When you load a technology library into LeonardoSpectrum, it becomes an EDIF-tylibrary in the design database, which contains all of the cells of that technology. Yodesign in the work library will reference this technology library as an external EDIFlibrary.

• LeonardoSpectrum creates an EDIF style library ofPRIMITIVES automatically. Thislibrary represents all primitive logic functions that LeonardoSpectrum may require wcompiling or elaborating HDL (VHDL and Verilog) descriptions.

• LeonardoSpectrum also automatically creates anOPERATORSlibrary. This librarycontains operator cells (adders, multipliers, muxes). When compiling HDL descriptiothese operators are generated when needed.

In summary, the following objects are typically contained within a view and are used torepresent netlists and hierarchies in a design:

• A view has ports, nets and instances.

• A port is a terminal of a view.

• An instance is a pointer to a view.

• A net is a connection between ports and/or port instances (pointer to the port of theunder an instance).


Understanding the In-Memory Design Data Structure Reading Your Design

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Understanding the In-Memory DesignData Structure

The LeonardoSpectrum Design Browser allows you to graphically browse through all in-memory libraries and the design hierarchy. Understanding the object naming conventionshelp you understand some of the commands that appear in the transcript and will also preyou to write Tcl scripts in the future.

To identify an object in the design database, LeonardoSpectrum uses a formalized designnaming convention. Any object in the database is accessible from a single root (the set oflibraries). The root is identified by the design name. (dot). A library is identified by the designname:

The general design name for a view is:

Wildcards and regular expressions are accepted and expanded in design names to identimultiple objects simultaneously.

LeonardoSpectrum also has the concept of a “present design”. This is a design name thatidentifies the top of your design hierarchy. When LeonardoSpectrum starts up, the defaultto the root (.). After you read in a design, the “present design” is set to the top level view adescribed in the source file(s).

The formalized naming convention can uniquely identify libraries, cells and views in a singname. However, since a view can contain three different types of objects (ports, nets, instathere may be a problem identifying these uniquely. For example, the name:

.l.c.v.x

does not identify an objectx in view v of cell c in library l as a port, net or instance. To workaround this problem, thelist_design command (and other commands that accept nets, poor instances) all have an option that you can use (-port , -net , or -instance ) to identify anobject type.

. library_name

.library_name.cell_name.view_name


Reading Your Design Understanding the In-Memory Design Data Structure

again:

ctive

The result oflist_design is a (Tcl) list, which can easily be used in scripts. The followingexample script reports how many cells are in each library in the database:

After thedemo/mancala.vhd file, for example ($EXEMPLAR/LeoSpec/demo ), has been read andthe flex10 library loaded, this script will produce the following output:

The object separator is programmable; the default is. (dot). You can change the separator bysetting the Tcl variablelist_design_object_separator . For example, the following scriptprints the present design name, changes the object separator, and prints the design name

Produces the output:

LeonardoSpectrum notifies you with a message when it recognizes the setting of aLeonardoSpectrum built-in variable, rather than a normal Tcl variable.

You can use the following example commands to list commands and variables in the interacommand line shell:

for each i [list_design .] {set the_length [llength [list_design $i]]puts “library $i contains $the_length cells”

}

library .PRIMITIVES contains 19 cellslibrary .work contains 2 cellslibrary .OPERATORS contain 6 cellslibrary .flex10 contains 925 cells

puts “The present design is [present_design]”set list_design_object_separator /

puts “The present design is [present_design]”

The present design is .work.mancala_32.exemplarInfo: setting list_design_object_separator to /The present design is /work/mancala_32/exemplar

help (lists all commands)help present_design (lists options and information)help list* (lists all list commands)help -variables (lists all variables)help -var write* (lists information about writevariables)


How LeonardoSpectrum Infers and Implements Operators Reading Your Design

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How LeonardoSpectrum Infers andImplements Operators

When LeonardoSpectrum reads an HDL design, it infers arithmetic and relational operato(e.g. adders) and implements the operators as blackboxes (there is no underlying functionin the design. LeonardoSpectrum does not implement operators until global area optimizawhen it replaces these blackboxes with technology-specific netlists (from the Modgen LibrKeeping operators as blackboxes reduces the database size and “reading” runtime.

Each blackbox operator uses a naming convention to convey parameter information such(type, size, sign, carry). for example:

add_16u_16u_0 -- 16 bit adder, unsigned operands, no carryoutgte_8s_8s -- 8 bit greater than, signed operands

Understanding Modgen LibrariesA Modgen library contains implementations of technology-mapped operator architecturesmeet area and performance specifications, and in general produce smaller or faster operaimplementations compared to generic cell implementations. To take advantage of area/sptrade-offs, most operators have more than one implementation.

Operator implementation has a great effect on the resulting quality of an optimized designAlso, the structure of idea operators differs greatly depending on whether area or performathe main goal of optimization. This is why most optimization tools on the market today havspecial ways of handling operators.

In LeonardoSpectrum, the term “operator” refers to arithmetic operators such as add, submultiply, and increment. Also, comparison operators like equal and less-than-or-equal areimplemented. Shifts and rotates are considered operators, and have corresponding Modggenerators as well.

Consider the adder. Depending on design requirements, a designer might choose a ripple(slow, but very compact) or a full carry lookahead adder (much faster, but about twice as mlogic). These types of trade-offs are what Modgen allows.

Since most critical paths include operators, using a Modgen library enables the synthesizeproduce a better starting point for optimization and decrease synthesis runtimes (since opeare implemented with technology cells instead of generic primitives, the optimizer does nohave to run on modgen operator blocks). You can also read user-defined module generatlibrary files written in VHDL (using theload_modgen command). TheLeonardoSpectrumHDL Synthesis Manualpresents guidelines for creating your own modgen components.


Reading Your Design Understanding Pre-Optimization

are

Understanding Pre-Optimization

What is Pre-Optimization?

After the generic RTL-data base is created, LeonardoSpectrum does what is called pre-optimization (technology-independent optimization). During this process, the following isaccomplished:

• Components are extracted. Objects such as counters, decoders, RAMs and ROMsseparated from generic logic. New views of these items are created.

• Operators that are “disjoint” (only used in different clock cycles) are shared

• Unused logic (logic that doesn’t affect the output signals) is removed

• Wide XORs and comparators are optimized by removing common sub-expressions


The Input FlowTab Reading Your Design

The Input FlowTabFigure 5-1. The Input FlowTab


Reading Your Design The Input FlowTab

mo

urce

ce

A typical sequence for using this FlowTab is to:

1. Set the working directory.

This defines the place where all the generated output files are placed.

2. Open files for input.

Files may be opened from any directory for reading. The list of open files is read frotop to bottom. Order is important when reading VHDL files. You may “drag” files intthe correct order with the mouse pointer, once the files are open for reading.

3. Click Read to read your entire design into the in-memory database.

You have the option to select the state machine encoding style. You may also turn off resosharing. This is typically done when reading an already optimized module.

RMB over your input file to popup the following shortcuts:

Note: Before compiling, LeonardoSpectrum checks (analyzes) for syntax errors in your sourcode. These errors, if any, are highlighted in the HDL editor window with a message.

Add Input File: (Opens Set Input Files.)Reverse OrderToggle SelectionSelect AllOpen File: (Opens file in the Information Window.)Set Work Library: (Opens Change work library.)Set Technology (source): (Clears or Opens lists for FPGA, CPLD, and ASIC)Set File Type: (Opens lists of output formats including XDB.)Remove: (Click to remove highlighted input file.)Remove All: (Click to clear the entire workspace.)



n

is

The VHDL Input PowerTab

Figure 5-2. The VHDL Input PowerTab Options

Option Description

Use this PowerTab when your input design is in VHDL format. These options are used whereading a design from Input tab without selectingo Analyze Only. These options apply only toread. Refer to the example screen settings.

Top Entity: Defines the top level of design hierarchy. If blank, the last entityread in is used. The top level is the last one found in the inputfile(s). Override this rule with the Entity option and specify thename of the top level entity.

Architecture:Specify name in lower caseonly.

When used with Entity option, defines the top level of designhierarchy. If blank, the last architecture that can be synthesizedused.

Generic (data_width=5) Sets the value for specified generics in the format<generic>=<value> [<generic>=<value>...]Multiple generics may be specified in this format.

VHDL Style VHDL 93 VHDL_87 either the 1993 or 1987 style of VHDLis read.


Reading Your Design The Input FlowTab

at

at

.

The Verilog Input PowerTab

Figure 5-3. The Verilog Input PowerTab Options

Option Description

Use this PowerTab when your input design is in Verilog format. LeonardoSpectrum appliesautotop detection to Verilog files. Specify the name of the top module to override this rule.Refer to the following example settings.

Top Module: my_top_module

Parameters top_module_nooptThe Parameters field allows you to set the value forparameter(s). Multiple parameters may be specified:[<parameter>=<value>[<parameter>=<value>... ]These are variable parameters like RAM, ROM.

Full Case: This is a true full synthesis directive. Select to guarantee ththe case statement is interpreted as a full case. If a defaultassignment was not used, then this option prevents theimplementation of extraneous latches.

Parallel Case: This is a parallel synthesis directive. Select to guarantee ththe case statement is parallel. A multiplexer may be thepreferred implementation when case conditions are mutuallyexclusive. A multiplexer may also be the preferredimplementation instead of priority encoding a state machine



The EDIF Input PowerTab

Figure 5-4. EDIF Input PowerTab Options

Option Description

You should use this PowerTab when your input design is in EDIF format.

DesignThis is the top level of thedesign to read.

priority_encoder.edf

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-16-18-20-22-24

Chapter 6Setting Timing Constraints

LeonardoSpectrum allows you to control the optimization and mapping process by settingtiming constraints. A common synthesis flow is to first optimize a design for the smallest a(without setting any timing constraints), then check for the proper fit. Normally, you shouldto fit your design into 80% of the chip’s capacity without any timing violations. If there areviolations, you can set timing constraints on the reported critical paths using the methodsdescribed in this chapter. When you re-optimize with these constraints applied,LeonardoSpectrum will work hard to eliminate the violations on these paths. This usuallyresults in more hardware on the critical paths (due to the increase of parallel structures), bonly the critical paths are affected, not the whole design.

You can set timing constraints using theConstraints FlowTab and its associated PowerTabs.The PowerTabs give you a more refined degree of control over the settings. Later you willhow to save the constraint settings in a constraints file (a.ctr file) that can be loaded intomemory during future Tcl script-driven or batch mode operations.

Setting Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Setting Global Timing Constraints on Sub-Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Setting Clock Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Setting Clock Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Multiple Synchronous Clocks per Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Setting the Input Arrival Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Setting Output Required Times: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Setting Multicycle Path Constraints: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Known Problem with Setting Multicycle Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6False Path Constraints: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Constraining Purely Combinational Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Constraining Mixed Synchronous and Asynchronous Designs . . . . . . . . . . . . . . . . . . . .Setting Multicycle Path Constraints: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

The Constraints FlowTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6The Clock Constraints PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6The Input Signal PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6The Output Signal PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6The Internal Signal PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6


Setting Timing Constraints

-266-28

-30

The Module PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6The Path Constraints PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .The Report Constraints PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6


Setting Timing Constraints Setting Timing Constraints

esignints

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Setting Timing ConstraintsSetting timing constraints in LeonardoSpectrum can be as simple as specifying the target dfrequency or as powerful as indicating multi-cycle paths between flip flops. Timing constraindicate the desired target arrival and required times used for setup and hold analysis.Constraints can be applied after the design is read into LeonardoSpectrum and beforeoptimization. LeonardoSpectrum assumes intuitive defaults. At a minimum, you must definthe clock, input port arrival times, and output port required times.

Note: LeonardoSpectrum does not support timing constraints relative to a particular clock.Everything is referenced to time zero. This includes input arrival times and output setup timwithout any reference to a particular clock.

Setting Global Timing Constraints on Sub-Blocks

Like all Tcl variables, Global timing variables apply to the present design in memory. Wheyou explicitly defined timing constraints, these explicit constraints override the globalconstraints. Setting these variables saves considerable time and effort when you performbottom-up optimizations. Refer toFigure 6-1.

Figure 6-1. Setting Global Timing Constraints on Sub-Blocks

Guideline: Set theinput2register andregister2output variables to one-half of the clockperiod. This ensures that the boundary logic of sub-blocks meets timing when combined intop-level design.

set register2register 20set input2register 10set register2output 10set input2output 10

in p u t 2 re g i s t e rre g i s t e r2 re g i s t e r

re g i s t e r2 o u t p u t

in p u t 2 o u t p u t



o

onous

rered

0ns,

s atet the

Resets

Sequential element set and reset pins are automatically blocked during timing analysis. Nspecial settings or constraints are required to block reset timing paths.

Clocks

LeonardoSpectrum supports one or more synchronous clocks. However, multiple asynchrclocks are not supported.

Setting Clock Constraints

Clocks define timing to and from registers. When the clocks are not defined, all registers aassumed to be unconstrained. Therefore all combinational logic between registers is ignoduring timing optimization. When you define a clock, you have effectively constrained thecombinational logic between all registers to one clock period. Refer toFigure 6-2.

Figure 6-2. Clock Constraints

The logic between FF1 and FF2 is constrained to one clock period. If the clock period is 5then Logic Cloud B has approximately 50ns minus setup of FF2 to meet timing.LeonardoSpectrum describes clocks by using three basic commands:

clock_cycle <clock_period> <primary_input_port>pulse_width <clock_pulse_width> <primary_input_port>clock_offset <clock_offset> <primary_input_port>

By default, the clock network is assumed to be ideal - with no clock delay. The clock arrivethe same time between all flops. To change the clock network propagated delay, you can spropagate_clock_delay variable toTRUE.

Logic C loudA

Logic C loudB

FF2

clk

D Q

FF1

clk

D Q

dat a

clock

The cl ock const rai ntw i lldefi ne t he requi red t im ingfor al ll ogic bet w eenfl ops



ortowset the

n thee

valuect for

Example of clock constraints:

In the first example inFigure 6-3, the clock period is defined as 40 ns and attached to clock p“clk”. The default duty cycle is 50%, or a clock pulse width of 20ns. The second example shhow to change the pulse width to 15ns. The third example demonstrates how one can offsclock. This is useful for specifying a clock skew relative to zero.

Figure 6-3. Clock Network

Setting Clock Skew

When constraining a design you may want to accommodate clock skew. Clock skew is ofteresult of a clock delay incurred by the input clock driver. This may effect the offsetting of thclock by the skew value. LeonardoSpectrum does not provide a method to directly input afor clock skew, however the clock may be offset by the skew value to create the same effetiming analysis and optimization.

0.0 20. 0 40. 0

15. 0

5.0 45. 0

clock_cycl e 40 cl k

clock_cycl e 40 cl kpulse_w idth 15 cl k

clock_cycl e 40 cl kpulse_w idth 15 cl kclock_offset 5 cl k

5 ns

15 ns



ired

ed

Figure 6-4. Clock Skew

Figure 6-5. Clock Skew Timing

Setting a clock skew reduces the input arrival time by the skew value. This provides arelaxedconstraint for the optimization of that logic. Clock skew does not effect register-to- registerlogic since all flip flops are subject to the same skew. Clock skew reduces the output-requtime whichtightensthe timing constraint on the output logic by the skew value.

Multiple Synchronous Clocks per Block

The timing analyzer for LeonardoSpectrum supports only 1 clock per block for exhaustivetiming analysis. Designs with multiple synchronous or asynchronous clocks can be analyz

Logic C loudA

Logic C loudB

FF2

clk

D Q

FF1

clk

D Qdat a

clock

Logi c C loudA

C lock S kew dueto C lock D ri ver

InputLogi cC onstrai nti s"R el axed"

R eg to R eg logicrem ains unchanged

O utputLogi cC onst rai nti s"t ightened"

M ore Ti m e

Less Ti m e

clock

input _arri val

output_requi red

offset _cl ock



using a technique involving the clock offsets. Refer toFigure 6-6, where Block A and Block Bare each driven by different, synchronous clocks.

Figure 6-6. Multiple Synchronous Clocks

Figure 6-7. Synchronous Clocks

Logi c C loudA

Logi c C loudB

FF2

D Q

FF1

clk

D Q

data

clock_a

Logi c C loudA

Logi c C loudB

FF2

clk

D Q

FF1

clk

D Q

data

clock_b

10ns peri od

15ns peri od

S ignalcrossesclock dom ai ns

C lo ck d o m a in A

C lo ck d o m a in B

0 n s 5 n s 1 0 n s 1 5 n s 2 0 n s 2 5 n s

1 2 . 5 n s 2 0 n s 2 7 . 5 n s

cl o ck_ a

cl o ck_ b

cl o ck_ b (o f fs e t )

5 nsoffset

10 ns del aybet w een

1stcycl e aci veedges

5 ns m inim um tim ebet w een act ive edges

occurng i n the 2ndcycl e



s.the

elta

lock

t (6 +

p. Theonousnal

Procedure for setting multiple, synchronous clock constraints

1. Draw the clock waveforms starting from time zero and complete several clock cycleManually determine the minimum time between active edges - this may not occur infirst clock cycle - this depends on how the active edges meet. InFigure 6-6, theminimum time is 5 ns.

2. Determine what the time between active edges is during the first clock cycle. The dis 10 ns inFigure 6-6.

3. Subtract the minimum active edge time from the first cycle active edge time. Thisnumber becomes the clock offset for the clock of signal origin. Set the appropriate coffset:

> clock_offset 5 clock_b

CAUTION : Setting the clock offset alters the input arrival timing. If you set an input arrivaltime of 6 for example, then the clock offset has essentially added that number to the offseoffset). You now have to adjust the input arrival time to correct for the offset by adding theoffset to the input arrival.

Multiple Asynchronous Clocks

LeonardoSpectrum does not analyze timing for signals that cross between two or moreasynchronous clock domains. This is because the clocks do not have a defined relationshibest way to handle this is to ignore all timing between signals that cross between asynchrclock boundaries. This can be accomplished by assigning a clock offset to the clock of sigorigin that is equal to or greater than two clock periods. To disable timing between clockboundaries inFigure 6-7issue the following command:

> clock_offset 30 clock_b

Input arrival times, if any, need to be increased by the amount of the clock offset.



to

ral

Setting the Input Arrival Time

The input arrival time specifies the maximum delay to the input port through external logicthe synthesized design.

arrival_time <delay_value> <input_port_list>

Figure 6-8. Input Arrival Time

In Figure 6-8, data arrives approximately 3 ns after the rising edge of clock. Therefore, toaccurately constrain the input port data, you must apply the following constraint:

> arrival_time 3 { data }

If the clock period were defined as 10ns, then the setup of FF2 must be added to thecombinational delay of logic cloud A, and needs to be 7ns to meet timing.

Note: All input arrival times start at time zero and cannot be specified relative to a particulaclock edge. To adjust for a particular clock edge, you must add the clock offset to the arrivtime.

3ns

FF1

clock peri od of 10ns i s at tached t oinputport"cl k"

D ata arri ves atinputport"dat a"3ns aft er ri singedge of cl ock cl k-> Q delay

Q

clk

DFF2

clk

DLogic

C loud A

ExternalV i rt ualC ircui t

Q

B lock A

clk

data

10ns

3ns



ith

dA in

Setting Output Required Times:

The output required time specifies the data required time on output ports. Time is always wrespect to time zero. In other words, output required time cannot be specified relative to aparticular clock edge

> required_time <required_value> <output_port_list>

Refer toFigure 6-9.

Figure 6-9. Output Time

When specifying required times all constraints are assumed to begin at time zero. Thiseliminates the need to specify a constraint relative to a particular clock edge. The specifierequired time becomes the time constraint on the output logic cloud shown as logic cloudFigure 6-9.

> required_time 7 { d1 }

clk

D Q

Logic C loudA

R equired Ti m e direct lyspeci fi es t he t im ing throughlogic cl oud A



lock.

Setting Multicycle Path Constraints:

If you have a combinational logic path that, by design, has a delay that is more than one ccycle, you can define this constraint by specifying a multi-cycle path in LeonardoSpectrumConsider the circuit in the illustration below:

To appropriately constrain the above design, you should apply the following constraint:

set_multicycle_path -from {FF1} -to {FF2} -value 2

M ethod f orSpeci fyi ng M ultiple M ulticycl e Paths

Ifyou havem or ethan onepat h leadi ng f rom ort wo aregi stert hathast hesam em ulticycl especi ficat ion,t hen you can sett heconst raintw i th onecom m and. Consi dert hef ol lowingexam ples:

Exam ple 1

A ssum ethatt hreem ulticycl epat hsf an outf rom thest arting regi ster FF1:

set_multicycle_path -from {FF1} -value 2

Exam ple 2

A ssum ethatt w o m ulticycl epat hsf an i nto an endi ng regi ster FF3:

set_multicycle_path -to {FF3} -value 2

FF1

D Q

clk

clock

data valid for 2 clock cycles

CloudLogic

FF1

D Q

clk

Need to “relax” timingrequirement for logiccloud to 2 cycles

Data only changes everyother clock cycle



ation.

ogicen

ry

s

Know n Probl em w ith Setting M ulticycl e Paths

D ueto the auto_disolve funct ion,t hehi erarchalnam eofar egi sterm ay changedur ing gl obalareaopt im izat ion.I fyou speci fy thenam eofar egi steri n the set_multicycle_pathcom m and,t hatnam em ay becom ei nval id af teryou exer ci set he optimize com m and.Thewor karound so t o setm ul ticycl epat h const raintsaf tergl obalar eaopt im izat ion,butbef oretim ingoptim izat ion.A nd,i n the set_multicycle_path com m and,you shoul d speci fy thef ul lpathnam eto aregi ster.Forexam pl e:

set_multicycle_path -value 2 -from .work.fir_filter.rtl.U1.U2.il

False Path Constraints:

False paths are design paths that you want LeonardoSpectrum to ignore for timing optimizRefer toFigure 6-10:

Figure 6-10. False Path Constraints

By taking advantage of theset_multicycle_path command, you can specify the path fromFF2 to FF3 as false. Refer again toFigure 6-10:

> set_multicycle_path -value 10000 -from {FF2} -to {FF3}

Essentially, the path from FF2 to FF3 has been constrained to 10000 clock cycles. Since lcloud B probably would not ever take more than 10000 cycles, this path has effectively beeliminated from timing optimization and timing analysis. Any multicycle path that isconstrained to 10000 or more cycles is reported as a False Path in the Constraint Summareport.

Constraining Purely Combinational Designs

A purely combinational design contains no clocks. You can constrain these blocks byspecifying the global variable input2output. This constrains any purely combinational paththrough a circuit. For example:

Logi c C loudA

Logic C loudB

FF3

clk

D Q

FF1

clk

D Q

dat a

FF2

clk

D Q

False Pat h



ints to

set input2output 9

Figure 6-11. Combinational Design

Constraining Mixed Synchronous and AsynchronousDesigns

Some blocks have both synchronous and purely combinational paths through the circuit. Amealy state machine is a good example of this. To constrain these designs, you applysynchronous constraints to the ports of the synchronous paths and asynchronous constrathe ports of the asynchronous paths.

Figure 6-12. Constraining Designs with Mixed Signals (1 of 3)

9 nsdata_i n dat a_out

Logi c C loud Logi c C loud

FF 2

cl k

D Q

AB

C

7ns

Logi c C loud

F F2

cl k

D Q

3 ns D el ay

V irt ualC i rcui t

Logi c B lock Z



s for



Procedure for Setting Constraints on Mixed Designs

1. Define the clock constraints.

> clock_cycle 16 clk

2. Apply an input arrival constraint assuming the design is entirely sequential.

> arrival_time 3 A

3. Apply an output-required time to the sequential output ports only. Set the constrainta sequential circuit ignoring the combinational paths for now.

> required_time 4 B

Logi c C loud Logi c C loud

F F2

cl k

D QB

C

7ns

Logi c C loud

F F 2

cl k

D Q

12 ns D el ay

V irtualC i rcui t

Logi c B lock Z

A

C lock P eri od = 16 ns

InputS etup A = 3 ns

O utputR equi red C = 10ns

O utputR equi red B = 4ns

3ns

10ns

4ns

16 ns



he

t

ced atmorel to0ns

bal

4. Apply an output arrival time to the combinational output paths. The maximum delayconstraint applied to these paths is the window created by the difference between tinput arrival time and the output-required time. InFigure 6-14, an input arrival of 3 is setand a maximum delay through the combinational path of 7ns is desired. The outpurequired time must be 10ns (10ns - 3ns = 7ns).

required_time 10 C

Constraining Sub-blocks for Timing

Ideally, registers are placed at hierarchical boundaries. However, random logic can be plathe hierarchical boundaries, which forces you to constrain the logic appropriately. Unlessdetailed information about the sub-block timing is known, you should use constraints equaone-half of the clock period. For example, is the clock period is 20ns, you should specify 1for the required time and 10ns for the arrival time.

If both sides meet timing, then when the blocks are combined, timing is met. Define the gloregister2output and input2register variables to equal one-half of the clock period. Refer toFigure 6-15.

Figure 6-15. Constraining Sub-Blocks

clock_cycle 20 clkset input2register 10set register2output 10

B lo ckA

B lo ckB

1 cl ock1/2

cl ock1/2

cl ock1 cl ock


The Constraints FlowTab Setting Timing Constraints

The Constraints FlowTabFigure 6-16. The Constraints FlowTab - Global Constraint Options


Setting Timing Constraints The Constraints FlowTab

u.

.

to

Option Description

Specify ClockFrequency, (Mhz):

This radio button choice is mutually exclusive with Clock Period. Yocan specify the required frequency for your design which is 1/period

Specify Clock Period,(ns):

This radio button choice is mutually exclusive with Clock FrequencySee clock period in diagram.

Specify MaximumDelay Between all:

This radio button choice gives you control over the delays from portregister, register to register, register to port, and port to port.

Input Ports toRegisters:

Delay from input port to input of register in nanoseconds.

Registers toRegisters:

Delay from output of one register to input of another register innanoseconds.

Registers to OutputPorts:

Delay from output of register to output port in nanoseconds.

Inputs to Outputs Delay from input port(s) to output port(s).



The Clock Constraints PowerTab

Figure 6-17. The Clock Constraints PowerTab Options



d.

ls

ulse

t

e.

ds.y.

.

Figure 6-18. Clock Waveform Diagram

Option Description

Reference Clock Properties: The Reference Clock isrelative to the signal. Everysignal is measured relative to the reference clock.Reference Clocks are saved in your constraint file.

Frequency: (2 digits of accuracy) Frequency (Mhz) is mutually exclusive with perio

Period: (2 digits of accuracy) Period is a waveform that repeats at fixed interva(ns).

Offset, ns: (Offset of Leading Edge) This is the delay after time=0. Timing isabsolute.Timing is offset in nanoseconds from time=0.

Pulse Width, ns: (Duration of Pulse) Pulse width is a measure of the duration of the pin nanoseconds.

Duty Cycle, %: (Duration of Pulse) Duty cycle percentage is equal to the pulse widthdivided by the period times 100. Some pulses do norepeat at fixed intervals. The pulse widths and timeintervals may differ.

Pin Location: This is the equivalent of the PIN_NUMBER attribut

Buffer: (BUFG, None) Select None to imply that ports are not assigned paBUFG I/O pads are available for selected technologEquivalent of the BUFFER_SIG attribute.

Clock(s) Browse through the interactive, filtered list of clocksThis list was built when you read in your design.

Delete Constraints ButtonClick Apply to apply deletions.

Select an object and clickDeleteand thenApply. Allconstraints set on this object are deleted.



The Input Signal PowerTab

Figure 6-19. The Input Signal Constraints PowerTab Options



ad

he

ut

d

a

ans,

s is

is

s

Option Description

Input Constraint Specify the input arrival time and drive characteristics foreach input port. The default is 0 ns arrival time and infinitedrive.

Arrival Time: (ns) Select a signal for your reference clock. Arrival times atprimary inputs define the maximum delay through logicexternal to the design before arrival at that input.

Infinite Drive This is the default when arrival is 0 ns and load is 0.

Input Drive Select this option to specify the additional delay per unit lo(ns) for the selected input port(s). This option allows anaccurate modeling of the effects of the load presented at tgate by the synthesized circuit.

Max Input Load: pf (pico farad) This is the capacitance load for your gates. The load inpcontrols operation of the output. If the synthesized circuitexceeds the number of loads, then LeonardoSpectrumbuffers the load. A buffer or inverter gate with an input loaless than the value specified must exist in the targettechnology to meet the constraint. If the technology has aglobal maximum load value, then an input cannot presentload at an input that exceeds the technology maximum.

Max Input Fanout: (loads) Fanout is the number of loads that the output of a gate cdrive. If the synthesized circuit exceeds the number of loadthen LeonardoSpectrum buffers the load.

Max Transition: ns (Rise) This is the rise time in the leading edge of the pulse. Thithe time required for the pulse to go from low level to highlevel.

Max Transition: ns (Fall) This is the fall time in the trailing edge of the pulse. Thisthe time required for the pulse to go from high level to lowlevel.

Pin Location: This is the attribute PIN_NUMBER.

Insert Buffers: (Global, none,SCLK)

I/O Pads available for selected technology. This is theattribute BUFFER_SIG.

Delete Constraints Button:Click Apply to apply deletions.


Input Port(s): window Browse through the interactive, filtered input port list. Thilist was built when you read in your design.



The Output Signal PowerTab

Figure 6-20. The Output Signal Constraints PowerTab Options



rts

r

fy

n

g

y

e.

s.y.

n

Option Description

Output Constraints Specify the output required time and loadcharacteristics for each port. The default is outputports with no load applied.

Required Time (ns): These choices allow you to constrain the output poand apply the required loads. The output clock isrelative to the output port. This is the time required foa signal to be available at this port.

Load: (pf), pico farad: (Number ofloads driven by output)

This is the capacitance load of the output port. Specithe amount of external loading on the design output.The loads value is used to calculate delays and toensure that sufficient drive capability is available at aoutput. Meeting load and drive requirements mayrequire choosing a gate with higher drive or replicatinlogic. The default output load for the technology isused, if a load value is not specified.

Fanout: loads: (Number of loadsdriven by output)

The output fanout depends on the input. Fanoutspecifies the maximum loading a gate can handle.Specify the number of external fanout loads driven bthe output.

Max Transition: ns (Rise) This is the rise time in the leading edge of the pulsThis is the time required for the pulse to go from lowlevel to high level.

Max Transition: ns (Fall) This is the fall time in the trailing edge of the pulse.This is the time required for the pulse to go from highlevel to low level.

Pin Location: This is the attribute PIN_NUMBER.

Pad: (pull down: 0BUF, OBUFT,None)

Select None to imply that ports are not assigned padBUFG I/O pads are available for selected technologEquivalent to the PAD attribute.

Delete Constraints Button:Click Apply to apply deletions.


Output Port(s): windowInteractive filtered list

This list of ports is available in your design. Doubleclick on a port name to select. This list was built wheyou read in the design.



The Internal Signal PowerTab

Figure 6-21. The Internal Signal Constraints PowerTab Options



s

Option Description

Instance Constraints Specify which signal to preserve duringoptimization.

�Preserve Signal If selected, your customized signal is preservedduring optimization.

�Assign to Low Skew Sets the attribute USELOWSKEWLINES on theselected nets.

Max Fanout Sets the limit for the maximum number of fanoutfor the selected signal.

Signals Scroll Window This is an interactive list of signals. This list wasbuilt when the design was read.


Select an object and clickDeleteandApply. Allconstraints set on this object are deleted.



The Module PowerTab

Figure 6-22. The Module PowerTab Options



is

;

d

Option Description

Module Constraints

Don’t Touch(Refer to auto_write in CommandReference Utilities chapter.)

If selected, the specified technology cells are notoptimized (NOOPT). dont_touch is an attributeused for preserving custom implementations andtechnology instantiation; used for optimizinghierarchically and for protecting buffering.

Optimize for: (pull down with area,delay)

Choose from pulldown. Choose area. The circuitoptimized to minimize area and not delay; orchoose delay to optimize for speed and not area.The default is area.

Effort: (pull down with quick, standard) Choose from pulldown. Choose quick. Only oneoptimization strategy is attempted on the networkor choose standard to run multiple optimizationalgorithms. The default is quick.

Modules: This is a filtered, interactive list of the modgenlibrary instances. This list was built when you reain the design.


Select an object and clickDeleteandApply. Allconstraints set on this object are deleted.



The Path Constraints PowerTab

Figure 6-23. The Path Constraints PowerTab Options



ts.

ts.nhs

t

ts.onhs

You

e

Option Description

From: This is the starting point for a multicycle or absolute path. Alist of filtered inputs and registers is displayed if the checkboxes are selected. Double click to select.

Inputs The input ports in your design are shown in the list of objecClick to select these ports.

Registers The registers in your design are shown in the list of objecClick to select the starting input port(s) and/or register(s) owhich to apply path constraints from the list of objects. Patin your design may be assigned various constraints.

To: This is the end point for a multicycle or absolute path. A lisof outputs and registers is displayed if the check boxes areselected. Double click to select.

Outputs The output ports in your design are shown in the list ofobjects. Click to select these ports.

Registers The registers in your design are shown in the list of objecClick to select the starting output port(s) and/or register(s)which to apply path constraints from the list of objects. Patin your design may be assigned various constraints.

False Path: False path disables timing analysis between the specifiedpoints. This options executes aset_multicycle_pathcommand with a value set to 10000 cycles (a false path).

MultiCycle Path (cycles): Sets a path constraint that is greater than one clock cycle.can specify any number of clock cycles in the field. A valueof 10000 or greater causes LeonardoSpectrum to report thpath as a False Path in the Constraint Summary report.

Click Add to add an input to output path. Highlight an existing path, clickDeleteto delete thepath. Highlight an existing path, complete your From: To: changes, and clickChangeto changea path. ClickApply afterAdd, Delete, Change.

Summary Window Example:lat_mem[1][0]...lat_mem[0][3][2]



The Report Constraints PowerTab

Figure 6-24. The Report Constraints PowerTab Options



a file

or

.

or

Option Description

This report shows all the constraints set on your design. You can save these constraints toor load a file of previously saved constraints.

Load From: Click on folder 1to bring up Loading Constraint File. Selectenter constraint file from Files of type: with *.ctr extension.Use the Windows browser, click, and drag rules as requiredClick on Load button.

Save To: Click on folder 1to bring up Saving Constraint File. Selectenter constraint file with *.ctr extension. Use the Windowsbrowser, click, and drag rules as required. Click on Savebutton.


7-27-2

7-5

7-5-6

-77-77-8

7-9-12

Chapter 7Optimizing Your Design

Understanding Global Area Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .How LeonardoSpectrum Optimizes a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Understanding Extended Optimization Effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Managing Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Design Partitioning Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Implementing Hierarchy in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Flattening Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Protecting Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The Optimize FlowTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Advanced Optimization PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7


Understanding Global Area Optimization Optimizing Your Design

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ass,

s

Understanding Global Area OptimizationLeonardoSpectrum preforms global area optimization and critical path timing optimizationseparately on each module in the design. Area optimization is automatically run first, followby critical path optimization if required to meet a timing constraint that may be optionallyspecified.

How LeonardoSpectrum Optimizes a Design

LeonardoSpectrum uses different techniques during optimization. Depending on the optiochosen, and algorithms run, a design can fall at different points on the area/performance c

The following paragraphs provide an overview of some of the techniques thatLeonardoSpectrum uses to optimize a design for area. LeonardoSpectrum uses this procewhenever you click on theRun Flow button.

1. Propagate constants (removes redundant logic introduced during pre-optimization

2. Implement operators (resolve_modgen)

During global optimization, LeonardoSpectrum implements the operator blocks in tsteps (Theoptimize command does both of these steps without user interaction):

a. Extracts macro operators (e.g. counters and rams) during the pre-optimizationcan control whether these macros are inferred using theextract_ram andextract_counter variables.

b. Populate the operator block with technology cells during modgen resolving.

3. Optimize the Design

The number of optimization passes that LeonardoSpectrum runs differs based onwhether you select the “Quick” or “Standard” optimization efforts. An optimization pais a pre-determined set of optimization algorithms. The “Quick” effort runs only onepass, while the “Standard” effort runs four passes. At the end of each optimization pLeonardoSpectrum reports the Area, number of Flip-flops, Delay, and time for eachhierarchical block.

When optimizing a hierarchical circuit, each block is optimized independently.Combinational logic is not moved across hierarchical boundaries. This feature allow

Note

LeonardoSpectrum sets theNOOPTattribute on all ModGen produced gates. Inaddition, the-default_resolving switch forces generic implementations,even if a Modgen library has been loaded


Optimizing Your Design Understanding Global Area Optimization

c

ortest

inton”.

ecificign.

toit ans).

you to quickly re-read blocks into the in-memory design without producing bad logi(due to previous optimization moving functionality between blocks). IfLeonardoSpectrum preforms multiple passes, it keeps either the smallest area or shdelay result depending on the -area or -delay switch on the Optimize FlowTab.

LeonardoSpectrum also runs different optimization algorithms based on the targettechnology. For example, LeonardoSpectrum attempts to map combinational logic4-input lookup tables for Altera designs. This is called “Fan-in limited decompositioIt is one of several technology-specific optimization algorithms built intoLeonardoSpectrum. This algorithm is especially appropriate for lookup-table-basedarchitectures. The algorithm limits the number of inputs within a circuit partition toallow fitting into a lookup table.

Optimization is a process of partitioning the circuit, running specific algorithms, andtesting to see if improvements are made. Each of the optimization passes runs a spset of algorithms starting with the unmapped (generic primitives from synthesis) desExamples of optimization algorithms include:

• BDD construction

A Binary Decision Diagram (BDD) decomposes the logic into a tree of decisionblocks. Sometimes LeonardoSpectrum cannot build a BDD for certain types ofcircuits such as very large multipliers or circuits that are very large. A BDD tendsgrow in size in a linear manner as the number of inputs increase which makesefficient means for representing data (unlike truth tables or PLA representation

Figure 7-1. A Binary Decision Diagram

I0 I1 I2 I3 Z

0000000011111111

0000111100001111

0011001100110011

0101010101010101

1000011001100000

1 0

1 0 1 0

1 0 1 0

1 0 1 0

I0

I1

I2

I3

ÿþýüûúÿùø÷ö Binary Decision Diagram

Z=1

Z=0

Z=0

Z=0 Z=0 Z=1


Understanding Global Area Optimization Optimizing Your Design

tualcret.

gy.

all

itical

e

• Factoring - combining like terms to reduce area.

• Circuit Restructuring - a more global technique.

• Remapping- utilizing wider gates.

Each pass iterates through a series of algorithms and measures the results. The acoperations performed in each pass are not released, as this is viewed as a trade se

4. Technology mapping.

After the design has been optimized to a minimal area, it is mapped into a technolo

5. Adding IO buffers

If you optimize in Chip mode (Add I/O pads), LeonardoSpectrum adds I/O buffers ontop-level ports that are not driven by IO buffers.

6. Starting with a design of minimal area, LeonardoSpectrum then re-optimizes the crpaths to meet timing. This usually means adding more hardware and more parallelstructures to speed things up. Only the critical paths are optimized, thus reducing thoverall increase in area.


Optimizing Your Design Understanding Extended Optimization Effort

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ase.

(orse

usto

Understanding Extended OptimizationEffort

LeonardoSpectrum has four groups of algorithms that it can be run on each module in youdesign. By default, the Quick Setup flow runs Algorithm Group #1. This group produces thbest results 70% of the time. If you selectExtended Optimization Effort , LeonardoSpectrumwill run all four algorithm groups on each module in your design. A built-in results filterautomatically selects and retains the best results for each module in the in-memory datab

Figure 7-2. Setting Extended Optimization Effort

Managing HierarchyYou can affect the optimization results/methods by modifying the hierarchy in your designjust portions of it). Before you create or change design hierarchy, you should consider theramifications:

• Timing constraints do not propagate through hierarchy. If you have hierarchy, you mset constraints on each block individually. If you have a flat design, you only need tapply constraints to top level IO.

• Hierarchical Designs constrain the optimizer

• Flat Designs are more difficult to understand than hierarchical designs.

• Instance naming in flat designs will become more abstract

P ass 1 P ass 2 P ass 3 P ass 4

L eon ard oS p ectru mD atab ase

A lg ori thmG rou p

#1

A lgorit h mG ro up

#2

A lgori th mG ro up

#3

A lgo rithmG roup

#4

R esu l tF il ter

R esu l t #1 R esul ts #2 R esult s #3 R esul t#4

B est R esu l t


Managing Hierarchy Optimizing Your Design

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• Hierarchy allows you to isolate and/or separate area and timing critical portions of ydesign

Design Partitioning Hints

• Group similar logic together(e.g. state machines, data path logic, decoder logic, andROMs).

Pay close attention to blocks that may lend themselves to special area or delayoptimizations. For example, if you know a particular block is going to contain thecritical path, you should move any non-critical logic from that block.

• Gate counts in leaf blocks should not exceed 50K gates.

Optimization can be performed on much larger designs provided that the sub-hierafalls within this guideline.

The maximum size of a single level of hierarchy is difficult to define since it is sodependent on the design. The number of operators, the type and style of the RTL cthe amount of random logic, etc all play a role in the max size LeonardoSpectrum chandle. With this said, for designs which are not timing critical, LeonardoSpectrumeasily handle up to 50k flat blocks, assuming you have sufficient memory. When timbecomes an issue, then LeonardoSpectrum has limitations that are similar to othersynthesis tools.

LeonardoSpectrum propagates global constraints down the hierarchy. And, if you wyou can constrain each block individually if you want to achieve realistic constraintsacross hierarchy. Another technique is to use the -force option during timing opt whwill attempt to speed up each hierarchical block by 10%.

• Separate timing critical blocks from non-timing critical blocks.

Keep in mind that LeonardoSpectrum performs area and timing optimization separaBy separating timing critical logic into one block, it may be possible to performaggressive area optimizations on a greater percentage of the design (thus creatingsmaller circuit that meets timing).

• Limit clocks to 1 per block.

LeonardoSpectrum does not support multiple, unrelated clocks at this time. If yourdesign has multiple clocks, you may be able to define a main clock and specify a cloffset for the other related clocks in the hierarchical block.

• Place registers at end of hierarchical boundaries.

Since optimization tools can only reduce combinational logic, there are two “barrierthat constrain optimization, hierarchical boundaries and registers. When designing


Optimizing Your Design Managing Hierarchy

f thers”

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hierarchically, you should attempt to place registers at either the front or back end ohierarchical boundary. This register placement essentially combines the two “barrieinto one thus minimizing the impact to overall results when optimizing hierarchicaldesigns.

• Place state machines into separate blocks of hierarchy.

This partitioning will speed the optimization and provide greater control over encod

• Place tristate drivers at the same level of hierarchy.

This allows you (and LeonardoSpectrum) more flexibility in handling/implementingtristates. By default, LeonardoSpectrum will not move tristate dirvers across hierar(because it would require changing the port interface on the hierarchical block to pathe enable signal). You can explictly set all the tristate drivers at the same level bysetting thebubble_tristatesoptions on the Advanced Settings PowerTab of theOptimize FlowTab.

Implementing Hierarchy in VHDL

The only way to introduce hierarchy within your VHDL design is by using ComponentInstantiations.

Flattening Hierarchy

LeonardoSpectrum provides the capability to flatten your entire design or portions of the desuch that you can affect the resulting optimization. The optimizer cannot merge logic acrohierarchical boundaries. As a result, you find that LeonardoSpectrum can achieve better rif you flatten specific blocks where logic could be optimized together.

Currently, LeonardoSpectrum does not propagate timing constraints down the hierarchy.order to timing optimize a hierarchical design, you need to apply the constraints and optimeach block separately. On the other hand, you can flatten the design, apply your input andoutput constraints to the design, and optimize the entire design for timing. However, the timoptimization on a flattened design likely will take longer than optimizing each block separa

For example, to flatten your entire design, enter the following command at theLeonardoSpectrum command line with the top level of your design set as the present desi

ungroup -hier -all

You can also select the instances in the Design Browser, and use the Right Mouse Buttonselect the Ungroup popup menu item.


Managing Hierarchy Optimizing Your Design

ing.

aveon. If

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Protecting Hierarchy

The Difference Between Don’t Touch and “No Opt”

There are two ways to protect a hierarchical block from optimization. You can apply thedont_touch attribute to the design object or apply the noopt attribute. The difference is asfollows:

• dont_touch prevents an instance from change, including optimization and unmappIn contrast to noopt,dont_touch also prevents changing the lower levels of hierarchyand leaf instances.

• noopt also prevents an instance from change. However, in contrast todont_touch ,lower levels of hierarchy and leaf instances are not protectedfrom change.

Specifying “Don’t Touch”

You can use thedont_touch attribute in LeonardoSpectrum to specify a “don’t touch”condition on selected instances in the design. You may have portions of your design that hbeen hand-implemented and you don’t want LeonardoSpectrum to perform any optimizatiyou have specified a technology component instantiation in your VHDL design, you can“dont_touch” it after synthesis so LeonardoSpectrum will not substitute it with a differenttechnology cell.

Sometimes you have a better idea of buffering requirements than the optimizer can underFor example, you may want to create a fast-transition clock signal. To do this, you could spthe buffer as a technology instantiation and retain it through optimization by setting thedont_touch attribute on the buffer.

You can protect instances in the design such that LeonardoSpectrum will not optimize theSpecifying “don’t touch” is useful for:

• Preserving custom implementations

• Preserving technology instantiations

• Optimizing hierarchically (e.g. Optimize a low-level block, then “don’t touch” it andoptimize a level above)


Optimizing Your Design The Optimize FlowTab

andinganelhyonthe

The Optimize FlowTabThere are two major optimization functions within LeonardoSpectrum. The optimize commpreforms global area optimization and may be run with or without timing constraints. Runnwithout timing constraints produces the smallest area design.This FlowTab is the control pto the optimize command. Global optimization is run on each module in the design hierarcseparately. Normally, LeonardoSpectrum has four groups of algorithms that it can be runeach module. By default, Algorithm Group #1 is run and produces the best results 70% oftime.

Figure 7-3. The Optimize FlowTab Options


The Optimize FlowTab Optimizing Your Design

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ign.

d

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ore

Option Description

Select design to optimize: Click to select an object from the filtered, embedded design browtree.

Current Path: This is the design you select from the design browser tree or your present desTarget Technology: Your current target is shown in the window.

Run type:Control your run.

Optimize: Default. Runs multiple optimization passes. Optimizemeans to reduce and improve logic in your design in terms of area andelay.

Remap: Does not optimize the network, but maps it into the targettechnology. The target may be another technology (retarget).

Optimize Effort - As you move the slider to the right, different combinations of (1) ExtendedOptimization, (2) Optimize for, and (3) Hierarchy are set for the synthesis run. Your circuittiming should improve. The tradeoff is increased synthesis run time.

Extended Optimization Effort: If this box is selected, then LeonardoSpectrum runs anadditional three optimization algorithms (assuming all 4 Pass boxes are selected). Whileselecting Passes (1-4) may cause a slower run, an improvement in the use of design spaceoccur. The Run type: Optimize: must also be selected.

A report is made for: Pass 1 Pass 2 Pass 3 Pass 4

Optimize for: Auto - LetLeonardoSptecrumdecide what is thebest solution

Delay - Thedesign is fasterand the areamay be bigger.

Area - The design may beslower and the area may besmaller.

Hierarchy Auto(default -auto_dissolve)

Hierarchy Auto is selected by default. Views with 50 or fewer gatesare dissolved.

Hierarchy Preserve If Hierarchy Preserve is not selected then your design is flatten befoptimizing.If Hierarchy Preserve is selected then your design hierarchy is notchanged during optimization.

Hierarchy Flatten If Hierarchy Flatten is selected then your entire design hierarchy isflattened.



te

Add I/O Pads Add I/O Pads is selected by default. LeonardoSpectrum runs theoptimization in the chip mode and inserts I/O pads in your design. IfAdd I/O Pads is not selected, then LeonardoSpectrum runs theoptimization in the macro mode.

Optimize a single levelof hierarchy

If this box is selected then optimizing is limited to a single level (thecurrent level) instead of all levels.

Run timingoptimization

The optimizations are concentrated on paths in the design that violatiming.



Advanced Optimization PowerTab

Figure 7-4. Advanced Optimization PowerTab Options



d.

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re

.

Option Description

Do not use wire delay during delay calculations. (Variable: wire_tableFALSE). Select wheninterconnect delays are ignored. The use of a wire table during delay calculations is disable

Allow converting internal tri-states. (Variable: tristate_mapFALSE). Select to allow theconversion of internal tristates to combinational logic that matches the target technology.

Allow transforming Set/Reset on DFFs and Latches. (Variable: transformationFALSE). Selectto allow transformations to match the target technology.

Break combinational loops statically during timing analysis. (Variable: delay_break_loopsFALSE). Select to allow combinational loops to be broken statically for timing analysis andcritical path reporting. The default is dynamic analysis of combinational loops. This optionspeeds up timing analysis, optimization and critical path reporting when dynamic analysis tatoo much time. However, timing analysis is not accurate when this option is used and the deshas combinational loops.

Bubble Tristates: Use these rules: If tristates are not in common levels, then by selectingBubble Tristates, the tristates bubble up to the common top level.If tristates are in a common level and feeding the output port, then by selecting BubbleTristates, the tristates bubble up to the top primary output port. This also occurs if tristates anot in a common level.

Operator Options: (For VHDL and Verilog input formats only.)

Use technology specific module generation library. If the box is not checked, then a defaultinternal module generation routine is used.

Operator select:(For VHDL and Verilogformats only)

Auto: Picks smallest if in area mode; picks fastest if optimizationin delay mode.

Smallest: Picks the most compact implementation available.

Small: Picks a compact implementation.

Fast: Picks a fast implementation.

Fastest: Picks the fastest implementation available.

Extract Clock Enables: Map to clock-enable flip-flops from VHDL and Verilog.

Extract Decoders: Controls automatic extraction of decoders in VHDL and Verilog

Extract ROMs Controls automatic extraction of ROMs in VHDL and Verilog.

Extract Counters: Controls automatic extraction of counters in VHDL and Verilog.

Extract RAMs Controls automatic extraction of RAMs in VHDL and Verilog.

Optimization CPU Limit:min

Time needed for optimization algorithms to complete. 0 minutes,no time limit.



Auto Dissolve Limit: 50 gates, default for CPLDs

Add I/O Pads If I/O Pads is not selected, then LeonardoSpectrum runs theoptimization in the macro mode. If I/O Pads is selected, then theoptimization runs in the chip mode and pads are inserted in yourdesign.

Click Apply to apply options. ClickHelp for assistance.Note: Your original design is copied with an RTL extension, my_design_RTL. The originaldesign is optimized, while the copy is retained as a record.


o

8-28-48-58-6-7

Chapter 8Saving Your Design

After you click onRun Flow, your design will be Read (if not already read), optimized, andwritten as an output netlist. Before you click onRun Flow, however, you can make changes tthe output options as described in this chapter, thenApply those options before you start therun.

The Output FlowTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .The EDIF Out PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .The SDF Out PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .The Verilog Out PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .The VHDL Out PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8


The Output FlowTab Saving Your Design

The Output FlowTabFigure 8-1. The Output FlowTab Options


Saving Your Design The Output FlowTab

d is

Option Description

Filename:Note: Use a “-” forfilename to have outputappear on the mainwindow.

Click on folder to bring up the Set Output Files. This is the place-and-route file. Select from list or type in another filename. Thisfilename defaults to <input design>.<ext>, where <ext> is based onthe output format.Note: Point at filename to popup the full pathname.

Format: The radio button output netlist format choices are listed.

Auto By default the output file is written out in EDIF format (.edf). Autodetermines the actual format based on the filename extension.

VHDL The output design file is in the VHDL netlist format.

Verilog The output design file is in the Verilog netlist format.

EDIF The output design file is in the EDIF netlist format.

SDF (Standard DelayFormat)

The output file is in the SDF netlist format. Output files in SDF areaccepted by all technologies. This is a back-annotated SDF file.

XDB (ExemplarDatabase)

The output file is saved in a format that can be read back intoLeonardoSpectrum without processing the netlist to removetechnology-specific information. XDB writes a binary dump of yourdatabase to a file. You can read this file back intoLeonardoSpectrum to restore the design database to the originalconditions when the design was produced.Note: If your inputformat is XDB, then load the technology library before reading theinput file. This sequence prevents problems with report delay andwith symbols in the schematic viewer.

Write vendor constraints file: Select to write output file and a vendor’s constraint file.

Pre-Process Netlist: By default executes auto_write command to write a netlist that meetsrequirements of your P&R tool. If Pre-Process Netlist is not selected, then the write commanexecuted.

Write only the top level of hierarchy to file: Select to limit output file to only the top hierarchyof file.

Downto:(leaf-level)

Technology Cells: Output file includes technology cells.Primitives: Output file includes your original design (leaf level).

Click Write to apply your options.



und

The EDIF Out PowerTab

Figure 8-2. EDIF Out PowerTab Options

Option Description

Set EDIF specific options before writing out the EDIF output format.

EDIF GND Accept default GND or type in your choice. This is yourspecial name for ground nets. Be sure to select Write outpower and ground as undriven nets with special names.

EDIF Power Accept default VCC or type in your choice. This is yourspecial name for EDIF power. Be sure to select Write outpower and ground as undriven nets with special names.

Allow Writing Buses: Before V1998.2, LeonardoSpectrum split buses. For example, A0 andA1 were split into individual bits for writing buses. Now you can write A+B=sum to indicatethat A bus + B bus is the sum.

Write out power and ground as undriven nets with special names: Enter your names for groand power.

Write the contents of cells marked Don’t Touch. Objects marked withdont_touch are notoptimized or unmapped. In contrast tonoopt , dont_touch prevents optimization of the lowerlevels of hierarchy and leaf instances.



The SDF Out PowerTab

Figure 8-3. SDF Out PowerTab Options

Option Description

Set your specific SDF options before writing out an SDF file. SDF is not a netlist; SDF is aformat.

SDF Names Style: SDF is a netlist format which derives a style from VHDL or Verilog.

VHDL The output file is in a SDF netlist format with a VHDL style.

Verilog The output file is in a SDF netlist format with a Verilog style.

none The output file is in a SDF netlist format with the default VHDL style.

Write flat netlist The hierarchy of your design is flattened unless this choice is selected.



The Verilog Out PowerTab

Option Description

Allow Writing Buses: Before V1998.2, LeonardoSpectrum split buses. For example, A0 andA1 were split into individual bits for writing buses. Now you can write A+B=sum to indicatethat A bus + B bus is the sum.

Click Apply to apply options. ClickHelp for assistance.



d

The VHDL Out PowerTab

Figure 8-4. VHDL Out PowerTab Options

Option Description

Type used for bit by VHDLwriter:

std_logic - This type allows a choice of nine values (0, 1, X, L,H, W, U, -, Z). Other bit choices allow 0, 1 only.

VHDL Vector Type std_logic_vectorSpecify the type for the bit-vector used in VHDL writer.

Allow Writing Buses: - Before V1998.2, LeonardoSpectrum split buses. For example, A0 anA1 were split into individual bits for writing buses. Now you can write A+B=sum to indicatethat A bus + B bus is the sum.

Write VHDL_87: This directs LeonardoSpectrum to read 1987 style VHDL instead of 1993style VHDL.


9-2-29-49-5

Chapter 9Performing Physical Layout

The Place & Route Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .The Altera MAX+PLUS II Place & Route Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9The Altera Quartus PowerTab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Quartus Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


The Place & Route Tab Performing Physical Layout

The Place & Route Tab

The Altera MAX+PLUS II Place & Route Tab

Figure 9-1. Altera MAX+PLUSII Physical Tab Options


Performing Physical Layout The Place & Route Tab

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Option Description

Before this P&R tab is available you must load the Altera library, complete the design flow, anwrite an output netlist file.

Setup MAX+PLUS II Create (Assignment and Configuration File) ACF file: This option isselected by default. Setup MAX+PLUS II allows you to change or overwrite an existing ACFfile.

Auto Fast I/O Select to allow the MAX+PLUS II compiler to implementregisters in Fast I/O. Reduces area requirements, but slowsinternal circuitry.

Auto Implement in EAB(Altera FLEX 10K)

Select this box if you are using wide gates and want to embedthe array block.

Auto Register Packing If your registers always have a constant input, for example “1then these registers are merged in the EDIF. Implements registpacking by placing a combinational logic function and a registerwith a single data input in the same logic cell.

Run MAX+PLUS II Select this box if you want to run MAX+PLUS II for your EDIFfile.

q Bring up MAX+PLUS II You want to bring up the MAX+PLUS II GUI.

Timing Analysis Use the timing information in the SDF, VHDL, or Verilog file tocheck place and route for accuracy. Creates either an input tooutput delay matrix, a setup/hold matrix, or a registerperformance report.

Input-Output Delay Select for typical delay.

Setup/Hold You want to check on setup and hold violations.

Register Performance You want to verify that constraints are met.

Verification: Produce a VHDL or Verilog netlistfor simulation. Generate simulation files and SDF2.1; enables MAX+PLUS II writers.

VHDL Verilog

Click Run PR to create your ACF file and to invoke MAX+PLUS II using specified options.



.

The Altera Quartus PowerTab

Figure 9-2. Altera Quartus PowerTab Options

Option Description

Before this Tab is activated, you must load the Altera library, complete the design flow, andwrite an output netlist file.

Run Quartus Select this box if you want to run Quartus on your EDIF netlist

Bring up Quartus GUI In contrast to MAX+PLUS II, this selection gives you theadditional step of setting up a project and completing the designcompilation.

Verification: Produce a VHDL or Verilog netlistfor simulation. Generate simulation files and SDF2.1; enables MAX+PLUS II writers.

VHDL Verilog



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Quartus Integration

Quartus is encapsulated in the Quick Setup FlowTab and the Advanced P&R FlowTab ofGUI for LeonardoSpectrum as follows:

• All constraints are set in LeonardoSpectrum for Quartus.

• Quartus is executed automatically by P&RIntegrator when the pathname to the Quexecutable directory is specified. See the topicSetting the Place and Route ExecutablePathnameson page3-6 for details. The results of cross probing are available in theinformation window.

Constraint Passing

LeonardoSpectrum supports passing constraints to Quartus using the Quartus NativeLinkfeatures. The following constraints are defined on the GUI or with attributes on the interaccommand line shell and passed to Quartus:

• Global Constraints

• Clock Frequency

• Input and Output: Pin Locations

• Part Numbers and Speed Grades

Constraint Passing Examples

Three project files are generated by LeonardoSpectrum for Quartus.

• traffic.psf (project settings )

• traffic.csf (compiler settings)

• traffic.quartus (project file)

Traffic.psf (project settings)

DEFAULT_DEVICE_OPTIONS

Note

Depending on the options selected, mapping to APEX 20K/20KE WYSIWYprimitives is either done by LeonardoSpectrum or by Quartus. By default,LeonardoSpectrum does the mapping to WYSIWYG primitives.



{RESERVE_PIN = "AS INPUT TRI-STATED";RESERVED_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";HEXOUT_FILE_COUNT_DIRECTION = UP;HEXOUT_FILE_START_ADDRESS = 0;GENERATE_HEX_FILE = OFF;GENERATE_RBF_FILE = OFF;GENERATE_TTF_FILE = OFF;RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = OFF;RESERVE_RDYNBUSY_AFTER_CONFIGURATION = OFF;RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = OFF;DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE = OFF;AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;CONFIGURATION_DEVICE = EPC2LC20;USE_CONFIGURATION_DEVICE = ON;ENABLE_INIT_DONE_OUTPUT = OFF;ENABLE_LOCK_OUTPUT = OFF;ENABLE_DEVICE_WIDE_OE = OFF;ENABLE_DEVICE_WIDE_RESET = OFF;RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;AUTO_RESTART_CONFIGURATION = ON;USER_START_UP_CLOCK = OFF;CONFIGURATION_SCHEME = "PASSIVE SERIAL";JTAG_USER_CODE = FFFFFFFF;}Traffic.csf (compiler settings)CHIP(traffic){AUTO_RESTART_CONFIGURATION = ON;RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;USER_START_UP_CLOCK = OFF;ENABLE_DEVICE_WIDE_RESET = OFF;ENABLE_DEVICE_WIDE_OE = OFF;ENABLE_INIT_DONE_OUTPUT = OFF;ENABLE_LOCK_OUTPUT = OFF;JTAG_USER_CODE = FFFFFFFF;CONFIGURATION_SCHEME = "PASSIVE SERIAL";USE_CONFIGURATION_DEVICE = ON;CONFIGURATION_DEVICE = EPC2LC20;CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE = OFF;GENERATE_TTF_FILE = OFF;GENERATE_RBF_FILE = OFF;GENERATE_HEX_FILE = OFF;HEXOUT_FILE_START_ADDRESS = 0;HEXOUT_FILE_COUNT_DIRECTION = UP;RESERVED_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = OFF;RESERVE_RDYNBUSY_AFTER_CONFIGURATION = OFF;



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e

RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = OFF;DEVICE = "EP20K200RC208-3";|sensor1 :LOCATION = PIN_3;|red1 :LOCATION = PIN_12;}

Traffic.quartus (project file)

COMPILER_SETTINGS{FOCUS_ENTITY_NAME = |traffic;RUN_TIMING_ANALYSES = ON;USE_TIMING_DRIVEN_COMPILATION = ON;COMPILATION_LEVEL = FULL;SAVE_DISK_SPACE = ON;SPEED_DISK_USAGE_TRADEOFF = NORMAL;FAMILY = APEX20KE;}

Cross Probing

LeonardoSpectrum provides support for cross probing from within Quartus into the originaHDL files.

When targeting APEX 20K/20KE, LeonardoSpectrum generates a cross reference .xrf filetogether with the EDIF netlist. This allows Quartus users to seamlessly cross probe into thoriginal HDL design files from the floor plan view. Refer to the following example for thetraffic.vhd demo.



Example Demo:design_name = traffic.vhd

instance = comp, red1_obuf, red1_obuf, traffic, 1, 57::57:

instance = comp, green1_obuf, green1_obuf, traffic, 1, 57::57:

instance = comp, red2_obuf, red2_obuf, traffic, 1, 57::57:

instance = comp, green2_obuf, green2_obuf, traffic, 1, 57::57:

instance = comp, reg_state7, reg_state7, traffic, 1, 35::35:


instance = comp, reg_state5 reg_state5, traffic, 1, 57::57:






instance = comp, clock clock, traffic, 1, 29::29:

instance = comp, sensor1 sensor1, traffic, 1, 29::29:

instance = comp, sensor2, sensor2, traffic, 1, 29::29:

instance = comp, reset reset traffic, 1, 29::29:

instance = comp, red1 red1 traffic, 1, 30::30:

instance = comp, yellow1 yellow1 traffic, 1, 30::30:

instance = comp, green1 green1 traffic, 1, 30::30:

instance = comp, red2 red2 traffic, 1, 30::30:

instance = comp, yellow2 yellow2 traffic, 1, 30::30:

instance = comp, green2 green2 traffic, 1, 30::30:


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Chapter 10Altera FLEX, ACEX, and MAX

Synthesis

This chapter presents information specific to the use of Altera FLEX, ACEX, and MAX assource or target technology.

The FLEX and ACEX Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

The MAX Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

The Altera Synthesis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Summary of FLEX, ACEX, and MAX Specific Control Variables . . . . . . . . . . . . . . . . . . . 10

User Options that Control Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Assigning Device Pin Numbers to Primary I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Mapping to the Logic Element (LE) in FLEX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Fanin Limited Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Lookup Table (LUT) Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Managing the Inclusion of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Managing the Inclusion of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Managing the Inclusion of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Understanding LeonardoSpectrum Modgen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Mapping Combinatorial Logic to Embedded Array Blocks (EABs) . . . . . . . . . . . . . . . 10

Mapping Memory Elements to FLEX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Inferring ROMs from the HDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-Mapping RAMs to the FLEX 10K Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-Generating Simulation Memory Models with Genmem . . . . . . . . . . . . . . . . . . . . . . . . 10LPM Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-

Writing the EDIF Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-

Using FLEX Designs as Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

FLEX 6000/8000 Devices Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

FLEX 10K Devices Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ACEX Devices Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MAX Family Devices Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10


The FLEX and ACEX Architecture Altera FLEX, ACEX, and MAX Synthesis

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The FLEX and ACEX Architecture

Introduction

The FLEX and ACEX device families are based on the Altera Flexible Logic Element Matrarchitecture. This SRAM-based architecture offers high-performance, reister-intensive, higate-count devices with embedded arrays. LeonardoSpectrum supports the FLEX 6000, F8000, FLEX 10K/ 10KA/10KB/10KE and ACEX 1K familys.

Logic Elements (LEs)

LEs are also known as Logic Cells (LCells). The combinational logic part of an LE is a looktable (LUT). LEs are at the core of Altera FLEX and ACEX architecture and contain bothcombinational logic and registers. The combinational logic is limited by the number of inpufunctions of up to four inputs can be implemented in one LE. Functions with more inputs mbe separated into multiple levels of LEs. Each LE also contains a register with clear and pinputs. In addition, LEs are grouped in LABs. All LEs in a LAB share control signals andconnect to each other through special cascade routing resources.

Input/Output Elements (IOEs)

IOEs in Altera FLEX and ACEX can be configured as inputs, outputs, tristate outputs, or bdirectional pins, with a register in either input or output path.

Embedded Array Blocks (EABs)

EABs are included in the architecture for FLEX 10K and ACEX 1K and are used to implemmemory functions and pterm configurations. Each EAB provides 2048 bits which can creaRAM, ROM, FIFO, or dual-port RAM. EABs can also be configured as pterms to efficentlyimplement circuits such as state-machines and wide address decoders.

The MAX ArchitectureThe MAX family is composed of EPROM devices that are based on the Altera Multiple ArrMatriX architecture. These devices are primarily used to implement functions such as widaddress decoders and state machines that are best implemented in pterm logic.LeonardoSpectrum provides synthesis for MAX 3000A, 5000; and 7000/A/AE/E/S; and 90devices and provide synthesis for these families into any of the other supported technolog

The basic MAX structures are: macrocells, expanders, and I/O cells.


Altera FLEX, ACEX, and MAX Synthesis The Altera Synthesis Flow

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Macrocells contain combinational logic and registers. Macrocells can also be referred to aLogic Cells (LCELLs). Combinational logic is limited by the number of product terms.Functions of up to four (MAX5000) or five (MAX7000/9000) product terms can beimplemented on one macro cell. Efficient use of the XOR gate resident in the Macrocell caincrease the number of product terms.

Functions of more product terms must use Expanders, or be broken into multiple levels ofMacrocells. Each Macrocell also contains a register that can be programmed to be a flip-fllatch with clear and preset inputs. In addition, Macrocells and Expanders are grouped in Lwhich are fanin limited. The Macrocells and Expanders impose a fanin limitation on the proterm limitation.

I/O cells in Altera MAX can be configured as inputs, outputs, tri-statable outputs, or bi-directional pins.

LeonardoSpectrum uses dedicated algorithms to optimize logic for the MAX devices givenproduct term and fanin limitations of the architecture. The optimization takes advantage ofMAX resources such as Expanders, XORs and enabled flip-flops. This enables significantreductions in area and delay for the MAX devices.

The number of Macrocells as well as the number of Expanders is reported. The number oMacrocells and Expanders is only an estimate. The exact number can only be determinedfitting, because MAX+PLUS II trades off Macrocells for Expanders, to achieve maximumutilization of resources. If too many Expanders are used, MAX+PLUS II converts someExpanders into Macrocells, and consequently may use too many Macrocells for the targetdevice. Try to fit the other results as well, even if the first pass seems to be the smallest on

The Altera Synthesis Flow

The QuickSetup Flow

Quick Setup is the default synthesis flow presented to users when LeonardoSpectrum isinvoked. Quick Setup can be used by advanced as well as beginning users as a simple andmeans to achieve a good first-pass synthesis result. You specify the target technology, opyour input design files, optionally set the target clock frequency, and verify the name andlocation of the generated output netlist. You click theRun Flow button to run the entiresynthesis flow. Optionally, you can have Quick Setup automatically invoke the vendor placand route tools to generate a set of vendor place and route files. You can read a more detdiscussion about this flow inChapter 2of theLeonardoSpectrum User’s Manual.


Summary of FLEX, ACEX, and MAX Specific Control Variables Altera FLEX, ACEX,

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The Advanced (Level 3) Synthesis Flow

The Advanced (Level 3) Flow is an incremental flow that allows you full access to the in-memory database while you guide the data transformation process step-by-step. FlowTaband PowerTabs provide easy access to the basic incremental steps. In addition, you can ea fine degree of control over the usage model with the Interactive Command Line Window.can read a more detailed discussion about this flow inChapter 2of theLeonardoSpectrumUser’s Manual.

Summary of FLEX, ACEX, and MAXSpecific Control Variables

When you select FLEX, ACEX or MAX as you target technology, LeonardoSpectrum willautomatically optimize you design to the architecture features of that device family. Theseoptimizations are explained in more detail in the remainder in this chapter. The following tsummarizes the Tcl variables that control these optimizations:

FLEX, ACEX and MAX Specific Control Variables

Variable FLEX MAX Description

lut_max_fanout X Overrides the maximum fanout limits are derived fromthe synthesis library. SeeMax Fanout (FLEX andACEX).

altera_use_cascades X Use this switch to control whether LeonardoSpectrmaps logic to CASCADES during LUT mapping.Mapping to cascades can improve density andpreformance, but increase routing congestion. Toincrease routability, try turning this off for non-speedcritical modules. SeeMap Cascades (FLEX andACEX).

dont_lock_lcells X X When set false, this gives the implementation softwarmore freedom to re-map portions of the design ifnecessary. SeeLock LCells (FLEX and ACEX).

max_fanin X Controls the maximum fanin into a function.

max_pt X Controls the maximum number of product terms in afunction.

altera_add_carry_sum

X Directs LeonardoSpectrum to use the Altera carry_sumprimitive gate in the EDIF netlist. SeeUse theCarry/Sum Primitive.


Altera FLEX, ACEX, and MAX Synthesis User Options that Control Mapping

y

rB

ppedof

ntainableis

fore

User Options that Control Mapping

Device

Selects a particular target device for implementation.

Speed

Selects a particular speed grade for implementation.

Map IO Registers (FLEX 10K and ACEX 1K)

If your design meets register2register timing, but does not meet input2register orregister2output timing, then mapping the first and last register in each path to the IOBs maspeed up the input2register or register2output path. Also, if an internal register is drivingmultiple I/O ports, then selecting this option will replicate the register multiple times, one foeach port. This also improves the register2output timing. In addition, by utilizing unused IOregisters, you save on area. The disadvantage to IOB mapping might be that if an IOB maregister is in a critical path, then the register2register delay might be made worse becauseincreased routing delay.

Max Fanin (MAX only)

Controls the maximum fanin into a function.

Max PT (MAX only)

Controls the maximum number of product terms in a function.

Max Fanout (FLEX and ACEX)

To eliminate the need for the implementaton tool to split a net, the synthesis tool must maia reasonable number of fanouts for each net. LeonardoSpectrum tries to maintain reasonfanout limits for each target technology. Default fanout limits are derived from the syntheslibrary.

You can use option on the GUI to override the default max fanout load specified in thetechnology library. However, a synthesized netlist with high fanout nets may be a problemthe implementation tool. High fanout nets can cause significant delays on wires and becomunroutable. On a critical path, high fanout nets can cause significant delays in a single netsegment and cause the timing constraints to fail.


User Options that Control Mapping Altera FLEX, ACEX, and MAX Synthesis

n.

en

where

eed

theneoes

.

If you are a Level 3 user, you can use theinteractive command line shell syntaxto set anattribute on a specific net to control the max_fanout value. The command syntax is:

set_attribute -net <net_name> -name lut_max_fanout -value <int>

Setting this attribute on a specific net takes precedence over the global fanout specificatio

Lock LCells (FLEX and ACEX)

By default, this option is selected in the GUI. If you turn this option off, thenLeonardoSpectrum does not to force LCell buffers into the output EDIF netlist. You can threly on MAX+PLUS II to map the combinational logic into LCells. (FAST is the recommendedsetting for MAX+PLUS IIGLOBAL_PROJECT_SYNTHESIS_STYLE.)

Map Cascades (FLEX and ACEX)

By default this option is selected and directs LeonardoSpectrum to map to cascade gatesapplicable. Mapping to cascades can improve density and preformance, but may increaserouting congestion. To increase routability, you should try turning this option off for non-spcritical modules.

Use the Carry/Sum Primitive

By default, LeonardoSpectrum uses the carry_sum primitive gate in the EDIF netlist to tellimplementation software that two elements (the carry LUT and sum LUT) go together as oLcell. You should turn off this mapping OFF if you are using implementation software that dnot support this mapping. (Versions earlier than MAX+PLUS II Version 10.0.)

Exclude Gates

This field instructs LeonardoSpectrum to exclude the selected gates from the target libraryMultiple gates may be selected.


Altera FLEX, ACEX, and MAX Synthesis Assigning Device Pin Numbers to Primary

mary

ter

ion

Assigning Device Pin Numbers toPrimary I/Os

You can use the Input PowerTab on the Constraint Editor to assign pin numbers to the priI/Os or you can set thePIN_NUMBERattribute on a port interactively from the LeonardoSpectruminteractive command line shell. The syntax is as follows:

If you prefer to assign pin numbers from the HDL source code, you can insert aPIN_NUMBERattribute. The syntax is as follows:

For example:

LeonardoSpectrum translates thePIN_NUMBERproperty to the Altera-specificCHIP_PIN_LCproperty.

Mapping to the Logic Element (LE) inFLEX Devices

The following descriptions are provided as background information so you will have a greaunderstanding of how LeonardoSpectrum synthesizes and optimizes your design.

Fanin Limited Optimization

The key architectural feature of the FLEX CPLD is that the LE can be any function of fourinputs. A 4-input XOR uses the same area and is as fast as a 4-input AND gate. The functshown in the following equation can be solved in two ways.

Solution (1)

set_attribute -port name -name PIN_NUMBER -val value

ATTRIBUTE PIN_NUMBER OFsignal_name: SIGNAL IS: value

attribute pin_number of en: signal is “P14";

X = (A*(B+C))+(B*D)+(E*F*G*H*I)


Mapping to the Logic Element (LE) in FLEX Devices Altera FLEX, ACEX, and MAX

split

-

the

acedn a

You can decompose a function into a simpler AND/OR equivalent representation, and thenthe gates with large fan-in into multiple gates. Represented in AND and OR gates, X isdecomposed as:

Since T3 has more than four inputs, further decomposition is required:

After fully decomposing the design, you can use the Altera FLEX MAX+PLUS II place-androute software to place the design into physical LEs. In this example, T3 and T5 cannot bemerged because of fan-in limitations. Next, combine T1 with T4 and X with T2. This givesfollowing partitioning to four LEs:

The critical path is LE_4→ LE_3 → LE_1, resulting in three levels of LEs for the delay.

Solution (2)

A different decomposition of the equation yields partitioning into three LEs:

Since each of the three equations have no more than four inputs, each equation can be plinto a LE. This design, when implemented, has only two LEs in the critical path, resulting ifaster and smaller design.

Lookup Table (LUT) Mapping

Lookup table mapping puts logic into 4-input lookup tables and CASCADE gates with theobjective of minimizing the total number of lookup tables or to minimize the delay. In the

X = T1+T2+T3T1 = A*T4T2 = B*DT3 = E*F*G*H*IT4 = B+C.

T3 = E*F*G*T5T5 = H*I

LE_1: X = T1+(B*D)+T3LE_2: T1 = A*(B+C)LE_3: T3 = E*F*G*T5LE_4: T5 = H*I

X = T1+(T2*E)T1 = A*(B+C)+(B*D)T2 = F*G*H*I


Altera FLEX, ACEX, and MAX Synthesis Mapping to the Logic Element (LE) in

le, a

atic

output EDIF netlist, the lookup table boundaries are marked with LCell buffers. For examp4-1 multiplexer description follows:

LUT mapping maps this multiplexer to two 4-input LUTs and one cascade gate. The schemof the mapped circuit is shown inFigure 10-1.

Figure 10-1. Mapped Circuit Schematic

LeonardoSpectrum decomposes the LUTs,Figure 10-1, to AND-OR gates for output toMAX+PLUS II. The output netlist is represented inFigure 10-2.

Figure 10-2. Output Netlist

module mux4 (out, in, sel) ;output out ;input [3:0] in ;input [1:0] sel ;assign out = in[sel];endmodule

in(0)

xmplr_INST_4

in(1)

sel(0)

in(2)

in(2)

xmplr_INST_3

LeoRG 19

I0

I1

I2

I3

0

F4_LUT

xmplr_INST_5

sel(1)

I0

I1

I2

I3

0

F4_LUT

CASCADE2

I0

I10

out_rename

I0 0

F1_LUT

out

LeoRG 20

out

in(2)

sel(1)

in(1)

sel(0)

in(3)

in(0)

AND2

OR3

IN1

IN2

AND2

IN1

IN2

AND2

IN1

IN2

NOTINV

NOT

AND2

IN1

IN2

INV

NOTINV

NOTINV

NOTINV

NOTINV

IN1

IN1IN3

IN2

NOTINV OR3

IN1

IN3

IN2AND2

IN1

IN2 NOTINV

Y

Y

Y

Y

Y

Y

YY

xmplr_INST_13

CASCADE


Managing the Inclusion of Modules Altera FLEX, ACEX, and MAX Synthesis

dignedasterLEX

ures

re.

Managing the Inclusion of Modules

Understanding LeonardoSpectrum Modgen

LeonardoSpectrum supports various technology-specific implementations of arithmetic anrelational operators used in VHDL or Verilog. Since these implementations have been desoptimally for a specific target technology, the synthesis results are usually smaller and/or fand take less time to compile. LeonardoSpectrum supports module generation for Altera F6000, FLEX 8000 and FLEX 10K.

The following operators are supported for Altera FLEX technologies:

• Relational Operators = /= < <= > >=

• Arithmetic Operators + - *

• Miscellaneous Functions: counters (up/down, loadable, etc), RAMs,incrementer/decrementer, absolute value, unary minus

The module generator for each technology uses dedicated hardware resources wheneverpossible. Therefore, modgen implementation of operators, such as addition, subtraction,counters, relational operators is generally smaller in area and faster in delay.

Examples:

• Adder in FLEX modgen is implemented using dedicated CARRY chain available inFLEX architectures to implement the adder carry logic. This leads to very fast carrypropagation and results in excellent timing performance.

• Counters in FLEX modgen make use of counter modes available in FLEX architectwhich results in faster and smaller designs.

• RAMs in FLEX 10K modgen use dedicated RAMs available in FLEX 10K architectu

Modgen Options

As shown inTable 10-1, you can control the modgen implementation by selecting from theoptimization options.


Altera FLEX, ACEX, and MAX Synthesis Managing the Inclusion of Modules

her

t

ic

Table 10-1. Modgen Options

Mapping Combinatorial Logic to Embedded ArrayBlocks (EABs)

By default, the MAX+PLUS II Compiler maps memory and other LPM functions to EABs inFLEX 10K and ACEX 1K devices. In addition, you can direct the compiler to implement otcombinatorial logic to an EAB by attaching animplement_in_eab attribute to an instance.

Optimize Options On/Off Interactive Command LineShell

Batch Mode

Auto - Picks smallest ifoptimization in areamode; and picks fastestif optimization in delaymode.

on(default

)

set modgen_select auto -select_modgen=auto

Smallest - Picks thebest compactimplementationavailable.

off set modgen_select smallest -select_modgen=smalles

Small - Picks acompactimplementation.

off set modgen_select small -select_modgen=small

Fast - Picks a fastimplementation.

off set modgen_select fast -select_modgen=fast

Fastest - Picks thefastest implementationavailable.

off set modgen_select fastest -select_modgen=fastest

If Use Technology Specific Module Generation Library is selected then a technology-specifmodgen library is selected. If not selected, then a default library is used.



n
Following is a VHDL example that directs the compiler to implement the mult component iEAB logic.
...continued EABs example.

entity mult isport (A,B: integer range 0 to 15;Q: out integer range 0 to 255);

end mult;

architecture behavior of mult isbegin

Q <= A*B;end behavior;

entity eab_test isport (CLK,MAC,RST:bit; A,B: integer range 0 to 15;Q: buffer integer range 0 to 255);

end eab_test;

architecture behavior of eab_test issignal P: integer range 0 to 255;

component mult;port (A,B: in integer range 0 to 15;Q: out integer range 0 to 255);

end component;

attribute logic_option:string;attribute noopt:boolean;attribute logic_option of ul:label is “implement_in_eab=on”;attribute NOOPTof ul:label is true;

beginU1:mult port map (A,B,P); -- Product of A and Bprocess (RST,CLK)begin

if (RST=’1’) then --ResetQ <= 0;

elseif (CLK=’1’ and CLK’event) then --Clock (edge triggered)

if (MAC=’1’) thenQ <= P+Q;

elseQ <= P;

end if ;end if ;end process ;

end behavior;



by

allow

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Implementing a Pipelined Multiplier

LeonardoSpectrum can implement pipelined multipliers for Altera devices.

Introduction

Pipelining combinational logic involves putting levels of registers in the logic to introduceparallelism and, as a result, improve speed.

Flip flops introduced by pipelining, typically incur a minimum of additional area on CPLDsoccupying the unused flip flops within logic cells that are already used for implementingcombinational logic in the design.

The LeonardoSpectrum Approach to Pipelining

LeonardoSpectrum requires certain constructs in the input RTL source code description tothe pipelined multiplier feature to take effect. These constructs call for “m” levels of registers tobe inferred at the output of the multiplier, wheremis an integer greater than 1.

Let n be the smallest integer that is greater than or equal to the base 2 logarithm of the widthe multiplier/multiplicand. LeonardoSpectrum automatically pipelines the multiplier bymoving the firstx levels of the inferred registers into the multiplier, where

x = m-1, for 2 <= m <= n

or

x = n-1, for m > n

Turning off the Pipelined Multiplier Feature

The pipelined multiplier feature is turned on by default. This feature can be disabled by sethe variablepipeline_mult to false.

set pipeline_mult false

Quality of Results

Post layout areas and delays are presented for Altera FLEX 10K. A comparison is madebetween the non-pipelined version and the 4-stage pipelined version of a 16-bit unsignedmultiplier; the non-pipelined version has one level of register at the output.

As shown inFigure 10-2, the speed improvements are significant. Moreover, in the contextan entire design, the percentage of additional area is minimal.



ed in

ed atet isa

edfers

Table 10-2. Effect of Pipelining on Quality of Results

Note: Clock Enable, Asynchronous Clear/Set

In the final pipelined multiplier, common clock enable and asynchronous clear are supportall levels of registers.

Asynchronous set is supported with these restrictions: Among the levels of registers inferrthe output of a multiplier, only the last level can have asynchronous set. If asynchronous spresent on an inferred register level other than the last, then the multiplier is not pipelined;message appears to that effect.

Source Code Examples of Pipelined Multipliers

The following source code examples represent an RTL level description of a 16-bit, unsignmultiplier. The operand inputs are registered on the first clock edge. LeonardoSpectrum infour levels of registers at the output of the multiplier and generates a 4-stage pipelinedmultiplier.

VHDL Template for an unsigned pipelined multiplier

library ieee ;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;

entity pipelined_multiplier is-- generic size is the width of multiplier/multiplicand;-- generic level is the intended number of stages of the-- pipelined multiplier;-- generic level is typically the smallest integer greater-- than or equal to base 2 logarithm of size, as returned by -- functionlog, which you define.generic (size : integer := 16; level : integer := log(size));port (a : in std_logic_vector (size-1 downto 0) ;b : in std_logic_vector (size-1 downto 0) ;clk : in std_logic;pdt : out std_logic_vector (2*size-1 downto 0));end pipelined_multiplier ;

architecture exemplar of pipelined_multiplier is

Altera FLEX 10K P & R Area (LCs) Delay, ns Mhz

non-pipelined 541 27.4 36.49

pipelined 587 12.8 78.12



type levels_of_registers is array (level-1 downto 0) of unsigned (2*size-1downto 0);signal a_int, b_int : unsigned (size-1 downto 0);signal pdt_int : levels_of_registers;beginpdt <= std_logic_vector (pdt_int (level-1));

process(clk)beginif clk'event and clk = '1' then-- multiplier operand inputs are registereda_int <= unsigned (a);b_int <= unsigned (b);-- 'level' levels of registers to be inferred at the-- output of the multiplierpdt_int(0) <= a_int * b_int;for i in 1 to level-1 looppdt_int (i) <= pdt_int (i-1);end loop;end if;end process;end exemplar ;

Verilog Template for an unsigned pipelined multiplier

module pipelined_multiplier ( a, b, clk, pdt);/** parameter 'size' is the width of multiplier/multiplicand;* parameter 'level' is the intended number of stages of the* pipelined multiplier;* which is typically the smallest integer greater than or equal * to base2 logarithm of 'size'*/parameter size = 16, level = 4;input [size-1 : 0] a;input [size-1 : 0] b;input clk;output [2*size-1 : 0] pdt;

reg [size-1 : 0] a_int, b_int;reg [2*size-1 : 0] pdt_int [level-1 : 0];integer i;

assign pdt = pdt_int [level-1];

always @ (posedge clk)begin// registering input of the multipliera_int <= a;b_int <= b;


Mapping Memory Elements to FLEX Devices Altera FLEX, ACEX, and MAX

riety

Thiss are

r in

e

// 'level' levels of registers to be inferred at the output // of themultiplierpdt_int[0] <= a_int * b_int;for (i = 1; i < level; i = i + 1)pdt_int [i] <= pdt_int [i-1];end

endmodule

Mapping Memory Elements to FLEXDevices

Inferring ROMs from the HDL Code

Currently you can implement ROM behavior in the HDL source code. You can do this withCASEstatements or you can specify the ROM as a table. The HDL is then converted to a vaof combinational logic in LeonardoSpectrum and mapped to LEs.

The ROM table can be mapped into a combination of decoders, muxes, or constant nets.depends on the output data bit pattern. Better utilization may be achieved if the ROM tablemapped to specialized blocks in CPLDs: for example, an EAB in the Altera FLEX10Ktechnology.

LeonardoSpectrum can detect ROMs and can support the mapping of ROM tables. Sinceseveral types of combinational logic can be mapped to ROMs, a flexibility is needed todetermine if a detected ROM should be implemented. The implementation will use defaultmapping or map the ROM into EABs.

ROM Detection

By default, the minimum size of a detected ROM is 256. If you want to detect ROMs smallesize, then you must set themem_minimum_size variable to a different value. For example:

set mem_minimum_size 64set mem_minimum_size 0 (to detect ROMs of all sizes)

ROM Data Extraction

After the ROM network is detected, the ROM data for the network must be elaborated. ThROM data is created and converted to the format expected by the target technology.

The following code segments illustrate how ROMs can be specified in your HDL source.


Altera FLEX, ACEX, and MAX Synthesis Mapping Memory Elements to FLEX

Verilog Design Example with ROM

Note: set mem_minimum_size 0module rom_32x4 (addr, dout);input [4:0] addr;output [3:0] dout;reg [3:0] dout;always @(addr)begincase (addr)0:dout = 4'b1110;1:dout_ = 4'b0100;2:dout_ = 4'b1110;3:dout_ = 4'b1001;4:dout_ = 4'b1111;5:dout_ = 4'b0011;6:dout_ = 4'b1000;7:dout_ = 4'b0001;8:dout_ = 4'b0110;9:dout_ = 4'b0001;10:dout_ = 4'b1100;11:dout_ = 4'b0000;12:dout_ = 4'b0110;13:dout_ = 4'b0000;14:dout_ = 4'b0100;15:dout_ = 4'b0110;16:dout = 4'b1110;17:dout_ = 4'b0100;18:dout_ = 4'b1110;19:dout_ = 4'b1001;20:dout_ = 4'b1111;21:dout_ = 4'b0011;22:dout_ = 4'b1000;23:dout_ = 4'b0001;24:dout_ = 4'b0110;25:dout_ = 4'b0001;26:dout_ = 4'b1100;27:dout_ = 4'b0000;28:dout_ = 4'b0110;29:dout_ = 4'b0000;30:dout_ = 4'b0100;



VHDL Design Example with ROM

Note: set mem_minimum_size 0Library ieee;use ieee.std_logic_1164.all;package Table_rom isType rom_type is array ( 0 to 32 - 1 ) of STD_LOGIC_VECTOR( 8 - 1 downto 0 ) ;constant ROM : rom_type :='("00011111","01111111","11111111","01111111","00011111","01111111","11111111","11111111","00111111","11111111","00000011","11111111","00001111","00111111","00001111","11111111","11111111","00111111","00001111","01111111","00111111","11111111","01111111","01111111","01111111","00111111","00111111","01111111","11111111","01111111",



Model ROM Code

The following is an example of VHDL code from model ROM, primitive, block code M01.

Input Data Sets for ROM Inferencing

VHDL example (one of two):

Library ieee;use ieee.std_logic_1164.all ;entity rom_example1 isgeneric ( DEPTH : in INTEGER ;DATA_WIDTH : in INTEGER ;ADDR_WIDTH : in INTEGER );port ( ADDR : in STD_LOGIC_VECTOR((ADDR_WIDTH-1)downto 0);DATAOUT : out STD_LOGIC_VECTOR((DATA_WIDTH-1)downto 0));end rom_example1 ;

Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use work.Table_rom.all;architecture ex1 OF rom_example1 is

beginproc_addr: process (ADDR)variable addr_int: integer range 0 to DEPTH-1;beginaddr_int := CONV_INTEGER(UNSIGNED(ADDR));DATAOUT <= ROM(addr_int);end process;end ex1;



VHDL example (two of two):

Library ieee;use ieee.std_logic_1164.all ;

entity top is

port ( addr_in : in STD_LOGIC_VECTOR((5-1) downto 0) ;

clock : in STD_LOGIC ;reset : in STD_LOGIC ;output_enbl : in STD_LOGIC;data_out : out STD_LOGIC_VECTOR((8-1) downto 0) ) ;

end top ;

architecture top of top iscomponent rom_example1

generic ( DEPTH : in INTEGER ;

DATA_WIDTH : in INTEGER ;ADDR_WIDTH : in INTEGER );

port (ADDR : in STD_LOGIC_VECTOR((ADDR_WIDTH-1)downto 0);

DATAOUT :out STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0));

end component ;

begin

M0 : rom_example1

generic map (DEPTH => 32 ,

DATA_WIDTH => 8 ,ADDR_WIDTH => 5 )

port map ( ADDR => addr_in,

DATAOUT => data_out);

end top ;



in the

s part

Mapping

The detected ROM network is mapped to a parameterized library module as shown in thefollowing table:

The target place and route tool then maps the LPM_ROM to the appropriate logic elementtechnology.

ROM Data File

LeonardoSpectrum generates a ROM data file that contains the ROM programming data aof the LPM ROM instantiation. This data is in the Intel Hex Object File format which issupported by Altera tools. The following example is for a 32x5 ROM:

Type of Inferencing ROMs

LeonardoSpectrum supports both synchronous and asynchronous ROMs.

LPM_TYPE element type (set to LPM_ROM)

LPM_WIDTH data size

LPM_WIDTHAD address size

LPM_NUMWORDS memory size

LPM_ADDRESS_CONTROL unregistered or registered

LPM_OUTDATA unregistered or registered

LPM FILE name of file containing the ROM data

:020000040000fa:08000000030f1f0f030f1f1f68:08000800071f001f0107011f83:080010001f07010f071f0f0f6e:080018000f07070f1f0f0f1f58:00000001ff



hegy.

f theROM

f

I. By

mes

Altera FLEX 10K Modgen Support for ROMs

The Altera FLEX 10K Modgen Library supports asynchronous and synchronous ROMs. Tlpm_roms are mapped to Embedded Array Blocks (EABs) in the Altera FLEX 10K technoloThis allows for better utilization of the device.

If the selected device contains the number of EABs that are required to implement a ROM odesired size, then LeonardoSpectrum automatically checks and creates lpm_roms. If thesize does not fit the available EABs, then the default implementation is used.

Mapping RAMs to the FLEX 10K Architecture

LeonardoSpectrum supports LPM RAM components for FLEX 10K. There are two levels osupport for RAMs in LeonardoSpectrum:

• RAM instantiation

LeonardoSpectrum supportsRAM_DQ, RAM_IOthrough modgen. You can instantiate theRAM_IO, RAM_DQcomponents from VHDL and Verilog. LeonardoSpectrum thenimplements them using Altera's LPM components (LPM_RAM_DQ, LPM_RAM_IO) andspecifies all the necessary names and properties that are required by MAX+PLUS Iinstantiating the modgenRAM_DQ, RAM_IO, you do not need to know what names andproperties are required.

• Direct LPM components instantiation

LPM components can be instantiated directly. You must specify the correct LPM naand properties required by MAX+PLUS II.

Instantiating RAMs (ram_dq) in the VHDL Source Code

Since the description ofram_dq is in file: $EXEMPLAR/data/modgen/flex10.vhd , you shouldrun analyze $EXEMPLAR/data/modgen/flex10.vhd in LeonardoSpectrum, before reading inyour design.

A VHDL Example

Note: before beginning the following VHDL example, read in thelpm_components packagefrom the Altera installation:

read $ALTERA_PATH/vhdl93/lpm/lpm_components.vhd



r a

Instantiating LPMs in the Verilog Source Code

You must use theDefparam construct to specify generic values for the instantiated RAM. Fodescription ofDefparams needed for each RAM and their default values, refer to theLibrary ofParameterized Modules (LPM), an Altera document.Defparms values that are not specified usedefault values.

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use work.LPM_components.all;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use work.lpm_ram_dq.all;

entity ram256x6 isport (

RD_ADR : in std_logic_vector (7 downto 9);WR_ADR : in std_logic_vector (7 downto 0);WR_DATA : in std_logic_vector (5 downto 0);WE : in std_logic;WR_ACCESS :in std_logic;RAM_DATA : out std_logic_vector (5 downto 0));

end RAM256x6;

architecture RAM256x6_A of RAM256x6 issignal ADR: std_logic_vector (7 downto 0);

beginADR <= WR_ADRwhen WR_ACCESS=’1’ else RD_ADR;RAM0:LPM_RAM_DQgeneric map (LPM_WIDTH=>6;LPM_WIDTHAD=>8)

port map (DATA => WR_DATA,ADDRESS => ADR,WE => WE,Q => RAM_DATA);

end RAM256x5_A;



Verilog example:

Verilog Example:

module lpm_ram_dq ( q, data, inclock, outclock, we, address) ;

parameter lpm_type = "lpm_ram_dq" ;parameter lpm_width = 1 ;parameter lpm_widthad = 1 ;parameter lpm_numwords = 2 ;parameter lpm_file = "UNUSED" ;parameter lpm_indata = "REGISTERED" ;parameter lpm_outdata = "REGISTERED" ;parameter lpm_addr_control = "REGISTERED" ;parameter polar_data = "NORMAL" ;parameter polar_inclock = "NORMAL" ;parameter polar_outclock = "NORMAL" ;parameter polar_we = "NORMAL" ;parameter polar_address = "NORMAL" ;parameter polar_q = "NORMAL" ;

input [lpm_width-1:0] data ;input [lpm_widthad-1:0] address ;input inclock, outclock, we ;output [lpm_width-1:0] q;

endmodule // lpm_ram_dq

module test_lpm_ram (q, data, inclock, outclock, we, address);

parameter width = 8 ;parameter widthad = 2 ;parameter numwords = 4 ;

input [width-1:0] data ;input [widthad-1:0] address ;input inclock, outclock, we ;output [width-1:0] q;

lpm_ram_dq Instance_r (q, data, we, inclock, outclock, address);defparam Instance_r.lpm_width = width;defparam Instance_r.lpm_numwords = numwords;defparam Instance_r.lpm_widthad = widthad;

endmodule



ry

Inferring RAM from the HDL Source Code

LeonardoSpectrum infers RAMs automatically from VHDL and Verilog. If the modgen librais loaded, the library uses the LPM description from modgen to implement the RAMs.

For example, consider this Verilog description:

LeonardoSpectrum infers an LPMram_dq for this design.

The following is a schematic of LeonardoSpectrum output:

module ram (clk, datain, addr, dataout);input clk;input [0:3] datain ;input [0:1] addr;output [0:3] dataout;reg [0:3] r[0:3];reg [0:1] addr_out;

assign dataout = r[addr_out];always @(posedge clk)begin

addr_out = addr;r[addr] = datain;

endendmodule

datain(1)

xmplr_INST_181_11_10_10

datain(2)

datain(3)

addr(1)

addr(0)

LeoRG 21

address(0)

address(1)

data(0)

data(1)

data(2)

data(3)

inclock

outclock

wedatain(0)

clklpm_ram_dq_4_2

q(0)

q(1)

q(2)

q(3)

Y

Vcc

'1'

dataout(3)

dataout(2)

dataout(1)

dataout(0)



.

Ms

h anwing

Using RAMs

Types of RAMs Inferred

LeonardoSpectrum supports two types of RAMs:

• RAM_DQ. RAM_DQ is a single-port RAM with separate input and output data lines

• RAM_IO. RAM_IO is a single-port RAM with bidirectional data lines.

Both of these RAM types support synchronous or asynchronous read and write. These RAare automatically inferred by LeonardoSpectrum from VHDL or Verilog.

The inferencing process distinguishes between RAMs that perform the read operation witaddress clocked or not clocked by the write clock (read address clocked). Both of the folloVHDL examples perform synchronous writes (inclock) and synchronous reads (outclock);LeonardoSpectrum recognizes these VHDL processes as RAMs:

• The first,entity ram_example1 , is when the read operation does not have a clockedaddress.

• The second,entity ram_example2 , is when the read operation does have a clockedaddress.



ss.
The first,entity ram_example1 , is when the read operation does not have a clocked addre
library ieee, exemplar;use ieee.std_logic_1164.all;use exemplar.exemplar_1164.all;entity ram_example1 is

port (data: in std_logic_vector(7 downto 0);address: in std_logic_vector(5 downto 0);we, inclock, outclock: in std_logic;q: out std_logic_vector(7 downto 0));

end ram_example1;

architecture ex1 of ram_example1 istype mem_type is array (63 downto 0) of

std_logic_vector (7 downto 0);signal mem: mem_type;

beginl0: process (inclock, outclock, we, address) begin

if (inclock = '1' and inclock'event) thenif (we = '1') then

mem(evec2int(address)) <= data;

if (outclock = '1' and outclock'event) then

end if ;end process ;

end ex1;

q <= mem(evec2int(address));

end if ;end if ;



Ms

al

The second,entity ram_example2 , is when the read operation has a clocked address.

Altera FLEX 10K Modgen Support for RAMs

The Altera FLEX 10K Modgen Library supports asynchronous RAMs and synchronous RAthat clock the read address with the write clock.

Generating Simulation Memory Models with Genmem

The Genmem flow is supported for Altera FLEX devices. Genmem is an altera utility thatgenerates simulation models for memory. You can generate RAMs, ROMs, FIFOs, and duport RAMs in different sizes. The memory can be synchronous or asynchronous. Genmemwrites the simulation model in VHDL or Verilog.

Use the following flow:

1. Run genmem to generate the desired memory.

library ieee, exemplar;use ieee.std_logic_1164.all;use exemplar.exemplar_1164.all;entity ram_example2 is

port (data: in std_logic_vector(7 downto 0);address: in std_logic_vector(5 downto 0);we, inclock, outclock: in std_logic;q: out std_logic_vector(7 downto 0));

end ram_example2;architecture ex2 of ram_example2 is

type mem_type is array (63 downto 0) ofstd_logic_vector (7 downto 0);

signal mem: mem_type;signal address_int: std_logic_vector(5 downto 0);

beginl0: process (inclock, outclock, we, address) begin

if (inclock = '1' and inclock'event) then

if (outclock = '1' and outclock'event) then

end if ;end process ;

end ex2;

address_int <= address;if (we = '1') then

mem(evec2int(address)) <= data;end if ;

end if ;

q <= mem(evec2int(address_int));



el in

ack-rilog

outes

y

ox by

ed as

For example:

This command generates a 256x15 asynchronous RAM model and writes the modVerilog.

2. Instantiate the RAM module in your Verilog input file.

LPM Instantiation

You can instantiate any LPM component from VHDL and Verilog formats.

Genmen Verilog Design

Synthesize your Verilog design with LeonardoSpectrum by targeting FLEX 10K.

• The-simple_port_names option is supported.

• Generate an EDIF netlist as the output. The genmem component is treated as a blbox by LeonardoSpectrum. The EDIF netlist that describes your design and the Vefile generated by genmem is used as input to MAX+PLUS II. The MAX+PLUS IIsoftware merges the genmem description into the top level design and places and rthe design.

• You need to include the module declaration in this file. In the following Veriloggenmem example, a module declaration is shown.

• Set thehdl_array_name_style variable to%s%dto ensure that port names generated bLeonardoSpectrum match port names generated by genmem.

• Generate EDIF netlist as an output. The genmem component is treated as a black-bLeonardoSpectrum.

The EDIF netlist that describes the design and the Verilog file generated by genmem is usinput to MAX+PLUS II place and route. The MAX+PLUS II software merges the genmemdescription into the top level design and places and routes it.

genmem asynram 256x15 -verilog


Writing the EDIF Output Altera FLEX, ACEX, and MAX Synthesis

ple:

are.

e

LeonardoSpectrum for Genmem

The genmem module declaration must be included in this file as shown in the Verilog exam

Writing the EDIF OutputEDIF is the only interface between LeonardoSpectrum and the Altera MAX+PLUS II softwThe following are known problems when writing out EDIF for Altera:

• Altera EDIF file name should match the design name. The design name, and the filname are case sensitive. You can change the design name if needed by using themovecommand in LeonardoSpectrum.

• If the hierarchy is preserved for hierarchical designs, LeonardoSpectrum writes outhierarchical EDIF. If sub-modules have busses on the boundary, usuallyLeonardoSpectrum renames these busses.

module ram_example ( addr, we, d, o);input [0:7] addr;input we;input [0:14] d;output [0:14] o;

asyn_ram_256x15 i1(.Address(addr), .WE(we), .Q(o), .Data(d));endmodule

// This module declaration is copied from the genmem file */module asyn_ram_256x15 (Q, Data, WE, Address);

parameter LPM_FILE = "UNUSED";parameter Width = 15;parameter WidthAd = 8;parameter NumWords = 256;

input [WidthAd-1:0] Address;input [Width-1:0] Data;input WE;output [Width-1:0] Q;

endmodule


Altera FLEX, ACEX, and MAX Synthesis Writing the EDIF Output

ndle

s.

For example:

This causes problems with Altera MAX+PLUS II EDIF reader since the reader does not hatherename construct properly. You can solve the problem in two ways:

(1)

Note: -simple_port_names creates simple name for vector ports.

(2)

Set the variablehdl_array_name_style to the Altera bus format.

LeonardoSpectrum then creates the following EDIF:

This EDIF is handled correctly by MAX+PLUS II.

LMF file: To take the EDIF generated by LeonardoSpectrum into MAX+PLUS II. Theexemplar.lmf file is required. Theexemplar.lmf file is installed in the$EXEMPLAR/data area.This file maps the cells LeonardoSpectrum writes to MAX+PLUS II primitives and functionMake sure that your MAX+PLUS II environment is set to pick up this.lmf file:

If using the MAX+PLUS II GUI then go to menuInterfaces-->EDIF Reader Settings andmakeLMF1point toexemplar.lmf and click on the checkbox forLMF1.

(port (rename p23 "Q(0)") (direction OUTPUT))(port (rename p22 "Q(1)") (direction OUTPUT))(port (rename p21 "Q(2)") (direction OUTPUT))(port (rename p20 "Q(3)") (direction OUTPUT))(port (rename p19 "Q(4)") (direction OUTPUT))(port (rename p18 "Q(5)") (direction OUTPUT))(port (rename p17 "Q(6)") (direction OUTPUT))(port (rename p16 "Q(7)") (direction OUTPUT))))))

set hdl_array_name_style = %s%d

(port Q0 (direction OUTPUT))(port Q1 (direction OUTPUT))(port Q2 (direction OUTPUT))(port Q3 (direction OUTPUT))(port Q4 (direction OUTPUT))(port Q5 (direction OUTPUT))(port Q6 (direction OUTPUT))(port Q7 (direction OUTPUT))))))


Using FLEX Designs as Input Altera FLEX, ACEX, and MAX Synthesis

ngle

acare

load

ralhe

s,

If you are using the MAX+PLUS II through command line then edit the.acf file. Search forEDIF_INPUT_LMF1 and makeEDIF_INPUT_LMF1 = exemplar.lmf . Search forEDIF_INPUT_USE_LMF1 and makeEDIF_INPUT_USE_LMF1 = ON.

Using FLEX Designs as Input

EDIF Input

To retarget a FLEX design into other technologies or to optimize a FLEX design usingLeonardoSpectrum, the design must fit into a single FLEX device. This ensures that the siEDIF netlist generated by MAX+PLUS II captures the whole design. Also, the EDIF writermust be turned on when running the MAX+PLUS II compiler. If the design does not fit intosingle device, switch to a bigger device until the design fits. (LeonardoSpectrum does notwhat the input device is, only the input device family or technology.) Use the EDIF filegenerated by MAX+PLUS II as input to LeonardoSpectrum, with the FLEX library as thesource technology, and synthesize to the chosen technology. In LeonardoSpectrum, firstthe technology library, then read the design:

If the design cannot fit into a single device, let MAX+PLUS II partition the design into sevedevices and generate several EDIF files. Then, manually write an HDL file that connects tdevices correctly. The MAX+PLUS II report file (multiple pin connections section) can behelpful in writing this file. Finally, read all the files into LeonardoSpectrum, first the EDIF filethen the top level file.

EDIF files generated by MAX+PLUS II contain, in addition to all functional I/O pins, a VCCpin and a GND pin. These pins are specific to Altera EDIF files. Consequently,LeonardoSpectrum has a special command for reading Altera files:read_altera .

1> load_lib flex8--source lib flex8 is loaded2> read_altera my_flex_design.edf3> load_lib z_tech4> optimize -target z_tech5> write output_file.edf--output netlist EDIF file, mapped to target technology z_tech


Altera FLEX, ACEX, and MAX Synthesis FLEX 6000/8000 Devices Supported

nd

FLEX 6000/8000 Devices SupportedDevices Families supported are: FLEX 6000, FLEX 8000, FLEX 10K/10KA/10KB/10KE aACEX 1K.

FLEX 6000 Family

Default Speed Grade: 2

Speed Grades supported: 2, 3

Devices Supported

EPF6010A TC100 TC144

EPF6016 TC144 QC208 QC240 BC256 ATC100 ATC144 AQC208

EPF6-24A TC144 QC208 QC240 BC256

FLEX 8000 Family


Speed Grades supported: 4, 3, 2

Devices Supported

EPF8282A LC84 TC100 VTC100

EPF8452A LC84 TC100 GC160 QC160

EPF8636A LC84 QC160 GC192 QC208 RC208

EPF8820A TC144 QC160 QC208 RC208 BC225 GC192

EPF81188A QC208 QC240 RC240 GC232

EPF81500A QC240 RC240 GC280 RC304


FLEX 10K Devices Supported Altera FLEX, ACEX, and MAX Synthesis

FLEX 10K Devices Supported

FLEX 10K Family


Speed Grades supported: 3, 4

Devices Supported

EPF10K10 LC84 TC144 QC208

EPF10K20 TC144 RC208 RC240

EPF10K30 RC208 RC240 BC356

EPF10K40 RC208 RC240

EPF10K50 RC240 BC356 GC403

EPF10K70 RC240 GC503

EPF10K100 GC503

FLEX 10KA Family


Speed Grades supported: 4, 3, 2, 1

Devices Supported

EPF10K10A TC100 TC144 QC208

EPF10K30A TC144 QC208 QC240 FC256 BC356 FC484

EPF10K50V R240 BC356

EPF10K100A RC240 BC356 FC484 BC600

EPF10K130V GC599 BC600

EPF10K250A GC599 BC600


Altera FLEX, ACEX, and MAX Synthesis FLEX 10K Devices Supported

FLEX 10KB Family


Speed Grades supported: 4, 3, 2, 1

Devices Supported

EPF10K100B QC240 QC208

FLEX 10KE Family


Speed Grades supported: 3, 2, 1, 1XES, 2XES

Devices Supported

EPF10K30E TC144 QC208 FC256 FC484

EPF10K50E TC144 QC208 QC240 FC256 FC484

EPF10K100E QC208 QC240 FC256 FC484

EPF10K130E TC144 FC484 FC672

EPF10K200E GC599 BC600 FC672


ACEX Devices Supported Altera FLEX, ACEX, and MAX Synthesis

ACEX Devices Supported

ACEX 1K Family


Speed Grades supported: 3, 2, 1, 1XES, 2XES

Devices Supported

EP1K10 TC100

EP1K30 TC144 QC208 FC256

EP1K50 TC144 QC208 FC256 FC484

EP1K100 QC208 FC256 FC484


Altera FLEX, ACEX, and MAX Synthesis MAX Family Devices Supported

MAX Family Devices SupportedDevices supported are: MAX 3000A, MAX5000, MAX7000/A/AE/E/S, MAX9000

MAX 3000A Family

Default Speed Grade: -10

Speed Grades supported: -4, -5, -6, -7, -10

Devices Supported

EPM3032 ALC44, ATC44

EPM3064 ALC44, ATC44, ATC100

EPM3128 ATC100, ATC144

EPM3256 ATC144, AQC208

MAX 5000 Family



Devices Supported

EPM5032 LC, LI, PC, PI, DC , JC

EPM5064 LC, LI , JC

EPM5128 ALC , LC, LI , JC, GC, GI

EPM5130 LC, JC, QC, GC

EPM5192 LC, LI , JC, GC, GI


MAX Family Devices Supported Altera FLEX, ACEX, and MAX Synthesis

MAX 7000 Family


Speed Grades supported: -6, -7, -10, -12, -15, -15T, -20

Devices Supported

EPM7032 LC44, LI44, QC44, QI44, TC44, TI44, VLC44, VTC44, VTI44

EPM7064 LC44, LI44, TC44, LC68, LI68, LC84, LI84, QC100, QI100

EPM7096 LC68, LI68, LC84, LI84, QC100, QI100

MAX 7000A Family


Speed Grades supported: -6, -7, -10, -12

Devices Supported

EPM7128A LC84, LI84, TC100 , TI100 , FC100, TC144, TI144, FC256

EPM7256A TC100, TI100, TC144, TI144, QC208, QI208 , FC256, FI256

MAX 7000AE Family


Speed Grades supported: -4, -5, -6, -7, -10, -12

Devices Supported

EPM7032AE LC44, TC44

EPM7064AE LC44, LI44, TC44, TI44, LC84, TC100, FC100

EPM7128AE LC84, TC100, FC100, TC144, FC256

EPM7256AE TC100, TC144, QC208, FC256

EPM7384AE TC144, QC208, FC256

EPM7512AE TC144, QC208, FC256, BC256


Altera FLEX, ACEX, and MAX Synthesis MAX Family Devices Supported

MAX 7000B Family


Speed Grades supported: -3, -4, -5, -6, -7, -10

Devices Supported

EPM7032B LC44, TC44, TC48

EPM7064B LC44, TC44, TC48, TC100, FC100

EPM7128B TC48, UC169, FC256,

EPM7256B TC100, FC100, TC144, UC169, QC208, FC256

EPM7384B TC144, QC208, FC256

EPM7512B TC100, TC144, UC169, QC208, BC256, FC256,

MAX 7000E Family


Speed Grades supported: -7, -10, -10P, -12, -12P, -15, -20

Devices Supported

EPM7128E LC84, LI84, QC100, QI100, QC160

EPM7160E LC84, LI84, QC100, QI100, QC160, QI160

EPM7192E QC160, QI160, GC160, GI160

EPM7256E QC160, RC208, RI208, GC192, GI192


MAX Family Devices Supported Altera FLEX, ACEX, and MAX Synthesis

8,

MAX 7000S Family



Devices Supported

EPM7032S LC44, LI44, TC44, TI44

EPM7064S LC44, LI44, TC44, TI44, LC84, LI84, TC100, TI100

EPM7128S LC84, LI84, QC100, QI100, TC100, TI100, QC160, QI160

EPM7160S LC84, LI84, TC100, TI100, QC160, QI160

EPM7192S QC160, QI160

EPM7256S RC108, RI208, QC208

MAX 9000 Family



Devices Supported

EPM9320 LC84, LI84, RC208, RI208, GC280, BC356, ALC84, ALI84, ARC208,ARI208, ABC356

EPM9400 LC84, RC208, RC240

EPM9480 RC208, RC240

EPM9560 RC208, RI208, RC240, RI240, RC304, RI304, GC280, BC356, ARC20ARI208, ARC240, ARI240, ABC356


nsrtus.nd

f,

Chapter 11Altera APEX Synthesis

APEX 20K/20KE/20KC FamilyLeonardoSpectrum supports mapping your design to the APEX Family of devices wichincluded APEX 20K/20KE/20KC, APEX II, Mercury and Excalibur. Depending on the optioselected, mapping to WYSISYG primitives is either done by LeonardoSpectrum or by QuaBy default, LeonardoSpectrum does mapping to WYSIWYG primitives. Quartus is place aroute software from Altera. The Altera APEX technology provides support for WYSIWYGdevice primitives.

Mapping Options

By default, mapping to WYSIWYG primitives isTRUEand mapping to complex I/Os isFALSE.

The variableapex_wysiwyg_support enables mapping to WYSIWYG ATOMs (an ATOM is aWYSIWYG primitive or cell) in APEX 20K/20KE devices. If you need to turn this variable ofyou must also setdont_lock_lcells to TRUE. For example,

set apex_wysiwyg_support falseset dont_lock_lcells true

The variable altera_map_complex_ios enables mapping to I/O flip flops. This variable isfunctional if the variableapex_wysiwyg_support is also set toTRUE. For example,

set altera_map_complex_ios TRUEset apex_wysiwyg_support TRUE

LeonardoSpectrum for Altera User’s Manual, v2001.1a 11-1

APEX 20K/20KE/20KC Family Altera APEX Synthesis

es:

t

tustusto

As shown in the following figure, thealtera_map_complex_ios option is also available on theGUI as Map I/O Registers.

LeonardoSpectrum APEX 20K/20KE Mapping

LeonardoSpectrum support for mapping to Altera APEX 20K/20KE WYSIWYG cells includ

1. By default, LeonardoSpectrum maps to all modes of Lcells:

• Counters

• QFBK_Counters

• Arithmetic

• Normal

2. Mapping to I/Os, including various complex I/O configurations is available.

3. RAMs/ROMS are now mapped to LPM_RAMs and LPM_ROMs. In the future, direcmapping to APEX 20K WYSIWYG primitives - RAM slices and Pterms (productterms) - will be provided by LeonardoSpectrum. LPM_RAMs and LPM_ROMs areimplemented as RAM slices by Quartus.

4. APEX 20K/20KE libraries are supported.

5. The current P&R GUI for Quartus provides support for the P&R flow using the QuarNativeLink API features. This allows you to access and modify designs in the Quardatabase. Currently, the EDIF format is supported for the output netlist. In contrastMAX+PLUS II, the choice box selection of "Bring up the Quartus GUI" allows theadditional step of setting up a project and completing the design compilation.

6. Wireload model support is functional.

7. When possible, LeonardoSpectrum supports the absorption of NOT gates intoWYSIWYG primitives.

LeonardoSpectrum for Altera User’s Manual, v2001.1a11-2

Altera APEX Synthesis APEX 20K/20KE/20KC Family

e

8. By default, GND/VCC are exported as cells. In Quartus, the preference is to exportGND/VCC as undriven nets. As shown in the following figure, you can writepower/ground as undriven net by selecting the options in the GUI, or you can set thfollowing variable in the Interactive Command Line:

set edifout_power_ground_style_is_net TRUE

Figure 11-1. Writing Power/Ground as Undriven Nets

APEX Technology Support

The APEX 20K/20KE devices use the best features from the current Altera FLEX 10K andFLEX 6000 family architectures as follows:

• The LE (logic element) structure for FLEX 6 remains the same.

• Each LE consists of 4 i/p LUT, D flip flops, carry and cascade chains.

• A LAB (logic array block) consists of 10 LEs.

• A set of 16 LABs + 1 ESB (embedded system block) makes a MegaLAB.

The LAB wide control signals are:

• Synchronous Load - FLEX 10

• Asynchronous Load - FLEX 6

• Synchronous Clear - FLEX 6

• Clock Enable - similar to FLEX 10

Click



s

t

ilar

uld

suchs forinput

erall

Note: References to FLEX 10K and FLEX 6000 in this chapter are for comparison purposeonly.

Note: There are two new LAB wide clock enable functions. The clock enable in FLEX 10Kutilizes one LUT input.

The following are carry chain changes:

• Counter mode incorporates lab-wide up/down or count enable.

• Dedicated logic to start counter from LE1.

The following are output configurations. The normal mode LE can implement three distincoutputs:

• combinational out

• registered output

• cascade output

APEX ESB (Embedded System Block)

The ESB can be usedm to implement RAM, ROM, or pterm logic as follows:

• Single-port RAMs and dual-port RAMs - both synchronous and asynchronous - simto FLEX 10KE.

• ROMs - similar to FLEX 10KE.

• pterm logic: Each ESB contains 32 literals with 16 macrocells in each ESB. You shomplement the following circuits with pterm: wide multiplexers, state machines, wideinput OR gates, and high fan-in sum-of-product equations.

Directing Quartus to Implement a Design Block inPTERM

Normally, APEX Embedded System Blocks are used to first implement memory elementsas RAM and ROM. In cases where you have a design doesn’t use all of the ESB resourcememory, but does have design elements such as wide multiplexers, state machines, wideOR gates, and high fan-in sum-of-product equations, then you can direct Quartus (throughLeonardoSpectrum) to use ESB resources to implement these circuits. This will improve ovsystem performance.


Altera APEX Synthesis APEX 20K/20KE/20KC Family

oduleDo

with

Assume, for example, that you have a complex state machine that is implemented as a min you HDL design, and you want to implement the state machine as pterm logic in ESBs.the following:

1. Choose the APEX technology, then read your design into LeonardoSpectrum.

2. As part of setting the design constraints, move to the Constraints FlowTab, then to theModule PowerTab.

3. Select the state machine block in the Module window, select the optionImplement InPTERM , then clickApply .

This actions flattens the block and tags the block to be implemented as pterm logic whenQuartus maps the logic to the resources in the chip.

If you are aLevel 3 user, you can perform the same action from a script or the InteractiveCommand Line shell by executing a command similar to the following:

implement_in_pterm .work.state_machine.rtl

Simulation with Pre-Layout Verification (Optional)

After optimization is complete, you may write out and complie a VHDL or Verilog netlist,compile the WYSIWYG cell models, and then test and simulate the design.

LPM (Library Parameterized Module) RAMs/ROMs

If you have LPM RAMs and ROMs in a design, then you should create simulation modelsgenmem (generate memory). Refer to theAltera FLEX Synthesischapter.



d astegerselect

nd

uto).

SMs

five

FSM Encoding (binary, gray, random, onehot, twohot,auto)

For auto encoding, LeonardoSpectrum varies the encoding based on bit width. Moreover,enumerated types with fewer elements than global integer lower_enum_break are encodebinary; while larger enumerated types are encoded as onehot. Values larger than global inupper_enum_break are encoded as binary. The auto default allows LeonardoSpectrum toencoding on a case-by-case basis.

NOTE: If LeonardoSpectrum selects onehot for your auto encoded design, then “onehotencoding” is printed for the log file of your design.

The encoding variable determines how LeonardoSpectrum encodes enumerated types, aimplements a state machine with a state vector of an enumerated type.

Twohot Encoding

Twohot encoding is now added to FSM encoding (binary, gray, random, onehot, twohot, aTwohot sets two flip flops high for each state. The twohot encoding requires more flip flopsthan binary and fewer flip flops than onehot. Twohot encoding may be beneficial to large Fwhere onehot uses too many flip flops, and binary requires too much decode logic.

Refer also to Chapter 2 in theLeonardoSpectrum HDL Synthesis Manual.

Note: Encoding is supported for APEX technologies with small enumerated types of up toelements.


Altera APEX Synthesis APEX 20K Devices Supported

APEX 20K Devices Supported

APEX 20K Devices Supported

EP20K100 TC144 QC208 QC240 FC324 BC356

EP20K200 RC208 RC240 RI240 BC356 FC484

EP20K400 BC652 BI652 FC672

APEX 20K Speed Grades

Default Speed Grade: -3,

Speed Grades supported: -3, -2, -1, -1X, -2X, 1V, 1XV, 2V

APEX 20K Wire Load

apex20_default apex20_quadrant_default

apex20_lab_default apex20_device_default

apex20_megalab_default apex20_uncons_default


APEX 20KE Devices Supported Altera APEX Synthesis

APEX 20KE Devices Supported

APEX 20KE Devices Supported

EP20K30E TC144 QC208 FC144 FC324

EP20K60E TC144 QC208 QC240 FC144 FC324 BC356

EP20K100E TC144 QC208 QC240 FC144 FC324 BC356

EP20K160E TC144 QC208 QC240 BC356 FC484

EP20K200E QC208 QC240 BC356 FC484 BC652 FC672

EP20K300E QC240 BC652 FC672

EP20K400E BC652 FC672

EP20K600E BC652 FC672 FC33

EP20K1000E BC652 FC672 FC33

EP20K1500E BC652 FC33

APEX 20KE Speed Grades

Default Speed Grade: -3,

Speed Grades supported: -3, -2, -1, -1X, -2X

APEX 20KE Wire Load

apex20e_default apex20e_quadrant_default

apex20e_lab_default apex20e_device_default

apex20e_megalab_default apex20e_uncons_default


Altera APEX Synthesis APEX 20KC Devices Supported

APEX 20KC Devices Supported

APEX 20KC Devices Supported

EP20K100 CT144C CF144C CQ208C CQ240C CF324C CB356C

EP20K200 CQ208C CQ240C CB356C CF484C CB652C CF672C

EP20K400 CB652C CF672C

EP20K600 CB652C CF672C CF33C

EP20K1000 CB652C CF672C CF33C

EP20K1500 CB652C CF33C

APEX 20KC Speed Grades



APEX 20KC Wire Load

apex20c_default apex20c_quadrant_default

apex20c_lab_default apex20c_device_default

apex20c_megalab_default apex20c_uncons_default


APEX II Devices Supported Altera APEX Synthesis

APEX II Devices Supported

APEX II Devices Supported

EP2A15 F672C

EP2A25 F672C

EP2A40 F672C

APEX II Speed Grades


Speed Grades supported: 7

APEX II Wire Load

apexii_default


Altera APEX Synthesis Mercury Devices Supported

Mercury Devices Supported

Mercury Devices

EP1M120F484C

EP1M350F780C

APEX 20KC Speed Grades

Default Speed Grade: 5ES

Speed Grades supported: 5ES, ES, and 8ES

APEX 20KC Wire Load

Default: STD-1

STD-1, STD-2, STD-3


Excalibur Mips Devices Supported Altera APEX Synthesis

Excalibur Mips Devices Supported

Excalibur Mips Devices

EPXM10F1020C

Excalibur Mips Speed Grades



Excalibur Mips Wire Load





Altera APEX Synthesis Excalibur Arm Devices Supported

Excalibur Arm Devices Supported

Excalibur Mips Devices

EPXA10F1020C

Excalibur Mips Speed Grades



Excalibur Mips Wire Load





Excalibur Arm Devices Supported Altera APEX Synthesis


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Appendix ASynthesisWizard Tutorial

Welcome to the SynthesisWizard tutorial. The SynthesisWizard is one of three ways tosynthesize your design; Quick Setup and FlowTabs are the other two ways. basically, theSynthesisWizard guides you throughUnderstanding the Quick Setup Flowdescribed on page1-4.

The SynthesisWizard consists of four steps that must be completed in the order presentedyou are a first-time user, then the SynthesisWizard is recommended to get you started rigaway.You can open the SynthesisWizard by clicking on the toolbar SynthesisWizard hat.

Note: While the SynthesisWizard is open, you are restricted entirely to the functions availaon the SynthesisWizard.

SynthesisWizard TourThe following screens and four steps give you a tour of the SynthesisWizard. The steps asto apply example choices and to use defaults.

• Step 1 - Set the Technology: Altera FLEX 6K

• Step 2 - Open the Input Files:pseudorandom.vhd (demo file)

• Step 3 - Set Global Constraints: 20 MHz

• Step 4 - Specify the Output File and Finish:pseudorandom.edf (default)

Wizard Buttons

Each of the four SynthesisWizard steps contains buttons that you can click at any time:

• Help: select for further assistance.

• Cancel: select to exit the SynthesisWizard.

• Back: select to return to the previous SynthesisWizard step, if any.

LeonardoSpectrum for Altera User’s Manual, v2001.1d A-1

SynthesisWizard Tour SynthesisWizard Tutorial

’s

Specifying the Technology Library - Step 1 of 4

Use the following steps:

Figure A-1. Specifying the Technology Library, Step 1of 4

1. Optional: Click the Altera logo to open your default web browser and access AlteraWeb page, if a Web page is available

2. Click FPGA to extend the tree and select Altera

3. Select Altera FLEX 6K

4. Click Next>

LeonardoSpectrum for Altera User’s Manual, v2001.1dA-2

SynthesisWizard Tutorial SynthesisWizard Tour

rum

Input Files, Step 2 of 4

Open your design Input Files.

Figure A-2. Opening the Input Files, Step 2 of 4

Use the following steps.

1. Set the working directory. The working directory is the place where LeonardoSpectsaves output files. Click on the Working Directory folder to open the Set WorkingDirectory dialog box. Highlight your working directory folder and click Set.

Note: The path to the working directory is also displayed in the status bar near thebottom of main window.



.
Note: The working directory is automatically saved and restored between sessions
Figure A-3. Setting the Working Directory

2. Click Cancelon Set Working Directory. You now return to Input Files

3. Next, click theOpen filesbutton and select the designpseudorandom.vhd

4. Click Open



ll be

z

5. Use the default Encoding Style for the state machine

Figure A-4. Set Input File(s)

6. Resource Sharing - If you select this option, then operators (adders, multipliers) wishared if they are disjoint (never used twice in the same clock cycle).

7. Click Next>

Global Constraints, Step 3 of 4

You can set the timing constraints for the entire design. Use these steps:

1. Use the global constraint defaults.

Type 20 in the Mhz field. A repeating wave form appears in the window with 20 Mhvalues.



ns.
2. If you desired, you can further customize the global constraints with the radio butto
Figure A-5. Global Clock, Step 3 of 4

3. If necessary, refer toSetting Timing Constraintson page6-3 for more information onhow to set timing constraints.

4. Click Next>



t

Output File, Step 4 of 4

The Output File dialog, shown inFigure A-6, allows you how to specify the location and formaof your FPGA netlist. The Downto: for Technology or Primitive Cells includes the selectedcells in your output file.

Figure A-6. Output File, Step 4 of 4

Use these steps:

1. Examine the output file pathname forpseudorandom.edf

2. If you desire, click the Filename button to change the output file pathname.



the

ar.

. If

3. Click Save/Cancel to return to the Output File, step 4 of 4.

Figure A-7. Set Output File

4. Use the Format: defaults.

5. Click Finish. The wizard closes and the synthesis run starts.

Run

During the synthesis run, you can view the Transcript in the Information Window and seeentire flow run. The device utilization report forpseudorandom.vhd is presented. If you closethe information window, click Window-> pseudorandom.vhd to open your file again. Duringsynthesizing, the toolbarStop icon turns red to indicate that the system is working. ClickStopto stop the run at anytime. The progress of the run appears in the lower left of the status bReadyindicates that the run is complete;Stop is grayed out.

Note: Before the run starts, you are prompted with a warning if an output file already existsyou click Yes, then the current output file is replaced.

Figure A-8. Screen A-8. Warning - Overwriting Output File


Index

INDEX

AACEX 1K devices supported,10-36Adobe Acrobat Reader,1-9Advanced (Level 3) Synthesis Flow,10-4Advanced Settings

FPGA PowerTabs,4-6Aliases

setting,3-9Altera

Quartus,9-5Quartus P&R Integration,9-5

Altera Place & RouteMAX+PLUS II, 9-3QuartusI,9-4

APEX 20K devices supported,11-7APEX 20K/20KE mapping,11-1APEX 20KC devices supported,11-9, 11-10APEX 20KE devices supported,11-8APEX technology

WYSIWYG primitives,11-1architecture, Altera MAX,10-2Attributes

relationship to commands/variables,3-3setting,3-4

Auto-Dissolve Hierarchy,7-10

BBatch Mode

LUT mapping,4-3black box,10-29Bubble Tristates,7-13Buffers

global,4-4

Ccarry

chain, Altera FLEX,10-10cascade

routing resource,10-2cascade gate

Altera FLEX,10-8CHIP_PIN_LC, Altera FLEX,10-7Clock Constraints

PowerTab,6-18Clock Skew,6-5

setting constraints,6-5Clocks

setting constraints,6-4Combinational Designs

setting constraints,6-12command line options

-auto,10-11-fast,10-11-fastest,10-11-simple_port_names,10-29, 10-31-small,10-11-smallest,10-11

Commandsbatch mode,3-9leonardo command,3-9relationship to variables/attributes,3-3spectrum command,3-9standard Tcl,3-3Tcl extensions,3-4using within Tcl scripts,3-4

Constraint Editormodule,6-27output,6-22signal,6-24

ConstraintsFlowTab,6-16

counterAltera FLEX,10-10

CPLDcomplex programmable logic device,1-1

DDatabase

object,5-4decrementer

LeonardoSpectrum for Altera User’s Manual, v2001.1d Index-1

INDEX [continued]

Index

Altera FLEX,10-10Defparms, Verilog,10-23Design

partitioning hints,7-6Design Browser,5-4

view options,3-29Design Files

opening,1-6, 5-2Design Partitioning,2-5

hints,7-6Devices Supported

ACEX 1K, 10-36APEX 20K,11-7APEX 20KC,11-9, 11-10APEX 20KE,11-8Excalibur Arm,11-13Excalibur Mips,11-12FLEX 10K, 10-34FLEX 10KA, 10-34FLEX 10Kb,10-35FLEX 10KE,10-35FLEX 6K, 10-33FLEX 8K, 10-33MAX 3000A, 10-37MAX 5000, 10-37MAX 7000, 10-38MAX 7000A, 10-38MAX 7000AE, 10-38, 10-39MAX 7000E,10-39MAX 7000S,10-40MAX 9000, 10-40Mercury,11-11

dont_touch Attributevs. noopt Attribute,7-8

EEDIF

bus,10-30Input,10-32netlist,10-30

EDIF (Input) PowerTab,5-12EDIF (Output) PowerTab,8-4embedded array block (EAB),10-2, 10-30Excalibur Arm devices supported,11-13Excalibur Mips devices supported,11-12Exclude Gates,4-7exemplar.lmf file,10-31expander, Altera MAX,10-3Extended Optimization Effort,7-5

FFalse Paths

setting constraints,6-12FIFO, Altera FLEX,10-2Files

.lsp file, 3-8

.scr file,3-8

.xdb file, 3-7exemplar.ini,3-6

Flattening Hierarchy,7-7FLEX 10K devices supported,10-34FLEX 10KA devices supported,10-34FLEX 10KB devices supported,10-35FLEX 10KE devices supported,10-35FLEX 6K devices supported,10-33FLEX 8K devices supported,10-33flip-flop

enable, Altera MAX,10-3FlowTabs

Constraints,6-16Input,5-8Optimize,7-9Output,8-2Place & Route,9-2Technology,4-5

FPGA TechnologyAdvanced Settings PowerTab,4-6

Ggenmem

LeonardoSpectrum for Altera User’s Manual, v2001.1dIndex-2

Index

INDEX [continued]

Altera,10-29support,10-28

Globalspecify clock period,6-17specify maximum delay,6-17

Global Areaoptimization,7-2

Global Buffers,4-4GND, pin,10-32GUI options

optimize options,10-11

HHDL

mixing design languages,1-2second language,1-2

hdl_array_name_style, variable,10-29, 10-31HDLInventor

bookmarks,3-23line numbering,3-21printing the window content,3-26templates,3-21

Helpabout,3-18contents,3-17

helponline,1-9

Hierarchyauto-dissolve,7-10flattening,7-7, 7-10preserve,7-10protecting,7-8

II/O

assign manually,4-2complex,4-2size of,4-2

I/O Mapping,4-4Icon

editing,3-19Exemplar’s logo,3-18task,3-18

incrementerAltera FLEX,10-10

Information windowprinting the content,3-20transcript,3-23

InputFlowTab,5-8

Input Arrival Timesetting constraints,6-9

Input shortcuts,5-9Input Signal Constraints

PowerTab,6-20Interactive Command Line,4-3

list commands,5-5list variables,5-5

interactive command line shell,10-11Internal Signal Constraints

PowerTab,6-24Introducing,1-1

LLABs, Altera,10-3LCELL

primitive, 10-9Library

cell, 5-3defined,5-3primitives,5-3

Loadinga technology library,4-2

Lock LCellsAltera,10-6

logicarray block, Altera,10-2element, Altera,10-2

lookup tableAltera FLEX,10-8


INDEX [continued]

Index

Lookup Table Mapping,4-3lookup table mapping

Altera,10-8LPM

instantiation,10-23LPM_RAM_DQ, component,10-22LPM_RAM_IO, component,10-22

Mmacrocell,10-3Main Window

banner,3-13header,3-13major elements,3-12Quick Setup vs Advanced FlowTabs,3-13

Main windowinformation window,3-20menu bar,3-13startup,3-10

MappingI/O mapping,4-4lookup table,4-3

MAX 3000A devices supported,10-37MAX 5000 devices supported,10-37MAX 7000 devices supported,10-38MAX 7000A devices supported,10-38MAX 7000AE devices supported,10-38, 10-39MAX 7000E devices supported,10-39MAX 7000S devices supported,10-40MAX 9000 devices supported,10-40Mercury devices supported,11-11Mixed Synchronous and Asynchronous

Designssetting constraints,6-13

Modgen librarydefined,5-6

Module ConstraintsPowerTab,6-26

move command,10-30Multicycle Paths

setting constraints,6-11Multiple Asynchronous Clocks,6-8Multiple Synchronous Clocks,6-6

NNet,5-3noopt Attribute

vs. dont_touch Attribute,7-8

OObject Names,5-4Opening Design Files,1-6Operators,5-3

how they are inferred,5-6operators

arithmetic,10-10relational,10-10

Optimizationextended effort,7-5global area,7-2

Optimization Effortsetting from the Quick Setup FlowTab,1-7

OptimizeFlowTab,7-9

optionHDL languages,1-2

Output FlowTabs,8-2Output Required Times

setting constraints,6-10Output Signal Constraints

PowerTab,6-22

PPartitioning,2-5Partitioning Hints,7-6Partitioning Your Design,2-5Path Constraints

PowerTab,6-28pin location

Altera,10-7


Index

INDEX [continued]

pin_number, attribute,10-7Pipelined multiplier

Altera,10-13Place & Route FlowTab

Altera MAX+PLUS II, 9-2Place and Route tools

setting the pathname to,1-7Port instance,5-3PowerTabs

Clock Constraints,6-18EDIF, 8-4FPGA Advanced Settings,4-6Input Signal Constraints,6-20Input-EDIF,5-12Input-Verilog,5-11Input-VHDL, 5-10Internal Signal Constraints,6-24Module Constraints,6-26Output Signal Constraints,6-22Output-EDIF,8-4Output-SDF,8-5Output-Verilog,8-6Output-VHDL,8-7Path Constraints,6-28Report Constraints,6-30SDF,8-5Verilog, 8-6VHDL, 8-7

Pre-Optimizationwhat is it?,5-7

PrintingHDLInventor window,3-26Information window content,3-20

product terms,10-3Project

new,3-9open,3-14optimization,3-8portable,3-8save,3-9, 3-14

save as,3-15starting a project,3-9synthesis runs,3-8

projectsave and restore,1-2

Project Files.lsp file, 3-8, 3-14.src file,3-8.xdb file, 3-7

project Level 3checkpoint,3-8

Projectsrecent,3-15

Protecting Hierarchy,7-8

QQuick Set Flow

opening design files,1-6Quick Setup Data Flow,1-4, 10-3Quick Setup Flow

activating integrated place and route,1-7setting the clock frequency,1-6setting the working directory,1-6

RRAM

Altera FLEX,10-2dual-port,10-2inferencing, RTL,10-25instantiation, Altera FLEX,10-22

RAM_DQcomponent,10-22

ram_example1,10-27ram_example2,10-28RAM_IO

component,10-22Reading VHDL Libraries and Packages,1-6Ready Message,A-8Report Constraints

PowerTab,6-30


INDEX [continued]

Index

Resetssetting constraints,6-4

Restoring a Project,3-7Results

check for critical paths,3-20check the fit,3-20

right mouse button (RMB),,1-1RMB(Right Mouse Button),3-11, 3-23ROM

Altera FLEX,10-2Root,5-4

libraries,5-3RTL

templates,3-21RTL Coding

checking your style,2-2supported state machine styles,2-2

RTL Coding Stylechecking your style,2-1

Runwarning prompt,A-8

Run Flow button,1-4, 1-7, 10-3

SSaving a Project,3-7Schematic

RTL, 7-14Scripts,5-5SDF (Output) PowerTab,8-5Selecting a Technology,1-6Session Settings

options,3-27Setting

aliases,3-9attributes,3-4the path to place and route tools,3-6variables,3-4

Setting Constraints,6-3clock skew,6-5global timing,6-3

input arrival time,6-9multicycle paths,6-11multiple asynchronous clocks,6-8multiple synchronous clocks per block,6-6on clocks,6-4on combinational designs,6-12on false paths,6-12on mixed synchronous and asynchronous

designs,6-13on resets,6-4output required times,6-10

Setting the Working Directory,1-6Source Code Editor,3-21spectrum command,3-9standard features

HDLInventor,1-2save and restore project,1-2

StartupMain window,3-10

Startup Filesexemplar.ini,3-6

State Machine Encodingsetting with Encoding Variable,2-3setting with Verilog pragmas,2-3

State Machinessupported styles,2-2

Status Barworking directory path,A-3

SynthesisWizard,3-11, A-1FPGA technology,A-2global clock,A-6input files,A-3output file,A-7step 1 of 4,A-2step 2 of 4,A-3step 3 of 4,A-6step 4 of 4,A-7

TTcl, 5-5


Index

INDEX [continued]

Tcl language,3-3Tcl script

command line with path,3-4interactive command line shell,3-4level 2,3-14level 3,3-14run script,3-4

TechnologyFlowTab,4-5

Technology FlowTab,1-6Technology Library

loading for a synthesis run,4-2Tip of the Day,3-10Toolbar

editing icons,3-19stop icon,A-8

Toolsvariable editor,3-31

Top Entity,5-10tristatable output,10-3

VVariable Editor,3-31Variables

altera_use_cascades,4-3dont_lock_lcells,4-6flex_use_cascades,4-6relationship to commands/attributes,3-3setting from the command line,3-4setting with the Variable Editor,3-4

VCC, pin,10-32Verilog

full case,5-11input,5-11parallel case,5-11top module,5-11

Verilog (Input) PowerTab,5-11Verilog (Output) PowerTab,8-6Version number,3-18VHDL

architecture,5-10VHDL (Input) PowerTab,5-10VHDL (Output) PowerTab,8-7VHDL Libraries

reading,1-6, 5-2VHDL Packages

reading,1-6, 5-2Video demo,3-17View

instance,5-3port,5-3

Virtex-IIcontrol variables,10-4

WWildcards,5-4Working Directory,A-3

creating a simple structure,2-7setting,1-6

XXDB format,8-3


INDEX [continued]

Index


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