susanta k pal variable energy cyclotron centre 1/af, bidhan nagar, kolkata – 700 064, india much...

Susanta K PalVariable Energy Cyclotron Centre

1/AF, Bidhan Nagar, Kolkata – 700 064, India

MUCH Electronics: Indian Effort

Physics with FAIR: Indian PerspectiveMarch 8 to 10, 2010

10 March 2010 1Physics With FAIR: Indian Perspective, Susanta K Pal

•Introduction : PMD from SPS to RHIC and LHC•Electronics and Readout for STAR

•FEE Development•TRIGGER•DAQ

•Electronics and Readout for ALICE•FEE Development•TRIGGER•LV Distribution

•MUCH Electronics: •Understanding of Electronics•FEE •RORC

•INDIAN Contribution to CBM MUCH Electronics•Remarks


MUCH Electronics: Indian Effort

At SPS (WA93/WA98 Experiments)

Scintillator pads with wavelength shifting fibres using image intensifier + CCD camera systems readout. 3 X0 thick Lead converter

Scintillator pads of size: 10, 15, 20, 25 mm2

•WA93 (1990-92) : 8000 pads covering 3m2

•WA98 (1993-96): 53000 pads covering 21m2

At RHIC and LHC (STAR and ALICE experiments)

Honeycomb gas proportional counter with copper honeycomb cathode, gold plated tungsten wire anode, anode signal processing using GASSIPLEX and MANAS, 3X0 thick lead converter.

STAR : 83,000 cells, 1 sq.cm cross-section, 8mm gas depth. Installed in 2002 and data taking is going on

ALICE : 220,000 cells, 0.22 sq.cm cross-section, 5mm gas depth. Installed in 2008 and data taking is going on

PMD probes thermalisation (flow), phase transition (multiplicity fluctuation),Chiral symmetry restoration (charged-neutral fluctuation)

Introduction: Preshower Photon Multiplicity Detector (PMD)

SPS RHIC LHC CBM


WA98 PMD

53000 pads, 21 sq.m. area


PMD @ STAR(Identical with ALICE PMD TDR design)

Preshower Detector with fine granularity

• Two planes: Veto + Pre-shower

• Coverage: 2.3 – 3.9

• Total no. of cells: 82,944

• Distance from vertex: 550cm

•Cell cross section: 1.0 cm2, depth: 0.8 cm

• Readout: GASSIPLEX 0.7-3 + C-RAMS• 24 Supermodules, 144 Unit modules

• Rhombus geometry of unit modules

PMD front view

Joining of two halves


FEE boardWith 4-Gas Chips

Copper honeycomb

Bottom PCB

Top PCB

Basic design of PMD

70-pin connector


DETECTOR GAS-4 BOARDS FEE

BUFFER CRAMS

TRANSLATOR SEQUENCER

Detector signals processed by GASSIPLEX (16 channel Analog Signal Processor) chips.Entire Readout consists of 48 chains for 82944 channels.

Each Chain consists of : Translator ( NIM to + 2.5 V Levels) for control Signals 27 No. Gas-4 Boards (1728 channels) Buffer to carry Analog Mux Signal to Digitizer(CRAMS ,SEQ)

Clear,

CLK

T/HOLD

BLOCK DIAGRAM for READOUT SCHEME at STAR


Technology : Alcatel-Mietec-0.7m Silicon area : 3.63 x 4 = 14.5 mm2

Peaking time 1.2 sPeaking time adjust. 1.1 to 1.3 sNoise at 0 pF 530 e- rmsNoise slope 11.2 e- rms/pFDynamic range ( + ) 560 fC (0 to 2 V)Dynamic range ( - ) 300 fC (0 to –1.1 V)

Gain 3.6 mV/fCNon linearity 2 fCBaseline recovery .5% after 5 sAnalog readout speed 10MHz (50 pF load) Power consumption 8mW/chan. at 10 MHzOutput Temp Coeff. 0.05 mV/0C

SPECIFICATIONS

BLOCK DIAGRAM OF GASSIPLEX


Buffer Translator

Gas-4(M)Gas-4(N)

Protection Board

PCB LAYOUTS : GAS -4 Boards


80 Translator boards fabricated and tested at VECC

80 Buffer boards fabricated tested at VECC

8 –10 % Gas-4 Boards were found to be faulty after assembly.2000 GAS-4 boards assembled at KHMD BANGALORE

3000 Protection Boards assembled and tested at VECC


Physics With FAIR: Indian Perspective, Susanta K Pal

C-RAM Sequencer CRAMS

Translator,Gas-4 board, Buffer

Pedestal for 1728 channels

10 March 2010 11

VME

VME

NIM

NIM

NIM

RACK-1

CP

U

Se

qu

en

ce

rC

RA

MS

CR

AM

S

CR

AM

S

CP

U

Se

qu

en

ce

rC

RA

MS

CR

AM

S

CR

AM

S

CP

UEthernet SW

DAQ Room

Experimental Site

PMD01 PMD02

PMD03

VME Crate-1 VME Crate-2

PMD DAQ SETUP at STAR

Arrangement of C-RAMS


Most Crucial Challenges faced :

To Design the Trigger Logic - L0 of STAR is after 1 us

-Peaking time of Gassiplex is 1.2 usSolution: - Use PreTrigger form ZDC of BBC with L0 - Separate Trigger Logic for PMD was designed in tune with STAR main Trigger


PMD TRIGGER SETUP @ STAR Experiment


STAR PMD running since January, 2004


Photon Multiplicity Detector (PMD) in STAR

PMD

PMD in ALICE @ LHC


PMD in ALICE

, coverage 2.3-3.5, 2

Distance from IP 361.5 cm

Cell cross-section 0.22 cm2

Cell depth 0.5 cm

No. of UMs 48

No. of cells in a UM 4608

No. of HV channels 48

Signal processing MANAS

Total Cells 221184


Electronics Architecture for PMD in ALICEElectronics Architecture for PMD in ALICE

3 Level hierarchy

- Integrated preamplifiers (16 channels per chip)

• MANAS– Embedded read-out daugther board with

coding and zero suppression (64 channels)• MANU + MARC (digital asic)

– Concentrator and processing board• CROCUS


FEEFEEFeatures

– 64 cell inputs– Embedded on the chambers– On-board analog to digital

conversion• 12 bit / 32 µs for 64 channels

– Digital communication with upper level

• 20 Mbyte/s

– Zero suppression

MANAS MARC

DE

T

E

C

T

O

R

MANAS

MANAS

MANAS

MANAS

T/H

CLRCLK-1

CLK-2

Analog Out

Analog Out

ADC 0

ADC 1

CS

CLK-ADC

12 Bit ADC

12 Bit ADC

AD 7476

AD7476

KM 4110

KM4110

MARC

CAL

TO

KE

N-I

NT

OK

EN

-OU

T

CO

NT

RO

L S

IGN

AL

S

DIGITAL BUS-LVTTL

DA

TA

SIG

NA

LS

, LP

CL

K

LIN

K P

OR

T

Main Components: 1.MANAS (Multiplexed-Analog-Signal-Processor )2. MARC ( Muon-Arm-Readout-Chip )3. ADC (Analog to Digital Converter )


Timing sequence of the control signals for the MANAS-16 multiplexed readout.

MARC block diagram.


FEE Board-Top side

FEE-Board (Bottom side)

LVDS LVTTL Translator

Bridge Board (Digital buffer)

Readout Boards Using MANAS ( 4-Chips: 64 Channels) 4000 Boads

6 layer, Size 70*24 m 1 mm thick PCB

4 layer boards- Size 63*36 mm 1mm thick PCB


UM-long

FEE

FEE

LV

Flexible link

BB TB

Patch Cable

LVTTL bus

12 boards on UM, Back plane PCB

Vertical Mounting of Boards


Concentrator board :

FPGATRIGGER

FPGASIU

InterfaceSIU

INTERFACE BOARD

Debug

Trigger & config

DDL to RORC

JTAG

JTAG

Front board

JTAG

JTAG

Front board

JTAG

JTAG

Front board

JTAG

JTAG

Front board

JTAG

JTAG

Front board

JTAG

JTAG

CROCUS StructureCROCUS Structure

DSP Analog Device 21160

BGA 400 Pins at 80Mhz

EEPROM

TO VMEDISPATCHING

TO 10 PATCH

BUS

Front board : UP TO 10 PATCH connected via linkport and serial port

2 DSPs analog Devices

From 1 to 5 front boards •2 DSPs analog Devices, driving the front board

•2 DSPs for the event building, the monitoring, the debug.

•1 FPGA for the trigger and board control

•1 FPGA to make the interface with the SIU

•1 SIU interface board


Tra

nsl

at

or

Patch Bus

2 *3

2 ce

lls

FRONT

BOARD

FRONT

BOARD

FRONT

BOARD

CONCENTRTOR

BOARD

FRONT

BOARD

FRONT

BOARD

FRONT

BOARD

CONCENTRTOR

BOARD

DSP DSP DSP DSP

FFT

TTCRX

DSPDSP DSPDSP DSPDSP DSP

FFT

TTCRXTRIGGERL0

BUSY

LTUCTP

VME TRIGGER DISPATCHING

40 meters LVDSLINKPORTS TRIGGER

BUSY, and L0

DDLLDC

GDC

CROCUS

CHAIN

Total no of cells : 221184Total no of Modules : 481 module = 4608 cells.

1 CROCUS - 50 Patch Buses6 CROCUS – 300 Patch Buses

Connection of a ChainConnection of a Chain

8.5 mt


ALICE LV Distribution

Chain 1 Chain 2 Chain 3

Chain 4 Chain 5 Chain 6

LV In

3486- 48V supply

Filter-Box 3-phase supply

With senseWire

EASY 3000

A3009B LVDB

One detector module = (72 FEE) i.e. 6 chains with 12 FEE boards per chain

ALICE-FEE having 6chains in a module

DC-DC Converter

+2.5V-2.5V+3.3V

DAQ-ARCHITECTUREDAQ-ARCHITECTURE


Timing of the acquisition Sequence


Contribution to STAR and ALICE

•PMD with Full Electronics

•Readout Concentrator Board

•Integration of PMD DAQ with main STAR and ALICE DAQ

•EPICS based Detector control system at STAR

•PVSS based Detector Control System integrated with main ALICE DCS

•Tier2 for LHC Grid for processing large volume of data

Next, FOR MUCH Electronics at CBM Experiment


• measure: π, K

• measure: K, , , ,

• measure: D0, D±, Ds, c

• measure: J/, ' e+e- or μ+μ-

• measure: , , e+e- or μ+μ-

• measure: γ

Hadrons

Leptons

Photons

trigger <10 AGeV

trigger

trigger e+e-

offline

offline >10 AGeV

offline ?

offline for e+e-

trigger for μ+μ- ?

assume archive rate:few GB/sec20 kevents/sec

trigger on high pt e+ - e- pair

trigger ondisplaced vertex

drives FEE/DAQarchitecture

trigger μ+μ-

μ identification

Data Acquisition at CBM(FAIR)Data Acquisition at CBM(FAIR)

From Walter F.J. Mueller’s lecture10 March 2010 29Physics With FAIR: Indian Perspective,

Susanta K Pal

Conventional FEE-DAQ-Trigger Layout in HEPConventional FEE-DAQ-Trigger Layout in HEP

Detector

Cave

Shack

FEE

Buffer

L2 Trigger L1 Trigger

DAQ

L1 A

ccep

t

L0 Trigger

fbunch

Archive

Trigger

Primitives

Especially

instrumented

detectors

Dedicated

connections

Specialized

trigger

hardware

Limited

capacity

Limited

L1 trigger

latency

Modest

bandwidth

From Walter F.J. Mueller’s lecture10 March 2010 30Physics With FAIR: Indian Perspective, Susanta K Pal

Limits of Conventional ArchitectureLimits of Conventional Architecture

Decision time for first level trigger limited.

typ. max. latency 4 μs for LHC

Only especially instrumenteddetectors can contribute to

first level trigger

Large variety of veryspecific trigger hardware

Not suitable for complexglobal triggers like secondary

vertex search

Limits future triggerdevelopment

High development cost


Typical Self-Triggered Front-EndTypical Self-Triggered Front-End

• Average 10 MHz interaction rate• Not periodic like in collider• On average 100 ns event spacing

0 5 10 15 20 25 30 time

ampl

itude

50

100

a: 126 t: 5.6

a: 114 t: 22.2

Use sampling ADCon each detector

channel running withappropriate clock

Time is determinedto a fraction of thesampling period

threshold

From Walter F.J. Mueller’s lecture10 March 2010 32Physics With FAIR: Indian Perspective, Susanta K Pal

L1 Select

High

bandwidth

The way out .. use Data Push ArchitectureThe way out .. use Data Push ArchitectureDetector

Cave

Shack

FEE

DAQ

Archive

fclock

L2 Select

Self-triggered front-end

Autonomous hit detection

No dedicated trigger connectivity

All detectors can contribute to L1

Large buffer depth available

System is throughput-limited

and not latency-limited

Use term: Event Selection

Buffer


Front-End for Data Push ArchitectureFront-End for Data Push Architecture• Each channel detects autonomously all hits• An absolute time stamp, precise to a fraction of

the sampling period, is associated with each hit• All hits are shipped to the next layer (usually

concentrators)• Association of hits with events done later using

time correlation

• Typical Parameters:– with few 1% occupancy and 107 interaction rate:

• some 100 kHz channel hit rate• few MByte/sec per channel• whole CBM detector: 1 Tbyte/sec


Read-out ASIC to be used for MuCh is n-XYTER / CBM-XYTER

mixed signal chip process: AMS 0.35 μm CMOS 128 channels 1 test channel with analogue diagnostic output architecture for AC-coupling, employable for positive and negative signals self triggered, data driven de-randomizing, sparcifying readout at 32 MHz digital time stamp output analogue peak hight output maximum data loss at 32 MHz average input rate over 16 μs: 4% analogue pile-up registry

Key Features


programmable dead time local threshold adjustment Dynamic Range: 120000 e Shaping time and noise performance:

30 ns fast shaper at 30 pF input, 850 enc for positive signals, 1000 enc for negative signals 130 ns slow shaper at 30 pF input, 600 enc

Timing resolution ~ 2-3 ns, time stamp resolution 1 ns

Key Features contd..


MuCh Electronics PerspectiveMuCh Electronics Perspective

Main Issues :– Detector PCB design– FEE Board Design– LV distribution to FEEs– HV distribution to Detectors– Connectivity and Placement ROC Boards– Cooling design


Basic n-XYTER Readout ChainBasic n-XYTER Readout Chain

Detector

FEB ROCX

YT E R

XY

T E R

XY

T E R

AD

C

XY

T E RTag data

Tag data

Tag data

Tag data

ADC data

clockFP

GA

control

SFPM

GT

DCB

FP

GA

SFPM

GT

MGT

Front-EndBoard

Read-OutController

Data CombinerBoard

to otherROC's

to ABB

SFP

SFPM

GT

MGT

From Walter F.J. Mueller’s lecture


For next Test beam

Top copperPad area-67*73 Sq mm For 3mm. For 4mm - 88*97 sq mm

Detector PCB design

Main Features :Both 3 and 4mm square pad sizesNot Staggered (‘09 test beam module)Symmetric Square PadsMulti Layers ( 4) with GND PlanesSignal Tracks are distributed in 3 planes

•Reduce the capacitance•Track to Track spacing increases•Reduce Cross talk

Blind Vias for gas integrityGnd Tracks between Signal Tracks

Bottom copper

Connector with resistors

Top copper

GND Plane

Bottom copper

GND Plane

GND Plane

Connectors for FEBs

Inner 1

Inner 2


Slat Type

2m

20 ChambersWidth of each chamber 10 cm.

X-section of chamber

Chambers layout for MuChChambers layout for MuCh

Profile is less as compared to Square type (30cmX30cm) designSome Wastage of chamber space

Detector PCB design

Let us proceed with some conceptualModular Design with Slat Type


Inner 1 Inner-2 Bottom CopperTop copper

Blind vias from inner layers( blue)

Blind vias (red ) to inner layer

2.6 mm square pads

Pads arranged in one block of 32*8=256.

Connected to 300 pin connector.

Tracks - shorter and not closer .

can be easily duplicated for

bigger sizes. 40 such FEE Boards for One

Slat of 1mt. Length..

Each block read by 1 FEB with 2/4 n-XYTERs ( 128/64 Channels)

FEBs can be mounted horizontal or vertical

Modular Approach

Detector PCB design


10 March 2010 Physics With FAIR: Indian Perspective, Susanta K Pal 42

BLOCK DIAGRAM OF FEE BOARD

Wire Bonding Scheme Representative Diagram

WIRE BONDING 3D VIEW

COMPLEX PART OF FEE BOARD GERBER VIEW

Prototyping

3 CM X 3 CM

Small PCB made

at VEC

It has been found that the most of the pads are not suitable for bonding

Front-End Electronics Board (FEE) – PCB for Wire Bonding

•We are discussing with PCB manufacturrer very actively for 256 channels FEE board with our design which involves wirebonding and PCB fabrication to accommodate 50 micron pitch effectively

•We can also check fabrication capability of FEE board with the new design by GSI Gerber file

•It is observed that it will help us if the XYTER ASIC is a packaged chip

Crtical part o

f

FEE Prototype

Developmnt

FEB--Probable scheme??

64 channel chip-- No of Pin outs 125-150?

For inputs- 64 For I2c - 6For CLK - 6For SDA, SCl - 2I2C Reset - 2Reset 2 DATA (diffl) --- 18 ( 16 for digital, 2 analog)

Total -100 PLUS Bias ,GND, other control inputs -25 to 50 ??

Considering BGA144(1,27mm pitch) /

SQFP148(10*14) ???

with 148 pin count and if we arrange-see the board size-10cm*3.2cm

BGA-144

ADC

300 Pin CON

SQFP148

ADC

ROC CON


Block Diagram of ROC BoardBlock Diagram of ROC Board

Two nos. of such Boards are already fabricated in India

Functional testing is in progress

Diagram taken from CBM-Wiki page10 March 2010 44Physics With FAIR: Indian Perspective,

Susanta K Pal

Gas out

Conceptual sketch of Triple GEM chamber module

Gas in

Segmented LV power line/power plane on Detector PCB each power line is feeding 5-FEBsground plane of LV line is in other layer of PCB

HV

1 mt

10cm

To be decided

LV connector

40 FEBs in one module in 1mt slat with about 10240 channels


FEBs-LV Channels to be read= 500,000

One N-XYTER reads =128 channels. FEB with 2 n-XYTERS reads-256 channels No of FEB s Required = 500,000÷256 = 2000 No (512,000 channels).

Each ROC can handle = 2 FEBs (512 channels). No Of ROCs required =1000Nos.

LV Specifications

2chip Feb With 3.3 v supply the power dissipation =10watts.

2000 FEBs consume =2000x 10Watts =20KW.

One ROC need -3.5A @5V ( one FEB connected). With two FEBs it is 4A

1000 ROC s consume = 1000x5Vx4A=20KW.

Power consumption expected for 2000FEBs +1000 ROCs = 40KW


CAEN A3009B -2to 8 V, 9A @5V. Max =45W. Has 12 independent channels. Max 480Watts

For 1000 ROCS Need 1000÷12= 84 modules For 2000 FEBSs = 2000÷12= 167 modules. Need 167+84 =251 modules. Separate LV channels for FEB and ROC. Alternative:

Reduce LV channels to 168÷2=84 by using LVDB to feed 2 FEBS (from 1 channel)

Need 84+84 =168 modules.

No of 3009s in one EASY crate =4 (2KW) CAEN EASY crates Required = 250÷4=63 or 164 ÷4=41 With 2 channels 3486 has =48V /40A , Power Capacity =5KW3486 s required = 40KW÷5 = 8Nos. Filter for 3486 =8 Nos

One Branch Controller (A1676A) controls 6 EASY- 3000 Crates.

For 63/41 Crates we need = 11 /7 Branch controllers

LV distribution : some preliminary thoughts


Connectivity Between FEB and ROC

Radiation dose•ROC boards may be affected by this radiation environment•Plan to put the ROC boards 3mt apart from the 0-axis•Detail dose calculation is needed at that point (seems to be falling fast)•The breakdown value of TID is also to be investigated for ROC components

Cable Type• Length of the cable to be known for error free communication•Shielded twisted pair flat type may be a good choice

TID: Total Ionizing Dose at the outer edged of thedetector is around 10krad

Ref : http://cbm-wiki.gsi.de/cgi-bin/viewauth/Radiationstudies/WebHome?CGISESSID=2bce338388a71f099de8d3ca43e0f2b7


Tracking station plane

2m

ROC stack

3mt (approx)

Placement of ROC BoardsROC stack


FEE BoardInfra Structure Board

Optical Link to ROC

Some thoughts : Transmitting data through Optical Link

FEE BoardInfra Structure Board

Optical Link to ROC

Forced air cooling for FEE

Cool air input duct(above dew point)

Hot airExtraction duct

Air-tight enclosure


Indian Contribution to CBM MUCH Electronics

• India could supply complete electronics for MUCH

• XYTER integration for 0.5x106 detector channels:

-two chips (256 channels) to one hybrid FEE PCB (estimated

2000 boards)

• FPGA-based readout controller (ROC)

-adaptation and assembly ( ~500 boards needed)

• For a test case 2 ROC boards of current version have already

been fabricated in India


Remarks :Some Preliminary thoughts has been put for the design ofDetector PCB : Here we need the following for the final design

Type of Module ( Square or Slat or Sector) and its sizePad size

FEE PCB : Here we need the following for the final design

Type of package of XYTER chip (??) No. of channels in one XYTER chip ( 64 or 128 or 32??) Gap between chamber and absorber i.e maximum available profile for FEB for mounting ( Horizontal/Vertical)

Placement of ROC :Radiation dose near to the Detector.Detector Control System:EPICS or PVSS will be used for controlling/monitoring LV/HV/Temperature etc.(?)We need to finalise the LV/HV Modules

Selection of HV/LV and Cooling If radiation environment permits (at 3mt distance), we propose to use TRD electronics for MUCH as well.


susanta k pal variable energy cyclotron centre 1/af, bidhan nagar, kolkata – 700 064, india much...

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