stanford universitysmirc.stanford.edu/papers/isscc98s-derek.pdf · 2009-08-19 · stanford...
TRANSCRIPT
FA 8.1: A 115mW CMOS GPS Receiver
D. Shaeffer, A. Shahani, S.S. Mohan, H. Samavati, H. Rategh
M. Hershenson, M. Xu, C.P. Yue, D. Eddleman, and T.H. Lee
Stanford University
OVERVIEW
� GPS Overview
� Architecture
� Circuits� Experimental Results
� Summary
GPS OVERVIEW: TYPICAL RECEIVER ARCHITECTURES
Distinguishing Features:
� Typical on-chip PD
is 100mW – 500mW
� Off-chip LNA oractive antenna
� Off-chip IF filtering
� 1 or 2 bit quantization
PLL
Off-Chip
2
1- OR -
Dual-Conversion
2
PLL
Off-Chip
Single-Conversion
GPS OVERVIEW: SIGNAL STRUCTURE
� C/A code is a BPSK, D.S. spread-spectrum signal. Tc = 1�s, Tb = 20ms.
� Large processing gain. Gp = 10 log�
TbTc
�= 43dB
� Important fact: SNR� 0 dB at antenna! (PR � -130dBm)
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Subsequent image
this sideband.rejection suppresses
~ 20dB (Tr = 290K)Channel FilterGPS C/A Code
GPS P-Code
1.57542 GHz
2 MHz20MHz
-12 MHz -8 MHz -2 MHz 2 MHz 12 MHz8 MHz
2 MHz
Thermal Noise Floor
DownconvertIF RF
ARCHITECTURE: LOW-IF RECEIVER
Primary Goal: Make choices to minimize PD, maximize integration.
� Low-IF) On-chipactive channel filter.
� Image in GPS band )
Relaxed I/Q matching.
� Eliminate PLL prescaler
) Saves power / noise.
� 1-bit quantizationfor simplicity.
BandGap
π/2
M*f0
N*f0
I[n]
Q[n]
PLL(M=17)
(N=23)
f0=4.024MHz
2.036MHz
Signal Path
1.57542GHz
APD
APD=1.573384GHzN*M*f0
ARCHITECTURE: WEAVER IMAGE REJECTION
Question: Can we use 1-bit quantization in an image-reject architecture?
Key: Show that summing the two output channels yields 3dB improvement.
BA
+
-
I
Q
n(t)
I
Q� A: �IQ(t) = sgn [sin(2!t)]
� B: �IQ(t) = 0
� I/Q channels are de-correlatedafter the lowpass filter!
Answer: Yes, if the noise has equal sidebands and SNR � 0 dB. (As in GPS.)
CIRCUITS: LNA / MIXER
Vb
LOp LOm
RFm
IFA
Ibias
RFp
LNA Mixer
1550 1560 1570 1580 1590 1600Frequency (MHz)
2.0
2.2
2.4
2.6
2.8
3.0
Noi
se F
igur
e (d
B)
Measured LNA Noise Figure
NF = 2.4dB @ 1575MHz
Ibias = 4.9mA
Shahani, Shaeffer and Lee, ”A 12mW Wide Dynamic Range CMOS GPS Receiver,” ISSCC 1997
CIRCUITS: IFA
� Low input capacitance, high linearity.
� Load resistors terminate the active filter input.
Inp InmM1
M3
Ibias
Outp
M4
M2Outm
Ibias
-0.2 -0.1 0.0 0.1 0.2DC Input Voltage (V)
-40
-30
-20
-10
0
10
20
30
Vol
tage
Gai
n (d
B)
Simulated IFA Voltage Gain
CIRCUITS: GM-C FILTER (ARCHITECTURE)
� Design based on a 5th-order L-C elliptical prototype.
� The dynamic-range limiting block in the system.
Gy Gy Gy Gy
Bias CircuitReplica
Gyrators (2 Transconductors, ea.)
IFA
Gm
Gm-C Filter (LC Ladder Prototype)
CIRCUITS: GM-C FILTER (DESIGN APPROACH)
The filter is the most critical signal path element, and therefore requires the mostattention to detail. Some relevant ideas:
� Interesting fact: Fmin = 2 (1 + N). Independent of filter Z0!This implies a fixed amount of power gain to suppress filter noise.
� Fixed GP ) AV /p
Z0.Need to minimize Z0 to maximize dynamic-range.
� Seek linearization techniques that maximize Gm=Ibias .One sub-optimal approach would be linearization by degeneration.
� Use Class-AB techniques, if possible, to maximize power efficiency.
In short: It all depends on the transconductor!
CIRCUITS: GM-C FILTER (TRANSCONDUCTOR)
Use two square-law transconductors to build a linear, class-AB transconductor.A little positive feedback (M10) compensates for mobility degradation in M1.
M2
M10
M1
M5Ibias
M6
Inp InmOutp Outm
-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4DC Input Voltage (V)
0.90
0.95
1.00
1.05
1.10
Rel
ativ
e G
m
Simulated Gyrator Transconductance
With Positive FB (M10)Without Positive FB+/- 10% M10 Variation
CIRCUITS: PLL OVERVIEW
A research goal: Explore techniques that reduce PLL power consumption.
� Maximize Q of spiral inductors in RF section.
) Use patterned ground shields (PGS). (Also aids isolation.)C.Yue and S. Wong, ”On-chip spiral inductors with patterned ground shields for Si-based RF IC’s,”
VLSI Symposium, 1997
� Prescaler consumes a large amount of power, and generates noise.
) Eliminate prescaler by only doing phase comparisons during periodic“apertures” positioned around reference edges. This saves power andreduces switching noise.
� Accomplished with an “Aperture Phase Detector” (APD).
CIRCUITS: APERTURE PHASE DETECTOR (APD)
� Aperture opens when pre-charge period ends.
� Aperture closes when the first edge arrives, discharging the circuit.
ApertureOpens
DelayedReference
(Implicitly)
ApertureCloses
REFin
D
U
LOin
FFE1
FFE2
FFE3 Delay
ApertureTiming Diagram
t
DelayLOin
Phase Error
Problem: Loop can lock to any harmonic of reference!
CIRCUITS: PLL ARCHITECTURE
An interesting idea: With dual APDs, the loop should lock to the least-commonharmonic of the two references.
� Works in theory, if APDdetects frequency.
� Problem in practice:APD only detects phase.
) Acquisition problem.
� Better solution:Use acquisition aidplus APD.
fRF=15*f0
Apertures
f2=3*f0
f1=5*f0
1 period of f0
Example: N=5, M=3
N*M*f0 I
Q
f1=N*f0
f2=M*f0
PLL Architecture
EXPERIMENTAL RESULTS: FREQUENCY RESPONSE
0 5 10 15 20Frequency (MHz)
-80
-60
-40
-20
0F
requ
ency
Res
pons
e (d
B)
Signal Path Frequency Response
I ChannelQ ChannelSimulated
1.0 3.5
01
-3
Passband Detail
EXPERIMENTAL RESULTS: NOISE FIGURE
1.0 1.5 2.0 2.5 3.0 3.5 4.0IF Frequency (MHz)
3.0
6.0
9.0
12.0N
oise
Fig
ure
(dB
)
Coherent Receiver Spot Noise Figure(Pre-Limiter)
Fine Quantization1-bit Quantization
EXPERIMENTAL RESULTS: LINEARITY
-45 -40 -35 -30 -25 -20 -15 -10Input Power (dBm)
-80
-60
-40
-20
0
20
40O
utpu
t Vol
tage
(dB
Vrm
s)
Signal Path 3rd Order Intermodulation
Slope=3
EXPERIMENTAL RESULTS: BLOCKING PERFORMANCE
0 10 20 30 40 50 60Offset Frequency (MHz)
-60
-50
-40
-30
-20B
lock
ing
Sou
rce
Pow
er (
dBm
)
Receiver 1-dB Blocking De-Sensitization(No Front-End RF Filter)
INMARSATUplink Band
EXPERIMENTAL RESULTS: PLL SPURIOUS
1475 1525 1575 1625 1675Frequency (MHz)
-80
-70
-60
-50
-40
-30
-20
-10
0
10R
elat
ive
Pow
er (
dBc)
PLL Spurious
INMARSATUplink
f1 f2
f1-f2
EXPERIMENTAL RESULTS: PLL PHASE NOISE
104
105
106
107
108
Offset Frequency (Hz)
-140
-130
-120
-110
-100
-90N
oise
Pow
er D
ensi
ty (
dBc/
Hz)
PLL Phase Noise
HP8780A
HP8664A
PLL
EXPERIMENTAL RESULTS: OUTPUT SPECTRUM
0 1 2 3 4 5 6 7 8Frequency (MHz)
-120
-100
-80
-60
-40
-20
0M
agni
tude
(dB
FS
)
Receiver Output Spectrum(Pre-Correlation)
HP8664ASpur
EXPERIMENTAL RESULTS: CODE CORRELATION
-512 -384 -256 -128 0 128 256 384 512Code Phase
0.000
0.005
0.010
0.015
0.020N
orm
aliz
ed C
ross
-Cor
rela
tion
Mag
nitu
de
Non-Coherent Receiver OutputGold Code Cross-Correlation
SNR = 15dB
PERFORMANCE SUMMARY
Signal Path Performance PLL PerformanceLNA Noise Figure 2.4dB Loop Bandwidth 5MHzLNA S11 � -15dB Spurious Tones � -42dBcCoherent Receiver NF 4.1dB VCO Tuning Range 240MHz (� 7.6%)IIP3 (Filter-limited) -16dBm @ -43dBm Ps VCO Gain Constant 240MHz/VPeak SFDR 57dB LO Leakage @ LNA < -53dBmFilter Cutoff Freq. 3.5MHzFilter PB Peaking � 1dB Power/TechnologyFilter SB Atten. � 52dB @ 8MHz Signal Path 79mW
� 68dB @ 10MHz PLL / VCO 36mWPre-FilterGp 19dB Supply Voltage 2.5VPre-FilterAv 32dBTotalGp � 82dB Die Area 11.2mm2
TotalAv � 107dB Technology 0.5�m CMOSNon-Coherent Output SNR 15dB
ACKNOWLEDGMENTS
Rockwell InternationalDr. Christopher HullDr. Paramjit Singh
Tektronix, Inc.Ernie McReynolds
Defense Advanced Research Projects Agency