spheres avionics design - mitalvarso/thesis-phd/appendix - avionics.pdf · spheres avionics design...
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421
Appendix F
SPHERES AVIONICS DESIGN
This appendix presents detailed descriptions of the SPHERES avionics. The SPHERES
laboratory avionics sub-systems implements electronics for the satellites, communications
with the control computer, metrology beacons, and a beacon tester. This appendix also
presents the design of several expansion port items already in use. Each section presents
the functional block diagram and the complete schematics (when applicable) for all the
electronic components of the SPHERES laboratory:
• SPHERES nano-satellites
- Power & control panel
- Data processing unit (C6701 DSP / SMT375)
- Metrology
- Communications
- Propulsion
- Expansion Port
- Internal beacon
• Laptop communications
• Metrology Beacons
• Metrology Beacon Tester
• Expansion Port Items
422 APPENDIX F
F.1 SPHERES nano-satellites
The electronics of the SPHERES nano-satellites, shown in Figure F.1, are implemented in
two primary "electronics stacks", with several peripheral electronic boards. The groupings
are as follows (third level bullets indicate peripheral electronic boards which support the
primary board of that stack):
• First stack (power & propulsion)
- Power
Batteries (2x)
Power Switch
Circuit Breaker
Control Panel
- Propulsion
Propulsion LEDs
• Second stack (data processing)
- SMT375 (C6701 DSP)
- Metrology (Motherboard 1)
Metrology 6 (ultrasound / IR)
Accelerometer Boards
On-board beacon
- Communications (Mother board 2)
DR200x wireless boards (2x)
Expansion Port
APPENDIX F 423
Figure F.1 SPHERES avionics overview
Stack 1 - Power & PropulsionDSP Memory BusSerial LinesDigital I/O signalsAnalog signalsPower signals
Micro Processor(C6701 DSP)
Metrology AvionicsFPGA
CommunicationsAvionics
(PIC MCU’s)
A2D
US/IR12x
STLRF
STSRF
Watchdog
ControlPanel
Power Propulsion
Solenoids
Amplifiers
Accels.
Gyros.
ExpansionPort
BatteryPacks
Beacon
Stack 2 - Data
424 APPENDIX F
F.1.1 Power & Control Panel
Design Drivers
• Provide the necessary power and voltages for all sub-systems
- 3.3 V: DSP, Metrology, Communications
- 5 V: DSP, Metrology, Communications, Propulsion
- ±15 V: Metrology (gyros and accelerometers)
- 22 V: Propulsion
• Meet applicable ISS safety guidelines
• Maximize battery utilization
Functional Block Diagram
The power sub-system is comprised of three main type of electronic boards: battery packs,
control panel, and the power regulation board. The circuit breaker and power switch are
wired independently. The functional description, inputs, and outputs of each component
are presented below.
Battery packs
There are two types of battery packs: flight and rechargeable. The functions of the two
types are:
• Flight: Provides up to two hours of operations to the SPHERES nano-satel-lites through 8 AA alkaline batteries. It also provides diode and fuse protec-tion to meet NASA Safety requirements (triple redundancy).
• Rechargeable: Provides up to two hours of operations to the SPHERESnano-satellites through 8AA NiMH rechargeable batteries. The batterycharging circuit resides within the packs themselves, requiring only a 15Vdcexternal supply. The external supply can have an optional LED to indicatecharging status. The board provides the same diode and fuse protection asthe flight packs.
Its inputs and outputs are listed in Table F.1
APPENDIX F 425
Power Switch
The power switch is a two phase mechanical switch. The switch is two phase so that the
battery positive power connections are isolated when the switch is open (the SPHERES
are off), preventing any current from flowing between the battery packs. While not neces-
sary for NASA safety requirements, it allows the battery packs to remain inserted in the
satellites without risk. Its inputs and outputs are listed in Table F.2
Figure F.2 Power sub-system functional block diagram
Enable
Mainpowerswitch
12V unreg(6.4-13.6V)
5V RegulatorTraco TSI5.0S2ROSH
Max out: 2A - 10W
15V DC-DCMAXIM MAX772Max out: 1A - 15W
3.3V RegulatorTraco TSI3.3S2ROSHMax out: 2A - 6.6W
Magneticovercurrentcircuit breaker
5.0 V
3.3 V
15.0 V
Bypass cap.3300µF 16Velectrolytic
8AA 6.4-13.6V 8AA 6.4-13.6V
-15V DC-DCMAXIM MAX776Max out: 1A - 15W
-15.0 V
ToPropulsion
Control Panel
PowerEnableLow Bat
Reset /ResetPB/ENABLE
5.0 V LED-enable/LowBat
Watch dogVcc(unreg)
/RESET
WDOG
426 APPENDIX F
Circuit Breaker
The magnetic circuit breaker provides 5A current protection. A thermistor is connected in
series with the circuit breaker to prevent power-surges larger than 5A when the satellites
are turned on and the large bypass capacitor (3300µF) charges. Once heated the thermistor
has a resistance of approximately 0.1Ω. The inputs and outputs of this board are listed in
Table F.3
TABLE F.1 Battery packs signals description
Signal Type DescriptionFlightVin In Unregulated input voltage from 8AA batteries (6.4-
13.6V)Vout Out Protected, unregulated voltage (5.8-13.0V due to 0.6V
drop through diodes)GND Pwr Common reference groundRechargeableVin In Unregulated input voltage from 8AA batteries (6.4-
13.6V)Vout Out Protected, unregulated voltage (5.8-13.0V due to 0.6V
drop through diodes)Vsupply In 15V input voltage for recharging circuitFT Out Signal to external LED which indicates charging in pro-
cess (blinking) or done (solid on)GND Pwr Common reference ground
TABLE F.2 Power Switch signals description
Signal Type DescriptionTwo phase power switch which isolates the battery packs when turned off
Vin1, Vin2 In Protected, unregulated voltage from battery packsVout1, Vout2 Out Switched, unregulated voltage to circuit breaker
APPENDIX F 427
Control Panel
The control panel is the primary manual interface of the satellites. The panel mechanically
holds the power switch, although it is not connected electrically. The panel electronics
only include digital I/O lines powered through the regulated 5V supply. The elements in
the panel are:
• Reset button - creates a negative logic signal which connects directly to thewatchdog module, which in turn generates a correctly timed reset signal forthe rest of the electronics.
• Enable button - creates a negative logic signal which is sent directly to theSPHERES FPGA as a general I/O signal; the SPHERES Core Softwarechecks the state of this button to enable operations (go from "idle" to "ready"or "running" mode).
• Power LED - driven directly off the regulated 5V supply indicates when thepower is on; since it is driven directly off the 5V supply, it is only on whenthe supply operates correctly, giving a reasonable indication that the powerregulation module is operating correctly.
• Low Battery LED - the watchdog measures the unregulated battery voltageand indicates a low battery condition when there are approximately 20 min-utes remaining of operation.
• Enabled LED - the LED is driven directly off the SPHERES FPGA as a gen-eral I/O signal; it is turned on by the SPHERES Core Software when the sat-ellites are in a "ready" or "running".
The inputs and outputs of this board are listed in Table F.4
Power Regulation Board
The power regulation board is the most complex board of the power sub-system. It pro-
vides power regulation for the data stack and all other avionics1, contains the watchdog,
and serves as a bypass for the propulsion signals. The board outputs four voltages to the
TABLE F.3 Circuit breaker signals description
Signal Type DescriptionVin1, Vin2 In Switched, unregulated voltage from power switchVout Out Switched and protected, unregulated voltage to power
board
428 APPENDIX F
second stack: +3.3V, +5V, +15V, and -15V. The +3.3V and +5V signals are used through-
out the system to power electronic components. The ±15V powers the accelerometers and
gyroscopes. The power board is the mechanical attachment point for two of the gyro-
scopes, although no electrical signals from the gyroscopes pass through the board.
Table F.5 lists the inputs and outputs of this board (or refers to other tables as applicable).
1. The propulsion sub-system increases the unregulated voltage to 20V; the power board does not provide the higher voltage required by the propulsion circuit.
TABLE F.4 Control panel signals description
Signal Type DescriptionVcc Pwr Input +5V dcGND Pwr Common reference groundLED-enable In Enable LED control signalLED-lowbat In Low battery LED indicator control signal/Reset Out Reset signal to power board watchdog module/Enable Out Enable signal for SPHERES FPGA
TABLE F.5 Power regulation board signals description
Section Signal Type DescriptionPower to second elec-tronic stack
Vcc(+5V) Pwr +5V outputVcc(+3.3V) Pwr +3.3V outputVcc(+15V) Pwr +15V outputVcc(-15V) Pwr -15V outputGND Pwr Common ground
Data con-nector to second elec-tronics stack
THR 1-12 In Pass through signals for thrusters 1-12/Enable Out Enable button pass through signal/LED-enable In Enable LED pass through signal/Batlow Out Low battery output to DSPWDOG In Watchdog control signal from DSP/RESET Out Reset control line to second electronics
stack
APPENDIX F 429
Schematics
The schematics of the power sub-systems follow.
Data and power to propulsion board
THR 1-12 Out Pass through signals for thrusters 1-12Vcc(5V) Pwr 5V power for propulsion boardVcc(unreg) Pwr Switched, protected, unregulated voltage
for propulsion boardGND Pwr Common ground
Data to/from con-trol panel
See Table F.4
TABLE F.5 Power regulation board signals description
Section Signal Type Description
430 APPENDIX F
5 5
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APPENDIX F 431
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432 APPENDIX F
5
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B B
A A
SPH-1-0800-### -
PowerSwitch Schematic - REFERENCE ONLY, NOT A PCB
A
1 1Sunday, May 19, 2002
Title
Size Document Number Rev
Date: Sheet of
BAT2 +
BAT1 +
BAT2 +
BAT1 +
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11
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SPH-1-0800-215 A
Circuit Breaker Board
A
1 1Tuesday, September 17, 2002
Title
Size Document Number Rev
Date: Sheet of
SW1
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2 3
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1 1
APPENDIX F 433
5 5
4 4
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434 APPENDIX F
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APPENDIX F 435
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436 APPENDIX F
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APPENDIX F 437
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
1.25V = Rbot / (Rtop + Rbot) * Vthr
if Vthr = 6.8V (Low Battery @ 7.5V battery - .7V of thermistor voltage drop)
1.25V/6.8V = Rbot / (Rtop + Rbot)
if Rbot = 102 kOhm
Rtop = 442 kOhm
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438 APPENDIX F
F.1.2 Propulsion
Design Drivers
• Create a spike and hold signal for the solenoids as presented in Figure F.3
- Spike at +22V
- Spike hold time: 7ms
- Hold at +5V
- Minimum impulse bit: 5ms
- Maximum impulse bit: infinite
• Provide visual indication of solenoid states (open or closed)
Functional Block Diagram
Figure F.4 presents the functional block diagram of the propulsion system. A propulsion
board receives the propulsion inputs from the data processing stack (pass through in the
power board) and creates a spike and hold signal independently for each solenoid. The
driver signals are sent to the solenoid via shielded wire to reduce the EMI effects of the
spike on other circuits. A board with an LED attaches to the front face of the nozzle of
each solenoid to indicate its state (off = closed, on = open). The propulsion board creates
the +22V supply needed for the spike from the unregulated voltage input.
Figure F.3 Propulsion spike and hold timing diagram
time
outp
utin
put
22V
5V
0
1
0V
7ms
spike
hold
APPENDIX F 439
Propulsion Board
The propulsion board creates the spike and hold signal necessary to operate the solenoids.
The board utilizes a Maxim MAX668 step-up switching regulator to create 22V from the
variable 8-13V unregulated input. Each spike and hold circuit uses the schematic pre-
sented in Figure F.5 (with the necessary current limiting resistors and reverse voltage pro-
tection diodes). The inputs and outputs of this board are described in Table F.6.
Solenoid Board
The solenoid boards provide visual indication of the state of their corresponding solenoid.
Their small size allows them to be mounted directly on top of the connector side of each
nozzle, ensuring immediate correlation between an LED and a solenoid. The inputs and
outputs of this board are listed in Table F.7.
Figure F.4 Propulsion avionics functional block diagram
Figure F.5 Propulsion spike and hold circuit
5V
prop12
unregGND
thr13
thr123
LED
LED 2
2 Solenoid
Solenoid
Driver 1
Driver 12
22VSupply
LM555
22V 5V
in Out-
Out+
22V
Shield
440 APPENDIX F
Schematics
The schematics for the propulsion sub-system follow.
TABLE F.6 Propulsion board signals description
Signal Type DescriptionGND Pwr Common groundVcc(5V) Pwr +5V supplyVcc(unreg) Pwr Unregulated (8-13V) powerProp[1-12] In Command signals from the data processing stackPosDriver[1-12] Out Positive terminal for each solenoidNegDriver[1-12] Out Negative terminal for each solenoid
TABLE F.7 Solenoid board signals description
Signal Type DescriptionThr + I/O Positive terminal of signal / solenoidThr - I/O Negative terminal of signal / solenoid
APPENDIX F 441
5 5
4 4
3 3
2 2
1 1
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pIn
Pro
pO
ut-
NegDriver_4PosDriver_4
thr9
thr7thr8
thr12
NegDriver_1PosDriver_1
NegDriver_7PosDriver_7
NegDriver_6PosDriver_6
NegDriver_5PosDriver_5
NegDriver_12PosDriver_12
NegDriver_11PosDriver_11
NegDriver_10PosDriver_10
NegDriver_9
thr1
thr4thr3
thr2
thr5thr6
thr10thr11
PosDriver_3
PosDriver_2
NegDriver_3
NegDriver_2
PosDriver_8
PosDriver_9
NegDriver_8
Po
sD
rive
r_5
Po
sD
rive
r_6
Po
sD
rive
r_7
Po
sD
rive
r_8
Po
sD
rive
r_9
Po
sD
rive
r_1
0
Po
sD
rive
r_1
1
Po
sD
rive
r_1
2
Po
sD
rive
r_1
Ne
gD
rive
r_1
Ne
gD
rive
r_5
Ne
gD
rive
r_6
Ne
gD
rive
r_7
Ne
gD
rive
r_9
Ne
gD
rive
r_1
0
Ne
gD
rive
r_1
1
Ne
gD
rive
r_1
2
Po
sD
rive
r_4
Po
sD
rive
r_3
Ne
gD
rive
r_3
Ne
gD
rive
r_4
Ne
gD
rive
r_2
Po
sD
rive
r_2
Ne
gD
rive
r_8
thr1
thr2
thr3
thr4
thr5
thr6
thr7
thr8
thr9
thr1
0
thr1
1
thr1
2
442 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Pro
pu
lsio
n B
oa
rd 2
- S
PH
-1-0
80
0-2
02
-
So
len
oid
Co
nn
ecto
rs
A
21
6F
rid
ay,
Ap
ril 1
9,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
Po
sD
rive
r_1
Po
sD
rive
r_2
Po
sD
rive
r_4
Po
sD
rive
r_5
Po
sD
rive
r_6
Po
sD
rive
r_7
Po
sD
rive
r_8
Po
sD
rive
r_9
Po
sD
rive
r_1
1
Po
sD
rive
r_1
2
Ne
gD
rive
r_1
Ne
gD
rive
r_2
Ne
gD
rive
r_3
Ne
gD
rive
r_4
Ne
gD
rive
r_5
Ne
gD
rive
r_6
Ne
gD
rive
r_7
Ne
gD
rive
r_8
Ne
gD
rive
r_9
Ne
gD
rive
r_1
0
Ne
gD
rive
r_1
1
Ne
gD
rive
r_1
2
Po
sD
rive
r_1
0
Po
sD
rive
r_3
J4
TH
R-4
123
J8
TH
R-8
123
J1
2
TH
R-1
2
123
J1
TH
R-1
123
J5
TH
R-5
123
J9
TH
R-9
123
J2
TH
R-2
123
J6
TH
R-6
123
J1
0
TH
R-1
0
123
J3
TH
R-3
123
J7
TH
R-7
123
J1
1
TH
R-1
1
123
APPENDIX F 443
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Pro
pu
lsio
n B
oa
rd 2
- S
PH
-1-0
80
0-2
02
-
22
V S
up
ply
A
31
6F
rid
ay,
Ap
ril 1
9,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
VC
C(2
2V
)
VC
C(u
nre
g)
+C
13
3u
F
+C
22
2u
F
L1
22
uH
C4 1u
F
C7
0.2
2u
F
C6
0.0
01
uF
C3
1u
FR
20
.02
oh
ms
R3
12
.0k
R4
10
0 k
D1
MB
RS
340T
3
R1
20
0.0
k
C5
0.1
uF
U1
MA
X668
1 9
10 4 2
8 6 7 5
3
LD
O
Vcc
SY
NC
-/S
HD
N
RE
FF
RE
Q
EX
T
CS
+
PG
ND
FB
GND
N1
FD
S6
68
0
4
8 567321
444 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Pro
pu
lsio
n B
oa
rd 2
- S
PH
-1-0
80
0-2
02
-
Inp
ut
Co
nn
ecto
rs
A
41
6F
rid
ay,
Ap
ril 1
9,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
TH
R1
0T
HR
11
TH
R7
TH
R1
2
TH
R8
TH
R9
TH
R4
TH
R2
TH
R1
TH
R3
TH
R5
TH
R6
thr1
thr2
thr4
thr7
thr9
thr1
1th
r12
thr3
thr8
thr1
0
thr5
thr6
VC
C(5
V)
VC
C(u
nre
g)
JP
1
Inp
ut
12
34
56
78
91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
2
APPENDIX F 445
The following schematic repeats twelve times, once per signal/solenoid:5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Pro
pu
lsio
n B
oa
rd 2
- S
PH
-1-0
80
0-2
02
-
Pro
pu
lsio
n F
irin
g C
ircu
it
A
516
Frid
ay,
Ap
ril 1
9,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
VC
C(5
V)
VC
C(2
2V
)
+C
9.0
1u
R6
10
k
R8
2.2
k
R7
10
k
D4
DIO
DE
D2 DIO
DE
D3 DIO
DE
R5
59
.0k
Q1
2N
22
22
C
B
E
U2
LM
555
2 5
3 7 6
4
8
TR
CV
Q
DIS
TH
R
R
VCC
+C
10
.04
7u
+C
8.1
0u
Pro
pO
ut+
Pro
pIn
Pro
pO
ut-
446 APPENDIX F
F.1.3 Data Processing (C6701 DSP / SMT375)
Design Drivers
• Support other subsystems’ data processing needs
- Communications data processing
- Metrology computational support
- Propulsion thruster actuation
- Provide house-keeping information to user
Battery information
Tank usage
• Allow reconfiguration of control algorithms
- Enable the complete software to be changed to allow testing of programswith different configurations and goals
• Maximize processing power for available volume and power
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Propulsion LEDs - SPH-1-0800-501 A
Thursters LED Indicators
A
1 1Tuesday, September 17, 2002
Title
Size Document Number Rev
Date: Sheet of
THR-THR+
J2
Solenoid Out
12
D1
LED
J1
PropIn
12
R14.9k
D2
1N4148
APPENDIX F 447
- Minimize processing needs of ‘bus’ system to maximize processingpower available for control algorithms
Functional Block Diagram
A COTS product was selected to perform the data processing within each SPHERES sat-
ellite. The selected product is a Sundance Multiprocessor Technology Ltd SMT375 board
which features a Texas Instruments TMS320C6701 Digital Signal Processor (DSP). The
SMT375 board utilizes the Texas Instruments Module standard for the C40 DSP (TIM40),
used in the prototype design of SPHERES. The standard implements a 32 bit global data
bus with 31 address lines, plus six TI communications ports which split 32 bit data into
bytes for a maximum data speed of 20MBps. A block diagram (simplified from [Sun-
dance, 2003]) of the SMT375 board is presented in Figure F.6. The SPHERES metrology
FPGA interfaces via the global data bus, while the communications system utilizes the
commports.The features of the SMT375 board are summarized in Table F.8
Figure F.6 SMT375 functional block diagram
TMS320C6701
SDRAM4M x 32
SBSRAM128k x 32
FLASH512k x 32
VIRTEX FPGA
Global BusCommports
SDB
SDB
(2)
Global DataBus
Commports6x
448 APPENDIX F
The SMT375 interfaces to the rest of the sub-systems through the metrology FPGA board
via three 80-pin connectors. The signal descriptions of these connectors are explained in
the metrology and communications sections which utilize them.
F.1.4 Metrology
Design Drivers
• Provide real-time position and attitude information of each satellite
• Implements measurement circuitry for metrology
- One infrared transmitter command (protected)
- 12 infrared receiver channels
- 24 ultrasound receiver channels
- Six 12-bit A/D channels, up to 1KHz
• Propulsion register (to control solenoid valves)
- 12 outputs with read-back capability
• General output register
- Two outputs with read-back capability
• General input register
- Two inputs
TABLE F.8 Features of the SMT375 board
Form Factor Single-width TIM40CPU TMS320C6701Speed 167MHzFLOPS 1 GFLOPS peakRAM 16MB (4M x 32)Cache 512k (128k x 32)Commports 6 x 20MBpsProgramming C and C++Power Consumption 7 W
APPENDIX F 449
Functional Block Diagrams
Because the metrology motherboard is the only board which interfaces directly with the
SMT375 DSP board, it functions not only to support metrology, but also to provide gen-
eral input/output signals and pass-through of the commports and power to the communica-
tions system. To implement these functions the metrology system centers its design
around an FPGA as pictured in Figure F.7. The system interfaces to the twelve US/IR
boards, the internal beacon, three gyroscopes, and three accelerometers (with amplifiers).
An EEPROM stores the configuration of the FPGA and interfaces to a JTAG port to
update the programming as necessary.
The four boards that support the metrology sub-system (motherboard, US/IR, accelerome-
ter amplifier, and internal beacon) are described next.
Figure F.7 Metrology sub-system functional block diagram
Metrology Motherboard
DSPFPGA
A/D
Gyro
Amp Accel
US/IRBoard(12x)
Prop12x
ControlPanel
InternalBeacon
xmitID
reset
IR rcv
US rcv
IR xmt
5V
2
4
12 5
Exp.Port
15.0 VGND
5V15.0 V
JTAG
EEPR
OM
6
GND
GND
22
Power
Global bus
Comm.
Commport (3x)
450 APPENDIX F
Metrology Motherboard
The metrology system utilizes a Xilinx FPGA which interfaces with the DSP via the glo-
bal bus and implements general input/output for the propulsion and control panel boards.
The FPGA also collects the range measurements of the US/IR system independently of the
DSP, to minimize the load of the metrology system on the DSP. The FPGA implements its
own 25MHz counter which is reset automatically when an IR signal is received; registers
on the FPGA store the time taken to receive an ultrasound signal at each of the 24 receiv-
ers without interrupting the DSP. The DSP is only interrupted once after each beacon
transmits its signal (i.e., a total of five times when five beacons are in use, but not 120
times if each receiver interrupted). The parallel processing of the FPGA ensures that the
signals from each receiver are recorded correctly. The FPGA interfaces with a 12-bit ana-
log to digital converter to provide up to 1kHz data from the gyroscopes and accelerome-
ters. The board provides a single pole low-pass filter with a drop-off frequency at 300Hz
implemented with a simple RC circuit. Because the metrology motherboard is oriented in
the X plane, it hosts one accelerometer and its amplification circuit. Figure F.8 shows a
schematic of the FPGA firmware design.
Table F.9 describes the inputs and outputs of the metrology mother board.
TABLE F.9 Metrology motherboard signals description
Section Signal Type DescriptionFrom Power
Vcc(+5V) Pwr +5V powerVcc(+3.3V) Pwr +3.3V powerVcc(+15V) Pwr +15V powerVcc(-15V) Pwr -15V powerGND Pwr Common ground
APPENDIX F 451
Data to power and propulsion stack
THR 1-12 Out Pass through signals for thrusters 1-12/Enable In Enable button signal/LED-enable Out Enable LED signal/Batlow In Low battery indicator signalWDOG Out Watchdog control signal/RESET In Reset
Data and power to SMT375
Vcc(+5V) Pwr +5V powerVcc(+3.3V) Pwr +3.3V powerGND Pwr Common groundC[0-5] D[0-7] I/O Commport data linesCACK[0-5] I/O Commport acknowledge signalCRDY[0-5] I/O Commport ready signalCREQ[0-5] I/O Commport request signalSTRB[0-5] I/O Commport strobe/RESET Out Reset LineIR_RCV_INT Out Infrared reception interrupt. It is asserted
when an IR is received so the DSP can prepare for a global metrology cycle
PADS_INT Out 1kHz interrupt. Provides timing for the DSP and indicates IMU data is available.
A0-A30 Out Global bus address linesD0-D31 I/O Global bus data linesRDY1 Out Global bus readyPAGE1 In Global bus page selectSTRB1 In Global bus strobeR/W1 In Global bus read/write/CE1 Out Global bus control lines enable/OE Out Global bus data lines enable/AE Out Global bus address lines enable
TABLE F.9 Metrology motherboard signals description
Section Signal Type Description
452 APPENDIX F
Data and power to communica-tions board
Vcc(+5V) Pwr +5V powerVcc(+3.3V) Pwr +3.3V powerVcc(+15V) Pwr +15V powerVcc(-15V) Pwr -15V powerGND Pwr Common groundA0-A30 Out Global bus address lines (expansion port)D0-D31 I/O Global bus data lines (expansion port)RDY1 I/O Global bus ready (expansion port)PAGE1 I/O Global bus page select (expansion port)STRB1 Out Global bus strobe (expansion port)R/W1 I/O Global bus read/write (expansion port)/RESET Out Reset line/Exp_port_in In High when an expansion port selects to
bypass the satellite US/IR metrology boards
IR_XMIT Out IR transmit commandUS-RX[11-12]-[1-2]
In Input ultrasound signals from the expan-sion port board
IR-RX[11-12] In Input infrared signals from the expansion port board
EXP A2D [0-2] In Input analog signals from the expansion port board
C[1,2,4] D[0-7] I/O Commport data linesCACK[1,2,4] I/O Commport acknowledge signalCRDY[1,2,4] I/O Commport ready signalCREQ[1,2,4] I/O Commport request signalSTRB[1,2,4] I/O Commport strobe
US/IR Boards (12x)
Vcc(+5V) Pwr +5V powerGND Pwr Common groundIR_XMIT Out IR transmit commandUS-RX[1-2] In Input ultrasound signalsIR-RX In Input infrared signal
TABLE F.9 Metrology motherboard signals description
Section Signal Type Description
APPENDIX F 453
Onboard beacon
Vcc(+5V) Pwr +5V powerVcc(+15V) Pwr +15V powerGND Pwr Common groundIR_RCV_INT Out IR Received interrupt signal - commands
the beacon to initiate its US transmit pro-cess
B-MCLR Out Beacon enable/resetB-NUM[0-3] Out Beacon configuration number
Gyros.(3x)
Vcc(+15V) Pwr +15V powerGND Pwr Common ground[X,Y,Z] Gyro In Gyroscope analog signal
Accels.(2x)
Vcc(+5V) Pwr +5V powerVcc(+15V) Pwr +15V powerVcc(-15V) Pwr -15V powerGND Pwr Common ground[Y,Z] Accel-Amp In Y and Z accelerometer amplified analog
signals[Y,Z] Temp-Temp
In Y and Z accelerometer temperature sensor signal
JTAG Vcc(+3.3V) Pwr +3.3V powerGND Pwr Common groundPTCK In ClockPTDO Out Data outPTDI In Data inPTMS In Select
TABLE F.9 Metrology motherboard signals description
Section Signal Type Description
454 APPENDIX F
Metrology US/IR Boards
The metrology ultrasound/infrared board receive and amplify the ultrasound signals emit-
ted by the global metrology beacons. They also transmit and receive the infrared signal
which initiates the global metrology process. Therefore, as pictured in Figure F.9, each
board consists of three main elements: infrared transmit, infrared receive, and ultrasound
receive. The infrared transmit circuit uses a transistor to drive 1A of current through an
Figure F.8 FPGA firmware design
APPENDIX F 455
infrared LED; the FPGA ensures the 1A pulse is no longer than 10µs and has a maximum
duty cycle of 10% to protect the LEDs. The infrared receive utilizes a COTS receiver
which directly outputs a logic signal to the FPGA. The ultrasound receive signal required
the use of a quad op-amp to amplify, rectify, and digitize the signal. A schematic of the
circuit is presented in Figure F.10. The signals of the US/IR boards are described in
Table F.9, reversing inputs and outputs.
Figure F.9 US/IR boards functional block diagram
Figure F.10 Ultrasound amplification schematic
US RX 1
IR RXUS RX 2
IR RX
IR TX
Amplifier Rectifier Comparator
Driver
5V
IR TX
Amplifier Rectifier
US RX 1
US RX 2
GND
Comparator
2.5V 2.5V
5V
US out+-
+-
+-
+-
OriginalSignal
AmplifiedSignal
RectifiedSignal
DigitizedSignal
456 APPENDIX F
Accelerometer Amplifier Boards
The selected accelerometers have an operational range of ±30g but are capable of measur-
ing accelerations with milli-g precision. Because the SPHERES thrusters create accelera-
tions in the milli-g range, the accelerometer require custom amplifiers to provide the
necessary 0-5V analog signal required by the A2D converter. The accelerometer operate
like current sources, therefore they require a sense resistor at the output to create a voltage
for measurement. The circuit selected a sense resistor which allows the use of a high-fre-
quency op-amp to amplify the input signal 40 times. The accelerometers also output a
temperature measurement signal from a thermistor, so that software can take into account
temperature changes. While not used in the initial implementation of SPHERES, the
accelerometer boards send the temperature signal to the FPGA in case it proves necessary
in the future. A description of the signals of the accelerometer boards is presented in
Table F.9, reversing inputs and outputs.
Internal Beacon
The internal beacon replicates an external beacon (see Section F.3 below), but omits the
infrared reception circuitry, does not use a manual switch, and utilizes custom power reg-
ulation circuitry. The infrared circuitry and ID number selector are replaced by signals
from the FPGA. The power sub-system provides regulated 5V. The internal beacon regu-
lates +15V to +12V using a linear regulator. Descriptions of the signals are presented in
Table F.9, reversing inputs and outputs.
Schematics
The schematics for all the metrology boards are presented next.
APPENDIX F 457
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
NOTES:
1. Place capacitors C1, C2, and C3 as close to the associated pins of U6 as
possible.
2. Place capacitors C4 and C5 as close to the associated pins of U5 as
possible.
3. Place capacitors C6 and C7 as close to the associated pins of U7 as possible.
Opti
onal
Plac
e as
close
to R
EF as
poss
ible.
Plac
e as
clo
se t
o RE
F as possible.
MB
1: M
etr
olo
gy
- S
PH
-1-0
800-2
12
A
A/D
Conve
rters
and R
efe
rence
B
19
Thurs
day,
Septe
mber
19, 2002
Titl
e
Siz
eD
ocu
ment N
um
ber
Rev
Date
:S
heet
of
AD
CLO
CK
AD
DA
TA
0
AD
DA
TA
3A
DD
AT
A4
AD
DA
TA
5A
DD
AT
A6
AD
DA
TA
7A
DD
AT
A8
AD
DA
TA
10
AD
DA
TA
11
AD
AR
DL
AD
AW
RL
AD
AC
SL
AD
AIN
TL
AD
DA
TA
1A
DD
AT
A2
AD
DA
TA
9
AD
BR
DL
AD
DA
TA
4
AD
DA
TA
8A
DD
AT
A7
AD
DA
TA
1
AD
BIN
TL
AD
DA
TA
11
AD
DA
TA
10
AD
DA
TA
3
AD
DA
TA
6
AD
DA
TA
9
AD
DA
TA
2
AD
BC
SL
AD
DA
TA
0
AD
DA
TA
5
AD
BW
RL
AD
CLO
CK
X-A
ccel-A
mp
Y-A
ccel-A
mp
Z-A
ccel-A
mp
X-A
ccel-
Tem
p
Z-A
ccel-T
em
p
X G
yro
Y G
yro
Z G
yro
EX
P A
2D
2E
XP
A2D
1E
XP
A2D
0
AD
AR
DL
AD
AW
RL
AD
AC
SL
AD
AIN
TL
AD
BR
DL
AD
BW
RL
AD
BC
SL
AD
BIN
TL
AD
CLO
CK
AD
CLO
CK
AD
DA
TA
0A
DD
AT
A1
AD
DA
TA
2A
DD
AT
A3
AD
DA
TA
4A
DD
AT
A5
AD
DA
TA
6A
DD
AT
A7
AD
DA
TA
8A
DD
AT
A9
AD
DA
TA
11
AD
DA
TA
0A
DD
AT
A1
AD
DA
TA
2A
DD
AT
A3
AD
DA
TA
4A
DD
AT
A5
AD
DA
TA
6A
DD
AT
A7
AD
DA
TA
8A
DD
AT
A9
AD
DA
TA
10
AD
DA
TA
11
AD
DA
TA
10
Y-A
ccel-T
em
p
VC
C(5
V)
VC
C(1
5V
)
U2
MA
X6250
18 7
2 3 46 5
NC
1N
C8
NC
7IN N
RG
ND
OU
TT
RIM
C1
4.7
uF
C46
TB
DC
47
TB
DC
48
TB
DC
50
TB
DC
51
TB
DC
52
TB
D
C53
TB
D
U1
MA
X1294A
EE
I
21
20
19
18
17
16
25
24
22
10 9 8 7 6 5 4 3 2 1
28
27
26 23
12
13
15
14
11
CH
0C
H1
CH
2C
H3
CH
4C
H5
RE
FR
EF
AD
JC
OM
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
VDD GND
RD
WR
CS
CLK
INT
C54
TB
D
C3
0.1
uF
C55
TB
DC
56
TB
DC
57
TB
DC
58
TB
D
U3
MA
X1294A
EE
I
21
20
19
18
17
16
25
24
22
10 9 8 7 6 5 4 3 2 1
28
27
26 23
12
13
15
14
11
CH
0C
H1
CH
2C
H3
CH
4C
H5
RE
FR
EF
AD
JC
OM
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
VDD GND
RD
WR
CS
CLK
INT
C5 1 u
F
C4 2.2
uF
C8
4.7
uF
C9
0.1
uF
C7
4.7
uF
R9
TB
D
R1 5
.1
R10
TB
DR
11
TB
DR
39
TB
D
C6 2.2
uF
R40
TB
DR
41
TB
D
R42
TB
DR
43
TB
DR
44
TB
DR
45
TB
DR
46
TB
DR
47
TB
D
C2
4.7
uF
458 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
1:
Me
tro
log
y -
SP
H-1
-08
00
-21
2A
Co
mm
Bo
ard
Co
nn
ecto
rs
A
29
Th
urs
da
y,
Se
pte
mb
er
19
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
D2
5
A28
/RD
Y1
A27
A4
D6
/ST
RB
1
D2
9
A30
D1
7
A5
D7
D3
1R
/W1
A24
D2
4
A21
A18
A6
D8
D0
D2
0
D1
5
D2
1
A7
D9
D1
2
D1
D1
9
D1
1
A26
D3
0
A25
A15
A8 D2
3
A0
D2
A20
D2
8
A10
D2
2
A14
A19
A9
A1
D3
D1
0
A13
D2
7
D1
4
A29
A2
A17
A12
D4
A11
D1
3
D1
6
A22
A3
D5
A23
A16
PA
GE
1
/CE
1
D1
8
D2
6
C4
-D3
C2
-D3
C2
-D0
CS
TR
B2
C1
-D3
C2
-D7
C1
-D0
CR
EQ
1
CR
EQ
2
C2
-D2
C1
-D7
C2
-D6
CS
TR
B1
C1
-D2
C4
-D7
C1
-D6
C2
-D1
CR
DY
2
CS
TR
B4
CR
EQ
4
C4
-D5
C2
-D5
CR
DY
1
CA
CK
1
C4
-D2
C1
-D5
CR
DY
4
CA
CK
2
C4
-D4
C4
-D0
C2
-D4
C4
-D6
C1
-D4
CA
CK
4
C4
-D1
C1
-D1
IR-R
X1
1
US
-RX
12-2
US
-RX
11-1
Exp
-Po
rt-I
n
US
-RX
12-1
IR_X
MIT
IR-R
X1
2
US
-RX
11-2
EX
P A
2D
0
EX
P A
2D
1
EX
P A
2D
2
IR_
RC
V_
INT
/RE
SE
T
VC
C(-
15
V)
VC
C(1
5V
)
VC
C(3
.3V
)
VC
C(5
V)
JP
4 Co
mm
Glo
ba
l
1 2 3 4 5 6 7 8 91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
23
33
43
53
63
73
83
94
0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
JP
5 Co
mm
Co
mm
Po
rts
1 2 3 4 5 6 7 8 91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
23
33
43
53
63
73
83
94
0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
JP
6
Co
mm
PW
R
12
34
56
78
91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
4
APPENDIX F 459
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
1:
Me
tro
log
y -
SP
H-1
-08
00
-21
2A
DS
P C
om
mP
ort
Co
nn
ecto
rs
A
39
Th
urs
da
y,
Se
pte
mb
er
19
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
IIO
F0
IIO
F1
/RE
SE
T
CS
TR
B0
CS
TR
B1
CS
TR
B2
CA
CK
0
CA
CK
1
CA
CK
2
CR
DY
0
CR
DY
1
CR
DY
2
CR
EQ
0
CR
EQ
1
CR
EQ
2
CA
CK
3
CA
CK
4
CA
CK
5C
RE
Q3
CR
EQ
4
CR
EQ
5
C0
-D0
C0
-D1
C0
-D2
C0
-D3
C0
-D4
C0
-D5
C0
-D6
C0
-D7
CR
DY
3
CR
DY
4
CR
DY
5
C3
-D0
C3
-D1
C3
-D2
C3
-D3
C3
-D4
C3
-D5
C3
-D6
C3
-D7
CS
TR
B3
CS
TR
B4
CS
TR
B5
C5
-D0
C5
-D1
C5
-D2
C5
-D3
C5
-D4
C5
-D5
C5
-D6
C5
-D7
C4
-D0
C4
-D1
C4
-D2
C4
-D3
C4
-D4
C4
-D5
C4
-D6
C4
-D7
C2
-D0
C2
-D1
C2
-D2
C2
-D3
C2
-D4
C2
-D5
C2
-D6
C2
-D7
C1
-D0
C1
-D1
C1
-D2
C1
-D3
C1
-D4
C1
-D5
C1
-D6
C1
-D7
PA
DS
_IN
TIR
_R
CV
_IN
T
VC
C(5
V)
VC
C(5
V)
VC
C(5
V)
VC
C(5
V)
VC
C(5
V)
VC
C(5
V)
VC
C(5
V)
VC
C(3
.3V
)V
CC
(3.3
V)
VC
C(5
V)
JP
1 TIM
40
J1
1 2 3 4 5 6 7 8 91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
23
33
43
53
63
73
83
94
0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
R2
01
0k
R2
5
10
k
R2
8
10
kR
29
10
k
R2
1
10
k
JP
2 TIM
40
J2
1 2 3 4 5 6 7 8 91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
23
33
43
53
63
73
83
94
0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
R2
61
0k
R3
0
10
k
R2
2
10
k
R2
7
10
k
R2
3
10
k
JH
1
DS
P P
WR
11
JH
2
DS
P P
WR
2
11
R3
1
10
k
R2
4
10
k
460 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
N.C.
N.C.
MB
1:
Me
tro
log
y -
SP
H-1
-08
00
-21
2A
DS
P G
lob
al B
us C
on
ne
cto
r
A
49
Th
urs
da
y,
Se
pte
mb
er
19
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
D1
0D
11
D1
2D
13
D1
4D
15
D1
6D
17
D1
8D
19
D2
0D
21
D2
2
D2
3D
24
D2
5D
26
D2
7D
28
D2
9D
30
D3
1
/CE
1
/RD
Y1
/RD
Y0
/CE
0/D
EP
AG
E1
/ST
RB
1R
/W1
/ST
RB
0S
TA
T0
ST
AT
1S
TA
T2
ST
AT
3R
/W0
PA
GE
0/A
E
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
/LO
CK
VC
C(5
V)
R3
21
0k
JP
3 TIM
40
J3
1 2 3 4 5 6 7 8 91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
23
33
43
53
63
73
83
94
0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
APPENDIX F 461
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
V2.5 BYPASS CAPS - PLACE AS CLOSE TO FPGA VCCINT PINS AS POSSIBLE
V3.3 BYPASS CAPS - PLACE AS CLOSE TO FPGA VCCO PINS AS POSSIBLE
MB
1:
Me
tro
log
y -
SP
H-1
-08
00
-21
2A
FP
GA
Byp
ass C
ap
acito
rs
A
59
Th
urs
da
y,
Se
pte
mb
er
19
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
VC
C(2
.5V
)
VC
C(3
.3V
)
C3
40
.1 u
F
C2
80
.1 u
FC
27
0.1
uF
C2
60
.1 u
F
C2
00
.1 u
F
C2
50
.1 u
F
C1
90
.1 u
FC
18
0.1
uF
C1
70
.1 u
FC
16
0.1
uF
C1
00
.1 u
F
C3
20
.1 u
FC
31
0.1
uF
C3
00
.1 u
FC
33
0.1
uF
C2
30
.1 u
FC
22
0.1
uF
C2
10
.1 u
F
C2
40
.1 u
F
C1
40
.1 u
FC
13
0.1
uF
C1
20
.1 u
FC
15
0.1
uF
C1
10
.1 u
F
C3
70
.1 u
FC
36
0.1
uF
C3
50
.1 u
F
C2
90
.1 u
F
462 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
1:
Me
tro
log
y -
SP
H-1
-08
00
-21
2A
FP
GA
Co
re
C
69
Th
urs
da
y,
Se
pte
mb
er
19
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
AD
DA
TA
0A
DD
AT
A1
AD
DA
TA
2A
DD
AT
A3
AD
DA
TA
4
AD
DA
TA
5A
DD
AT
A6
AD
DA
TA
7A
DD
AT
A8
AD
DA
TA
9A
DD
AT
A1
0A
DD
AT
A1
1
D0
D1
D2
D3
D6
D7
D8
D9
D1
0D
11
D1
2D
13
D1
4D
15
D1
6D
17
D1
8D
19
D2
0D
21
D2
2D
23
D2
4D
25
D2
6D
27
D2
8D
29
D3
0D
31
INIT
_S
PA
RE
9
AD
AR
DL
AD
AW
RL
AD
AC
SL
AD
AIN
TL
AD
BR
DL
AD
BW
RL
AD
BC
SL
AD
BIN
TL
D5
D4
AD
CL
OC
K
/ST
RB
1R
/W1
GC
K0
GC
K3
CC
LK
/PR
OG
RA
M
M2
DIN
_S
PA
RE
8
DO
NE
/RD
Y1
A2
/AE
A8
A7
A6
/CE
1
/DE
A5
A2
9
A0
A4
A9
A1
A3
A3
0M
1
IRO
UT
TH
R7
TH
R8
TH
R2
TH
R3
TH
R1
2
TH
R9
TH
R1
TH
R1
0
TH
R4
TH
R1
1
TH
R5
TH
R6
M0
PT
MS
PT
CK
PT
DO
PT
DI
IR_
XM
IT
PA
DS
_IN
T
Exp
-Po
rt-I
n/B
atL
ow
/EN
AB
LE
Din
3D
in4
Din
5
B-N
UM
0
B-N
UM
3B
-NU
M2
B-N
UM
1
LE
D-E
na
ble
WD
OG
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A2
9A
30
/ST
RB
1R
/W1
/RD
Y1
/CE
1/A
E/D
E
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D1
0D
11
D1
2D
13
D1
4D
15
D1
6D
17
D1
8D
19
D2
0D
21
D2
2D
23
D2
4D
25
D2
6D
27
D2
8D
29
D3
0D
31
AD
AR
DL
AD
AW
RL
AD
AC
SL
AD
AIN
TL
AD
BR
DL
AD
BW
RL
AD
BC
SL
AD
BIN
TL
AD
CL
OC
K
AD
DA
TA
10
AD
DA
TA
8A
DD
AT
A9
AD
DA
TA
4
AD
DA
TA
2A
DD
AT
A3
AD
DA
TA
1
AD
DA
TA
7
AD
DA
TA
11
AD
DA
TA
0
AD
DA
TA
6A
DD
AT
A5
IR_
XM
IT
IR_
RC
V_
INT
B-M
CL
R
IR-R
X9
IR-R
X1
0
IR-R
X1
2IR
-RX
11
IR-R
X2
IR-R
X1
IR-R
X4
IR-R
X3
IR-R
X5
IR-R
X6
IR-R
X7
IR-R
X8 U
S-R
X1
-2
US
-RX
11
-1
US
-RX
9-1
US
-RX
7-2
US
-RX
9-2
US
-RX
12
-1
US
-RX
3-1
US
-RX
7-1
US
-RX
4-2
US
-RX
8-2
US
-RX
10
-1
US
-RX
2-2
US
-RX
6-1
US
-RX
5-1
US
-RX
12
-2
US
-RX
2-1
US
-RX
1-1
US
-RX
6-2
US
-RX
10
-2
US
-RX
11
-2
US
-RX
4-1
US
-RX
8-1
US
-RX
5-2
US
-RX
3-2
TH
R2
TH
R7
TH
R1
1
TH
R3
TH
R1
2
TH
R4
TH
R5
TH
R8
TH
R9
TH
R1
TH
R6
TH
R1
0
Din
4
Exp
-Po
rt-I
nD
in3
/EN
AB
LE
Din
5
/Ba
tLo
w
/RE
SE
T
IR_
RC
V_
INT
B-N
UM
3
B-M
CL
R
B-N
UM
2B
-NU
M1
B-N
UM
0
VC
C(5
V)
VC
C(3
.3V
)
VC
C(3
.3V
)V
CC
(3.3
V)
VC
C(3
.3V
)
VC
C(3
.3V
)
VC
C(3
.3V
)
VC
C(2
.5V
)
VC
C(5
V)
VC
C(5
V)
VC
C(3
.3V
)
VC
C(1
5V
)
R3
44
70
C4
24
70
pF
C3
91
0 u
FC
40
10
uF
J1
7
Do
ut1 2 3 4 5 6 7 8 91
0
R3
18
0K
U4
MA
X1644
2 4
12
11 1 6 7
14
3 16
8 13
15
9
51
0
IN IN VC
CF
BS
EL
SH
DN
CO
MP
TO
FF
LX
LX
LX
FB
PG
ND
PG
ND
GN
D
SS
RE
F
D2
ZV
P2
10
6A
D
G
S
TP
1P
AD
S_
INT
1
C3
81
0 u
F
C4
50
.01
uF
TP
2IR
OU
T
1
D3 ST
AT
0
D4 ST
AT
1
R6
4.7
K
Britney
U5
Britn
ey F
PG
A (
Xili
nx X
C2
S2
00
-5P
Q2
08
C)
19
21
93
19
41
95
19
92
00
20
12
02
20
32
04
20
52
06
17
61
78
17
91
80
18
11
87
18
81
89
19
1
3 4 5 6 7 8 91
01
41
51
61
7
57
18
20
21
22
23
24
27
29
30
31
33
34
35
36
37
41
42
43
44
45
46
47
48
49
58
59
60
61
62
63
67
68
69
70
71
73
74
75
81
82
83
84
86
87
88
89
90
94
95
96
97
98
99
10
01
01
10
21
08
10
91
10
11
11
12
11
31
14
11
51
19
12
01
21
12
31
25
12
61
27
12
91
32
13
3
13
5
13
6
13
4
13
81
39
14
01
41
14
2
14
61
47
14
81
49
15
01
51
15
21
54
16
01
61
16
21
63
16
4
16
51
66
16
71
68
17
21
73
17
41
75
15
31
07
3240516472798593103116124131137145158169177
19111
25
15
51
04
10
65
25
05
4
15
71
59 2
20
7
80
77
18
21
85
5556
12263953657892105117130144156170184197208
132838667691118128143171186196
183190198
12
2
AD
DA
TA
0A
DD
AT
A1
AD
DA
TA
2A
DD
AT
A3
AD
DA
TA
4A
DD
AT
A5
AD
DA
TA
6A
DD
AT
A7
AD
DA
TA
8A
DD
AT
A9
AD
DA
TA
10
AD
DA
TA
11
AD
AR
DL
AD
AW
RL
AD
AC
SL
AD
AIN
TL
AD
BR
DL
AD
BW
RL
AD
BC
SL
AD
BIN
TL
AD
CL
OC
K
IRIN
0IR
IN1
IRIN
2IR
IN3
IRIN
4IR
IN5
IRIN
6IR
IN7
IRIN
8IR
IN9
IRIN
10
IRIN
11
IRO
UT
US
IN0
US
IN1
US
IN2
US
IN3
US
IN4
US
IN5
US
IN6
US
IN7
US
IN8
US
IN9
US
IN1
0U
SIN
11
US
IN1
2U
SIN
13
US
IN1
4U
SIN
15
US
IN1
6U
SIN
17
US
IN1
8U
SIN
19
US
IN2
0U
SIN
21
US
IN2
2U
SIN
23
TH
RU
ST
0T
HR
US
T1
TH
RU
ST
2T
HR
US
T3
TH
RU
ST
4T
HR
US
T5
TH
RU
ST
6T
HR
US
T7
TH
RU
ST
8T
HR
US
T9
TH
RU
ST
10
TH
RU
ST
11
DIN
0D
IN1
DIN
2D
IN3
DIN
4D
IN5
LE
D0
LE
D1
HD
AT
A0
HD
AT
A1
HD
AT
A2
HD
AT
A3
HD
AT
A4
HD
AT
A5
HD
AT
A6
HD
AT
A7
HD
AT
A8
HD
AT
A9
HD
AT
A1
0H
DA
TA
11
HD
AT
A1
2H
DA
TA
13
HD
AT
A1
4H
DA
TA
15
HD
AT
A1
6H
DA
TA
17
HD
AT
A1
8H
DA
TA
19
HD
AT
A2
0H
DA
TA
21
HD
AT
A2
2H
DA
TA
23
HD
AT
A2
4H
DA
TA
25
HD
AT
A2
6H
DA
TA
27
HD
AT
A2
8H
DA
TA
29
HD
AT
A3
1
HS
TR
BL
HD
AT
A3
0
HR
DW
RL
HR
DY
HC
EH
AE
HD
E
HA
DD
R0
HA
DD
R1
HA
DD
R2
HA
DD
R3
HA
DD
R4
HA
DD
R5
HA
DD
R6
HA
DD
R7
HA
DD
R8
HA
DD
R9
HA
DD
R1
0H
AD
DR
11
HIN
T
DO
UT
0D
OU
T1
DO
UT
2D
OU
T3
DO
UT
4D
OU
T5
DO
UT
6D
OU
T7
DIN
_S
PA
RE
8IN
IT_
SP
AR
E9
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GNDGNDGND
GND
CC
LK
DO
NE
PR
OG
RA
MM
0M
1M
2
TD
OT
DI
TM
ST
CK
GC
K0
GC
K1
GC
K2
GC
K3
NO_CONNECT0NO_CONNECT1
VCCOVCCOVCCOVCCOVCCOVCCOVCCOVCCOVCCOVCCOVCCOVCCOVCCOVCCOVCCOVCCO
VCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINT
GNDGNDGND
RE
SE
T
XC18V02-VQ44I
U6
XC
18
V0
240
29
42
27
9 25
14
19
43
13
15
10
21
33
1 57
6182841
8162636
173538
D0
D1
D2
D3
D4
D5
D6
D7
CL
KO
ER
ES
ET
CE
CF
CE
O
TD
IT
DO
TM
S
TC
K
GNDGNDGNDGND
VCCOVCCOVCCOVCCO
VCCVCCVCC
C4
11
00
uF
J1
6
Din
1 2 3 4 5 6 7 8 91
0
R2
10 C
44
2.2
uF
U7 EC
S-3
95
3C
-25
0
1 234
ST
AN
DB
Y
GN
DO
UT
PU
T
VC
C
R4
87
5
TP
4
GN
D
1
C4
31
uF
D1 P
RO
M D
ON
E
R8
4.7
K
R3
50
Oh
m
R7
4.7
K
L1
7.5
uH
J1
8
PR
OM
JT
AG
1 2 3 4 5 6 7 8 91
01
11
21
31
4
TP
3
/RE
SE
T
1
R3
74
70
R3
60
Oh
m
R3
84
70
APPENDIX F 463
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
US/IR 11 and 12 come from the Expansion Port
X Accel is on board, noconnector
MB
1:
Me
tro
log
y -
SP
H-1
-08
00
-21
2A
Me
tro
log
y C
on
ne
cto
rs
A
79
Th
urs
da
y,
Se
pte
mb
er
19
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
IR_X
MIT
US
-RX
1-1
US
-RX
1-2
IR-R
X1
US
-RX
2-2
US
-RX
2-1
IR-R
X2
IR_X
MIT
US
-RX
3-2
US
-RX
3-1
IR-R
X3
IR_X
MIT
US
-RX
4-2
US
-RX
4-1
IR-R
X4
IR_X
MIT
US
-RX
8-1
US
-RX
6-1
US
-RX
7-1
IR_X
MIT
US
-RX
5-2
IR-R
X6
IR_X
MIT
US
-RX
8-2
US
-RX
5-1
IR-R
X5
IR_X
MIT
IR_X
MIT
IR-R
X7
IR-R
X8
US
-RX
6-2
US
-RX
7-2
US
-RX
10-1
US
-RX
9-2
IR-R
X1
0
IR_X
MIT
US
-RX
9-1
IR-R
X9
IR_X
MIT
US
-RX
10-2
X G
yro
Y G
yro
Z G
yro
Y-A
cce
l-A
mp
Z-A
cce
l-A
mp
Y-A
cce
l-T
em
p
Z-A
cce
l-T
em
p
VC
C(5
V)
VC
C(5
V)
VC
C(5
V)
VC
C(1
5V
)V
CC
(15
V)
VC
C(-
15
V)
VC
C(5
V)
J8
US
/IR
8
12345678910
J1
2
Y G
yro
123
J2
US
/IR
2
12345678910
J1
US
/IR
1
12345678910
J1
4
Y A
cce
l
12345678
J9
US
/IR
9
12345678910
J3
US
/IR
3
12345678910
J1
3
Z G
yro
123
J1
5
Z A
cce
l
12345678
J1
0
US
/IR
10
12345678910
J4
US
/IR
4
12345678910
J5
US
/IR
5
12345678910
J6
US
/IR
6
12345678910
J1
1
X G
yro
123
J7
US
/IR
7
12345678910
464 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
1:
Me
tro
log
y -
SP
H-1
-08
00
-21
2A
Po
we
r B
oa
rd C
on
ne
cto
rs
A
89
Th
urs
da
y,
Se
pte
mb
er
19
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
OR
BU
RD
YL
BK T
HR
10
TH
R4
TH
R5
TH
R1
2
TH
R1
TH
R7
TH
R8
TH
R2
TH
R1
1
TH
R9
TH
R6
TH
R3
TH
R1
TH
R2
TH
R3
TH
R4
TH
R5
TH
R6
TH
R7
TH
R8
TH
R9
TH
R1
0T
HR
11
TH
R1
2
/EN
AB
LE
WD
OG
LE
D-E
na
ble
/RE
SE
T
/Ba
tLo
w
VC
C(-
15
V)
VC
C(1
5V
)V
CC
(3.3
V)
VC
C(5
V)
J2
1
Da
ta t
o P
WR
1234567891
01
11
21
31
41
51
61
71
81
92
02
12
22
32
4
J2
0
PW
R
1 2 3 4 5
APPENDIX F 465
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
1:
Me
tro
log
y -
SP
H-1
-08
00
-21
2A
Acce
lero
me
ter
Bu
ffe
r/A
mp
lifie
rs
A
99
Th
urs
da
y,
Se
pte
mb
er
19
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
X-A
cce
l-A
mp
X-A
ccel-T
em
p
VC
C(5
V)
VC
C(-
15
V)
VC
C(1
5V
)
VC
C(5
V)
VC
C(5
V)
R1
71
00
k
R1
91
0.0
k
R3
35
6.2
k
QA-750
U1
0
QA
-750
1 3 4678
Ou
t
-V +V
Te
mp
Te
st
GN
D
-+
U9
MA
X409
3 26
7 451
R1
51
00
k
R1
21
02
k
R1
6
10
0k
13
2
R1
34
.02M
R1
41
00
k
R1
82
k
C49
470p
466 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
bypass
bypass
All the grounds in this diagram must be one single
thick trace which connects the 470uF cap to the
IRL520N
Me
tro
log
y 6
- S
PH
-1-0
80
0-1
01
B
Bo
ard
Asse
mb
ly
A
13
Tu
esd
ay,
Fe
bru
ary
18
, 2
00
3
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
US
-2
US
Circu
it
US
Sig
na
l
US
-1
US
Circu
it
US
Sig
na
l
IR R
CV
US
RC
V 1
US
RC
V 2
IR X
MIT
IR X
MIT
VC
C(+
5V
)
VC
C(+
2.5
V)
VC
C(+
5V
)
VC
C(+
5V
)
VC
C(+
5V
)
C1
4
4.7
uF
J1
IR P
AD
12345678
D1IR LED
C20.1uF
D2IR LED
R5
22K
C3 47
uF
JP
1
HE
AD
ER
10
1 2 3 4 5 6 7 8 9 10
R6
22K
D3
IRL
ML
25
02
3
1
2
R1100 Ohm R
4 1M
R2
74
7 O
hm
R21 Ohm
R31 Ohm
C1
3
0.1
uF
C4
4.7
uF
C1
4.7
uF
APPENDIX F 467
Each metrology board includes two of these circuits:5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Keep trace as short as possible
Piggyback parallel to Rf
Piggyback parallel to Rf
Me
tro
log
y 6
B
Sin
lge
US
Am
plif
ier
Ch
an
ne
l
A
23
Th
urs
da
y,
Ma
rch
06
, 2
00
3
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
VC
C(+
5V
)
VC
C(+
5V
)
VC
C(+
5V
)V
CC
(+5
V)
VC
C(+
2.5
V)
VC
C(+
2.5
V)
VC
C(+
2.5
V)V
CC
(+5
V)
+ -
U1
C
LM
6154A
/SO
10 9
8
4 11
R1
410K
PO
T
13
2
+ -
U1
B
LM
6154A
/SO
5 67
4 11
+ -
U1
A
LM
6154A
/SO
3 21
4 11
D4
1N
91
4/S
O
R7
34K
R1
234K
C8
5p
R8
1M
R1
168K
D51N914/SO
C6
0.2
70
n
C7
5p
R1
0
10K
C5
10n
R1
668K
R1
3220K
J2
US
1
1 2
R9
68K
R1
51
M
+ -U
1D
LM
6154A
/SO
12
13
14
4 11
US
Sig
na
l
468 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Acce
l P
CB
- S
PH
-1-0
80
0-2
05
B
Acce
lero
me
ter
Bu
ffe
r/A
mp
lifie
rs
A
11
We
dn
esd
ay,
Se
pte
mb
er
18
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
VC
C(5
V)
VC
C(-
15
V)
VC
C(1
5V
)
VC
C(5
V)
VC
C(5
V)
VC
C(1
5V
)
VC
C(5
V)
VC
C(-
15
V)
R7
10
.0k
R5
10
0k
J1
Acce
l
12345678
R9
56
.2k
-+
U2
MA
X409
3 26
7 451
R6
2k
C1
470p
R4
10
0k
R1
10
2k
QA-750
U1
QA
-750
1 3 4678
Ou
t
-V +V
Te
mp
Te
st
GN
D
R3 10
0k
13
2
R8
10
0k
R2
4.0
2M
APPENDIX F 469
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SP
HE
RE
Be
aco
n -
SP
H-1
-08
00
-70
2-
Pro
ce
sso
r
A
12
Tu
esd
ay,
Se
pte
mb
er
17
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
NU
M1
NU
M3
NU
M2
NU
M0
IR_
RC
V
/MC
LR
US
_X
MIT
VC
C(5
V)
VC
C(5
V)
VC
C(5
V)
VC
C(1
5V
)
R2
C3
.1u
TP
1
IR_
RC
V
1
U1
PIC
16
C5
05
1 2 3 4 5 6 7891
0
11
12
13
14
Vcc
CL
K_
INC
LK
_O
UT
RB
3
RC
5R
C4
RC
3R
C2
RC
1R
C0
RB
2R
B1
RB
0
GN
D
D1 Sta
t L
ED
TP
2
GN
D
1
R3
R1
470
Y1
40M
Hz
4
3
2
1
VCC OU
T
GND
E/D
R5
JP
1
HE
AD
ER
101 2 3 4 5 6 7 8 9
10
R4
10
k
470 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SP
HE
RE
Be
aco
n -
SP
H-1
-08
00
-70
2-
US
Tra
nsm
itte
r
A
22
Tu
esd
ay,
Se
pte
mb
er
17
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
US
_X
MIT
-U
S_X
MIT
+
US
_X
MIT
VC
C(5
V)
VC
C(1
5V
)
R7
10
k
R6
10
k
R8
100
U3
CD
40
93
1 23 4
5 6
7
8 91
0
11
12
13
14
1A
1B
1Y
2Y
2A
2B
GND
3A
3B
3Y
4Y
4A
4B
Vcc
Q1
2N
39
04
C
B
E
TP
3
US
_X
MIT
1
C1
47
uF
U4
US
Xm
it
1 2
C2
.1u
F
U2
LM
3480-1
2/S
OT
23
21
3
INO
UT
GND
APPENDIX F 471
F.1.5 Communications
Design Drivers
• Two wireless communications channels
- Satellite to Laptop (STL) - Telemetry and Commands
- Satellite to Satellite (STS) - Control and Commands
• Support at least three satellites
• Should be expandable
• Accommodate a minimum volume of 6’ x 6’ x 6’
• Highest data rate possible
• Low power
Functional Block Diagrams
Figure F.11 presents the functional block diagram of the communications sub-system. The
major elements of the communications sub-system are three PIC processors that translate
TI Commport signals into standard 8-bit (plus start and stop bit) UART serial data and two
DR200x modules (one each for Satellite-to-Laptop STL and for Satellite-to-Satellite
STS communications) which convert the 8-bit UART data into 14-bit bit-balanced
words to minimize errors during wireless transmissions. The two elements are described
below.
DR200x Wireless Boards
The DR2000 development kit is a COTS product available from RFM Monolithics in. The
kit utilizes an ARM DSP to manage data for wireless transmissions. The ARM performs
four functions:
• Creates 12-bit bit-balanced words for every byte to be transmitted. Bit bal-anced words contain the same number of ones and zeros to reduce the errorrate in wireless transmission.
• Manages packets of a pre-set size. The DR200x can be configured to sendfixed sized packets immediately once the fixed number of bytes arereceived; alternatively, it will transmit a packet if there is a pause longer than2ms between bytes.
472 APPENDIX F
• Adds a start header to all transmissions which allows the crystals in thereceiving end to resonate at the correct frequency before the actual dataarrives.
• Allows identification of each module individually, so that data can bedirected to a specific DR200x board.
The basic features of the DR200x boards are listed in Table F.10. Table F.11 describes the
signals of the DR2000x.
To improve the bandwidth of the system, though, SPHERES uses custom firmware.
Therefore, while [RFM, URL] provides an overview of the hardware used in the board,
Appendix H should be consulted to understand the operations of firmware. Further, to
Figure F.11 Communications sub-system functional block diagram
Communications Motherboard
CommPort 1
12PIC
DR2000916.5MHz
PICCommPort 212
STL
PIC RS232CommPort 412
ExpansionPort
2 2
STS
DR2001868.35MHz
MetrologyMB
DSP
Power
A/D
FPGA
Global Bus69
3
US/IR
EXP_in
Analog inReset
Reset
Reset
2
2
Reset
UART
UART
APPENDIX F 473
minimize power consumption, the DR200x board used inside the satellites have been
modified by removing the power regulation circuit (because the satellite power system
provides regulated 3.3V) and the RS232 level converter, since the boards can connect
directly through TTL to the PIC processors.
Communications Interface Board
The communications interface board hosts the PIC processors which translate the DR200x
serial data to the TI commport standard. The DR200x utilizes a standard UART signal at
115.2kbps; the selected PIC (16C66) contains a serial port capable of handling up to
1.25Mbps communications with support via special registers. The implemented firmware
TABLE F.10 DR200x specifications
DR2000 DR2001Frequency 916.5MHz 868.35MHzMaximum wireless data rate 115.2kbpsImplemented wireless data rate 56.6kbpsUART data rate 115.2kbpsBuffer 64 bytesRF Mode ASKAvailable Addresses 1-255 (0x01-0xFF)Broadcast mode Yes (to address = 0x00)Packet size 1-255 (0x01-0xFF)Input Voltage 3.1V-3.6VPower <050mW
TABLE F.11 DR200x signals descriptions
Signal Type DescriptionVcc(+3.3V) Pwr +3.3V powerGND Pwr Common groundRX Out Serial data receive lineTX In Serial data transmit line/RST In Reset
474 APPENDIX F
provides 96-byte input and output buffers. The TI commport standard is a parallel bi-
directional data bus with token handshaking. The data consists of 32-bit words split into
four bytes. Four control lines are used to pass the token (REQ and ACK) between the two
units (in this case the DSP and the PIC) and to indicate that data is available (STRB) and
has been read (RDY). Chapter 8 of [TI, SPRU159A] describes the operations of the com-
munications ports in full.
Table F.12 describes the input and output signals of the communications motherboard.
TABLE F.12 Communications motherboard signals description
Section Signal Type DescriptionTo/From Metrology Mother-board
Vcc(+5V) Pwr +5V powerVcc(+3.3V) Pwr +3.3V powerVcc(+15V) Pwr +15V powerVcc(-15V) Pwr -15V powerGND Pwr Common groundA0-A30 In Global bus address lines (expansion port)D0-D31 I/O Global bus data lines (expansion port)RDY1 I/O Global bus ready (expansion port)PAGE1 I/O Global bus page select (expansion port)STRB1 In Global bus strobe (expansion port)R/W1 I/O Global bus read/write (expansion port)/RESET In Reset line/Exp_port_in Out Expansion port item indicatorIR_XMIT In IR transmit commandUS-RX[11-12]-[1-2]
Out Input ultrasound signals from the expan-sion port board
IR-RX[11-12] Out Input infrared signals from the expansion port board
EXP A2D [0-2] Out Analog signals from expansion portC[1,2,4] D[0-7] I/O Commport data linesCACK[1,2,4] I/O Commport acknowledge signalCRDY[1,2,4] I/O Commport ready signal
APPENDIX F 475
Met. MB (cont)
CREQ[1,2,4] I/O Commport request signalSTRB[1,2,4] I/O Commport strobe
Expansion Port Con-nector
Vcc(+5V) Pwr +5V powerVcc(+15V) Pwr +15V powerVcc(-15V) Pwr -15V powerGND Pwr Common groundA0-A30 Out Global bus address linesD0-D31 I/O Global bus data linesRDY1 I/O Global bus readyPAGE1 I/O Global bus page selectSTRB1 Out Global bus strobeR/W1 I/O Global bus read/write/RESET In Reset line/Exp_port_in In High when an expansion port selects to
bypass the satellite US/IR metrology boards
IR_XMIT Out IR transmit commandUS-RX[11-12]-[1-2]
In Input ultrasound signals
IR-RX[11-12] In Input infrared signalsEXP A2D [0-2] In Input analog signalsEXP RX In Serial data receive (RS232)EXP TX Out Serial data transmit (RS232)
Wired Serial Con-nector
EXP RX In Serial data receive (RS232)EXP TX Out Serial data transmit (RS232)GND Pwr Common Ground
DR200x (2x)
Vcc(+3.3V) Pwr +3.3V powerGND Pwr Common groundRX Out Serial data receive lineTX In Serial data transmit line/RST In Reset
TABLE F.12 Communications motherboard signals description
Section Signal Type Description
476 APPENDIX F
Schematics
The schematics of the DR200x boards are available in [RFM, URL]. The schematics of
the SPHERES communications motherboard are presented next.
APPENDIX F 477
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
2:
Co
mm
- S
PH
-1-0
80
0-2
13
A
Co
mm
Bo
ard
Co
nn
ecto
rs
A
15
Th
urs
da
y,
Octo
be
r 1
0,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
D2
5
A28
/RD
Y1
A27
A4
D6
/ST
RB
1
D2
9
A30
D1
7
A5
D7
D3
1
/AE
R/W
1
A24
D2
4
A21
A18
A6
D8
D0
D2
0
/DE
D1
5
D2
1
A7
D9
D1
2
D1
ST
AT
0
D1
9
D1
1
A26
D3
0
A25
A15
A8 D2
3
A0
D2
ST
AT
1
A20
D2
8
A10
D2
2
A14
A19
A9
A1
D3
ST
AT
2
D1
0
A13
D2
7
D1
4
/LO
CK
A29
A2
A17
A12
D4
A11
ST
AT
3
D1
3
D1
6
A22
A3
D5
A23
A16
PA
GE
1
/CE
1
D1
8
D2
6
C4
-D3
C2
-D3
C2
-D0
CS
TR
B2
C1
-D3
C2
-D7
C1
-D0
CR
EQ
1
CR
EQ
2
C2
-D2
C1
-D7
C2
-D6
CS
TR
B1
C1
-D2
C4
-D7
C1
-D6
C2
-D1
CR
DY
2
CS
TR
B4
CR
EQ
4
C4
-D5
C2
-D5
CR
DY
1
CA
CK
1
C4
-D2
C1
-D5
CR
DY
4
CA
CK
2
C4
-D4
C4
-D0
C2
-D4
C4
-D6
C1
-D4
CA
CK
4
C4
-D1
C1
-D1
IR-R
X1
1
US
-RX
12-2
US
-RX
11-1
US
-RX
12-1
IR_X
MIT
IR-R
X1
2
US
-RX
11-2
EX
P A
2D
0
EX
P A
2D
1
EX
P A
2D
2
IR_
RC
V_
INT
/RE
SE
TE
xp
-Po
rt-I
n
VC
C(-
15
V)
VC
C(5
V)
VC
C(3
.3V
)
VC
C(1
5V
)
JP
1 Co
mm
Co
mm
Po
rts
1 2 3 4 5 6 7 8 91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
23
33
43
53
63
73
83
94
0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
JP
2 Co
mm
Glo
ba
l
1 2 3 4 5 6 7 8 91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
23
33
43
53
63
73
83
94
0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
JP
3
Co
mm
PW
R
12
34
56
78
91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
4
478 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
2:
Co
mm
- S
PH
-1-0
80
0-2
13
A
Exp
an
sio
n P
ort
Co
nn
ecto
rs
A
25
Th
urs
da
y,
Octo
be
r 1
0,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
D1
D9
D2
7
D1
9
D2
9
D2
D1
3
D3
D2
2
D1
4
D1
0
D4
D2
3
D1
5
D3
0
D1
1
D5
D6
D2
4
D1
6
D3
1
D1
2
D2
8
D7
D2
5
D1
7
D2
0
D0
D8
D2
6
D1
8
D2
1
US
-RX
11-1
IR-R
X1
1
IR-R
X1
2
US
-RX
12-1
US
-RX
12-2
US
-RX
11-2
IR_X
MIT
EX
P-R
XE
XP
-TX
Exp
-Po
rt-I
n
A30
A17
A13
/RD
Y1
A11
A26
A14
A8
A6
A22
A18
A5
A3
A20
PA
GE
1
/CE
1
A28
A0
A10
A1
A27
A23
A7
/ST
RB
1
A29
A9
R/W
1
A25
A16
A15
A4
/LO
CK
A19
A24
A21
A12
A2
EX
P A
2D
1
EX
P A
2D
0
EX
P A
2D
2
/RE
SE
T
VC
C(-
15
V)
VC
C(5
V)
VC
C(1
5V
)
J3
Exp
PW
R
1 2 3 4 5 6
J1
Exp
1
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
J2
Exp
2
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
APPENDIX F 479
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
2:
Co
mm
- S
PH
-1-0
80
0-2
13
A
UA
RT
- E
xp
an
sio
n B
us S
eria
l P
ort
A
35
Th
urs
da
y,
Octo
be
r 1
0,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
OS
C-P
IC-2
OS
C-P
IC-1/R
ES
ET
C4
-D0
C4
-D1
C4
-D2
C4
-D3
C4
-D4
C4
-D5
C4
-D6
C4
-D7
EX
P-R
XE
XP
-TX
CS
TR
B4
CR
DY
4C
AC
K4
CR
EQ
4
VC
C(5
V)
VC
C(5
V)
VC
C(5
V)
C2
1 u
F
R2
2
50
C7
.1u
C3
1 u
F
RS232
TTL
U2
DS
14
C2
32
13
81
1
10
1 3 4 5 2 6
12 9
14
7
16 15
R1
IN
R2
IND
1IN
D2
IN
C1
+C
1-
C2
+C
2-
V+ V-
R1
OU
T
R2
OU
TD
1O
UT
D2
OU
T
VCC GND
R2
3
50
U1
PIC
16
C6
6
1 2 3 4 5 6 7
8
91
0
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
/MC
LR
RA
0R
A1
RA
2R
A3
RA
4/T
0C
KR
A5
/SS
GND
OS
C1
OS
C2
RC
0R
C1
RC
2R
C3
RC
4R
C5
RC
6/T
XR
C7
/RX
Vdd
RB
0R
B1
RB
2R
B3
RB
4R
B5
RB
6R
B7
C1 1 u
F
J6
HE
AD
ER
3
1 2 3
R1
10
kR
31
0k
R2
0
50
R2
10
k
C4 1 u
F
R4
10
kR
21
50
480 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
2:
Co
mm
- S
PH
-1-0
80
0-2
13
A
UA
RT
1 -
ST
L C
om
mu
nic
atio
ns C
ha
nn
el
A
45
Th
urs
da
y,
Octo
be
r 1
0,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
RS
T2
RX
2T
X2C
2-D
0C
2-D
1C
2-D
2C
2-D
3C
2-D
4C
2-D
5C
2-D
6C
2-D
7/R
ES
ET
OS
C-P
IC-2
OS
C-P
IC-1
OS
C-P
IC-1
OS
C-P
IC-2
CR
DY
2C
AC
K2
CS
TR
B2
CR
EQ
2
VC
C(5
V)
VC
C(5
V)
VC
C(3
.3V
)
C8
.1u
U3
PIC
16
C6
6
1 2 3 4 5 6 7
8
91
0
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
/MC
LR
RA
0R
A1
RA
2R
A3
RA
4/T
0C
KR
A5
/SS
GND
OS
C1
OS
C2
RC
0R
C1
RC
2R
C3
RC
4R
C5
RC
6/T
XR
C7
/RX
Vdd
RB
0R
B1
RB
2R
B3
RB
4R
B5
RB
6R
B7
R2
7
50
R5
10
k
C5
22
pF
R8
10
kR
61
0k
R2
4
50
R9
10
J4
ST
L C
om
m
123456
R2
5
50
Y1
20.0
MH
z
R7
10
k
C6
22
pF
R2
6
50
APPENDIX F 481
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
2:
Co
mm
- S
PH
-1-0
80
0-2
13
A
UA
RT
1 -
ST
G C
om
mu
nic
atio
ns C
ha
nn
el
A
55
Th
urs
da
y,
Octo
be
r 1
0,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
RX
1T
X1
RS
T1
/RE
SE
T
C1
-D1
C1
-D0
C1
-D2
C1
-D3
C1
-D4
C1
-D5
C1
-D6
C1
-D7
OS
C-P
IC-2
OS
C-P
IC-1
CA
CK
1
CR
EQ
1
CS
TR
B1
CR
DY
1
VC
C(5
V)
VC
C(5
V)
VC
C(3
.3V
)
U4
PIC
16
C6
6
1 2 3 4 5 6 7
8
91
0
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
/MC
LR
RA
0R
A1
RA
2R
A3
RA
4/T
0C
KR
A5
/SS
GND
OS
C1
OS
C2
RC
0R
C1
RC
2R
C3
RC
4R
C5
RC
6/T
XR
C7
/RX
Vdd
RB
0R
B1
RB
2R
B3
RB
4R
B5
RB
6R
B7
R1
01
0k
R3
0
50
R1
21
0k
R1
11
0k
J5
ST
G
123456
R3
1
50
C9
.1u
R2
8
50
R1
31
0k
R2
9
50
482 APPENDIX F
F.1.6 Expansion Port
Design Drivers
• Provide digital interface for future expansions
Functional Block Diagrams
The broad requirements in the definition of the expansion port resulted in a design which
provides a simple but limited serial line capable of up to 1.25Mbps data rates as well as the
very flexible but complex global bus. Figure F.12 presents the functional block diagram
for the Expansion Port.
Figure F.12 Expansion port functional block diagram
CommMB
PIC &RS232
CommPort 412
Expansion Port
2
MetrologyMB
DSP
Power
A/D
FPGA
Global Bus69
3
US/IR
EXP_in
Analog in
Reset
FX-8
0 C
onne
ctor
UART(RS232)
Reset
EXP_in
IR_xmit
US/IR 12US/IR 11
US-RX11
IR-RX11
US-RX11
IR-RX12
APPENDIX F 483
Apart from providing the required digital data lines, the Expansion Port also supports
three other functions:
• Provides power to expansion items via +5V, +15V, and -15V power lines. Itprotects these lines with 0.5A self-resetable fuses.
• Because three analog lines were available from the basic metrology design,the expansion port makes these lines available to expansion items.
• Allows an expansion item to bypass the internal US/IR metrology boardslocated on the expansion port face (+X face). This allows an expansion itemto replace the functionality of those boards if the expansion item covers thesensors. The expansion board uses high-speed multiplexers so that the sig-nals received by the FPGA are equivalent to any other US/IR signals. TheEXP_in line allows the DSP to account for the new physical locations(which must be programmed) of the US/IR boards when the signals havebeen bypassed.
Table F.13 describes the inputs and outputs of the Expansion Port.
TABLE F.13 Expansion port signals description
Section Signal Type DescriptionTo/From Comm. Mother-board
See Table F.12
Expansion Port Con-nector
Vcc(+5V) Pwr +5V powerVcc(+15V) Pwr +15V powerVcc(-15V) Pwr -15V powerGND Pwr Common groundA0-A30 Out Global bus address linesD0-D31 I/O Global bus data linesRDY1 I/O Global bus readyPAGE1 I/O Global bus page selectSTRB1 Out Global bus strobeR/W1 I/O Global bus read/write/RESET In Reset line
484 APPENDIX F
Expansion Port (cont)
/Exp_port_in In High when an expansion port selects to bypass the satellite US/IR metrology boards
IR_XMIT Out IR transmit commandUS-RX[11-12]-[1-2]-EXT
In External sensor input ultrasound signals
IR-RX[11-12]-EXT
In External sensor input infrared signals
EXP A2D [0-2] In Input analog signalsEXP RX In Serial data receive (RS232)EXP TX Out Serial data transmit (RS232)
Metrology Pass-through(2x)
Vcc(+5V) Pwr +5V powerGND Pwr Common groundIR_XMIT Out IR transmit commandUS-RX[11-12]-[1-2]-INT
In Internal sensor input ultrasound signals
IR-RX[11-12]-INT
In Internal sensor input infrared signals
TABLE F.13 Expansion port signals description
Section Signal Type Description
APPENDIX F 485
Schematics5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Exp
an
sio
n P
ort
- S
PH
-1-0
80
0-7
01
-
Exte
rna
l C
on
ne
cto
rs
A
13
Tu
esd
ay,
Se
pte
mb
er
17
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
A0
8
EX
P A
2D
0
EX
P A
2D
1
/LO
CK
A2
7
PA
GE
1
A0
7
A1
0
A2
1
A0
9
/ST
RB
1/R
DY
1
A1
4
A0
2
A3
0
A1
1
A0
0
A2
5
A2
8
A2
0
A1
5
A1
2
A0
3
A1
6
A0
4
A2
9
A2
4
R/W
1
EX
P A
2D
2
A0
6
/CE
1
A1
9
A0
5
A2
6
A0
1
A2
3
A1
7A
18
A2
2
A1
3
D0
3
D2
4
D0
0
D3
1
D0
7
D2
9
D1
8
D0
1
D2
3
D2
5
D1
9
D2
7
D1
6
D1
3
D0
4
D2
2
D0
9D
08
D0
6
D1
7
D1
1
D2
6
D1
0
D2
1
D1
5D
14
D3
0
D2
0
D0
2
D2
8
D0
5
D1
2
US
-RX
-12-1
-EX
T
IR-R
X-1
1-E
XT
IR-R
X-1
2-E
XT
US
-RX
-11-1
-EX
TU
S-R
X-1
1-2
-EX
T
US
-RX
-12-2
-EX
T
IR_X
MIT
Exp
-Po
rt-I
nE
XP
-TX
EX
P-R
X/R
ES
ET
VC
C(-
15
V)
VC
C(5
V)
VC
C(1
5V
)
R1
1M
F2
.2A
F3
.2A
F1
.2A
JP
1
EX
80-1
00
1 3 5 7 9
112 4 6 8
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10
0
PW
R1
3 5 7 9 11
PW
R2
4 6 8 10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PW
R5
1
PW
R5
2
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
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85
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91
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93
94
95
96
97
98
99
10
0
486 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Exp
an
sio
n P
ort
- S
PH
-1-0
80
0-7
01
-
Me
tro
log
y P
ass T
hro
ug
h
A
23
Tu
esd
ay,
Se
pte
mb
er
17
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
US
-RX
-11
-2-I
NT
IR-R
X-1
1-I
NT
US
-RX
-11
-1-I
NT
US
-RX
-12
-2-I
NT
IR-R
X-1
2-I
NT
US
-RX
-12
-1-I
NT
IR-R
X-1
1-E
XT
US
-RX
-11-2
-EX
T
US
-RX
-11-1
-EX
T
Exp
-Po
rt-I
n
Exp
-Po
rt-I
n
US
-RX
11-1
US
-RX
11-2
IR-R
X1
1
IR-R
X1
2
US
-RX
12-1
US
-RX
12-2
IR_X
MIT
US
-RX
-12-1
-EX
T
IR_X
MIT
IR-R
X-1
2-E
XT
US
-RX
-12-2
-EX
TVC
C(5
V)
VC
C(5
V)
U1
74LS
241
2 4 6 81
11
31
51
7 11
9
18
16
14
12
9 7 5 3
20 10
1A
11
A2
1A
31
A4
2A
12
A2
2A
32
A4
1G
2G
1Y
11
Y2
1Y
31
Y4
2Y
12
Y2
2Y
32
Y4
VCC GND
J4
US
/IR
1
1234567891
0
J5
US
/IR
11234567891
0
U2
74LS
241
2 4 6 81
11
31
51
7 11
9
18
16
14
12
9 7 5 3
20 101
A1
1A
21
A3
1A
42
A1
2A
22
A3
2A
4
1G
2G
1Y
11
Y2
1Y
31
Y4
2Y
12
Y2
2Y
32
Y4
VCC GND
APPENDIX F 487
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Exp
an
sio
n P
ort
- S
PH
-1-0
80
0-7
01
-
Co
nn
ecto
rs f
rom
Mo
the
r B
oa
rd
A
33
Tu
esd
ay,
Se
pte
mb
er
17
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
D0
9
IR-R
X1
2
US
-RX
11-2
D2
3
D1
1
D2
4
EX
P-T
XD1
2
A10
A14
EX
P A
2D
0
D1
3
R/W
1
PA
GE
1
A13
D1
4
A21
A07
A18
A04
D2
5
D0
0
D1
8D
19
IR-R
X1
1
A22
US
-RX
12-2
A15
A00
A26
EX
P-R
X
EX
P A
2D
1
A09
D3
0
A20
A17
D0
6
A24
A23
D3
1
D0
2
D2
2
D0
4
D0
7
D2
0
D2
6
A06
A16
A28
A11
A02
A29
A03
D0
1
A30
US
-RX
11-1
D2
7
A19
A27
US
-RX
12-1
IR_X
MIT
D1
5
D0
5
D1
6
D0
3
D1
0
Exp
-Po
rt-I
n
A01
A08
D2
8D
29
EX
P A
2D
2
A25
D1
7
/CE
1/R
DY
1
D0
8
A12
/ST
RB
1
A05
D2
1
/LO
CK
/RE
SE
T
VC
C(5
V)
VC
C(-
15
V)
VC
C(1
5V
)
J3
Exp
PW
R
123456
J1
Exp
1
12345678910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
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32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
J2
Exp
2
12345678910
11
12
13
14
15
16
17
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20
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22
23
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25
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50
488 APPENDIX F
F.2 Laptop Communications
Design Drivers
• Interface with standard equipment available on the ISS SSC
Functional Block Diagrams
The laptop transceiver is a modified DR2001 (868.35MHz) development kit (the backup
is a DR2000, 916.5MHz). The transceiver uses the custom firmware developed for
SPHERES and does not use the power regulation circuit. The power regulation has been
replaced with two diodes which step down the +5V voltage of a USB port of the SSC to
approximately 3.6V, the maximum allowed by the DR200x without power
circuitry.Figure F.13 presents the functional block diagram of the laptop communications.
[RFM, URL] provides information on the hardware design, and Appendix H on the firm-
ware and operations.
F.3 Metrology Beacons
Design Drivers
• Trigger on IR reception
• Transmit ultrasonic (US) pulse at
- ms
- N = beacon number (1-5)
• Provide selectable beacon number
Figure F.13 Laptop communications functional block diagram
DR200xTXRX
Power Mod3.6VUSB
Serial Line(RS232)
5V
∆t N –( ) +⋅ =
APPENDIX F 489
• Battery operation
- On/off switch
- Low battery LED
Functional Block Diagrams
The metrology beacons operate on two AA batteries (alkaline aboard the ISS, which pro-
vide approximately 24 hours of operation, and rechargeable in ground-based facilities).
The approximately 3V from the batteries are stepped-up to 5V to power a PIC microcon-
troller and 12V to drive the ultrasound transmitter. The PIC operates at 40MHz to create
the pulses required for the ultrasound with a timing accuracy (as per the function pre-
sented in the design drivers) of 1µs (0.3mm error). The PIC creates a pulse with 16 oscil-
lations at 40kHz. The driver circuitry effectively produces 24V pulses at the ultrasound
transmitter by alternating the two leads of the transmitter between ground and +12V dur-
ing the pulses (rather than using a 12V signal by holding one lead constant and only alter-
nating the other lead). When there are no pulses a constant 12V differential exists between
the leads, but the transmitter does not produce any ultrasound since it is a resonator which
must be exited to its resonant frequency (40kHz). The beacon uses the same IR receiver/
amplifier used in the satellite US/IR boards.
Two LED’s provide feedback on the status of the beacon. A green LED indicates the sta-
tus of the beacon. A solid green indicated the beacon is powered on; a flashing green indi-
cates the beacon is active (is transmitting ultrasound). An amber LED indicates a low-
batter condition.
The functional block diagram of the metrology beacons is presented in Figure F.14.
490 APPENDIX F
Figure F.14 Metrology beacon functional block diagram
IR RX
US TXDriverPIC
16C505
ID SW 4
Batteries(2AA)
+5V Reg +12V Reg
PWR/Active
Low Bat
APPENDIX F 491
Schematics5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Me
tro
log
y B
ea
co
n 3
- S
PH
-1-0
80
0-6
10
A
Pro
ce
sso
r &
IR
A
13
We
dn
esd
ay,
Ju
ne
12
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
US
_X
MIT
VC
C(5
V)
VC
C(5
V)
VC
C(5
V)
R1
TP
2
IR_
RC
V
1
U1
PIC
16
C5
05
1 2 3 4 5 6 7891
0
11
12
13
14
Vcc
CL
K_
INC
LK
_O
UT
RB
3
RC
5R
C4
RC
3R
C2
RC
1R
C0
RB
2R
B1
RB
0
GN
D
D4 Sta
t L
ED
C8
4.7
uF
TP
3
GN
D
1
R2
R1
2470
Y1
40M
Hz
4
3
2
1
VCC OU
T
GND
E/D
J1
IR P
AD
1 2 3 4 5 6 7 8
SW
1
TX
NU
M D
IP1 2 4 7
65
R1
1
C9
0.1
uF
R1
047
R3
10
k
492 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MAX1674 LBI: Rvin = Rout * (Vref - Vtrip) / (Vout - Vref)
Vref = 1.3, Vout = 3.3, Vtrip = 1.0 (desired)
---> Rvin = Rout * 0.15
-----> Rout = 260kohm (max) => Rvin = 39kohm
Me
tro
log
y B
ea
co
n 3
- S
PH
-1-0
80
0-6
10
A
Po
we
r S
up
plie
s
A
23
Th
urs
da
y,
Ju
ne
13
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
LBI
VC
C(+
12
V)
VC
C(5
V)
C2
47
uF
C6
47
uF
C3
0.1
uF
U3
MA
X16743
2 15 4
6
78
/LB
O
LB
I
FB
/SH
DN
RE
F
GND
LX
OU
T
D3 Lo
wB
at
LE
D
C5
0.1
uF
R5
470
L1
18
uH
JP
2
PW
R212
U2
MA
X761
1
2 345
6
7 8
LB
O
LB
I
FB
SH
DN
RE
F
GND
LX
V+
JP
1
PW
R112
JP
4
LB
I S
EL
1 2 3
C1
0.1
uF
R4
39
k
R6
26
0k
C7
0.1
uF
C4
47
uF
SW
2
Po
we
r S
W
D1
1N
58
17
12
L2
22
uH
D2
MB
R0520
APPENDIX F 493
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Me
tro
log
y B
ea
co
n 3
- S
PH
-1-0
80
0-6
10
A
US
Tra
nsm
itte
r
A
33
Mo
nd
ay,
Ju
ne
10
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
US
_X
MIT
-U
S_X
MIT
+
US
_X
MIT
VC
C(+
12
V)
VC
C(5
V)
VC
C(+
12
V)
VC
C(+
12
V)
R8
10
k
R7
10
k
R9
100
U4
CD
40
93
1 23 4
5 6
7
8 91
0
11
12
13
14
1A
1B
1Y
2Y
2A
2B
GND
3A
3B
3Y
4Y
4A
4B
Vcc
Q1
2N
39
04C
BE
TP
1
US
_X
MIT
1
U5
US
Xm
it
1 2
494 APPENDIX F
F.4 Metrology Beacon Tester
Design Drivers
• Allow operator to test each metrology beacon individually
- Manual operation
- Indicate beacon number
• Detect extraneous infrared and ultrasound signal in operational environment
Functional Block Diagrams
The beacon tester merges the design of the satellites US/IR boards and the metrology bea-
cons to allow an operator to determine correct operations of the metrology beacons. The
design uses the same infrared receiver product as the satellites and beacons. It uses the
same ultrasound amplification and infrared transmission electronics as the satellites. The
beacon tester uses the same PIC processor used in the beacons to create an infrared signal,
detect the ultrasound signals, and measure the time of flight to identify the beacon num-
ber. Figure F.15 presents the functional block diagram of the beacon tester.
The beacon tester has a manual push-button used to command an IR transmission, equiva-
lent of a satellite starting a global metrology cycle. If the beacon tester receives infrared or
Figure F.15 Beacon tester functional block diagram
IR RX
8Driver
PIC16C505
Batteries(2AA)
+5V Reg
PWR /Active/IR Rcv
Low Bat
US Rcv
IR xmt
US RX Amp
APPENDIX F 495
ultrasound signals when the push button has not been operated, it indicates an error (extra-
neous signals) by showing an E in the display. If the button is pressed and the beacon tester
receives a valid ultrasound signal it will display the beacon number (1-9). If the beacon
receives too many ultrasound signals or no signal at all, it will indicate an error (E). Any
time an ultrasound signal is received the tester flashes the blue LEDs. Whenever an infra-
red signal is received the beacon tester flashes the green status LEDs. An amber LED indi-
cates a low-battery condition.
496 APPENDIX F
Schematics
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
bypass
All the grounds in this diagram must be one single
thick trace which connects the 470uF cap to the
IRL520N
US
Be
aco
n T
este
r B
oa
rd
Bo
ard
Asse
mb
ly
A
14
Tu
esd
ay,
Se
pte
mb
er
17
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
US
-1
US
Circu
it
US
Sig
na
lU
S_
RC
V
IR_X
MIT
IR_X
MIT
IR_
RC
V
US
_R
CV
US
_R
CV
_L
ED
VC
C(+
2.5
V)
VC
C(+
5V
)
VC
C(+
5V
)
VC
C(+
5V
)
VC
C(+
5V
)
TP
1
US
_R
CV
1
C10.1uF
D1IR LED
D2IR LED
R8
22K
C2 47
uF
R9
22K
D3
IRL
ML
25
02
3
1
2
R1100 Ohm
R6
470
R5 1M
R7
470
R31 Ohm
R41 Ohm
D5 US
LE
D
C3
4.7
uF
D4 US
LE
D
C5
4.7
uF
J1
IR P
AD
1 2 3 4 5 6 7 8
C4
0.1
uF
R2
47
APPENDIX F 497
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
US
Be
aco
n T
este
r B
oa
rd
Pro
ce
sso
r &
IR
A
24
Tu
esd
ay,
Se
pte
mb
er
17
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
US
_R
CV
IR_
RC
V
IR_X
MIT
US
_R
CV
_L
ED
VC
C(+
5V
)
VC
C(+
5V
)
VC
C(+
5V
)
SW
1
SW
PU
SH
BU
TT
ON
U3
7-seg LED Display
123456
78910
Cat eCat dAn1Cat cCat dpCat b
Cat aAn2
Cat fCat g
U1
PIC
16
C5
05
1 2 3 4 5 6 7891
0
11
12
13
14
Vcc
CL
K_
INC
LK
_O
UT
RB
3
RC
5R
C4
RC
3R
C2
RC
1R
C0
RB
2R
B1
RB
0
GN
D
TP
2
IR_
RC
V
1
D6 Sta
t L
ED
R1
1470
D7 Sta
t L
ED
TP
4
GN
D1R1
0470
Y1
40M
Hz
4
3
2
1
VCC OU
T
GND
E/D
U2
DM
9374
1 2 3 4 5 6 7 891
0
11
12
13
14
15
16
A1
A2
/LE
/RB
O
/RB
I
A3
A0
GN
D/e/d/c/b/a/g/f
Vcc
TP
3
IR_X
MT
1
R1
21
M
498 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MAX1674 LBI: Rvin = Rout * (Vref - Vtrip) / (Vout - Vref)
Vref = 1.3, Vout = 3.3, Vtrip = 1.0 (desired)
---> Rvin = Rout * 0.15
-----> Rout = 260kohm (max) => Rvin = 39kohm
US
Be
aco
n T
este
r B
oa
rd
Po
we
r S
up
plie
s
A
34
Tu
esd
ay,
Se
pte
mb
er
17
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
LBI
VC
C(+
5V
)
C8
47
uF
U4
MA
X16743
2 15 4
6
78
/LB
O
LB
I
FB
/SH
DN
RE
F
GND
LX
OU
TD
9 Lo
wB
at
LE
D
C7
0.1
uF
R1
4470
JP
2
PW
R212
JP
1
PW
R112
JP
3
LB
I S
EL
1 2 3
R1
33
9k
R1
5
26
0k
C9
0.1
uF
SW
2
Po
we
r S
W
C6
47
uF
L1
22
uH
D8
MB
R0520
APPENDIX F 499
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Keep trace as short as possible
Piggyback parallel to Rf
Piggyback parallel to Rf
Me
tro
log
y 5
6.1
Sin
lge
US
Am
plif
ier
Ch
an
ne
l
A
44
We
dn
esd
ay,
Ma
rch
27
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
VC
C(+
5V
)
VC
C(+
5V
)
VC
C(+
5V
)V
CC
(+5
V)
VC
C(+
2.5
V)
VC
C(+
2.5
V)
VC
C(+
2.5
V)V
CC
(+5
V)
+ -
U5
C
LM
6154A
/SO
10 9
8
4 11
R2
310K
PO
T
13
2
+ -
U5
B
LM
6154A
/SO
5 67
4 11
+ -
U5
A
LM
6154A
/SO
3 21
4 11
D1
01
N9
14
/SO
R1
634K
R2
134K
C1
3
5p
R1
7
1M
R2
068K
D111N914/SO
C1
10
.27
0n
C1
25
p
R1
9
10K
C1
010n
R2
568K
R2
2220K
J2
US
1
1 2
R1
8
68K
R2
41
M
+ -U
5D
LM
6154A
/SO
12
13
14
4 11
US
Sig
na
l
500 APPENDIX F
F.5 Expansion Port Items
F.5.1 Expansion Port Beacon
The Expansion Port beacon was developed to allow formation flight algorithms where
each satellite can transmit an ultrasound signal from two opposite sides: one using the on-
board beacon (-X) and another using the expansion port (+X). The expansion port beacon
replicates the internal beacon, but uses the serial line in the expansion port instead of it
own IR or the use of the IR_rcv_int line which is not available to expansion items. The
firmware in the expansion port beacon accounts for the extra delay in serial communica-
tions to initiate the command so that the receiving units do not need to account for the
delay. The functional block diagram of the expansion port beacon is presented in
Figure F.16. Table F.14 describes the inputs and outputs of this expansion item.
Figure F.16 Expansion port beacon functional block diagram
TABLE F.14 Expansion port beacon signals description
Signal Type DescriptionVcc(+5V) Pwr +5V powerVcc(+15V) Pwr +15V powerGND Pwr Common GroundTX In Transmit data line (RS232)/RESET In Reset line
RS232
US TXDriverPIC
16C505
ID SW 4
+12V Reg
PWR /Active
APPENDIX F 501
Schematics5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SP
HE
RE
Be
aco
n -
SP
H-1
-10
00
-10
1-
Pro
ce
sso
r
A
12
Mo
nd
ay,
Ju
ne
09
, 2
00
3
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
NU
M1
NU
M0
NU
M2
NU
M3
US
_X
MIT
/RE
SE
T
EX
P-T
X
VC
C(5
V)
VC
C(5
V)
VC
C(5
V)
R2
C2
1 u
F
C5
.1u
TP
1IR
_R
CV
1
C3
1 u
F
U1
PIC
16
C5
05
1 2 3 4 5 6 7891
0
11
12
13
14
Vcc
CL
K_
INC
LK
_O
UT
RB
3
RC
5R
C4
RC
3R
C2
RC
1R
C0
RB
2R
B1
RB
0
GN
D
RS232
TTL
U2 DS
14
C2
32
13 8
11
10
1 3 4 5 2 6
12
91
4 7
16 15
R1
IN
R2
IND
1IN
D2
IN
C1
+C
1-
C2
+C
2-
V+
V-
R1
OU
T
R2
OU
TD
1O
UT
D2
OU
T
VCC GND
C1
1 u
F
D1 Sta
t L
ED
TP
2
GN
D
1
R3
R1
470
C4
1 u
F
Y1
40M
Hz
4
3
2
1
VCC OU
T
GND
E/D
SW
1
TX
NU
M D
IP1 2 4 7
65
R5
R4
10
k
502 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Exp
an
sio
n P
ort
- S
PH
-1-1
00
0-1
01
-
Exte
rna
l C
on
ne
cto
rs
A
13
Mo
nd
ay,
Ju
ne
09
, 2
00
3
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
A0
8
EX
P A
2D
0
EX
P A
2D
1
/LO
CK
A2
7
PA
GE
1
A0
7
A1
0
A2
1
A0
9
/ST
RB
1/R
DY
1
A1
4
A0
2
A3
0
A1
1
A0
0
A2
5
A2
8
A2
0
A1
5
A1
2
A0
3
A1
6
A0
4
A2
9
A2
4
R/W
1
EX
P A
2D
2
A0
6
/CE
1
A1
9
A0
5
A2
6
A0
1
A2
3
A1
7A
18
A2
2
A1
3
D0
3
D2
4
D0
0
D3
1
D0
7
D2
9
D1
8
D0
1
D2
3
D2
5
D1
9
D2
7
D1
6
D1
3
D0
4
D2
2
D0
9D
08
D0
6
D1
7
D1
1
D2
6
D1
0
D2
1
D1
5D
14
D3
0
D2
0
D0
2
D2
8
D0
5
D1
2
US
-RX
-12-1
-EX
T
IR-R
X-1
1-E
XT
IR-R
X-1
2-E
XT
US
-RX
-11-1
-EX
TU
S-R
X-1
1-2
-EX
T
US
-RX
-12-2
-EX
T
IR_X
MIT
EX
P-T
XE
XP
-RX
/RE
SE
T
VC
C(5
V)
VC
C(1
5V
)
JP
1
EX
80-1
00
1 3 5 7 9
112 4 6 8
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10
0
PW
R1
3 5 7 9 11
PW
R2
4 6 8 10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PW
R5
1
PW
R5
2
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10
0
APPENDIX F 503
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SP
HE
RE
Be
aco
n -
SP
H-1
-10
00
-10
1-
US
Tra
nsm
itte
r
A
22
Mo
nd
ay,
Ju
ne
09
, 2
00
3
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
US
_X
MIT
-U
S_X
MIT
+
US
_X
MIT
VC
C(5
V)
VC
C(1
5V
)
R7
10
k
R6
10
k
R8
100
U4
CD
40
93
1 23 4
5 6
7
8 91
0
11
12
13
14
1A
1B
1Y
2Y
2A
2B
GND
3A
3B
3Y
4Y
4A
4B
Vcc
Q1
2N
39
04
C
B
ET
P3
US
_X
MIT
1
C6
47
uF
US
1
US
Xm
it
1 2
C7
.1u
F
U3
LM
3480-1
2/S
OT
23
21
3
INO
UT
GND
504 APPENDIX F
F.5.2 Expansion Port Tether
The Expansion Port Tether mechanism is a prototype system to test control algorithms for
tethered formation flight spacecraft. The mechanism uses the expansion port serial line to
interface with a COTS pulse-width-modulation driver board, which drives a motor to
extend or retract a monofilament tether which connects two satellites. This prototype does
not have any sensors, allowing the design to be very simple.
Figure F.17 shows the functional block diagram of the expansion port tether board. The
board uses a SMC02B micro serial motor controller by Pololu Corporation ([Pololu,
URL]). A serial line commands the micro controller the speed and direction of the motor.
An adjustable (manual) voltage regulator in the expansion board allows testing of several
motors at voltage ranges between 6.5V to 9V. Table F.15 describes the expansion port sig-
nals used by the expansion tether board.
Figure F.17 Expansion port tether functional block diagram
TABLE F.15 Expansion port tether signals description
Signal Type DescriptionVcc(+5V) Pwr +5V powerVcc(+15V) Pwr +15V power - regulated to +7V for motorGND Pwr Common GroundTX In Transmit data line (RS232)/RESET In Reset line
RS232 MotorSMC02B
Adj Reg
2
APPENDIX F 505
Schematics5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SP
HE
RE
S E
xp
an
sio
n -
Te
the
r D
rive
r1
.0
Exp
an
sio
n P
ort
Co
nn
ecto
r
A
12
Th
urs
da
y,
Ju
ne
17
, 2
00
4
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
A0
8
EX
P A
2D
0
EX
P A
2D
1
/LO
CK
A2
7
PA
GE
1
A0
7
A1
0
A2
1
A0
9
/ST
RB
1/R
DY
1
A1
4
A0
2
A3
0
A1
1
A0
0
A2
5
A2
8
A2
0
A1
5
A1
2
A0
3
A1
6
A0
4
A2
9
A2
4
R/W
1
EX
P A
2D
2
A0
6
/CE
1
A1
9
A0
5
A2
6
A0
1
A2
3
A1
7A
18
A2
2
A1
3
D0
3
D2
4
D0
0
D3
1
D0
7
D2
9
D1
8
D0
1
D2
3
D2
5
D1
9
D2
7
D1
6
D1
3
D0
4
D2
2
D0
9D
08
D0
6
D1
7
D1
1
D2
6
D1
0
D2
1
D1
5D
14
D3
0
D2
0
D0
2
D2
8
D0
5
D1
2
US
-RX
-12-1
-EX
T
IR-R
X-1
1-E
XT
IR-R
X-1
2-E
XT
US
-RX
-11-1
-EX
TU
S-R
X-1
1-2
-EX
T
US
-RX
-12-2
-EX
T
IR_X
MIT
EX
P-T
XE
XP
-RX
/RE
SE
T
VC
C(5
V)
VC
C(1
5V
)
VC
C(-
15
V)
JP
1
EX
80-1
00
1 3 5 7 9
112 4 6 8
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10
0
PW
R1
3 5 7 9 11
PW
R2
4 6 8 10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PW
R5
1
PW
R5
2
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10
0
506 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SP
HE
RE
S E
xp
an
sio
n -
Te
the
r D
rive
r1
.0
Pro
ce
sso
r &
Drive
r
A
22
Th
urs
da
y,
Ju
ne
17
, 2
00
4
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
EX
P-T
X
/RE
SE
T
VC
C(5
V)
VC
C(5
V)
VC
C(1
5V
)
C3
0.1
uF
C5
1 u
F
U1
LM
317/S
OT
1
23
AD
J
VO
UT
VIN
C6
1 u
F
R1
500 P
OT
RS232
TTL
U3 DS
14
C2
32
13 8
11
10
1 3 4 5 2 6
12
91
4 7
16 15
R1
IN
R2
IND
1IN
D2
IN
C1
+C
1-
C2
+C
2-
V+
V-
R1
OU
T
R2
OU
TD
1O
UT
D2
OU
T
VCC GND
U2
SM
C02B
1
23
4 5
6 7 8 9
PWR
GNDVcc
RX
/RE
SE
T
OU
T0
+O
UT
0-
OU
T1
-O
UT
1+
R3
240
C4
1 u
F
C2
1 u
F
C1
0.1
uF
C7
1 u
F
R2
1k
J1
MO
TO
R
12