space the final frontier -...
TRANSCRIPT
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SpaceThe Final Frontier
Charles J. Vath, IIIASM Pacific Technology Ltd.
SEMICON West 2007July 18, 2007
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Industry Key Goals
Double the number of transistorson the chip every 18 month -Moore’s law Increase the device speed -reduce RC delayReduce power consumptionMore in less - volumetric scalinLower cost per function - always
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Moore s Law
Gordon Moore's original graph from 1965
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Gordon Moore Int
No Exponential IsForeverBut….
We Can Delay Forever
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The Question
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TrendsExtremely small form factor requirements in (X)*(Y)*(Z) Cost competitivenessAdded features/package Accelerated time to market
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Phones Of The FutureFuture products will have more volumetric dowsizing through:
Embedded ASICs and passives - transceiversIntegrated mechanics and electronics - MEMS anBiCMOSStacked packagesStacked die packagesFace to face silicon attachment
Copper to copper interconnectOptical data transfer between chips
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Example iPhone
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iPod Nano
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Planar scalingBOAC - bond on active circuitsCUP - circuit under padUltra fine pitch packages - 35 μm and belowStaggered multi-tier bondingInsulated wireFlip chip
Performance improvements - low k dielectricsVolumetric scaling - stacked dieHigher package usage efficiency Ultra low loop - below 50 μmOverhanging silicon - bond quality, loocontrol and bondability
Cost reduction - Cu wire bonding
Challenges
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Stacked Die
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Packages
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10 30 μm Die
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Small impact force to avoid diedeflection and fractureBonding 50 µm with 1.25 mm overhang
Solution
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ElpidaElpida
S Ad d P k i
Package thickness1.4 mm 30 µm die thickness40 µm looheightOverhang wirbonding technologyTechnology for injecting resin innarrow gap
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Capability Maximum 50 µm loop heightLoop height variation: < 0.5 milGood die edge clearance: > 10 µmWire : Au 0.8 mil
<WL: 2.4~3.0
Avg.4m
Avg 16µm Avg 15µm <WL:1.3~1.6
Avg.4m
(SLL)
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Increased process window for die to die bondingASM/Microbonds developed insulated wire bonding process solutions
Upper Die
Lower DieX Wire Stacked Die
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Ball Shear Data
Microbonds
X Wire 1 Bond
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Microbonds
X Wire 2 Bond
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Run Average SD
Ball Thickness (μm) 8.6 0.6
Ball Size (μm) 33.7 0.7
Wire Pull (grams) 6.46 0.2
Stitch Pull (grams) 4.31 0.4
Loop Height (mil) 9.2 0.3Shear Strength
(g/mil2)7.61
µSince2005
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BPP - 40 µmBPO - 108x34 µmWire - 18 µmBBD - 32 µmBBH - 6 µm
2007
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un Ball size Ball Thickness Ball Shear Wire Pull Wire Peel Loop H
X Y (um) (g) (g) (g) (mi
in 26.0 26.8 6.3 6.09 3.62 2.84 7.
ax 28.8 29.8 8.1 7.79 4.92 3.69 8.
ean 27.62 28.35 7.18 6.95 4.36 3.33 8.
SD 0.74 0.73 0.51 0.39 0.33 0.23 0.
/mil2 7.3
Production 2007Materials and specificationsPackage - PBGA 37µm BPPGold wire - 0.6 mil NL4 MEMCapillary:DFX-18047-221F-P38SMax WL - 6 mmTemperature - 170°C bond site
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PP with 15 meter wire
µ pwith Customers in 2007
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Drivers Cost Increasing Au price
Details Package - CSP BGAGold wire - 0.6 milBPP - 70 µmBPO - 60 µmBBD - 41 µm
Production 2007
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SpacerSpacer
ChipChip
ChipChipSpacerSpacerChipChip
SpacerSpacerChipChip
ChipChip
ChipChip
ChipChip
ChipChip
Adhesive
<Spacer process> <Spacer-less process >Shrinkage in package size
Simplification of
FOW Bonding ProcessFOW Bonding Process
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FOW Bonding Process
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BarriersExtreme low loop controlD2D stack distances become smallerPackage molded height above dibecomes thinnerBonding with thinner wiresWire stiffness concernsIncreased number of wires to offset low current capabilities
Insulated wire
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Copper Wire
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Cost reduction - price significantly lower than goldgold price up almost 3X sincelast yearBetter material characteristiElectrical - higher conductivityMechanical - stiffer
Increased in interest Applications with various
Copper Wire
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Development
4.0 – 6.0 mil Cu wire to replace thicker Al wire
0.8 – 3.0 mil Discrete/power
packages
In Mass Manufacturing
Power SO
Qualification & Pre-production
QFN
0.8 – 1.2 mil Fine pitch/IC
packages
Status
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Key achievementsMulti–tier looping for >1000 wires
Material details Package: BGAWire : 25 µmBPP : 70 µm
BondingBonding
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count: 78 length max: mmype: tape with
Loop Base
Triple Stitch FLooping Overview
Cu Wire Bonding on QFN
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ey challengesBending and twisting of tope during bondingInconsistent ball height & squeeze out
tatusASM in house development on goingDie thickness - 100 µmOver hang - 1.2 mm Wire - 20 µm
Normal D
OverhanDie
Dies
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BarriersCopper wire usage will continue to expandUpper limit on wire size gold/copper compatible systemsRigidity and strength issues dto material properties of coppwire
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Flip Chip
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Image senso
(Bump#31) BLT = 23.4µmmp#18) BLT = 25.0µm
Pre-bonding under low temperature and force to ensure contact between bump and padAdhesive is cured under high
bonding force and temperature at final bonding stageProcess concerns: NCP or ACF
material curing propertiesWarpage of the substrateAlignment of the
Thermal CompressionThermal Compression
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mple with wer degree particle formationbump does t touch ass rectly
mple with gher gree of rticle formationbump
~0.4 μm
0 3
~1.1 μm
Main bond pressure = 0.5 bar (Sample T7)
Main bond pressure = 0.7 bar
Using ACF
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Flat and normal bump
Bumping Capability
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Double and triple bump
Bumping Capability
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Flex and cone bump
Bumping Capability
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2mils Au Bump 1.3mil Au Bump
Au Bumping Experience
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Improved handling of thin dieNeed to understand impact of handling reliability and performance - t < 30 µ
Wire with more sophisticated propertiesManipulated regrowth in FABMinimized HAZ
Processes for cleaner interfacesReduce organic contamination prior to wire bondRemove oxides prior to wire bondRemove oxides prior to wafer bonding
Low k will still be a factor into the future – Fab variations in film characteristics - weakened mechanical characteristics
Technology Needs
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Increased use of:AES - Auger electron spectroscopXPS - x-ray photoelectron spectroscopyFIB - focused ion beamIon polishingOIM - orientation imaging microscopy
XRD - currently being investigatefor wafer level defectsEdge exclusion zone monitoringThermal slip monitoringRelaxation onset monitoring
Metrology Needs
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Orientation imaging microscopy (OIM)Grain structure using OIMOIM analysis to study crystalline microstructures of Cu
EDX mapping Ion beam polisher
Si KaAl Ka1Characterization Lab
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More Than Moore
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2005
Years
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What is 3D IntegrationWhat it is:
ITRS 2005: 3D technologies - substantial fraction of die to die interconnections are nplanar to the package substrateWafer level or die level technology
D2W and W2W stackingElectrical signals travel vertical directiodirectly from die to die
Very limited HVM today (Micron “Osmium”)What it’s not.
Package level technologies (stacked die and PElectrical signals travel through a looped wior solder ball via a carrierIn HVM today for SIP and other multi-chip devices
AdvantagesPackage size, hetero-integrationIncreased device speed and reduced power
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gh Si via SM ECMD Cu
SiSi
D Through Hole Via Fill and TBonding
Critical technologies
Via etch/laser drill
Sea of Cu-Cu Studs in Si. Sifor demonstration purpo
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•SOI wafers•Via last
•SiO fusion bonding
IBM
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Samsung Stacked Die
April 23, 2007 - Samsung Electronics Co., Ltd.Advanced Packaging
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The TrendExternal package planar scaling first utilized to reduce board area.Concurrently mask planar scaling used treduce chip size of increase functionalityInternal package scaling evolved with SiP, MCM and othersTrench technologies allowed for furtherchip scaling - volumetricStacked die, PoP and folded packages began the Z axis scaling in packaged chipsActive layer stacking with TSV will continue the volumetric scaling of functional density
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Most ImportantlyInnovation Will Be Defined By The Limits
OfOur Imagination
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