sonet/sdh.pdf

1Telecomm. Dept.Faculty of EEE

Telecom NetworksHCMUT

Telecommunication Networks

Dr. Ing. Vo Que Son

Email: [email protected]



Chapter 3: SONET/SDHCurrent transmission technologies (PDH)The Synchronous Digital Hierarchie (SDH)Bit rates, frame structures and interfaces in SDHBasic elements of STM-1SDH network elementsMonitoring, maintenance in SDH

Chapter 4: ATM NetworksATM FundamentalsRudimentary ATM ConceptsATM Reference ModelATM Service CategoriesTraffic Management ATM Transport Standards

Content



Bit rates in PDH

American National Standards Institute

European Conference of Postal and Telecommunications Administrations

Comparison of the ANSI and CEPT Hierachies



Plesiochronous Drop & Insert

OLTU

34 - 140

8 - 34

2 - 8

OLTU

34 - 140

8 - 34

2 - 8

OLTU

34 - 140

8 - 34

2 - 8

OLTU

34 - 140

8 - 34

2 - 8

main

stand-by

140 Mbit/s 140 Mbit/s

Line Terminating Unit Line Terminating UnitDrop & Insert Station

1,2 ................. 64 1,2 ................. 64

OLTU: Optical Line Terminating Unit



PDH Mux/Demux Bit interleave, Add/drop based on hieracchies

Besides the bit interleave, the multiplexer has a function to create a new CEPT frame for the sum signal. Within this frame, the tributary information is represented by the two complete CEPT framse of input signals I and II



PDH and SHD Plesiochronous Signals: Data signals, which have the

same nominal transmission rate, but come from different sources

Slightly higher or lower value than nomial but rate

Signals are almost synchronous

Synchronous Signals: Data signals with the same nominal

bit rate, but come from different sources

Controlled by a central clock (so-called Master Clock)

Signals are clock-aligned to each other: Synchronous



Why SDH?

Simpler multiplexing

low SDH level can be directly identified from higher SDH level

Simple Drop & Insert of traffic channels

direct access to lower level systems without synchronization

Allows mixing of ANSI and ETSI PDH systems

SDH is open for new applications

It can carry PDH, ATM, HDTV, MAN, IP...

SDH provides TMN (ECCs)

for centralized network control



Synchronous Network Structure

34Mbit/s140Mbit/s

STM-1

STM-1 / STS-3c Gateway to SONET

ATMSwitch

2Mbit/s

34Mbit/s

STM-1

LAN

STM-1, STM-4

2Mbit/s

8Mbit/s34Mbit/s

140Mbit/s

ADM : Add Drop MultiplexerDXC : Digital Cross ConnectTM : Terminal MultiplexerDSC: Digital Switching CenterLAN: Local Area NetworkDWDM: Dense Wavelength Multiplexing

DSC

DXC

ADMADM STM-4/-16

ADM

DWDM



SDH Bit rates



Path Denominations

VC-2VC-1

VC-4VC-3VC-12

VC-4VC-3

VC-2VC-1

VC-4 VC-3 VC-12

VC-4VC-3

Reg

S M

X

S M

X

MultiplexSection

RegeneratorSections

Higher Order Path

Lower Order Path

STM-nRSOH

STM-nRSOH

STM-n MSOH

VC-4/3 POH

VC-1/2/3 POH



Network Node Interface (NNI)

MU

X /

DEM

UX

MU

X /

DEM

UXPDH PDH

SDH SDH SDH

Reg.

CC

NNI NNI NNI

ITU-T Rec.:G.707 Synchronous Multiplex StructureG.703 Electrical characteristicG.957 Optical interface characteristic

The Network Node Interface (NNI) specifications are necessary to enable interconnection of synchronous digital network elements for transport of payloads



STM-1 Frame The 2-dimension representation of an STM-1 frame includes 9 rows with

270 bytes each 1 byte can carry a traffic = (1:125us)*8 = 64 kbit/s



STM-1 An STM-1 frame consists of three blocks: Section Overhead (SOH): additional transmission capacity Pointer (PTR): indicates the start address of the tributary information Payload: tributary signals/information

The frames are transmitted in intervals of 125us (from top left to bottom right) An STM-1 frame is repeated (1s:125u) = 8000 times per second. Thus, every byte

in an STM-1 frame has a transmission capacity of 64 kbit/s

(all values are given in bytes)



STM-N Multiplexing

Transmission Frame 3 x STM-1 1 x STMx3

What is the duration of STM-3 frame? (125us like STM-1 frame)

STM-1

STM-1

STM-1

STM-3

STM

270 bytes

3*270 bytes



Pointer Adjustment

In a synchronous network, the frames STM-1 #1 and STM-1 #2 are usually delayed in time (e.g. due to different run times): PTR adjustment

The modification of PTR during synchronization is called pointer adjustment operation

Types of pointer adjustment: positive and negative



Optical Line code The optical line code for all STM-N signals is a scrambled NONE-RETURN-

TO-ZERO (NRZ) code By scrambling the NRZ code it is ensured that when sending an STM signal

on the line, the signal includes sufficient clock edges to allow timing recovery on the receiver side. The transmission of long 0 or 1 bit sequence must be avoided



Mapping 140Mbps to container C-4 Container C-4: 260 byte x 9 row x 8 bit = 18720 bit Number of bits (Nominal bit rate: 139.264 Mbit):

139.264 Mbit/s : 8000 Hz = 17408 bit 140 Mbit/s can be mapped to C-4

Over-capacity: Fixed justification bits and byte (approximate clock alignment) Justification opportunity bits (positive justification for precise clock

alignment) Justification control bits (justification information bits)



Integrating 140Mbit/s into STM-1

Container

Virtual Container

Administrative Unit

Synchronous Transport Module

Path Overhead

Pointer

Section Overhead

Plesiochronous signal 140Mbit/s

C4

VC-4

AU-4

STM-1



Interleaving C-4 to STM-1

AU Pointer

RSOH

MSOH

9 261

J1B3C2G1F2H4Z3K3Z5

C-4140 Mbit/s

260

C-4 transport capacity?



Mapping 3x34Mbps -> STM-1 The reason for the over-capacity is a recommendation by ITU-T specifying

that the transmission of a 44,736 Mbit/s signal (ANSI) must also be carried out in the container C-3

44,736 Mbit/s : 8000 Hz = 5593 bit When considering the number of payload bits per STM-1 frame:

9 byte x 261 x8 = 18720 bit It emerges only 3 C-3 (3x 6048 bit) at maximum can be transmitted

per STM-1 frame: only 3x34 Mbit/s instead of 4 x 34 Mbit/s

6048 bit total capacity of the C-3

5593 bit of the 44 Mbit/s signal (ANSI)9

84



Mapping 3x34Mbps -> STM-1 The interleaving of 3 x 34 Mbit/s signals into the STM-1:

C-3 transport capacity: 84 X 9 x 64 kbit/s = 48.384 kBit/s

AU Pointer

RSOH

MSOH

J1

B3

C2

G1

F2

H4

Z3

K3

Z5

H1 H1 H1

H2 H2 H2

H3 H3 H3

260

fixed stuffing

84

C-3

J1

B3

C2

G1

F2

H4

Z3

K3

Z5

J1

B3

C2

G1

F2

H4

Z3

K3

Z5

J1

B3

C2

G1

F2

H4

Z3

K3

Z5

C3

34 Mbit/s

9 261

VC-3 #1

VC-3 #2

VC-3 #3

VC-4 POH

VC-3 POH



Mapping 3x34Mbps STM-1



RSOH

MSOH

AU pointer

VC-4

TUG-3

TUG-2

TU

-12

VC-12

Tu pointer

Mappings 63 x 2 Mbit/s



AU-4 Pointer

RSOH

MSOH

J1

B3

C2

G1

F2

H4

Z3

K3

Z5

1 2 3 4 5 6 7 8 9 10...........................................261

A B C A B C A A B CS

T

U

F

F

I

N

G

S

T

U

F

F

I N

G

. ......

1 86TUG-3

(A)

. ......

1 86TUG-3

(C)

. ......

1 86TUG-3

(B)

Mapping and Multiplexing (1)



1 2 3 4 5 6 7 8 9 10...........................................86

N

P

I

E3 F3 G3S T

U

F

F

I N

G

S

T

U

F

F

I N

G

A1 B1 C1 D1 E1 F1 G1 A2

1 2 3 1 2 3 1 2 3 1 2 3

TU-12

#1

TUG-2

(A)

TU-12

#3.....

1 2 3 1 2 3 1 2 3 1 2 3

TU-12

#1

TUG-2

(B)

TU-12

#3.....

1 2 3 1 2 3 1 2 3 1 2 3

TU-12

#1

TUG-2

(G)

TU-12

#3.....

TUG-3NPI: Null Pointer Indication

1001 XX11 1110 0000 XXXX XXXX

TU-12s

occupy 36

bytes per

frame

Mapping and Multiplexing (2)



V5R

32 bytes (32x8I)

RJ2

C1 C2 O O O O R R

32 bytes (32x8I)

32 bytes (32x8I)

32 bytes (32x8I)

RK4

R

N2R

C1 C2 O O O O R R

S2 I I I I I I I

140 B

yte

s

35

bytes in

one

VC-4

500 s

V5: VC-12 Path Overhead

R: fixed stuffing bits

J2: Path Trace

C1/2: Justification control bit

O: Overhead bit

N2: Network Operator byte

K4: APS

S2: Justification opportunity bit

I: Info-bit

Payload

VC-4 Payload

V4

XXX XX00

Payload

VC-4 Payload

V1

XXX XX01

Payload

VC-4 Payload

V2

XXX XX10

Payload

VC-4 Payload

V3

XXX XX11

Payload

VC-4 Payload

V4

XXX XX00

VC-12 Structure:

H4: Indicates the number of Vx

V1,V2,V3: TU-12 Pointer

H4

H4

H4

H4

H4

VC-4 POH

Mapping 2 Mbps (asynchronous)



Mapping ATM STM-1

ATM cell: 53 bytesMultimedia data



Summary



Jitter and Wander

Jitter: Jitter is the short-term phase variations of the significant instants of a digital signal from their ideal positions in time. It is

the deviation of the significant instants of a digital signal from

the ideal, equidistant values. The significant instant can be any

convenient, easily identifiable point on the signal such as the

rising or falling edge of a pulse. Otherwise stated, the

transitions of a digital signal invariably occur either too early or

too late when compared to a perfect square wave.

Wander: A second parameter closely related to jitter is wander. Wander similarly refers to long-term variations in the significant

instants. ITU-T G.810 classifies jitter frequencies below 10 Hz

as wander and frequencies at or above 10 Hz as jitter.



Jitter and Wander Definitions

Jitter

free

clock

(ideal)

jittered

clock

phase-

deviation

time



Sources of Jitter and Wander

Interference signals

Pattern dependent jitter

Phase noise

Delay variation

Stuffing and wait time jitter

Mapping jitter

Pointer jitter



Jitter Measurement Filters

Amplitude / dB

Frequency / Hz10 Hz

STM-1: 500 Hz 65 kHz 1.3 MHzSTM-4: 1 kHz 250 kHz 5 MHzSTM-16: 5 kHz 1 MHz 20 MHz

HighFrequency

Jitter

Jitterincluding

lowerFrequency

Components

TotalJitter

Wander

Values according to ITU-T Rec. G.825 and G.813

Max. Jitter Amplitude: 1,5UI 0,15UI



VC-4 Pointer The AU pointer block comprises 9 bytes, 3 of which are used to address a

VC-4 (AU-4 pointer) The remaining 6 bytes are required for two further pointers in the ANSI

hierarchy.



Negative justification Every MUX is controlled by an internal clock (values assumed: f1, f2, f3

which slightly differ from each other The clock f1 at the MUX 2 input is somewhat higher than the internal

clock (f2). Therefore, an additional transmission capacity must be provided in the MUX2 output signal

How to solve this problem in SDH without losing information?



Negative justification The VC-4 which participate the negative justification, is shifted 3 bytes. The

next VC-4 starts one address earlier (address -1) In SDH, a justification operation (positive or negative) can be carried out no

more than once in every third STM-1 frame



Positive justification The VC-4 involved in the positive justification operation is delayed

by 3 bytes. The next VC-4 starts one address later (address +1)



Overhead bytes



Overhead Byte Functionality

A1, A2 Frame synchronisationB1, B2 Parity bytes for transmission error monitoringJ0 Regenerator section trace D1... D3 Regenerator section DCCD4.. D12 Multiplex section DCCE1, E2 Orderwire for voice communicationF1 User channel for maintenance purposes (data, voice)K1, K2 Automatic protection switching (APS)S1 Synchronisation status messageM1 MS-REI (remote error idication)

J1 Higher order path traceB3 Path parity byte for error monitoringC2 Signal Label (composition of payload)G1 Path status and performanceF2, F3 Path user channelsH4 Payload specific byteK3 Automatic protection switching (APS)N1 Network operator byte (Tandem Connection Monit.)

V5 Error check, path status, signal labelJ2 Lower order path traceN2 Network operator byte (Tandem Connection Monit.)K4 Automatic protection switching (APS)

SOH

VC-3/4

POH

VC-1/2

POH



BIP

A special parity procedure is employed for bit error monitoring in an SDH signal/path, the so-called Bit Interleaved Parity procedure (BIP)



BIP - Principles A BIP-4 code, for example, is generated in the following way: The

message to be monitored (test block) is subdivided into 4-bit unit and passed to the parity generators



BIP - Principles

Interferences on the line can thus be detected

On the receiver side, a CODE WORD is generated on the basis of the same procedure, and is then compared to the code word on the transmit side



SOH-B1: Regenerator Section BIP-8 The B1 byte transmits a parity code, which is used for bit error monitoring

on STM-1 regenerator sections The b1 byte is transmitted only in STM-1 #1 of an STM-N B1 Byte is calculated over all bits of the previous STM-N frame after it has

been scrambled. This calculated value of B1 is then placed in the next following frame before it is scrambled. In the case of an STM-1 frame, the value of the parity byte (B1) is calculated over 9 rows by 270 columns or 2430 bytes



SOH-C1: STM Indication Byte Every STM-1 frame is assigned an identification (ID) number before being

multiplexed to an STM-N

During demultiplexing, the identification is used for determining or checking the position of the individual STM-1 in the STM-N



SOH-E1..E2: Orderwire Bytes These two bytes provide service channels and can be used for voice

communication (64kbit/s in each case)

The E1 byte is used as a voice channel between regenerators and multiplexers (OMNIBUS channel)

The E2 byte is used only as a voice channel between multiplexers (EXPESS channel)

E1 and E2 are defined in STM-1 #1 of an STM-N signal only



SOH-F1: User Channel Byte The F1 byte is reserved for the network operator and can be used as 64

kbit/s auxiliary channel (e.g. data communication via PC)

This byte is only transmitted in STM-1 #1 of an STM-N signal



SOH-D1..D12: Data Communication Bytes DCCThese 12 bytes are provided for the transport of monitoring and

control data in a network management system.

The byte D1-D3 (DCCR) are used for the communication between TMN and multiplexers and regenerators respectively

The byte D4-D12 (DCCM) handle only the communication between TMN and multiplexers

Example of a Small Management System



SOH-B2 : Multiplex Section BIP-243 bytes B2 transmit a parity code used for bit error monitoring on

multiplex sections. All B2 bytes are defined for transmission of an STM-N signal.

B2 bytes are calculated prior to scrambling, but exclude the Regenerator Section Overhead bytes (A1, A2, J0, B1, E1, Dn, etc.). They are then placed in the appropriate column, i.e., B2 Col.1, B2 Col.2, B2 Col.3 (for an STM-1). of the next following frame before it is scrambled



SOH-K2: Automatics Protection Switching APS

The entire K1 byte as well as bits 1-5 of the K2 byte can be used for an automatic, bi-directional 1+1 switchover to a standby line

MUX1 initiates (via K2 byte) the switchover in MUX2



SOH-K2: AIS, FERF The bit 6,7 and 8 of the K2 byte fulfill error indication functions. If these bits

are set to 110 and then transmitted, the receiver interprets the message as multiplex section FERF (Far End Receive Failure)

If these bits are set to 111: multiplex section AIS (Alarm Indication Signal)



SOH-S1: Synchronization Status Message

In order to avoid synchronization loops, the content of S1 in the backward direction is always Dont Use for Synchronization



SOH-M1: Multiplex Section-Far End Block Error Byte (MS-FEBE)

By evaluating the 3 x B2 bytes, the M1 byte can report bck the number of parity code violations



POH-J1: Path Trace Byte

Using the J1 byte, every path can be assigned a trace. This trace enables the path to be trailed through the SDH network

This is of particular importance in the case of cross-connect controlled through-connections



POH-B3: Path BIP-8 byte The B3 Byte is used to provide an error-monitoring function for Path data

including the payload and the Path Overhead POH

The bit error monitoring is performed in accordance with a parity procedure

The B3 byte transmits the parity code of an VC-4. The byte is generated at the beginning of the path and is evaluated only at the end of the path



POH-C2: Signal Label The C2 byte indicates type and composition of the VC-4 tributary

information



POH-G1: Path Status The G1 byte is used to report back the fault from path end to path start Bits 1-4: contain the number of defective blocks (parity violations)

detected by the receiver B3 byte and are returned to the opposite direction

0000: 0 error . 1000: 8 errors

Bit 5 contains an alarm indicator and is returned in the opposite direction if no valid signal was received in the VC-4. It is set to 1 if there is:

No valid signal An AIS A wrongly through-connected path (J1)



POH-F2: Path User Channel The F2 byte (64 kbit/s) is defined for communication purpose for the

network provider (e.g. exchange of data between 2 PC)



POH-H4: Multiframe Indicator Bits 7 and 8 functions as a frame

label for a multiframe TU-12 Bits 7 and 8 = 0 0 mark the

beginning of a multiframe TU-12 (V1) in the next VC-4



POH-V5: Path BIP-2, Signal Label and Path Status

The V5 byte is used for bit error monitoring, signal detection and path status indication on the VC-12

Bit 1 and bit 2 carry the parity code of a VC-12. It is generated at the beginning of a path and evaluated at the end of the path

Bit 3 is set to 1 and returned in the opposite direction if one or more errors were detected via the BIP-2 = PATH Far End Block Error

Bits 5 to 7 indicates the type and composition of the VC-12 tributary information

Bit 8 is an alarm indicator and is returned as 1 in the opposite direction if:

No valid signal An AIS A wrongly through-connected path (J1)

was received in the VC-12 = PATH Far End Receive Failure



Monitoring: Far End Block Error There are two types of FEBE:

PATH FEBE SECTION FEBEif a code error was determined in B3 byte: B3 BER>10-4

AIS in the VC-4 No signal in the VC-4 Wrong path trace in J1 byte Bit 5 of the G1 byte in VC-4 POH is set to 1

if a code error was determined in B2 byte: B2 BER>10-3

SECTION AIS Loss of STM-N signal Loss of frame alignment Bite 6,7 and 8 in K2 byte in MSOH are set to 110



Monitoring: Far End Receive Failure There are two types of FERF:

PATH AIS SECTION AIS

B3 BER>10-4

No signal in the VC-4 Wrong path trace in J1 byte Path AIS already received

Section AIS already received (in generators)

NO signal in the STM-N (in generators) Loss of frame alignment (in

generators) Internal functional disturbances in the

MUX/REG systems



Tandom Connection Monitoring



A simple network using SONET equipment



SDH Network Elements

SDH Repeater

STM-n STM-n Applications:Line Signal Regenerationin Point-to-Point and Ring Networks

Terminal Multiplexer

STM-nPDH & STM-mTributariesm



Add Drop Multiplexer (ADM)

STM-1/4STM-1/4

Tributary Ports : n x 2 Mbit/s ( 34 Mbit/s)

ADM

......

WEST EAST



Add Drop Multiplexer (ADM)



Synchronous Cross Connect (CC)

16x16x

4x 4x

VC11

34

2

SDH Multiplexer

VC 4VC 3VC 12

2.4 Gbit/s

622 Mbit/s

2.4 Gbit/s

622 Mbit/s

140 Mbit/s

34 (45)Mbit/s

2 (1.5)Mbit/s

140 Mbit/s

34 (45)Mbit/s

2 (1.5)Mbit/s

155 Mbit/s155 Mbit/s

VC12

VC3

140

VC4

VC12

VC3

140

2

2

VC12

VC12

2

2

140

VC12

2

2

34

34

2

2

VC12

140 Mbit/s

34 Mbit/s 34 Mbit/s

140 Mbit/s

VC4

140

155VC4

155 Mbit/s



Synchronous Line Equipment

OpticalReceive

UnitSyncDEMUX

4

4

4

4

OpticalTransmit

UnitSyncMUX

4

4

4

4

Management Communication Unit

Service Channel Unit

OverheadProcessing Unit

Data Channels

Service Channels

PC / TMN (Q)

16 x 140 Mbit/s

or

16 x STM-1

16 x 140 Mbit/s

or

16 x STM-1

STM-16

STM-16

SLX 1/16



AT4848 SoCMSTP: Multiservice Transport ProtocolMSPP: Multiservice Provisioning Platforms

http://www.arrivetechnologies.com/arrive_products_tech_msadm.htm



AT4848 SoC

http://www.arrivetechnologies.com/arrive_products_tech_msadm.htm



Hybrid Networks Connect Old and New Technologies

2Mbit/s

34Mbit/s

140Mbit/s

STM-1

STM-4

STM-1 / STS-3c Gateway to SONET

TM

DXC

ADMADMATM

Switch

STM-4/-162Mbit/s34Mbit/s

140Mbit/s

STM-1

LAN

2Mbit/s

ADM

STM-1

STM-1, STM-4

2Mbit/s

8Mbit/s

34Mbit/s

140Mbit/s

ADM : Add Drop Multiplexer

DXC : Digital Cross Connect

TM : Terminal Multiplexer



Local Network

STM-4

STM-16

STM-1

Exchange

FlexMux

Subscriber

Access

Mux

64/2M

Local

Exchange

Trunk Network

L 1

Trunk Network

L 2

Trunk

Network L 2

SDH Network Topology



Taxonomy of SONET networks



Configuration: SONET networks

Point-to-Point network

Multipoint network



Automatic protection switching in linear networks



A unidirectional path switching ring



A bidirectional line switching ring



A combination of rings in a SDH network



A mesh SDH network



Future Trends - WDM Systems

Pirelli : WaveMux 320032 x OC-48 channels80Gbit/s over 1200km

40 x OC-48 channels100Gbit/s over 600km

Ciena :

There may not be a near term need, but this is the direction that networking will take next for 3 or 4 years.

Current Systems : 4, 8, 16 x OC-48 (MCI, Sprint)

sonet/sdh.pdf

Documents

rate signals

data signals

sdh network elementsmonitoring

higher sdh level simple

etsi pdh systems sdh

shd plesiochronous signals

new cept frame

lower level systems