solid electrolytic capacitor design for high temp applications

23
© 2015 KEMET Electronics Solid Electrolytic Capacitors Designed for High Temperature Applications Kristin Tempel and Randy Hahn High Temperature Electronics Network July 7, 2015 http://go.kemet.com/wp1015

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Page 1: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Solid Electrolytic Capacitors Designed

for High Temperature Applications

Kristin Tempel and Randy Hahn

High Temperature Electronics Network

July 7, 2015

http://go.kemet.com/wp1015

Page 2: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Outline

• Basic construction of Solid Tantalum Capacitor

• High temperature timeline

• Known temperature related failure mechanisms

• Technical challenges at high temperature

• Performance testing and path forward

• Questions

2

Page 3: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Basic Construction of Solid Ta Capacitor

Fundamental Materials:

• Ta anode

• Ta2O5 Dielectric

• MnO2 Cathode

Secondary Materials:

• Carbon

• Metallized Layer

• Adhesive

• Leadframe

• Mold Epoxy

3

Page 4: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

What Makes Tantalum Special?

• Surface area per unit of weight creates high CV/g

– Volumetric efficiency

• Valve metal capable of growing thin dielectric

– High dielectric breakdown voltage: 470V/µm

VrTa2O5

Thickness (nm)

2 16

4 32

6 48

16 128

35 280

50 400

𝑪 ∝𝒌𝑨

𝒅

4

Page 5: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Surface Mount Tantalum Timeline

• 125°C maximum temperature for decades

• 2003 first 150°C release

• Capability increases by 25°C approximately every 4 years

• Multiple manufacturers poised to release 230°C platforms

125°C 150°C 175°C 200°C 230°C

2003 2007 2011 2015

5

Page 6: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Temperature Related Failure

Mechanisms

Page 7: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Temperature Related Failure Mechanisms

Known Failure Mechanism Method to Mitigate

Crystallization: defects in Ta-Ta2O5

interface creates leakage site

• Low charge Ta powders

• High Vf:Vr

• F-TECH technology increases

chemical purity and eliminates hidden

dielectric defects

Oxygen Migration into Ta metal from

Ta2O5 leave oxygen vacancies creating

conductivity across dielectric. Causes

cap change with bias, temperature,

frequency.

• Higher Vf:Vr

• Heat treatment

Ta

Ta2O5

7

Page 8: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Technical Challenges at High

Temperatures

Page 9: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

All of the external cathode layers were modified, and in some

cases replaced, in order to provide a robust design capable of

withstanding up to 1000 hours at 230°C.

Cathode Layers

Silver

MnO2

Carbon

Ta

Mold epoxy

9

Page 10: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

MnO2 Solid Electrolyte

• Stable to temperatures in excess of 500°C

• Deposition process modified to ensure adequate buildup to

protect the anode

-8

-6

-4

-2

0

2

4

6

8

-10

-8

-6

-4

-2

0

0 200 400 600 800

He

at

Flo

w

We

igh

t Lo

ss (

%)

TGA for MnO2

Weight Loss (%) Heat Flow

10

Page 11: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Carbon Layer

• Binder in conventional Carbon 1 degrades at temperatures in excess of 200°C

• In-house Carbon 2 formulated to withstand continuous operation at 230°C

• Weight loss observed between 230-400°C due to oxidation to CO2 of oxygen containing surface functional groups of carbon black

-10

0

10

20

30

40

-50

-40

-30

-20

-10

0

0 200 400 600 800

He

at F

low

We

igh

t Lo

ss (

%)

TGA for Carbon 1

Weight Loss (%) Heat Flow

-5

0

5

10

15

20

25

30

-40

-30

-20

-10

0

0 200 400 600 800

He

at F

low

We

igh

t Lo

ss (

%)

TGA for Carbon 2

Weight Loss (%) Heat Flow

-20

-15

-10

-5

0

0 100 200 300 400 500 600

We

igh

t Lo

ss (

%)

TGA for Components of Carbon 2

Carbon Black Graphite Binder11

Page 12: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Metallized Layer

• Binder in the silver paint improved the capability to withstand temperature: Conventional Silver 1 vs Modified Silver 2

• Silver migration at elevated temperatures is known issue

• Experiments confirmed leakage shifts occurred only after the application of the silver paint

-10

0

10

20

30

40

50

-20

-15

-10

-5

0

0 200 400 600 800

He

at F

low

We

igh

t Lo

ss (

%)

TGA for Silver 1

Weight Loss (%) Heat Flow

-10

0

10

20

30

40

50

-14

-12

-10

-8

-6

-4

-2

0

0 200 400 600 800

He

at F

low

We

igh

t Lo

ss (

%)

TGA for Silver 2

Weight Loss (%) Heat Flow

10001001010.1

99

95

90

80706050403020

105

1

0.1

Leakage (uA)

Pe

rce

nt

Initial

1000 hr

Leakage Shift During 220°C Shelf Strorage

12

Page 13: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Silver migration at elevated

temperature unstable leakageNickel plating stable leakage

Metallized Layer

100101

99

95

90

80

70

60

50

40

30

20

10

5

1

LC

Pe

rce

nt

16

1,555 0,5361 53 6,532 <0,005

1,438 0,3551 53 3,229 <0,005

1,403 0,3593 53 2,790 <0,005

1,477 0,3797 53 3,121 <0,005

1,400 0,3582 53 3,139 <0,005

Loc Scale N AD P

0h

250h

500h

750h

1000h

200C

Time @

Lognormal - 95% CI

Probability Plot of LC

DC Leakage (mA)

DC Leakage

10001001010,1

99

95

90

80

70

60

50

40

30

20

10

5

1

LC

Pe

rce

nt

16

0,6831 0,2943 30 1,591 <0,005

1,484 1,096 30 4,843 <0,005

3,032 1,308 30 0,962 0,013

3,802 0,9251 30 2,574 <0,005

Loc Scale N AD P

1xC/-/Ag 0h

1xC/-/Ag 250h

1xC/-/Ag 500h

1xC/-/Ag 750h

VAR 200ºC

TIME @

Probability Plot of LCLognormal - 95% CIDC Leakage

DC Leakage (mA)

KEMET has developed proprietary and patented materials and processes to successfully

plate metals on the carbon layer in Tantalum capacitors

Solid Electrolytic Capacitors with Improved Reliability, Chacko, Antony; US Patent 8,310,816 & 8,896,985 &

8,503,165

Solid Electrolytic Capacitors with High Temperature Leakage Stability, Chacko et al, USP Pending, US

2014/0055913

Several additional patents are pending13

Page 14: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Adhesive

• Replacing standard silver adhesive with Transient Liquid

Phase Sintering (TLPS) adhesive improves peel strength at

elevated temperatures when used with Ni plated metallized

layer

METHOD OF IMPROVING ELECTROMECHANICAL INTEGRITY OF CATHODE COATING TO

CATHODE TERMINATION INTERFACES IN SOLID ELECTROLYTIC CAPACITORS, Chacko,

Antony; US 8,896,986

0

0.05

0.1

0.15

0.2

0.25

0.3

Ag/Ag adhesive Ag/TLPS Ni/Ag adhesive Ni/TLPS (Trial 1) Ni/TLPS (Trial 2)

Pee

l Str

engt

h (

kg)

Plating Layer/Adhesive

Peel Strength Comparison

Room Temp 165°C

Peel Test

14

Page 15: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Encapsulant Material

• Severe layer separation occurred at high temperature with

conventional mold epoxies

• High temperature epoxy greatly enhanced ESR stability

Conventional Epoxy High Temperature Epoxy

Anode AnodeCathodeCathode

Epoxy Epoxy

Page 16: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

• Breakdown voltage (BDV) is the ultimate test of dielectric strength

• BDV correlates with long term reliability

• SBDS is a non-destructive testing technique that simulates BDV

• Does not damage dielectric

• Screening performed on 100% of product

Screening of Electrolytic Capacitors, Freeman, Yuri; US Patent 7,671,603

Apparatus and Method for Screening Electrolytic Capacitors, Paulsen, Jonathan, et al. US 8,441,265

Simulated Voltage Break Down Screening

(SBDS): Concept

LKG Before vs. After Screening495X107K016

0

2

4

6

8

10

12

14

16

18

0 2 4 6 8 10 12 14 16 18

DCL BEFORE uA

DC

L A

FT

ER

uA

I(V) in KO D16-25

0

5

10

15

20

25

30

35

40

0 20 40 60

Voltage, V

Cu

rre

nt,

uA

#9

#12

1.2 MOhm

7.1 MOhm9 MOhm

BDV

AVER

RV

16

Page 17: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Simulated Voltage Break Down Screening

(SBDS): Results

Final Voltage, V

Pe

rce

nt

50403020100

99.9

99

95

90

80

706050403020

10

5

1

0.1

Mean 37.26

StDev 4.604

N 290

AD 66.448

P-Value <0.005

SCREENING495X107K016 0646H128

BDV mean = 43 V. TEST V = 58.5. Rs = .47 Mohm. tmax = 90 s

Excellent

Weak

17

Page 18: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Performance Testing

Page 19: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Mounting Reflow Profile

• High Melting Point (HMP) Solder used to attach parts to

specially designed high temp boards for all testing

• Liquidus temperature 302°C

• Soldering iron and convection reflow oven used

• Zero post mount failures

19

Page 20: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Capacitance Change with Temperature

6.50

7.00

7.50

8.00

8.50

0 50 100 150 200 250

Cap

acit

ance

(m

F)

Temperature (°C)

Capacitance vs. Temperature

T502D685-035

Capacitance change with temperature follows typical curve for solid Ta capacitor

20

Page 21: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

DC Leakage vs Temperature

0.0001

0.01

1

100

2.00 2.25 2.50 2.75 3.00 3.25 3.50

y=11*exp((0.55/8.62)*(2.0-x)*100)Median DCL

25ºC65ºC105ºC155ºC200ºC

230ºC 175ºC 125ºC 85ºC 45ºC 0ºC

Vtest = 7VRs = 82k

Median DCL Calculated from a sample of 20pcs.

Inverse Absolute Temperature 1/T (10-3

, K-1

)

Me

dia

n D

CL

(mA

)

Inverse Absolute Temperature vs. Median DCL. T502D685K035

Test Procedure:

• Parts subjected to temperatures ranging from 230°C to

0°C with 0.2Vr bias applied.

• Measurements were plotted on a lognormal graph

• Median leakage values from each temperature were

plotted vs inverse absolute temperature.

• The following Arrhenius equation was used to form a fit

line:

𝑀𝑒𝑑𝑖𝑎𝑛 𝐷𝐶𝐿 = 𝐷𝐶𝐿𝑀𝑎𝑥 𝑇𝑒𝑚𝑝 × 𝑒𝐸𝑎ℎ

×1

𝑀𝑎𝑥 𝑇𝑒𝑚𝑝−

1𝑇𝑒𝑚𝑝

Where:

𝐸𝑎= Activation Energy (eV)

ℎ=Boltzmann’s constant (8.62x10-5 eV K-1)

Temperatures in Kelvin

21

Page 22: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

230°C Life Test Summary

• Qualification test – 500 hours at 0.2Vr

– Leakage generally increases 4x

– No leakage failures observed

– Initial shift in ESR observed, but stabilizes through 500 hours

• Additional testing to 1,000 hours

– Leakage shifts 2x from 500hr readings, but none above post test limit

– ESR continues to shift

22

Page 23: Solid Electrolytic Capacitor Design for High Temp Applications

© 2015 KEMET Electronics

Thank You!

Kristin Tempel

New Product Development Engineer

Tantalum Innovation Center

http://go.kemet.com/wp1015