soc clock synchronizers project elihai maicas harel mechlovitz characterization presentation

SoC Clock SoC Clock Synchronizers Synchronizers

Project Project

Elihai MaicasElihai MaicasHarel Harel MechlovitzMechlovitz

Characterization Presentation

Presentation Agenda:Presentation Agenda: The synchronization problemThe synchronization problem Project motivationProject motivation Synchronization classificationsSynchronization classifications Various solutionsVarious solutions Our goalsOur goals TimelineTimeline

The synchnization The synchnization problemproblem

Large chips have multiple clock domains Large chips have multiple clock domains because:because: Chip interfaces with several unrelated blocksChip interfaces with several unrelated blocks Chip has inner IPs that require different Chip has inner IPs that require different

frequency frequency Chip size is growing, what makes it hard to Chip size is growing, what makes it hard to

design one LARGE single clockdesign one LARGE single clock And more…And more…


Example: A communication HubExample: A communication Hub


When spreading out the problem, it comes to When spreading out the problem, it comes to transfer data from transmitter to receiver:transfer data from transmitter to receiver:

Given that ckA and ckB are not from the same Given that ckA and ckB are not from the same clock domain, there is a probability that the clock domain, there is a probability that the receiver won’t sample the data correctlyreceiver won’t sample the data correctly MetastabilityMetastability ts/th issuests/th issues Duplicate / dropped samplesDuplicate / dropped samples


What is the probability of this unfortunate situation to occur ?

In general, the probability of synchronization failure can be calculated as follows:P(failure) = P(enter metastable state) · P(still in metastable state after tw)


Flip-flop can enter a metastable state, when its data input D changes the state during the aperture time or sampling window of the flip-flop

Probability of an input transition to occur during the sampling window is computed by dividing the apeture time ta by the clock period tcy

aE a Clk

cy

tP t ft

Project motivationProject motivation Sync problems become more and more Sync problems become more and more

frequent in the industryfrequent in the industry Common knowledge is quite insufficientCommon knowledge is quite insufficient Solutions are not well categorizedSolutions are not well categorized Too little do we know about the various Too little do we know about the various

solutions solutions Common synchronization mistakesCommon synchronization mistakes Some of the solutions were never looked Some of the solutions were never looked

at closely for proper correctness at closely for proper correctness checkingchecking

Synchronization Synchronization classificationclassification

We can classify different synchronization We can classify different synchronization problems to number of groups:problems to number of groups:

Synchronization Synchronization classificationsclassifications

MesochronousMesochronous

Phase difference stays constantPhase difference stays constant We could have a problem if clkB came too We could have a problem if clkB came too

fast after clkA (not allowing proper ts), or fast after clkA (not allowing proper ts), or too slow (not allowing th) too slow (not allowing th)


PlesiochronousPlesiochronous

Phase difference driftsPhase difference drifts ∆∆f< f< εε OtherOther

Every few cycles we might have a sync problem Every few cycles we might have a sync problem needs to be solvedneeds to be solved


PeriodicPeriodic

Events are periodic, therefore enables Events are periodic, therefore enables predictionprediction

The sychronizer can detect a conflict enough The sychronizer can detect a conflict enough time a head for the resualt to be ready on time a head for the resualt to be ready on timetime


AsynchronousAsynchronous Communication between two asynchronic blocksCommunication between two asynchronic blocks Sampling asynchronic signals (real-world input Sampling asynchronic signals (real-world input

devices) for a synchronized blockdevices) for a synchronized block Synchronization is required when the Synchronization is required when the

outputs or output events depend on the outputs or output events depend on the order in which input events are receivedorder in which input events are received

Asynchronous design is sometimes selected Asynchronous design is sometimes selected for eliminating the need for synchronizationfor eliminating the need for synchronization

Various solutionsVarious solutions General solutionGeneral solution

The Two-FF synchronizer AKA Brute-Force The Two-FF synchronizer AKA Brute-Force synchronizersynchronizer

The first flop samples signal AThe first flop samples signal A AW has a high probability of being in a metastable AW has a high probability of being in a metastable

statestate The second flop samples AW after a large waiting The second flop samples AW after a large waiting

time allowing the metastable state to decaytime allowing the metastable state to decay

Various solutionsVarious solutions Mesochronous solutionMesochronous solution

By delaying the clock with the actual phase By delaying the clock with the actual phase difference, one of the registers will sample difference, one of the registers will sample correctly correctly

Various solutionsVarious solutions Plesiochronous solutionPlesiochronous solution

Using FIFO synchronizer, Using FIFO synchronizer, we can keep all timingwe can keep all timing needed for right sample needed for right sample

Various solutionsVarious solutions Periodic solutionPeriodic solution

Using prediction for shorter latencyUsing prediction for shorter latency Result (unsafe signal) is ready by the time input Result (unsafe signal) is ready by the time input

arrivesarrives

Various solutionsVarious solutions Asynchronous solutionAsynchronous solution

Both clocks are aperiodicBoth clocks are aperiodic AdvantagesAdvantages

Lower probability of synchronization failureLower probability of synchronization failure Inherent flow-controlInherent flow-control

Our goalsOur goals Our main goal is to compare between various Our main goal is to compare between various

synchronization methods, with the following synchronization methods, with the following criteria:criteria: LatencyLatency AreaArea PowerPower SimplicitySimplicity Plug-n-playPlug-n-play

Categorize the various solutions and give certain Categorize the various solutions and give certain parameters for the choosing process of a parameters for the choosing process of a synchronizersynchronizer

Our goalsOur goals In addition, we will check correctness of above In addition, we will check correctness of above

circuits with the following circuit:circuits with the following circuit:

TimelineTimeline

Q & AQ & A

soc clock synchronizers project elihai maicas harel mechlovitz characterization presentation

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