soc clock synchronizers project
DESCRIPTION
SoC Clock Synchronizers Project. Progress Presentation. D0827. Students: Elihai Maicas Harel Mechlovich. Instructor: Shlomi Beer-Gingold. Presentation Agenda. Abstract Introduction Hardware Software Conclusions Appendix. Abstract. Project essence - PowerPoint PPT PresentationTRANSCRIPT
SoC Clock SoC Clock Synchronizers Synchronizers
Project Project
Students:Students:
Elihai MaicasElihai Maicas
Harel MechlovichHarel Mechlovich
Progress Presentation
InstructorInstructor::
Shlomi Beer-Shlomi Beer-GingoldGingold
D0827D0827
Presentation AgendaPresentation Agenda AbstractAbstract IntroductionIntroduction HardwareHardware SoftwareSoftware ConclusionsConclusions AppendixAppendix
AbstractAbstract
Project essenceProject essence The synchronization problem becomes The synchronization problem becomes
more and more commonmore and more common The project's main objective is to examine The project's main objective is to examine
several solutions to the synchronization several solutions to the synchronization problem of classes Plesiochronous, problem of classes Plesiochronous, Periodic and AsynchronousPeriodic and Asynchronous
General working modeGeneral working mode The verious synchronizers were designed The verious synchronizers were designed
and programmed to an FPGA deviceand programmed to an FPGA device
Abstract contAbstract cont..
A test circuit was designed to envalope A test circuit was designed to envalope the different DUTs in order to test them the different DUTs in order to test them for correctness and performancefor correctness and performance
General requirementsGeneral requirements The project’s main objective was to test The project’s main objective was to test
the different solutoins for:the different solutoins for: CorrectnessCorrectness Several parameters such as: latency, area, Several parameters such as: latency, area,
power, simplicity and plug & play power, simplicity and plug & play capabilitiescapabilities
Abstract contAbstract cont..
ResultsResults All synchronizers were tested and were All synchronizers were tested and were
proven to be working or notproven to be working or not The different parameters were The different parameters were
calculated for the verious solutionscalculated for the verious solutions We’ve made some conclusions including We’ve made some conclusions including
recomandations regarding when to use recomandations regarding when to use each of the synchronizers each of the synchronizers
IntroductionIntroduction The project covered 5 selected synchronizersThe project covered 5 selected synchronizers The synchronizers match 3 different The synchronizers match 3 different
synchronization classes:synchronization classes: PlesiochronousPlesiochronous
FIFO Synchronizer with Multisynchronous Support Two-Register Synchronizer with Conflict Detector
PeriodicPeriodic Two-Register Synchronizer with Conflict Detector and
Predictor AsynchronousAsynchronous
Two-Flop (AKA Brute-Force) SynchronizerTwo-Flop (AKA Brute-Force) Synchronizer General Purpose Asynchronous FIFO Synchronizer
Introduction contIntroduction cont..
FIFO Synchronizer with Multisynchronous Support
Q
Q
Q
QSET
CLR
SET
CLR
D
D
Q
Q
Q
QSET
CLR
SET
CLR
D
D
Q
Q
Q
QSET
CLR
SET
CLR
D
D
U/D
Reset
B1
B4
Carry out
ENB
Counter
sync
ring
coun
ter
xclk
rclk
xp0
xp2
xp1
x
xs
xp
U/D
Reset
B1
B4
Carry out
ENB
Counter
ring
coun
ter
3
3rp
x0
x1
x2
resy
nc
Plesio
chro
n
Plesio
chro
n
ousous
Introduction contIntroduction cont..
LatencyLatency .. Does not include null injectionsDoes not include null injections
ProsPros No chance of synchronization failureNo chance of synchronization failure
ConsCons Quite a long latencyQuite a long latency Requires design consideration – not a plug & play Requires design consideration – not a plug & play
devicedevice
Plesio
chro
n
Plesio
chro
n
ousous
5
2z dCQ dMUX cyt t t t
Introduction contIntroduction cont..
Two-Register Synchronizer with Conflict Detector
Q
Q
Q
QSET
CLR
SET
CLR
D
D
Q
Q
Q
QSET
CLR
SET
CLR
D
D
Q
Q
Q
QSET
CLR
SET
CLR
D
D
Q
Q
Q
QSET
CLR
SET
CLR
D
D
xclk
rclk
x
rclk unsafe
δ
δ
kot
0
1
xs
sample
Plesio
chro
n
Plesio
chro
n
ousous
Introduction contIntroduction cont..
LatencyLatency ..
ProsPros Delay components required only for clocksDelay components required only for clocks Plug & PlayPlug & Play
ConsCons Small, but not zero, chance of sync failureSmall, but not zero, chance of sync failure AreaArea
2
2cyko
xcy rcy dCQ dMUXcy
ttt t t t
t
Plesio
chro
n
Plesio
chro
n
ousous
Introduction contIntroduction cont..
Two-Register Synchronizer with Conflict Detector and Clock Predictor
Q
Q
Q
QSET
CLR
SET
CLR
D
D
Q
Q
Q
QSET
CLR
SET
CLR
D
D
Q
Q
Q
QSET
CLR
SET
CLR
D
D
Q
Q
Q
QSET
CLR
SET
CLR
D
D
xclk
rclk
Clock Predictor
x
rclk unsafe
δ
δ
kot
0
1
xs
pxclk
sample Perio
dic
Perio
dic
Introduction contIntroduction cont..
LatencyLatency ..
ProsPros Delay components required only for clocksDelay components required only for clocks Plug & PlayPlug & Play
ConsCons Small, but not zero, chance of sync failureSmall, but not zero, chance of sync failure AreaArea
2
2cyko
xcy rcy dCQ dMUXcy
ttt t t t
t
Perio
dic
Perio
dic
Introduction contIntroduction cont..
Two-Flop (AKA Brute-Force) SynchronizerTwo-Flop (AKA Brute-Force) Synchronizer
Asynch
rono
Asynch
rono
usus
Q
Q
Q
QSET
CLR
SET
CLR
D
D
FF1
FF1rclk
Q
Q
Q
QSET
CLR
SET
CLR
D
D
FF2
FF2
A AS AW
Introduction contIntroduction cont..
LatencyLatency ..
ProsPros Easy to implementEasy to implement
ConsCons Latency! Latency!
Asynch
rono
Asynch
rono
usus
( 1) xcyN t
Introduction contIntroduction cont..
General Purpose Asynchronous FIFO Synchronizer
Asynch
rono
Asynch
rono
usus
13 Bit
Read Pointer
Read Pointer
EN
EN
ADDRWREN
EN
ADDRWREN
EN
ADDRWREN
EN
ADDRWREN
EN
A
A
B
B
Dual Port Ram
Dual Port Ram
DI
DI
DO
DO
13 Bit
Write Pointer
Write Pointer
EN
EN
Compare
Brute-Force Sync
Brute-Force Sync
Brute-Force Sync
Brute-Force Sync
Compare
xclk
shiftOutrclk
shiftIn
empty
full
x
sx
Introduction contIntroduction cont..
LatencyLatency No actual synchronization delay No actual synchronization delay
ProsPros No delayNo delay No failuresNo failures
ConsCons Extremely expansive in areaExtremely expansive in area Not a plug & play deviceNot a plug & play device
Introduction contIntroduction cont..
The boardThe board Was programmed with the different Was programmed with the different
synchronizers and a general test circuit synchronizers and a general test circuit that operates the DUTs and examines that operates the DUTs and examines them in terms of correctness and them in terms of correctness and latencylatency
Interface is done using a DLP device Interface is done using a DLP device used for writing to internal config used for writing to internal config registersregisters
Introduction contIntroduction cont..
OperationOperation BoardBoard DLPDLP PCPC GUIGUI ResultsResults
+
+ +
HardwareHardware
Block levelBlock level addr_pntraddr_pntr Ctrl (Registers)Ctrl (Registers) latency_chklatency_chk SyncSync DRAM_SRC DRAM_SRC
& & DRAM_DSTDRAM_DST
comperatorcomperator mis_cntrmis_cntr
SyncADDRWREN
EN
ADDRWREN
EN
A
B
DRAM_SRC
DO
DO
1024x18 ADDRWREN
EN
ADDRWREN
EN
A
B
DRAM_SRC
DO
DO
1024x18
mis_cntr
addr_pntr
latency_chk
en
xclk
Ctrl
en
DI
comparator
xclk
xclk xclk
rclk
Registers DLP Interface
Registers
Hardware contHardware cont..
DLP voltage connectivityDLP voltage connectivity All control and data bits were shorted All control and data bits were shorted
to relevant signals in the design to relevant signals in the design through the J5 wide connector on the through the J5 wide connector on the XUP boardXUP board
Hardware contHardware cont..
DLP FSMDLP FSM The satate machineThe satate machine
communicates with thecommunicates with thedesign according to thedesign according to theDLP protocolDLP protocol
DLP FSM
addr_reg[6:0] addr[6:0]wr_en
Rgisters (rw, ro, nns)
rd/wr
addr_decoder
data[7:0]
data_mux
RXF#
RD#
data_in[7:0]
TXE#
WR
data_out[7:0]
data_out_en
rnw
IDLE
GET_ADDR
rxf_b_sync = 0
cmd
dlp_timeout = 1 &&rnw = 0 &&
rxf_b_sync = 0
txe_b_sync = 0 &&dlp_timeout = 1 &&
rnw = 1
dlp_timeout = 1
rd_b <= ‘1’wr <= ‘0’data_out_en <= ‘1’wr_en <= ‘0’
rd_b <= ‘0’wr_en <= ‘1’
dlp_timeout = 1
rd_b <= ‘1’wr_en <= ‘0’
rd_b <= ‘0’
GET_DATA
SND_DATA
wr <= ‘1’data_out_en <= ‘0’
CMD
wr <= ‘0’WAIT1
dlp_timeout = 1
dlp_timeout = 1
SND_DATA_FIN
wr <= ‘0’
SoftwareSoftware
Used applicationsUsed applications RTL Simulations:RTL Simulations: ModelSimModelSim Synthesis:Synthesis: Symplify ProSymplify Pro P&R:P&R: Xilinx ISEXilinx ISE
RTL codingRTL coding VHDLVHDL
Summary & ConclusionsSummary & Conclusions
ResultsResults Out of 5 synchronizers tested all 5 were Out of 5 synchronizers tested all 5 were
found to be workingfound to be working Latency, power and area were Latency, power and area were
measured for working synchronizersmeasured for working synchronizers Sampled latency was stored in 18 bins with Sampled latency was stored in 18 bins with
a range of 5ns eacha range of 5ns each Power was determined by current Power was determined by current
measurement on boardmeasurement on board Area was pulled out of synthesis resultsArea was pulled out of synthesis results
Summary & Conclusions Summary & Conclusions contcont..
Plesio FIFO SynchronizerPlesio FIFO Synchronizer Expected Av. latency of ~62.5nsExpected Av. latency of ~62.5ns AreaArea
LUT2: 2LUT2: 2 LUT3: 3LUT3: 3 LUT4: 6LUT4: 6 FDC:FDC: 58 58
0
50
100
150
200
250
300
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Series1
Summary & Conclusions Summary & Conclusions contcont..
Plesio Synchronizer with conflict Plesio Synchronizer with conflict detectordetector Expected Av. latency of ~12.5nsExpected Av. latency of ~12.5ns AreaArea
LUT2: 3LUT2: 3 LUT3: 34LUT3: 34 LUT4: 4LUT4: 4 FDC:FDC: 39 39 MUXF: 15MUXF: 15
0
50
100
150
200
250
300
10 15 20 25 30 35
Series1
Summary & Conclusions Summary & Conclusions contcont..
Periodic Synchronizer with conflict Periodic Synchronizer with conflict detectordetector Expected Av. latency of ~15nsExpected Av. latency of ~15ns AreaArea
LUT2: 3LUT2: 3 LUT3: 31LUT3: 31 LUT4: 4LUT4: 4 FDC:FDC: 67 67 MUXF: 16MUXF: 16
0
50
100
150
200
250
300
10 15 20 25 30 35 40 45 50
Series1
Summary & Conclusions Summary & Conclusions contcont..
Async SynchronizerAsync Synchronizer No latencyNo latency AreaArea
LUT:LUT: 4040 FF:FF: 4040 Block RAM:Block RAM: 1 1
Summary & Conclusions Summary & Conclusions contcont..
Brute-force SynchronizerBrute-force Synchronizer Latency of 60nsLatency of 60ns AreaArea
LUT2: 2LUT2: 2
Our LegacyOur Legacy
DLP moduleDLP module Configure design registersConfigure design registers
Standart MAS formatStandart MAS format Macro tull barMacro tull bar
RTL modulesRTL modules Plug & PlayPlug & Play GeneralGeneral
Q & AQ & A