snug99 vhd bfm slide
DESCRIPTION
understanding VHDlTRANSCRIPT
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 1
Designing Procedural-Based BehavioralBus Functional Models for High
Performance Verification
Gregg D. [email protected]
Tim L. [email protected]
Intel Corporation
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 2
Purpose
• Enable faster testing, moresimulation cycles
• Find bugs faster, higher silicontapeout confidence
• Self-checking, automated for betterproductivity
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 3
Outline
• Test bench basics• Modeling devices as Bus Functional
Models (BFMs)• BFM high-level testing methodology• High-level testing gotchas• Synopsys PCI Source Model mods• Conclusion
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 4
The Problem
• Verification is 50% of Design Effort• Need fast-as-possible cycles/second
simulation speed• Need high level of test complexity,
control• Simulate designs without IP core or
gate-level models
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 5
Test Bench Basics
Test bench block diagram
StimulusGenerator
ResponseChecking
• Device Under Test is your design
DeviceUnderTest
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 6
Test Bench Basics
• Stimulus application methods– File-based vectors
– Basic assertion statements (VHDL)
– Use of Bus Functional Language in files to beapplied through a model
• Synopsys PCI Source models
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 7
Test Bench Basics
• Response checking– Human-based, look at simulation
– Automated (preferred)• Trace file comparison
• Run once, verify, run again and compareagainst “golden” trace files
• Self-checking• Test bench checks response during
simulation
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 8
Test Bench Basics
• Trace file comparison problems– Must first guarantee golden trace file manually
– Requires large vector files hanging around,possible revision control problems
– Slow, doesn’t compensate for cycle slips
– Won’t work with behavioral abstractions
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 9
Test Bench Basics
• Self-checking– Requires more model creation time
– No manual comparisons of golden trace tocurrent simulation required
– Can test timing and protocol
– Can allow for cycle slips
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 10
Modeling Devices as BFMs
• BFM acts as stimulus generationdevice– Cycle and protocol accurate
– Does timing and protocol checks
– Accepts stimulus commands in some high-levelformat
• Bus Functional Language in files• Procedural-based driven
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 11
Modeling Devices as BFMs
• Driving BFMs– Bus Functional Language Code most prevalent
– Synopsys Source Models use it
print_msg("PM: memory read to PT to verify
initialization ");
read_cycle(mem_read, "00000000",
1,"0","86551643", 0, false);
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 12
Modeling Devices as BFMs
• Why BFL from files is undesirable– File I/O slow compared to compiled and
memory resident VHDL
– Files must be parsed/processed• Intelligent parser for loops, conditions, etc• No ability to read-modify-writes• May require external compiler• Synchronization of models difficult• Sampling/driving test bench signals difficult
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 13
Modeling Devices as BFMs
• BFL code can’t do this example:
-- write 32-bit words to every 8-byte address of memory chunk
tv := to_stdlogicvector(X"a5a5e3e3");
for i in 16#00000100# to 16#00000140# loop
if (i mod 8 = 0) then -- every other dword
-- write value to DUT
wr(conv_std_logic_vector(i,32),tv,cmd);
tv := tv xor tv0; -- just for kicks, xor next data
end if;
end loop;
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 14
BFM High-Level Testing Methods
• Use VHDL procedure calls to driveBFM– Power of VHDL language for test code creation
– No external parsers required
– Compiled in native language, faster runtime
– Better synchronization methods
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 15
BFM High-Level Testing Methods
• Main components of VHDL-drivenBFMs– BFMs instanced within the test bench
– Package to contain globally accessible signals
– Separate test code entity & architectures forstimulus
– Configurations to bind abstractions
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 16
BFM High-Level Testing MethodsTest Bench
Test code
DUT
Stimulus andresponsechecking
BFM
• Global packages– Allow communication of test bench signals and
procedures between test code and BFMs
Global packagescontaining
types, signals,procedures, and
functions
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 17
BFM High-Level Testing Methods
• Global package example
type cycle_t is (idle, write, read);
type instruction is record
bus_cycle : cycle_t; -- cycle type
addr : std_logic_vector(31 downto 0); -- address
data : std_logic_vector(31 downto 0); -- write/read value
rdata : std_logic_vector(31 downto 0); -- actual read data
request : std_logic; -- request handshake
busy : std_logic; -- busy handshake
end record;
signal cmd : instruction := (idle, (others => '0'),
(others => '0'), (others => 'Z'), '0', 'Z');
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 18
BFM High-Level Testing Methods
• BFM procedure call example
swr("00000000","deadbeef",cmd); -- write cycle
idle(cmd); -- idle
srd("00000000","deadbeef",cmd); -- read cycle
In VHDL, the global signal “cmd” must bepassed with the procedure call to enableread/write access by the procedure
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 19
BFM High-Level Testing Methods
• BFM executes commands via mainprocedure call and handshakingsignals in “cmd” record
MainProcedure
BFM
cmd.request
cmd.busy
Specific(read/write/etc)
Procedures
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 20
BFM High-Level Testing Methods
• Operation flow– Test code issues specific (read, write, etc)
procedure.
– Specific procedure sets up data, calls mainprocedure.
– Main procedure requests cycle start BFM usingcmd.request signal if cmd.busy is not asserted.If BFM busy, procedure waits until BFM isfinished.
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SNUG’99 Gregg D. Lahti and Tim L. Wilson 21
BFM High-Level Testing Methods
• Operation flow continued– BFM does its operation, signals done through
cmd.busy signal.
– Operation flow returns back to test code(specific procedure call origination) for nextcommand.
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BFM High-Level Testing Methods
• Read-modify-write example-- first read the memory
av := to_stdlogicvector(X”00000020”);
srd(av,"babeface",cmd);
idle(cmd);
-- now get the actual data read in the tv variable
get_rdata(tv,cmd);
tv(15 downto 0) := tv(15 downto 0) - 16#0ac1#;
tv(31 downto 16) := tv(31 downto 16) + 16#1fbe#;
-- write it back
wr(av,tv,cmd);
-- read it for verification
rd(av,tv,cmd);
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BFM High-Level Testing Methods
• Configurations allow– Binding of different architectures to entities
– Binding of generic settings
Test codeTest #1Test #2Test #3
DUT
BFM
BehavioralRTLGates
Timing InformationGeneric SettingsIP core version
Test bench configuration
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High Level Testing Gotchas
• Multiple BFMs– Multiple test code processes drive multiple
BFMs
Process A
Process B
BFM #1
BFM #2
Not allowed!
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High Level Testing Gotchas
• Control multiple BFMs of a singletype with the same procedure syntax– Use array of records
– Each BFM has a generic “unique number”assigned through configuration
– Procedure calls include “unique number” todrive specific BFM
– Each BFM “pipelines” one instruction,allowing simultaneously execution
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BFM High-Level Testing Methods
• In one project test bench we had– 2 PCI Master BFMs
– 2 PCI Slave BFMs
– 1 PCI Monitor/Arbiter
– 1 486 BFM
– 2 SRAM/FLASH memory models
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High Level Testing Gotchas
• Coding BFMs for performance– Use as few processes as possible
– Limit component instantiations
– Avoid using after delays
– Use variables in processes
– Use IEEE library• IEEE packages usually built into simulators• Conversions & types quicker and proven
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Synopsys PCI Source Model Mods
• You too can have procedural-drivenPCI Source Models!– Enables procedure calls to drive PCI master
BFM instead of file-resident BFL code
– Patches done to your own source
– Patch files on websitehttp://www.primenet.com/~greggl/snug99.html
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Conclusions
• Procedure-driven BFMs enableshigher-level, more complex testing
• Enable thorough protocol and timingchecks
• Finds bugs faster, get better testedsilicon sooner
• See website for full example code