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VHDL CodingExercise 4: FIR Filter

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Where to start?

Algorithm Architecture

RTL-

Block diagramVHDL-Code

Designspace

ExplorationFeedback

Optimization

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Algorithm High-Level System Diagram

Context of the design Inputs and Outputs

Throughput/rates

Algorithmic requirements

Algorithm Description

Mathematical Description

Performance Criteria

Accuracy

Optimization constraintsImplementation constraints

Area

Speed

N

ii

ikxbky0

FIR ky kx

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Architecture (1) Isomorphic Architecture:

Straight forward implementation of the algorithm

0b

1b

2b

2Nb

1Nb

Nb

ky

kx

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Architecture (2) Pipelining/Retiming:

Improve timing

0b

1b

2b

2Nb

1Nb

Nb

ky

kx

Insert register(s) at the inputs or outputs

Increases Latency

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Architecture (2) Pipelining/Retiming:

Improve timing

0b

1b

2b

2Nb

1Nb

Nb

ky

kx

Insert register(s) at the inputs or outputs

Increases Latency

Perform Retiming: Move registers through the logic

without changing functionalityForward:

Backwards:

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Architecture (2) Pipelining/Retiming:

Improve timing

0b

1b

2b

2Nb

1Nb

Nb

ky

kx

Insert register(s) at the inputs or outputs

Increases Latency

Perform Retiming: Move registers through the logic

without changing functionalityForward:

Backwards:

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Architecture (2) Pipelining/Retiming:

Improve timing

0b

1b

2b

2Nb

1Nb

Nb

ky

kx

Insert register(s) at the inputs or outputs

Increases Latency

Perform Retiming: Move registers through the logic

without changing functionalityForward:

Backwards:

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Architecture (3) Retiming and simple transformation:

Optimization

0b

1b

2b

2Nb

1Nb

Nb

ky

kx

Reverse the adder chain

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Architecture (3) Retiming and simple transformation:

Optimization

0b

1b

2b

2Nb

1Nb

Nb

ky

kx

Reverse the adder chain

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Architecture (3) Retiming and simple transformation:

Optimization

0b

1b

2b

2Nb

1Nb

Nb

kx

Reverse the adder chain

Perform Retiming

ky

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Architecture (3) Retiming and simple transformation:

Optimization

0b

1b

2b

2Nb

1Nb

Nb

kx

Reverse the adder chain

Perform Retiming

ky

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Architecture (3) Retiming and simple transformation:

Optimization

0b

1b

2b

2Nb

1Nb

Nb

kx

Reverse the adder chain

Perform Retiming

ky

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Architecture (3) Retiming and simple transformation:

Optimization

0b

1b

2b

2Nb

1Nb

Nb

kx

Reverse the adder chain

Perform Retiming

ky

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Architecture (3) Retiming and simple transformation:

Optimization

0b

1b

2b

2Nb

1Nb

Nb

kx

Reverse the adder chain

Perform Retiming

ky

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Architecture (3) Retiming and simple transformation:

Optimization

0b

1b

2b

2Nb

1Nb

Nb

kx

Reverse the adder chain

Perform Retiming

ky

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Architecture (3) Retiming and simple transformation:

Optimization

0b

1b

2b

2Nb

1Nb

Nb

kx

Reverse the adder chain

Perform Retiming

ky

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Architecture (3) Retiming and simple transformation:

Optimization

0b

1b

2b

2Nb

1Nb

Nb

kx

Reverse the adder chain

Perform Retiming

ky

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Architecture (3) Retiming and simple transformation:

Optimization

0b

1b

2b

2Nb

1Nb

Nb

kx

Reverse the adder chain

Perform Retiming

ky

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Architecture (3) Retiming and simple transformation:

Optimization

0b

1b

2b

2Nb

1Nb

Nb

kx

Reverse the adder chain

Perform Retiming

ky

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Architecture (4) More pipelining:

Add one pipelining stage to the retimed circuit

0b

1b

2b

2Nb

1Nb

Nb

kx

The longest path is given by the multiplier

Unbalanced: The delay from input to the first pipeline stage ismuch longer than the delay from the first to the second stage

ky

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Architecture (5) More pipelining:

Add one pipelining stage to the retimed circuit

0b

1b

2b

2Nb

1Nb

Nb

kx

Move the pipeline registers into the multiplier:

Paths between pipeline stages are balanced

Improved timing

Tclock = (Tadd + Tmult)/2 + Treg

ky

hi ( )

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Architecture (6) Iterative Decomposition:

Reuse Hardware

Identify regularity and reusable hardware components

Add control

multiplexers

storage elements

Control

Increases Cycles/Sample

0b

1b

2b

2Nb

1Nb

Nb

ky

kx

kx

0b

Nb

0

ky

i

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RTL-Design Choose an architecture under the following constraints:

It meets ALL timing specifications/constraints: Throughput

Latency

It consumes the smallest possible area

It requires the least possible amount of power

Decide which additional functions are needed andhow they can be implemented efficiently:

Storage of samples x(k)=> MEMORY

Storage of coefficients bi=> LUTAddress generators for MEMORY and LUT

=> COUNTERS

Control => FSM

Iterative

Decomposition

kx

0b

Nb

0

ky

RTL D i

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RTL-Design RTL Block-diagram:

Datapath

N

ii

ikxbky0

FSM: Interface protocols

datapath control:

kx

0b

Nb

0

ky

RTL D i

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RTL-Design How it works:

IDLE

Wait for new sample

N

ii

ikxbky0

RTL D i

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RTL-Design How it works:

IDLE

Wait for new sample Store to input register

N

ii

ikxbky0

RTL D i

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RTL-Design How it works:

IDLE

Wait for new sample Store to input register

NEW DATA:

Store new sample to memory

N

ii

ikxbky0

RTL D i

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RTL-Design How it works:

IDLE

Wait for new sample Store to input register

NEW DATA:

Store new sample to memory

RUN:

N

ii

ikxbky0

N

ii

ikxbky0

RTL D i

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RTL-Design How it works:

IDLE

Wait for new sample Store to input register

NEW DATA:

Store new sample to memory

RUN:

Store result to output register

N

ii

ikxbky0

N

ii

ikxbky0

RTL D i

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RTL-Design How it works:

IDLE

Wait for new sample Store to input register

NEW DATA:

Store new sample to memory

RUN:

Store result to output register

DATA OUT:

Output result

N

ii

ikxbky0

N

ii

ikxbky0

RTL D i

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RTL-Design How it works:

IDLE

Wait for new sample Store to input register

NEW DATA:

Store new sample to memory

RUN:

Store result to output register

DATA OUT:

Output result / Wait for ACK

N

ii

ikxbky0

N

ii

ikxbky0

RTL D i

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RTL-Design How it works:

IDLE

Wait for new sample Store to input register

NEW DATA:

Store new sample to memory

RUN:

Store result to output register

DATA OUT:

Output result / Wait for ACK

IDLE:

N

ii

ikxbky0

N

ii

ikxbky0

T l ti i t VHDL

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Translation into VHDL Some basic VHDL building blocks:

Signal Assignments: Outside a process:

Within a process (sequential execution):

AxD YxD

AxDYxD

BxD

Sequential execution

The last assignment is

kept when the process

terminates

AxD YxD

BxD

This is NOT allowed !!!

T anslation into VHDL

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Translation into VHDL Some basic VHDL building blocks:

Multiplexer:

Conditional Statements:

AxD

BxD YxD

SELxS

CxD Default

Assignment

AxD

BxD

SelAxS

CxD

DxD

OUTxD

SelBxS

STATExDP

Translation into VHDL

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Translation into VHDL Common mistakes with conditional statements:

Example:

AxD

??

SelAxS

BxD

??

OUTxD

SelBxS

STATExDP

NO default assignment

NO else statement

ASSIGNING NOTHING TO A SIGNAL IS NOT AWAY TO KEEP ITS VALUE !!!!! => Use FlipFlops !!!

Translation into VHDL

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Translation into VHDL Some basic VHDL building blocks:

Register:

Register with ENABLE:

DataREGxDN DataREGxDP

DataREGxDN DataREGxDP

DataREGxDNDataREGxDP

Translation into VHDL

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Translation into VHDL Common mistakes with sequential processes:

DataREGxDN DataREGxDP

CLKxCI

DataRegENxS

DataREGxDN DataREGxDP

CLKxCI

DataRegENxS

DataREGxDN DataREGxDP

0

1

Can not be translated

into hardware and is

NOT allowed

Clocks are NEVER

generated within

any logic

Gated clocks are more

complicated then this

Avoid them !!!

Translation into VHDL

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Translation into VHDL Some basic rules:Sequential processes (FlipFlops)

Only CLOCK and RESET in the sensitivity list

Logic signals are NEVER used as clock signals

Combinatorial processes Multiple assignments to the same signal are ONLY possible within

the same process => ONLY the last assignment is valid

Something must be assigned to each signal in any case ORThere MUST be an ELSE for every IF statement

More rules that help to avoid problems and surprises:Use separate signals for the PRESENT state and the

NEXT state of every FlipFlop in your design.

Use variables ONLY to store intermediate results or evenavoid them whenever possible in an RTL design.

Translation into VHDL

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Translation into VHDL Write the ENTITY definition of your design to specify:

Inputs, Outputs and Generics

Translation into VHDL

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Translation into VHDL Describe the functional units in your block diagram

one after another in the architecture section:

Translation into VHDL

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Translation into VHDL Describe the functional units in your block diagram

one after another in the architecture section:

Translation into VHDL

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Translation into VHDL Describe the functional units in your block diagram

one after another in the architecture section:

Register with ENABLE

Register with ENABLE

Translation into VHDL

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Translation into VHDL Describe the functional units in your block diagram

one after another in the architecture section:

Register with CLEAR

Translation into VHDL

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Translation into VHDL Describe the functional units in your block diagram

one after another in the architecture section:

Counter

Counter

Translation into VHDL

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Translation into VHDL Describe the functional units in your block diagram

one after another in the architecture section:

Translation into VHDL

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Translation into VHDL The FSM is described with onesequential process

and onecombinatorial process

Translation into VHDL

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Translation into VHDL The FSM is described with onesequential process

and onecombinatorial process

Translation into VHDL

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Translation into VHDL The FSM is described with onesequential process

and onecombinatorial process

Translation into VHDL

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Translation into VHDL The FSM is described with onesequential process

and onecombinatorial process

MEALY

Translation into VHDL

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Translation into VHDL The FSM is described with onesequential process

and onecombinatorial process

Translation into VHDL

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Translation into VHDL The FSM is described with onesequential process

and onecombinatorial process

MEALY

Translation into VHDL

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Translation into VHDL The FSM is described with onesequential process

and onecombinatorial process

MEALY

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Other Good Ideas

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Other Good Ideas Keep things simple

Partition the design (Divide et Impera):Example:

Start processing the next sample, while the previousresult is waiting in the output register:

Just add a FIFO to at the output of you filter

Do NOT try to optimize each Gate or FlipFlop Do not try to save cycles if not necessary

VHDL code

Is usually long and that is good !!

Is just a representation of your block diagramDoes not mind hierarchy