smart reliable network on chip

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10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE VI

VIRTEX VI SYNTHESIS COMPARISONS BETWEEN THE RKT-NOC

AND A NONRELIABLE NOC

Slices Slices fRegisters LUTs (MHz)

RKT-NoC 8360 11672 419.211 1 Nonreliable NoC 6850 7904 386.68

Overhead 22.04% 47.67% -


Overhead 22.02% 55.28% -


Overhead 28.18% 63% -

of the network load for the faulty routers. The load ofrouter(3, 2) decreases from 4.39% to 3.53%. The maximumincrease of network load is obtained for router(2, 2), increasingfrom 4.78% to 7.09%. Fig. 9(c) shows the network load for anetwork containing one entirely faulty router. More precisely,the four input ports of router(3, 2) are disconnected from thenetwork. The network load clearly increases, especially aroundthe faulty switches. The largest network load increase is forrouter(2, 2), from 4.33% to 6.1%, which represents an increaseof 40%.

These simulation results clearly show the interest of ourerror detection approach. By disconnecting accurately only thefaulty parts of the NoC, we maintain the network load at alevel similar to that of a network without fault. We clearlyshow that by disconnecting one entire router, when using onlythe switch-to-switch error detection mechanism, or using thecode-disjoint mechanism in the case of an error inside therouter, the network load is much altered, which can lead tothe generation of network congestion.

B. Fault Injection Method

The following simulations have been realized in the Model-Sim environment through a C-VHDL co-simulation [26]. Weassume nonfaulty detection blocks. The RTL design of theNoC is modified to generate the errors. More precisely, theinput buffers, output buffers, data bus, and routing logic of allthe routers have a special input to activate errors. Furthermore,the position of the errors in the data is specified by usinga mask input. Similarly, the routing blocks have an input toforce a routing decision. For instance, we can force a routingblock to always route to the North direction. These inputsare activated by a specific IP modeled in C language, whichgenerates randomly the error positions. Each NoC router hasthe same probability to get an error, and the positions of thefaulty bits are random.

C. Network Robustness Against Transient Data Packet Errors

We have performed an analysis of the NoC against severalSEU (bit flips) frequencies. To evaluate the robustness of thenetwork, we simulated a 6 6 RKT-NoC connected to 24IPs. Each IP injects 100 000 data packets at the maximum PIRby using a random traffic pattern. Each packet contains four

Fig. 10. Throughput of a 6 6 RKT-NoC for several SEU (bit flips)frequencies.

flits of 64 b. The SEU locations in the network are random.The throughput and the data packets latency of the networkare shown in Figs. 10 and 11, respectively. The throughput isalmost constant at 116.5 Gbit/s until an SEU rate of 0.1 (onebit flip every 10 clock cycles). After this value, the throughputdecreases as the SEU rate increases. The latency of the datapackets is shown in Fig. 11, which increases linearly untilan SEU rate of 0.1. After this value, the latency increasesmore rapidly. These results can be correlated with Fig. 12,which shows the number of data packets lost for severalSEU injection rates. We can clearly see that the number ofpackets lost increases from the SEU rate of 0.1. Thus, thedegradation of the NoC performance is linked to the numberof packets lost. Indeed, with uncorrectable errors, the numberof retransmissions due to the Ack/Nack data flow controlincreases the data packet latency and decreases throughput.It can be seen that for an SEU rate of 0.2, only 81 datapackets have been lost during the transmission of 2 400 000data packets.

D. Evaluation of the Data Packets Error Localization Capacity

We propose an analysis of the capacity to locate the errorsources regarding permanent data packet errors. This localiza-tion capacity is given for a 6 6 RKT-NoC using randomtraffic. For this analysis, 3000 simulation cases have beenperformed. In each simulation, the position of the permanenterrors is random and the errors simulated are 2 b stuck at 1.The results are given in Table VIII. In this table, we canclearly see all the permanent errors are accurately localized.Regarding the case of permanent errors located on the databus, the faulty data bus is always localized. Moreover, whenlocalizing the data error sources on the data bus, no datapackets are lost by using the loopback module.

Regarding the cases where error sources are in the inputor output buffer; in 100% of these cases, the faulty port isaccurately disconnected. The impact of the threshold (numberof uncorrectable errors detected before activating the flags ofpermanent errors) of the journals in the local historic is shownin these results. The higher the threshold, the higher is thecriterion of discrimination allowing the detection of whether an


KILLIAN et al.: SMART RELIABLE NETWORK-ON-CHIP 11

TABLE VII

PERFORMANCE COMPARISONS BETWEEN A 6 6 RKT-NOC AND A 6 6 NONRELIABLE NOC FOR VIRTEX VI TECHNOLOGY

Throughput Average Latency Power Consumption

(Gbit/s) (Clock Cycles) (W)

Transposed Random Transposed Random Transposed Random

Traffic Traffic Traffic Traffic Traffic Traffic

RKT-NoC 205.95 117.49 74 173.833 5.69 5.57

Nonreliable NoC 268.19 154, 24 47 120.46 4.03 3.97

Difference 30.22% 31.27% 57.44% 44.30% 41.19% 40.30%

(a) (b) (c)

Fig. 9. Traffic distribution in a 4 4 RKT-NoC connected to 12 traffic generators with a random traffic pattern. (a) No faulty router in the NoC. (b) Westinput port of router(3, 2) is unavailable. (c) Four ports of router(3, 2) are unavailable.

error is in the input or in the output buffer of a router. Indeed,by increasing the threshold, the probability of testing morepaths inside a router increases. We can see that, with a lowthreshold of 2, in 82% of cases where error sources are in aninput buffer, both one input and one output are disconnected.If the threshold is 4, for the same case, only in 46.62% ofcases are both one input and one output disconnected. Wecan see that the more the threshold increases, the better isthe localization. However, we can also see that between athreshold of 2 and 3, the gain is important. On the contrary,between a threshold of 3 and 4 the gain is less important.Moreover, with a higher threshold more lost data packets arerequired by the router before taking a decision. The choice ofthe threshold is a very important point: when it is too low,the network can waste resources by disconnecting nonfaultyblocks; when it is too high, time is wasted before faulty partsof routers are localized. Regarding the impact of the thresholdon the logical resources, Table VIII gives the FPGA slicesregisters and LUTs required for these blocks. It can be noticedthat the area of the local historic increases with the threshold.However, this block requires a small area. For instance, only32 registers and 56 LUTs are required for a threshold of 3. Wecan conclude from this analysis of the impact of the thresholdthat a threshold of 3 demonstrates a good compromise betweenthe capacity to locate the sources of errors and the number ofdata packets required to activate the unavailable indicators.We can see that the number of cases for an error located in aninput, where both one input and one output are disconnected,is higher than for an error located in an output. Indeed, byusing adaptive XY algorithms, when a North or South inputreceives a data packet, this means the packet is in the columnof the destination and will always be sent towards the y-axis.Hence, when error sources are located in the input North or

Fig. 11. Average latency of data packets in a 6 6 RKT-NoC for severalSEU (bit flips) frequencies.

South, the mechanism will disconnect both one input and oneoutput. This is true only for the XY algorithm without bypass,and for the routers not connected to an IP.

Regarding the capacity to locate the errors of the proposedRKT-NoC compared with the switch-to-switch and the code-disjoint mechanisms, Table IX gives a comparison of thesethree data packets error source localization mechanisms. Themain advantage of the proposed mechanism is that, evenif the error sources are inside a switch, only the faultyport is disconnected, and in the worst cases just one inputand one output port are disconnected. Indeed, for the code-disjoint and the switch-to-switch mechanisms, when an errorsource is located inside a router, all the ports of the routerare disconnected. Moreover, compared with the code-disjointmechanism, when an error source is on a data bus, the RKT-



Fig. 12. Number of data packet lost in a 6 6 RKT-NoC for several SEU(bit flips) frequencies.

NoC can locate precisely the faulty bus and the loopbackmechanism ensures that the data packet is not lost.

E. Evaluation of the Routing Error Detection Rate

To evaluate the capacity to detect and locate routing errors,we have performed several simulation cases. We simulated a6 6 RKT-NoC surrounded by 24 communication modules.We used a random traffic pattern. The routing algorithm usedfor this simulation is the S-XY [20]. This adaptive algorithmis a straightforward solution for a dynamic mesh NoC. Thepackets are first routed in the x-axis, and, when reaching thedestination column, in the y-axis. If an obstacle is reachedin the XY path, a bypass decision is performed locally in thedirection of the destination or in a default direction if thedestination is in the same column or line.

We simulated an NoC with one, two, and three permanenterrors and each case was simulated 1000 times. The routingfaults simulated are permanent and simulate the routing logicblocks sending data packets always in the same direction. Forexample, a fault in a North routing logic block can alwayssend packets to the East direction. The faults are randomlyinjected at the beginning of each simulation and can be in anyrouting logic block of the 36 RKT-switches.

For each simulation, each communication module sends amaximum of 2000 data packets. If all the errors are detected,each communication module sends 2000 data packets again,in order to define whether the routing error detection blockswill not detect bypass as a routing fault. An error is locatedwhen the unavailable flag of the input port of the faulty routinglogic block is activated.

Table X gives the routing error detection rates for eachsimulation case. It can be seen that for one permanent error,the proposed solution can locate precisely the error in 83.3%of cases. Among the undetected errors, 13 percentage pointsare errors that did not modify the routing decisions. Theseundetected errors occur when a North or South faulty routingblock receives a data packet and sends it to the oppositedirection (to North for a South routing logic, and to the Southfor a North routing logic). Indeed, in the S-XY, the routersfirst route along the x-axis. Thus, when a router receives

TABLE X

ROUTING ERROR DETECTION RATES FOR A 6 6 RKT-NOC FOR ONE,TWO, AND THREE PERMANENT ERRORS

Number of Permanent Routing Routing ErrorError in the Network Detection Rate

1 error 83.5%2 errors 82.5%3 errors 81.1%

a data packet in its North routing block, this means thatthe packet has reached the destination column. In this case,to send the data packet along the y-axis matches with therouting algorithm and therefore is not detected as a fault.By considering these no detections as normal operation, therouting error detection rate is 96%.

The routing error detection rates are 82.5% and 81.1%for two and three permanent errors, respectively. The errordetection rates decrease as the number of faults increases.Indeed, the accumulation of errors can prevent the detectionof specific error cases. More precisely, if two errors are on thesame NoC row and on the same side of the two neighboringrouters, the detection of one will prevent the detection of thesecond. For instance, as illustrated in Fig. 13, a permanenterror has been detected in the West port of router(2, 2). Thebypass of this faulty port is made towards the North or Southdirection of router(1, 2). The West routing logic of router(3, 2)will not be used again due to the rules of the S-XY routingalgorithm. Then, if there are errors in the West port of thissecond router, they will not be detected. This lack of detectionis not problematic because this faulty routing logic is notused. We can conclude that the decrease of the routing errordetection rate is not problematic because the undetected faultsare in parts of the NoC that are not used (in the case of theS-XY routing algorithm), and the detection of real errors isclose to 96%.

VII. LIMITATIONS AND EXTENSIBILITY

We assumed nonfaulty correction/detection blocks and DAIthrough the presented simulations and estimations. If thishypothesis is false, the faults can generate two error cases.The first disables the detection capacity of the block, whichcannot detect any errors. The second is the generation of falsedetection. More precisely, a detection block generating falsedetection finds an error even when there is none. For bothcases, if the errors are transitory, their effects will not affectthe NoC. Indeed, the routers check journals where an errorneeds to occur consecutively three times before a faulty part isdisabled. Regarding the permanent faults generating the errordetection incapacity, the data packets error detection relies onthe subsidiarity of the NoC elements. More precisely, if anECC does not detect an error in a data packet, this faultypacket is sent to a neighbor. This neighbor will detect theerror and generate a Nack.

After three Nacks, the data packet is looped back to therouter that did not detect the error. After the loopback, theECC and the local historic will locate the port in whichthe error was not detected and the router will isolate theinput port including this faulty block. The permanent faultsgenerating error detection incapacity (fault in the detection


KILLIAN et al.: SMART RELIABLE NETWORK-ON-CHIP 13

TABLE VIII

CAPACITY TO LOCATE THE ERROR SOURCES FOR DIFFERENT THRESHOLD SIZE OF THE LOCAL HISTORIC

AND THE VIRTEX VI SYNTHESIS RESULTS OF THIS BLOCK

Permanent Error Localization Rate (and Percentage of FPGA SynthesisCase Having Both One Input and One Output Disconnected) Results

Threshold Between Error source Error Source Error Source Slices SlicesPermanent and Transient Errors in Input Buffer in Output Buffer on Data Bus Registers LUTs

2 100% (82%) 100% (53.5%) 100% (0%) 24 363 100% (57%) 100% (43.21%) 100% (0%) 32 564 100% (49.7%) 100% (30.65%) 100% (0%) 40 685 100% (46.62%) 100% (21.02%) 100% (0%) 48 74

TABLE IX

COMPARISON BETWEEN THE RKT-NOC, SWITCH-TO-SWITCH, AND CODE-DISJOINT MECHANISMS

OF PERMANENT DATA ERROR SOURCE LOCALIZATION

Error Source in Error Source in Error Source oninput Buffer Output Buffer Data Bus

Switch-to-Switch All the Ports All the ports All the portsare disconnected are disconnected are disconnected

Code-disjoint All the ports All the ports The faulty bus is disconnectedare disconnected are disconnected and the packet is lost

RKT-NoC Only the faulty input is disconnected Only the faulty output is disconnected The faulty bus is disconnected and the(57% of cases one input and one output) (43% of cases one input and one output) packet is not lost by using the loopback

Fig. 13. Case of undetectable errors due to a bypass for the S-XY routingalgorithm.

block or the DAI) in routing error detection cannot be detectedin the NoC. However, standard solutions of fault tolerancecan be applied to the routing error detection blocks and theDAI, like the duplication of the blocks/links [27]. Regardingthe permanent false detections, because the presented mech-anism can localize accurately the error sources, these errorcases will only disconnect small parts of healthy routers,which does not critically affect the NoC, as shown in thesimulations in Section VI-A. The presented error detectionmechanisms have been detailed for a router based on the store-and-forward switching technique. However, our mechanismsare also suitable for virtual cut-through and wormhole rout-ing. Indeed, the routing error detection as presented in theRKT-NoC can be used with these switching policies withoutany modification. Regarding the data packet errors based on

the use of the loopback module, routers using wormhole rout-ing need some modification. More precisely, with wormholetechniques, a data packet can be spread over several routers.Each output block receiving a header flit needs to store locallyits routing information. When a flit fails to be transmitted toa neighbor (i.e., the router receives three Nacks), the packetneeds to be looped back. A header flit is generated locallywith the information saved in the output buffer, and the flitsthat were not transmitted to the neighbor are looped back andanalyzed by the ECC located in the input port, as detailed inSection IV-B. The flit already transmitted to the neighborcontinues to be routed towards the destination. Thus, this des-tination will receive the data packet in two parts, each havingthe same header flit, which will permit the reconstitution ofthe data packet.

VIII. CONCLUSION

In this paper, we proposed new error detection mechanismsfor dynamic NoCs. The proposed routing error detection mech-anisms allow the accurate localization of permanent faultyrouting blocks in the network. They are suitable for adaptiverouting algorithms based on XY where the main difficultyis to distinguish the bypasses of an unavailable componentin the NoC (due to the use of the adaptive algorithm) fromreal routing errors (due to faulty components in the NoC).Validation simulations of our proposed routing error detectionshowed a routing error localization close to 96% for routingerrors on an adaptive algorithm based on XY in a 6 6NoC. Regarding the proposed data packet error localizationmechanisms, the simulations presented in this paper clearlyshow the efficiency of our techniques, which can localize per-manent sources of errors more accurately than the switch-to-switch or code-disjoint mechanisms. Moreover, both presentedtechniques can distinguish permanent and transient errors,and show attractive performance as presented in the FPGA



synthesis comparisons with a nonreliable NoC. Our ongoingwork focuses on evaluating accurately the impact of faultydetection blocks and improving the routing error detectionmechanisms, by protecting the DAI links and routing detectionblocks against errors.

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Cdric Killian received the M.S. degree in elec-tronic systems from the University of Metz, Metz,France, in 2009, the Ph.D. degree in electronicsystems from the University of Lorraine, Metz, in2012.

He is currently a Researcher with LICM. His cur-rent research interests include field-programmablegate array architecture design, adaptive network-on-chip, reliability, and VLSI design.

Camel Tanougast received the Ph.D. degree inmicroelectronic and electronic instrumentation fromthe Henri Poincar University of Nancy, Nancy,France, in 2001, and the Habilitation degree fromthe University of Metz, Metz, France, in 2009.

He is currently an Associate Professor in electron-ics with the University of Lorraine, Metz. He joinedthe Microelectronic and Sensor Interface Laboratoryof Metz (LICM) in 2008. He is the Head Researchof the networked adaptive and self-organized sys-tems. He has authored and co-authored more than

70 publications. His current research interests include reconfigurable sys-tems and NoCs, design and implementation real time processing architec-tures, System-on-Chip development, FPGA design, computing vision, imageprocessing, cryptography and the Digital Television Broadcast.

Fabrice Monteiro (M96) received the Ph.D. degreein microelectronics from the University of Montpel-lier, France, in 1992.

He has been an Associate Professor and Profes-sor with the University of Lorraine, France (for-merly University of Metz), since 1994. He has beeninvolved in several academic and industrial researchprojects targeting interdisciplinary topics in the areasof telecommunications, mecatronics, and sensor net-works. His current research interests include faulttolerant digital circuits and systems, coding theory

and related high throughput circuitry for communication applications, newMPSoC and NoC paradigms.

Abbas Dandache received the Ph.D. degree bothin computer sciences and microelectronics from theINPG, Grenoble, in 1983 and 1986, respectively, andthe Habilitation degree from the University of Metz,Metz, France, in 2000.

He is currently a Professor with the University ofLorraine, Metz, since 2001. Since 2007, he has beenthe Director of the LICM Laboratory. He has been aPrincipal Investigator of several research contractsfrom the French telecommunications industry. Hehas authored and co-authored several publications

in the domain. His current research and teaching interests include electronicsdesign are related to embedded systems and smart sensors. Keywords of hisactivity include high performance communicating circuitry, fault-tolerant anddependable computing and, error coding circuitry.

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