sip design and verification using ads · 2010-06-23 · 5 9a fully integrated system or sub-system...

1

SiP Design and Verification using ADSSiP Design and Verification using ADS

June 17, [email protected]

22

▣ Contents

• Introduction

• SiP Definition in Package Assembly Area

• SiP Test Board Design and Characterization

• ADS Applications for STATSChipPAC Technology

33

eWLB

QFN‐dr

FBGA‐SD

PoP

PiP

Fan‐out WLCSP

Low cost fc‐CSP

Emphasis on flip chip & wafer level packaging development

Low cost Flip Chip MUF base Cu fcPoP/Cu fcPiP+TSV

Memory stack

Packaging Focus

Emerging Enabling Technologies

Cu ColumnHybrid Bump

TSV & µbumpPb-free Bump

SOWStacked die

BOL Stacked WLCSP

3D Enabling Technologies

Enabling Technology Focus

Advanced and Standard Laminate Packaging• 3D Package Stacking (PiP, PoP, fcPiP, fcPoP, fiPoP)• System-in-Package (SiP) • Flip-chip Chip-scale Package (FCCSP)• Chip-scale packageAdvanced and Standard Leaded Packaging• Stacked Die• QFN, QFPWafer Level Packaging (WLCSP) / Embeded Wafer Level BGA (eWLB)Bumping and Wafer Process Services• 12”/8” Electroplated Bumping• Integrated Passive Device (IPD)• Redistribution Layer (RDL)

Packaging Products

▣ IntroductionHigh Experience in Product Designs

44

SiP Definition in Package Assembly Area

• System in Package Definition

• Key Technologies for SiP Module

55

A Fully Integrated System or Sub-System

• One or more semiconductor chips on a die interconnectsubstrate plus:

• Passive components that would otherwise be integrated on the mother board.

• Surface mount discrete passives.

• Embedded or patterned into substrate.

• Integrated passive components/die.

• Other subsystem components:

• Shield, SAW filters, packaged ICs, connectors, antennas, mechanical housings, etc.

• A fully integrated functional block bridging the gap between SOC and PCB implementations.

▣ System in Package Definition

66

Mold fill under Chip capIPD (Integrated

Passive Die ) TechHigh density SMT

Placement Stacked Die +Passive Mount

Stacked DieCapability

Chip Cap

PCB

• Design capability for customized module

• Highly integrated passive mounting

• Capable of Multi die and Stack die combination

• Consistent Wire Length and Wire Loop Control

• IPD tech. based on Si

• EMI metal shield application

• Build up and stubless substrate design

Metal Shield Integration

Passives on Leadframe

▣ Key Technologies for SiP Module

77

Test Board Design and Characterization

• Single Ended Transmission Line Design

• Differential Pair Design

• Printed Inductor / Capacitor

• Wire Bond Characterization

88

▣ Overall Test Board Layout

• Dimension: 40mm X 40mm• GSG Probe Pitch: 150um• Stack-up: 1-2-1 4 layer• Thickness: 0.26T

99

• The characteristic impedance of a simple trace can be calculated from its two-port S-parameters.

• These parameters can be derived from either simulation or direct measurement.

Single Ended Line Tester

Line Width Line Length

GSG Probe

• Widths range: 50um ~ 150um

• lengths Range: 10mm and 20mm

▣ Single Ended Transmission Line

1010


• The characteristic impedance can be calculated from

0 11 11/Z Z Y=

Momentum Simulation Results

Eqn Zo = sqrt(Z11/Y11)

2 4 6 80 10

50

45

55

freq, GHz

ma

g(Z

o)

TermTerm6

Z=50 OhmNum=6

S2PSNP59File=

21

Ref

TermTerm5

Z=50 OhmNum=5

Characteristic impedance

1111

▣ Single Ended Transmission Line (1cm)

Case4: Line width: 125um Case5: Line width: 150um

• Blue: Simulation / Red: Measurement• Reference Frequency: 1GHz

m1freq=Z_MoM=73.138

1.000GHzm2freq=Z_Mea=75.301

1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Z_

Me

a

m2

Z_

Mo

M

m1

m1freq=Z_MoM=73.138


1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Z_

Me

a

m2Z_

Mo

M

m1

m1freq=Z_MoM=54.444


1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Z_

Me

a

m2Z_

Mo

M

m1

m1freq=Z_MoM=48.331


1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Z_

Me

a

m2

Z_

Mo

M

m1

m1freq=Z_MoM=35.916


1.000GHz

Case1: Line width: 50um Case2: Line width: 75um Case3: Line width: 100um

1 2 3 40 5

50

100

150

0

200

freq, GHz

Z_

Me

a

m4

Z_

Mo

M

m3

m4freq=Z_Mea=72.139

1.000GHzm3freq=Z_MoM=69.212

1.000GHz

1212

▣ Single Ended Transmission Line (2cm)

Case1: Line width: 50um Case2: Line width: 75um Case3: Line width: 100um

Case4: Line width: 125um Case5: Line width: 150um


1 2 3 40 5

50

100

150

0

200

freq, GHz

Z_

Me

a

m2

Z_

Mo

M

m1

m1freq=Z_MoM=35.413


1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Z_

Me

a

m2

Z_

Mo

M

m1

m1freq=Z_MoM=79.999


1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Z_

Me

a

m2

Z_

Mo

M

m1

m1freq=Z_MoM=66.352


1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Z_

Me

a

m2Z_

Mo

M

m1

m1freq=Z_MoM=56.635


1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Z_

Me

a

m2

Z_

Mo

M

m1

m1freq=Z_MoM=42.183


1.000GHz

1313

50 75 100 125 15030

35

40

45

50

55

60

65

70

75

80

85

35.4142.18

56.64

66.35

80.00

35.40

42.90

57.83

67.21

Impe

danc

e [O

hm]

Width [um]

Simulation Measurement

80.85


• Max error rate is 4.06% (2.93 Ohm difference) for 1cm single ended transmission line tester, and is 1.77% (1.19 Ohm difference) for 2cm single ended transmission line tester.

1cm transmission line 2cm transmission line

50 75 100 125 150

35

40

45

50

55

60

65

70

75

80

73.14

69.21

54.44

48.33

35.92

35.78

49.34

56.38

72.14

Impe

danc

e [O

hm]

Width [um]


75.30

1414

▣ Differential Pair

• The capacitance increase and the inductance decrease of the odd-mode affect the characteristic impedance as follows:

Odd Mode

Electrical field of odd mode Magnetic field of odd mode

modd

m

L LZC C−

=+

Electrical field of even mode magnetic field of even mode

Even Mode• The inductance increase and the capacitance decrease of the even-mode affect the characteristic impedance as follows:

meven

m

L LZC C+

=−

1515


Differential Mode

Common Mode

2 2differential odddifferential odd

differential odd

V VZ ZI I

×= = = ×

differential oddI I=2differential oddV V= ×

oddodd

odd

VZI

=

2 2common even even

commoncommon even

V V ZZI I

= = =×

2common evenI I= ×common evenV V=

eveneven

even

VZI

=

1616

Extracting Self and Mutual Inductance

• Inductance matrix for differential lines can be extracted from two-port Z-parameters with the far ends grounded.

( ) /ij ijL imag Z ω=

• The low-frequency limit of this expression gives the self (L11 and L22) and mutual (L12) inductances.

TermTerm2

Z=50 OhmNum=2

TermTerm1

Z=50 OhmNum=1 MCLIN

CLin1

L=3000 umS=50.0 umW=50.0 umSubst="MSub1"

ADS model for inductance extraction

Ideal coupled line

0.5 1.0 1.5 2.0 2.5 3.0 3.50.0 4.0

5.0E-10

1.0E-9

1.5E-9

2.0E-9

2.5E-9

0.0

3.0E-9

Frequency [GHz]

Sel

f_In

duct

ance

Mut

ual_

Indu

ctan

ce

Extracted Inductance [ADS Model]

1.3nH@1GHz

0.6nH@1GHz


Inductance extracted from ADS Model

1717

Extracting Self and Mutual Capacitance

TermTerm2

Z=50 OhmNum=2

TermTerm1

Z=50 OhmNum=1 MCLIN

CLin1

L=3000 umS=50.0 umW=50.0 umSubst="MSub1"

ADS model for capacitance extraction

Ideal coupled line

• Capacitance matrix for coupled lines can be extracted from two-port Z-parameters with the far ends open-circuited.

( ) /ij ijC imag Y ω=

• The low-frequency limit of this expression gives the self (C11 and C22) and mutual (C12) inductances.

• Note that generally the off-diagonal elements of the capacitance matrix are negative, so Cm=-C12

1 2 30 4

1E-13

2E-13

3E-13

0

4E-13

freq, GHz

Sel

f_C

apac

itanc

eM

utua

l_C

apac

itanc

e

Extracted Capacitance [ADS Model]

0.23pF@1GHz

0.065pF@1GHz


Capacitance extracted from ADS Model

1818


Normal Coupled line

Coupled line with Coplanar Ground Coupled line with Coplanar Ground and Bottom Ground

Ground Plane

Differential Pair

Dielectric

Dielectric

Ground Plane

Via

Test Structures

Co-planar Ground

Dielectric

1919



Case1: w:50um / s:50um Case2: w:50um / s:75um

Case3: w:75um / s: 75um Case4: w:75um / w:125um

1 2 3 40 5

50

100

150

0

200

freq, GHz

Me

a

m2

Sim

m1

Differential Impedance

m2freq=Mea=107.889

1.000GHzm1freq=Sim=110.667

1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Me

a

m1

Sim

m2


m1freq=Mea=117.196


1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Me

a m1

Sim

m2


m1freq=Mea=93.550


1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Me

a

m1

Sim

m2


m1freq=Mea=99.319


1.000GHz

2020


▣ Differential Pair with Coplanar Ground

1 2 3 40 5

50

100

150

0

200

freq, GHz

Me

a

m2

Sim

m1


m2freq=Mea=115.557


1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Me

a

m2

Sim

m1


m2freq=Mea=121.056


1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHz

Me

a

m2

Sim

m1


m2freq=Mea=123.165


1.000GHz

1 2 3 40 5

50

100

150

0

200

freq, GHzM

ea m2

Sim

m1


m2freq=Mea=96.118


1.000GHz

W: 75um / S: 125um / D: 50um

W: 75um / S: 125um / D: 50um W: 75um / S: 125um / D: 90um

W: 75um / S: 125um / D: 70um

2121

75/125/50 75/125/70 75/125/900

50

100

150

200

96.1497.43

123.17121.06115.56

123.39121.51

Diff

eren

tial I

mpe

danc

e [O

hm]

Line Width/ Space / Distance

Simulation Measurement Simulation_BOT_GND Measurement_BOT_GND

117.73

• Significant Parameters for Differential Pair Design- Line Width- Line to Line Space- Signal Line to Coplanar Ground Distance- Existence of Bottom Ground

Normal Coupled Line Coupled Line with Coplanar Ground

50/50 50/75 75/75 75/1250

50

100

150

200

99.3293.55

117.20107.89

101.9895.55

119.16

Diff

eren

tial I

mpe

danc

e [O

hm]

Line Width / Space [um]


110.67


2222

▣ Printed Spiral Inductor / Capacitor

• Printed Inductor is widely used for System in Package Products.• Additional assembly process and cost are not needed to implement a printed inductor. • Main Parameters: Conductivity / Surface Roughness / Dielectric Thickness

Printed Inductor Example

Inductor

Capacitor

Quad Band PAM

SP4T

2323

1 2 3 40 5

-5.0E-8

0.0

5.0E-8

-1.0E-7

1.0E-7

freq, GHz

L_M

ea

m1

L_S

im

m2

m1freq=L_Mea=5.561E-9

100.0MHz

m2freq=L_Sim=5.287E-9

100.0MHz

1 2 3 40 5

-20

0

20

-40

40

freq, GHzQ

_Mea

m4

Q_S

im

m3 m3freq=Q_Sim=20.341

1.000GHz

m4freq=Q_Mea=21.610

1.000GHz

1 2 3 40 5

-5.0E-8

0.0

5.0E-8

-1.0E-7

1.0E-7

freq, GHz

L_M

ea

m1

L_S

im

m2

m1freq=L_Mea=4.152E-9

100.0MHz

m2freq=L_Sim=4.135E-9

100.0MHz

1 2 3 40 5

-10

0

10

20

30

-20

40

freq, GHz

Q_M

ea

m4

Q_S

im

m3 m3freq=Q_Sim=21.784

1.000GHz

m4freq=Q_Mea=23.070

1.000GHz

Turn: 2.5 Radius:250

Turn: 2.5 Radius:400

• Blue: Simulation / Red: Measurement• Reference Frequency: 100MHz

▣ Printed Spiral Inductor

2424

CAP01: 1mm2 CAP02: 2mm2

• For printed capacitors, it is not effective in the same size condition compare to SMT passives.

▣ Printed Capacitor

1 2 3 40 5

0

1E-12

2E-12

3E-12

4E-12

-1E-12

5E-12

freq, GHz

C_M

ea m1

C_S

im m2

m1freq=C_Mea=1.634E-12

1.000GHzm2freq=C_Sim=1.716E-12

1.000GHz

1 2 3 40 5

0

1E-12

2E-12

3E-12

4E-12

-1E-12

5E-12

freq, GHz

C_M

ea

m1C_S

im

m2

m1freq=C_Mea=8.567E-13

1.000GHzm2freq=C_Sim=9.350E-13

1.000GHz

2525

▣ Wire Bond Characterization

• Wire Lengths Range: 600um / 800um / 1000um / 1200um• Single bonding / Double bonding /Triple Bonding• Wire to Wire distance: 100um• 1mil gold wire

2626

▣ Wire bond Characterization Wire Loop Parameter

ADS Bond Wire Setup

GAP STRETCH600 228800 3041000 3801200 456

BONDW_ShapeShape1

FlipX=1StopH=0 umStretch=380 umTilt=0 umMaxH=270 umStartH=150 umGap=1000 umRw=12.5 um

TermTerm1

Z=50 OhmNum=1

TermTerm2

Z=50 OhmNum=2

P06

P05

P03

P04

S6PSNP1File=

1 5

4

6

3 Ref2

P05

P04

P06

P03

BONDW2WIRESET1

W2_Angle=180W2_Zoffset=0 um

W2_Yoffset=0 umW2_Xoffset=-680 umW2_Shape="Shape1"W1_Angle=0W1_Zoffset=0 umW1_Yoffset=0 umW1_Xoffset=0 umW1_Shape="Shape1"Zoffset=0 umSepY=0 umSepX=0 umLayer="cond"View=sideCond=1.3e7 SRadw=12.5 um

1

2

2727


WB1000_Double bonding WB1200_Double bonding

WB600_Double bonding WB800_Double bonding

1 2 3 40 5

-1E-8

1E-8

3E-8

-3E-8

5E-8

freq, GHz

Lsim m1

Lmea

s

m2

m1freq=Lsim=9.850E-10

1.000GHzm2freq=Lmeas=9.648E-10

1.000GHz

1 2 3 40 5

-1E-8

1E-8

3E-8

-3E-8

5E-8

freq, GHz

Lsim m1

Lmea

s

m2



1.000GHz

1 2 3 40 5

-1E-8

1E-8

3E-8

-3E-8

5E-8

freq, GHz

Lsim m1

Lmea

s

m2



1.000GHz

1 2 3 40 5

-1E-8

1E-8

3E-8

-3E-8

5E-8

freq, GHz

Lsim m1

Lmea

s

m2



1.000GHz


2828


600 800 1000 1200

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

1.27

1.08

0.910.92

1.56

1.34

1.13

0.76

2.17

1.83

1.49

Indu

ctan

ce [n

H]

Wire Length [um]

Single Bonding Double Bonding Triple Bonding

1.23

• Measured and simulated characteristics of the wire bonds show consistent trends- More parallel wire bonds decreases inductance and raises Q- Longer wire bonds increase inductance and lower Q

Inductance Q Value

600 800 1000 12005

10

15

20

25

30

7.69.3

14.3

17.0 16.918.3

22.7

24.722.8

23.8

27.6

Q

Wire Length [um]

Single Bonding Double Bonding Triple Bonding

28.9

2929

ADS Applications for STATSChipPAC Technology

• Example 1: IPD Front End Module for WiMAX

• Example 2: 5 Channels Balun Bank

• Example 3: PA Module using eWLB+IPD Technology

• Example 4: TSV+IPD Technology

• Example 5: Embedded IPD

3030

▣ Example 1 – IPD Front End Module for WiMAX

Existing LTCC Solution

IPD Solution

• Product Application: Mobile Broadband Devices

• Sawless Front End Module

• IPD type: Wire Bond

• IPD Application: Balanced BPF / LPF / BalunPackage Structure

RFSwitch

RF IC

RF IC

3131

▣ Example 2 – 5 Channels Balun Bank

RFIC

FC IPD

• Product Application: Mobile Broadband Devices

• Package Solution: FcVFBGA-SD2+1, 7.0 x 7.0 sq.mm

• IPD type: Fc-IPD

• IPD Application: Balun

Package Structure

WCDMA_HB

WCDMA_IMT

WCDMA_LB

GSM_HB

GSM_LB

IPD Baluns

3232

▣ Example 3 – PA Module using eWLB+IPD Technology

• Application – G3 WCDMA application (CMOS-PA + IPD)

• new package platform for PA+IPD multichip

• eWLB had excellent high frequency electrical performance

Package Structure

Actual Product

6.1mm

5.6 mm

3333

▣ Example 4 – TSV+IPD Technology

• Silicon TSV interposer with embedded passives• Integrated silicon batch process• Fine metal line width/spacing• High performance and miniaturized packaging solutions

20% Size Reduction!!!!

IPD with TSV Normal bumped IPD

3434

▣ Example 5 – Embedded IPD

sip design and verification using ads · 2010-06-23 · 5 9a fully integrated system or sub-system...

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