simulator for superh

Simulator for SuperH

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TRACE32 Documents ......................................................................................................................

TRACE32 Instruction Set Simulators ..........................................................................................

Simulator for SuperH ................................................................................................................. 1

TRACE32 Simulator License .................................................................................................. 4

Quick Start of the Simulator ................................................................................................... 5

Peripheral Simulation ............................................................................................................. 7

Troubleshooting ...................................................................................................................... 8

FAQ ........................................................................................................................................... 8

CPU specific SYStem Commands ......................................................................................... 9

SYStem.CONFIG Configure debugger according to target topology 9

SYStem.CPU CPU type 9

SYStem.CpuAccess Run-time memory access (intrusive) 9

SYStem.MemAccess Real-time memory access (non-intrusive) 10

SYStem.Option IMASKASM Disable interrupts while single stepping 10

SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 10

SYStem.Option LittleEnd Selection of little endian mode 11

SYStem.Option MMUSPACES Separate address spaces by space IDs 11

SYStem.RESetOut CPU reset command 12

CPU specific MMU Commands .............................................................................................. 13

MMU.DUMP Page wise display of MMU translation table 13

MMU.List Compact display of MMU translation table 15

MMU.SCAN Load MMU table from CPU 16

General Settings and Restrictions ......................................................................................... 18

Memory Classes ...................................................................................................................... 19

Support ..................................................................................................................................... 20

Available Tools 20

Compilers 22

Target Operating Systems 23

3rd-Party Tool Integrations 24

Products ................................................................................................................................... 25

Product Information 25

Simulator for SuperH 1 ©1989-2018 Lauterbach GmbH

Order Information 25


Simulator for SuperH

Version 16-Nov-2018

All general commands are described in the “PowerView Command Reference” (ide_ref.pdf) and “General Commands Reference”.


TRACE32 Simulator License

[build 68859 - DVD 02/2016]

The extensive use of the TRACE32 Instruction Set Simulator requires a TRACE32 Simulator License.

For more information, see www.lauterbach.com/sim_license.html.


www.lauterbach.com/sim_license.html

Quick Start of the Simulator

To start the simulator, proceed as follows:

1. Select the device prompt for the ICD Debugger and reset the system.

The device prompt B:: is normally already selected in the command line. If this is not the case, enter B:: to set the correct device prompt. The RESet command is only necessary if you do not start directly after booting TRACE32.

2. Specify the CPU specific settings.

The default values of all other options are set in such a way that it should be possible to work without modification. Please consider that this is probably not the best configuration for your target.

B::

RESet

SYStem.CPU <cpu_name>


3. Enter debug mode.

This command resets the CPU and enters debug mode. After this command is executed it is possible to access memory and registers.

4. Load the program.

See the Data.LOAD command reference for a list of supported file formats. If uncertain about the required format, try Data.LOAD.auto.

A detailed description of the Data.LOAD command and all available options is given in the reference guide.

5. Start-up example

A typical start sequence is shown below. This sequence can be written to a PRACTICE script file (*.cmm, ASCII file format) and executed with the command DO <filename>.

*) These commands open windows on the screen. The window position can be specified with the WinPOS command.

SYStem.Up

Data.LOAD.<format> <filename> ; load program and symbols

B:: ; Select the ICD device prompt

WinCLEAR ; Clear all windows

SYStem.CPU <cpu_name> ; Select CPU type

SYStem.Up ; Reset the target and enter; debug mode

Data.LOAD.<format> <filename> ; Load the application

Register.Set pc main ; Set the PC to function main

PER.view ; Show clearly arranged peripherals ; in window *)

Data.List ; Open source code window *)

Register /SpotLight ; Open register window *)

Frame.view /Locals /Caller ; Open the stack frame with ; local variables *)

Var.Watch %Spotlight flags ast ; Open watch window for ; variables *)


Peripheral Simulation

For more information, see “API for TRACE32 Instruction Set Simulator” (simulator_api.pdf).


Troubleshooting

No information available.

FAQ

No information available


CPU specific SYStem Commands

SYStem.CONFIG Configure debugger according to target topology

The SYStem.CONFIG commands have no effect on the simulator. They are only provided to allow the user to run PRACTICE scripts written for the debugger within the simulator without modifications.

SYStem.CPU CPU type

Selects the processor type.

SYStem.CpuAccess Run-time memory access (intrusive)

Default: Denied.

Format: SYStem.CPU <type>

<mode>: SH7040 | SH7041 …

Format: SYStem.CpuAccess Enable | Denied | Nonstop

Enable Allow intrusive run-time memory access.Since a non-intrusive run-time memory access (SYStem.MemoryAccess CPU) is available for all TRACE32 instruction set simulators, there is no need for an intrusive run-time memory access.

Denied Lock intrusive run-time memory access.

Nonstop Lock all features of the debugger that affect the run-time behavior.Nonstop reduces the functionality of the debugger to:• run-time access to memory and variables• trace displayThe debugger inhibits the following:• to stop the program execution• all features of the debugger that are intrusive (e.g. action Spot for

breakpoints, performance analysis via StopAndGo mode, condi-tional breakpoints etc.)


SYStem.MemAccess Real-time memory access (non-intrusive).

SYStem.Option IMASKASM Disable interrupts while single stepping

Default: OFF.

If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step.

SYStem.Option IMASKHLL Disable interrupts while HLL single stepping

Default: OFF.

If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step.

Format: SYStem.MemAccess CPU | Denied | <cpu_specific>SYStem.ACCESS (deprecated)

CPU Real-time memory access during program execution to target is enabled.

Denied (default) Real-time memory access during program execution to target is disabled.

Format: SYStem.Option IMASKASM [ON | OFF]

Format: SYStem.Option IMASKHLL [ON | OFF]


SYStem.Option LittleEnd Selection of little endian mode

With this option data is displayed little endian style.

SYStem.Option MMUSPACES Separate address spaces by space IDs

Default: OFF.

Enables the use of space IDs for logical addresses to support multiple address spaces.

For an explanation of the TRACE32 concept of address spaces (zone spaces, MMU spaces, and machine spaces), see “TRACE32 Glossary” (glossary.pdf).

Examples:

Format: SYStem.Option LittleEnd [ON | OFF]

Format: SYStem.Option MMUSPACES [ON | OFF]SYStem.Option MMUspaces [ON | OFF] (deprecated)SYStem.Option MMU [ON | OFF] (deprecated)

NOTE: SYStem.Option MMUSPACES should not be used if only one translation table is used on the target.

If a debug session requires space IDs, you must observe the following sequence of steps:

1. Activate SYStem.Option MMUSPACES.

2. Load the symbols with Data.LOAD.

Otherwise, the internal symbol database of TRACE32 may become inconsistent.

;Dump logical address 0xC00208A belonging to memory space with ;space ID 0x012A:Data.dump D:0x012A:0xC00208A

;Dump logical address 0xC00208A belonging to memory space with ;space ID 0x0203:Data.dump D:0x0203:0xC00208A


SYStem.RESetOut CPU reset command

The command asserts nRESET on the JTAG connector in the TRACE32 In-Circuit Debugger (ICD) but is ignored by the TRACE32 Instruction Set Simulator. However, the command is allowed in the simulator so that you can run scripts which have actually been made for the debugger. For more information about the effect in the debugger, refer to your Processor Architecture Manual (debugger_<arch>.pdf).


CPU specific MMU Commands

MMU.DUMP Page wise display of MMU translation table

Displays the contents of the CPU specific MMU translation table.

• If called without parameters, the complete table will be displayed.

• If the command is called with either an address range or an explicit address, table entries will only be displayed, if their logical address matches with the given parameter.

Format: MMU.DUMP <table> [<range> | <addr> | <range> <root> | <addr> <root>]MMU.<table>.dump (deprecated)

<table>: PageTableKernelPageTableTaskPageTable <task_magic> | <task_id> | <task_name> | <space_id>:0x0<cpu_specific_tables>

<root> The <root> argument can be used to specify a page table base address deviating from the default page table base address. This allows to display a page table located anywhere in memory.

PageTable Displays the current MMU translation table entries of the CPU. This command reads all tables the CPU currently uses for MMU translation and displays the table entries.

KernelPageTable Displays the MMU translation table of the kernel.If specified with the MMU.FORMAT command, this command reads the MMU translation table of the kernel and displays its table entries.

TaskPageTable <task_magic> | <task_id> | <task_name> | <space_id>:0x0

Displays the MMU translation table entries of the given process. Specify one of the TaskPageTable arguments to choose the process you want.In MMU-based operating systems, each process uses its own MMU translation table. This command reads the table of the specified process, and displays its table entries.• For information about the first three parameters, see “What to

know about Task Magic Numbers, Task IDs and Task Names” (general_ref_t.pdf).

• See also the appropriate OS Awareness Manuals.


CPU specific Tables for MMU.DUMP <table>

ITLB Displays the contents of the Instruction Translation Lookaside Buffer.

UTLB Displays the contents of the Unified Translation Lookaside Buffer.


MMU.List Compact display of MMU translation table

Lists the address translation of the CPU-specific MMU table.

• If called without address or range parameters, the complete table will be displayed.

• If called without a table specifier, this command shows the debugger-internal translation table. See TRANSlation.List.

• If the command is called with either an address range or an explicit address, table entries will only be displayed, if their logical address matches with the given parameter.

Format: MMU.List <table> [<range> | <addr> | <range> <root> | <addr> <root>] MMU.<table>.List (deprecated)

<table>: PageTableKernelPageTableTaskPageTable <task_magic> | <task_id> | <task_name> | <space_id>:0x0

<root> The <root> argument can be used to specify a page table base address deviating from the default page table base address. This allows to display a page table located anywhere in memory.

PageTable Lists the current MMU translation of the CPU. This command reads all tables the CPU currently uses for MMU translation and lists the address translation.

KernelPageTable Lists the MMU translation table of the kernel.If specified with the MMU.FORMAT command, this command reads the MMU translation table of the kernel and lists its address translation.


Lists the MMU translation of the given process. Specify one of the TaskPageTable arguments to choose the process you want.In MMU-based operating systems, each process uses its own MMU translation table. This command reads the table of the specified process, and lists its address translation.• For information about the first three parameters, see “What to

know about Task Magic Numbers, Task IDs and Task Names” (general_ref_t.pdf).

• See also the appropriate OS Awareness Manuals.


MMU.SCAN Load MMU table from CPU

Loads the CPU-specific MMU translation table from the CPU to the debugger-internal static translation table.

• If called without parameters, the complete page table will be loaded. The list of static address translations can be viewed with TRANSlation.List.

• If the command is called with either an address range or an explicit address, page table entries will only be loaded if their logical address matches with the given parameter.

Use this command to make the translation information available for the debugger even when the program execution is running and the debugger has no access to the page tables and TLBs. This is required for the real-time memory access. Use the command TRANSlation.ON to enable the debugger-internal MMU table.

Format: MMU.SCAN <table> [<range> <address>]MMU.<table>.SCAN (deprecated)

<table>: PageTableKernelPageTableTaskPageTable <task_magic> | <task_id> | <task_name> | <space_id>:0x0ALL<cpu_specific_tables>

PageTable Loads the current MMU address translation of the CPU. This command reads all tables the CPU currently uses for MMU translation, and copies the address translation into the debugger-internal static translation table.

KernelPageTable Loads the MMU translation table of the kernel.If specified with the MMU.FORMAT command, this command reads the table of the kernel and copies its address translation into the debugger-internal static translation table.


Loads the MMU address translation of the given process. Specify one of the TaskPageTable arguments to choose the process you want.In MMU-based operating systems, each process uses its own MMU translation table. This command reads the table of the specified process, and copies its address translation into the debugger-internal static translation table.• For information about the first three parameters, see “What to know

about Task Magic Numbers, Task IDs and Task Names” (general_ref_t.pdf).

• See also the appropriate OS Awareness Manual.

ALL Loads all known MMU address translations. This command reads the OS kernel MMU table and the MMU tables of all processes and copies the complete address translation into the debugger-internal static translation table. See also the appropriate OS Awareness Manual.


CPU specific tables for MMU.SCAN <table>

ITLB Loads the instruction translation table from the CPU to the debugger internal translation table.

UTLB Loads the unified translation table from the CPU to the debugger internal translation table.


General Settings and Restrictions


Memory Classes

Memory Class Description

D Data

P Program


Support

Available Tools

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SH2A-CORE YES YES YESSH7011 YES YES YESSH7014 YES YES YESSH7016 YES YES YESSH7017 YES YES YESSH7020 YES YESSH7021 YES YESSH7034 YES YESSH7040 YES YES YESSH7041 YES YES YESSH7042 YES YES YESSH7043 YES YES YESSH7044 YES YES YESSH7045 YES YES YESSH7047F YES YESSH7050 YES YES YESSH7051 YES YES YESSH7052 YES YES YESSH7053 YES YES YESSH7054 YES YES YESSH7055 YES YES YESSH7058 YES YESSH7058R YES YESSH7059 YES YESSH7083 YES YES YESSH7084 YES YES YESSH7085 YES YES YESSH7086 YES YES YESSH7144 YES YESSH7145 YES YESSH7147 YES YES YESSH7201 YES YES YESSH7203 YES YES YESSH7205 YES YES YES


SH7206 YES YES YESSH7211 YES YES YESSH7216 YES YES YESSH72165 YES YES YESSH72166 YES YES YESSH72167 YES YES YESSH7251 YES YES YESSH72531 YES YES YESSH72544 YES YES YESSH72544R YES YES YESSH72545 YES YES YESSH72546 YES YES YESSH72546R YES YES YESSH72567 YES YES YESSH725xxx YES YES YESSH7261 YES YES YESSH7263 YES YES YESSH7264 YES YES YESSH7267 YES YES YESSH7269 YES YES YESSH726A YES YES YESSH726B YES YES YESSH7294 YES YES YESSH7300 YES YES YESSH7315 YES YES YESSH73382 YES YES YESSH7357 YES YES YESSH74504 YES YES YESSH7615 YES YESSH7622 YES YESSH7705 YES YES YESSH7706 YES YES YESSH7709A YES YES YESSH7709BE YES YES YESSH7709LE YES YES YESSH7709S YES YES YESSH7710 YES YES YESSH7712 YES YES YESSH7720 YES YES YESSH7721 YES YES YESSH7722 YES YES YES

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Compilers

SH7723 YES YES YESSH7727 YES YES YESSH7729 YES YES YESSH7750 YES YESSH7750R YES YESSH7751 YES YES YESSH7751R YES YES YESSH7760 YES YES YESSH7761 YES YES YESSH7763 YES YES YESSH7764 YES YES YESSH7770 YES YES YESSH7780 YES YES YESSH7781 YES YES YESSH7785 YES YES YESSH7786 YES YES YESST40GX1 YES YES YESST40NGX1 YES YES YESST40RA166 YES YES YESST40STB1 YES YES YESSTB7100 YES YESSTB7109 YES YES

Language Compiler Company Option Comment

C GCCSH Free Software Foundation, Inc.

COFF

C GREEN-HILLS-C Greenhills Software Inc. COFFC ICCSH IAR Systems AB UBROFC SHC Renesas Technology,

Corp.SYSROF

C++ SHC++ Renesas Technology, Corp.

ELF/DWARF

C++ D-CC Wind River Systems ELF/DWARF

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Target Operating Systems

Company Product Comment

CMX Systems Inc. CMX-RTXRenesas Technology, Corp. HI7000- Linux Kernel Version 2.4 and 2.6, 3.x, 4.xMontaVista Software, LLC Linux 3.0, 3.1, 4.0, 5.0Mentor Graphics Corporation

Nucleus

ST Microelectronics N.V. OS21- OSEK via ORTIElektrobit Automotive GmbH

ProOSEK via ORTI

QNX Software Systems QNX 6.0 to 7.0Micro Digital Inc. SMX 3.4 to 4.3Express Logic Inc. ThreadX 3.0, 4.0, 5.x- uITRON HI7000, RX4000, NORTi,PrKernelWind River Systems VxWorks 5.x and 6.xMicrosoft Corporation Windows CE 4.0 to 6.0Microsoft Corporation Windows Mobile 4.0 to 6.0


3rd-Party Tool Integrations

CPU Tool Company Host

WINDOWS CE PLATF. BUILDER

- Windows

CODE::BLOCKS - -C++TEST - WindowsADENEO -X-TOOLS / X32 blue river software GmbH WindowsCODEWRIGHT Borland Software

CorporationWindows

CODE CONFIDENCE TOOLS

Code Confidence Ltd Windows

CODE CONFIDENCE TOOLS

Code Confidence Ltd Linux

EASYCODE EASYCODE GmbH WindowsECLIPSE Eclipse Foundation, Inc WindowsCHRONVIEW Inchron GmbH WindowsLDRA TOOL SUITE LDRA Technology, Inc. WindowsUML DEBUGGER LieberLieber Software

GmbHWindows

SIMULINK The MathWorks Inc. WindowsATTOL TOOLS MicroMax Inc. WindowsVISUAL BASIC INTERFACE

Microsoft Corporation Windows

LABVIEW NATIONAL INSTRUMENTS Corporation

Windows

TPT PikeTec GmbH WindowsCANTATA QA Systems Ltd WindowsRAPITIME Rapita Systems Ltd. WindowsRHAPSODY IN MICROC IBM Corp. WindowsRHAPSODY IN C++ IBM Corp. WindowsDA-C RistanCASE WindowsTRACEANALYZER Symtavision GmbH WindowsECU-TEST TraceTronic GmbH WindowsUNDODB Undo Software LinuxTA INSPECTOR Vector WindowsVECTORCAST UNIT TESTING

Vector Software Windows

VECTORCAST CODE COVERAGE

Vector Software Windows


Products

Product Information

Order Information

OrderNo Code Text

LA-2815L SIMULATOR-SH-FL

1 User Float. Lic. TRACE32 SH SimulatorFloating license to use the TRACE32 Instruction SetSimulator for automated tests via script languagePRACTICE or via the TRACE32 Remote APIsupports SH1/SH2/SH3/SH4for Windows32, Windows64, Linux32, Linux64and Solaris, other platforms on requestfloating license via RLM (Reprise License Manager)Please add the RLM HostID of the license serverto your order (please see our FAQ)

Order No. Code Text

LA-2815L SIMULATOR-SH-FL 1 User Float. Lic. TRACE32 SH Simulator
