simple processor control unit

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Instructor: Oluwayomi Adamo Digital Systems Design

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Simple Processor Control Unit. Instructor: Oluwayomi Adamo Digital Systems Design. Objective. Design a simple processor , capable of picking up data from a switch register, Operate the switch register using manually, Display output using LEDs or seven segment display, - PowerPoint PPT Presentation

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Page 1: Simple Processor Control Unit

Instructor: Oluwayomi AdamoDigital Systems Design

Page 2: Simple Processor Control Unit

Design a simple processor , capable of picking up data from a switch register, Operate the switch register using manually, Display output using LEDs or seven segment display, Perform basic operations such as add, subtract,

multiply and divide as well as data movement. Implement the processor in hardware, Test your implementation using basic set of

instruction you designed.

Page 3: Simple Processor Control Unit

What is the System Requirement? What are functional blocks required? What is the size of your instructions? Types of Instructions to design:

1. Data handling and manipulation (add, sub, increment, and clear etc.)

2. Branch instructions3. Input and Output

Page 4: Simple Processor Control Unit

Draw a block diagram of your simple processor,

The block diagram should show the interconnection of different registers, modules and control unit.

Sample instructions for testing, Control signal needed for your processor,

inputs and outputs needed. Inputs and outputs with respect to the FPGA

used for implementation.

Page 5: Simple Processor Control Unit

Design a control unit for picking up instructions from memory address given by the program counter (PC).

Interpret the instruction, Fetch the operands and feed them to the

ALU, Store the result in destination registers Load the pc with destination address in case

of branch instruction, Contents of destination will be forwarded to

the LED or 7 segment display for display.

Page 6: Simple Processor Control Unit

Op CC SRC DST

Register Instruction

01001011

Branch Instruction

11 CC ADDRESS

Halt and I/O Instruction

1100 L H DST

1100101111000110

11100011

Page 7: Simple Processor Control Unit

◦ To be drawn in class

Page 8: Simple Processor Control Unit

The control unit is like computer’s traffic cop. It coordinates and controls all operations occurring within

the processor. The control unit does not input, output, process, or store

data, it initiates and controls the sequence of these operations. Controls Data Movements in an Operational Circuit by

Switching Multiplexers and Enabling or Disabling Resources Follows Some ‘Program’ or Schedule Often Implemented as Finite State Machine or collection of

Finite State Machines

Page 9: Simple Processor Control Unit

Any Circuit with Memory could be called a Finite State Machine◦ Even computers can be viewed as huge FSMs

Design of FSMs Involves◦ Defining states◦ Defining transitions between states◦ Optimization / minimization

Above Approach Is Practical for Small FSMs Only

Page 10: Simple Processor Control Unit

Output Is a Function of a Present State Only TYPE state IS (S0, S1, S2); SIGNAL Moore_state: state;

U_Moore: PROCESS (clock, reset) BEGIN IF(reset = ‘1’) THEN Moore_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Moore_state IS WHEN S0 => IF input = ‘1’ THEN Moore_state <= S1; ELSE Moore_state <= S0;

END IF;

reset

Page 11: Simple Processor Control Unit

WHEN S1 =>

IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF; WHEN S2 => IF input = ‘0’ THEN Moore_state <= S0; ELSE Moore_state <= S1; END IF; END CASE; END IF; END PROCESS;

Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;

Page 12: Simple Processor Control Unit

Output Is a Function of a Present State and Inputs

TYPE state IS (S0, S1); SIGNAL Mealy_state: state;

U_Mealy: PROCESS(clock, reset) BEGIN IF(reset = ‘1’) THEN Mealy_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Mealy_state IS WHEN S0 => IF input = ‘1’ THEN Mealy_state <= S1; ELSE Mealy_state <= S0; END IF;

Page 13: Simple Processor Control Unit

WHEN S1 => IF input = ‘0’ THEN Mealy_state <= S0; ELSE Mealy_state <= S1; END IF; END CASE; END IF; END PROCESS;

Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;

Page 14: Simple Processor Control Unit

Fetch -> Decode -> Execute

Fetch Sequence t1: MAR <- (PC) t2: MBR <- (memory) PC <- (PC) +1 t3: IR <- (MBR) (tx = time unit/clock cycle)

Page 15: Simple Processor Control Unit

Good Luck!!!