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3544 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 10, OCTOBER 2010

A Method Based on Petri Nets and a Matrix Model toImplement Reconfigurable Logic Controllers

Celso F. Silva, Camilo Quintns, Member, IEEE, Antonio Colmenar,Manuel A. Castro, Fellow, IEEE, and Enrique Mandado, Life Member, IEEE

AbstractThis paper presents a method to implement reconfig-urable logic controllers (RLCs) using a new matrix model to de-scribe Petri nets (PNs). The method obtains the general equationsand directly translates them into a hardware description language(HDL) to configure a field-programmable gate array (FPGA). Toachieve a generalized model in a comprehensible way, several PNexamples including timers, counters, and hierarchical subnets aredescribed in detail. The working principles and robustness of themethod are validated by simulating each example and by theirpractical implementation in an RLC.

Index TermsField-programmable gate arrays (FPGAs), hard-ware design languages, industrial control, matrix equations,Petri nets (PNs).

I. INTRODUCTION

L OGIC controllers have commonly been implemented un-til now using programmable logic controllers (PLCs),and several methods have been used to describe their be-

havior. These methods can be based on ladder diagrams [1],

Petri nets (PNs) [2], the sequential function chart (SFC) [3], etc.

In particular, PNs provide a unified model for both sequential

(only one state being active at a time) and concurrent logic

controllers (several states can simultaneously be active) [4] in-cluding synchronization, shared resources, mutual exclusions,

and dispatching. These properties are difficult to handle without

using PNs. Useful tutorials describing PN fundamentals are

available in [5][7].

Logic controllers based on PNs are usually implemented

by means of a program executed in a sequential way using

a programmable processor such as a PLC. However, due to

the special advantages of PNs relating to the specification

of logic controllers, they can be implemented using sequen-

tial hardware without using a programmable processor [8].

Fixed-architecture standard off-the-shelf integrated circuits

(medium-scale integrated or large-scale integrated) andapplication-specific integrated circuits have been used until now

Manuscript received January 28, 2009; revised August 16, 2009; acceptedNovember 2, 2009. Date of publication January 8, 2010; date of current versionSeptember 10, 2010.

C. F. Silva is with the Department of System Engineering and Automation,University of Vigo, 36310 Vigo, Spain (e-mail: [email protected]).

C. Quintns and E. Mandado are with the Department of Electronic Technol-ogy, University of Vigo, 36310 Vigo, Spain.

A. Colmenar and M. A. Castro are with the Electrical and ComputerEngineering Department, Spanish University for Distance Education (UNED),28040 Madrid, Spain.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2009.2038946

to carry out the implementation of logic controllers. However,

due to the wired nature of these kinds of circuits, complex

logic controllers are difficult to implement. The development

of configurable digital integrated circuits over the last decade,

such as field-programmable gate arrays (FPGAs) [9], [10], has

allowed the introduction of new ways of implementing logic

controllers.

Several studies have been carried out to implement logic

controllers using FPGAs [1], [2], [11]. These controllers, calledreconfigurable logic controllers (RLCs) [12], are more flexi-

ble and cheaper than PLCs due to their great logic resource

capacity, reconfigurability, and running speed [13]. However,

from a practical point of view, it is worthwhile to note that

the design method is the same when implementing an RLC

and a PLC [14]. To achieve this, it is necessary to use a

unified electronic design automation tool including different

description, compilation, debugging, hardware configuration,

and testing tasks [15].

During the description stage, a data structure is necessary,

following a mathematical model easily joined to the graphic

project editor. Then, an algorithm translating the data structure

into a hardware description language (HDL) code, for example,very high speed integrated circuit HDL (VHDL) [4], [16], is

needed in the case of an RLC.

Many efforts have been made to describe logic controllers

with an HDL code exploiting the characteristics of some well-

known design methods [17]. In the case of PNs, there are

several PN-to-VHDL translators, but they are usually based on

the interpretation of a pseudocode or on a rule-based formal

language [2], [18]. In addition, these modeling methods do not

follow a mathematical notation on which one can work and

which may directly be translatable to VHDL.

Moreover, the translators based on intermediate languages,

which constitute an additional step, complicate the transforma-tion of the system model into a VHDL code. On the contrary,

a more universal mathematical model does not add more com-

plexity than that of the represented system [19]. Furthermore, it

is easier to generate a mathematical notation from the graphic

editor than to generate a pseudocode requiring a greater abstrac-

tion level.

This paper presents a method to implement logic controllers,

described by means of a PN, using a new matrix model in

such a way that the requirements are easily carried out by an

RLC. Matrix models [5] have mainly been used in the past

to optimize the necessary resources [20] or to determine the

PN behavior through simulation, implementing it by means

0278-0046/$26.00 2010 IEEE


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SILVA et al.: METHOD BASED ON PETRI NETS AND A MATRIX MODEL TO IMPLEMENT RLCs 3545

of a sequential programmable processor [21]. In contrast, the

new matrix model is expressly designed to provide a structure

defining the PN from which the controller state equations,

synthesizable with the FPGA hardware, can directly be ob-

tained. Moreover, any model defining a logic controller must

facilitate the utilization of timers and counters. These elements

are essential to allow the automation of any industrial process,and therefore, the matrix model is extended to include them.

In Section II, the definition, general equations, and structure

of the PN matrix model and its implementation as an RLC

are described. Section III contains a basic example that is

analyzed and simulated to demonstrate the method application.

Section IV deals with the aspects needed to be taken into

account when timers and counters are included in the require-

ments, and the previous example is modified to show the

necessary theoretical and practical changes. Practical results,

configuring an RLC based on a Cyclone FPGA [22] for the

different examples, are shown in Section V. In Section VI,

the model is enhanced to include subnets, showing how the

matrix model is easily extended to achieve the global matrices

of the whole system. Finally, conclusions are summarized in

Section VII.

II. METHOD DESCRIPTION AND IMPLEMENTATION

This section presents the general definition of the matrix

model elements and shows how a set of logic equations de-

scribing the PN behavior is achieved. The method presented

in this paper is focused on binary or safe (1-bounded) PNs,

with extensions such as inhibitor arcs [5] and without effective

conflicts. A dispatching subroutine can be used in conflict

resolution [21]. Alternatively, a fixed priority can be used(a fixed priority is used in this context because it is simpler [23]

and because an effective conflict constitutes a bad design). The

logic equations specify the evolution between the current and

next states without either glitches or extra clock cycles. Then,

the method to obtain the VHDL code showing the proposal

process organization, in a graphical way, is described. Finally,

an example of a platform implementing an RLC is analyzed.

A. Definition of the PN Matrix Model

To describe logic controller behavior using a PN, it is neces-

sary to establish an interpretation defining the transition firingconditions and the actions to be generated. This kind of PN is

called a control-interpreted PN (CIPN) [6], [8] and constitutes

a class of nonautonomous PNs in the same way as I/O place-

transition PNs [24] and signal-interpreted PNs are used to

formally specify control algorithms for PLCs [25], and fuzzy

PNs are used as a controller [26].

A CIPN is synchronized, safe, and deterministic [6] and is

the kind of PN used in this paper. The actions are associated

with places, and the transitions are associated with events

(input and output logic functions) and with pulse outputs. The

specifications with SFC are treated as a special form of CIPN.

The terms and definitions that are used by the PN matrix

model implementing a logic controller are shown in Table I.The dimensions of the model matrices are shown in Table II.

TABLE INOTATION DEFINITIONS

TABLE IIDIMENSION OF THE DOT-M ATRIX MODEL

B. General Equations and Structure of the Matrix Model

From the PN, the following matrices are obtained.

1) Preincidence TIand postincidence TO matrices

TI : m n (1)

TO : m n. (2)

A 1 in the ij position of the TI matrix indicates thatthere is an arc from place j to transition i, and a 1 inthe ij position of the TO matrix indicates that there is anarc from transition i to place j.

2) Input map matrix Eand output map matrix A

E= (E1 E2 Eh ) : 1 h (3)

A = (A1 A2 Aq ) : 1 q. (4)

3) Transition logic matrix

F = ( f1 f2 fm ) : 1 m. (5)

Matrix F is constituted by input, output, and internalconditions associated to transitions.


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4) Current marking matrix CP and next markingmatrix NP

CP = ( cp1 cp2 cpn ) : 1 n (6)

NP = (np1 np2 npn ) : 1 n. (7)

A 1 in position i of CP indicates that the pi placeis marked. In the same way, a 1 in position i ofNPindicates that thepi place will be marked in the next clockevent.

From the matrices defining the PN, the final equations are

found in accordance with the following sequence.

First, the PTmatrix is calculated as

PT = CP TIt (8)

where the operator between two matrices A1n and Bnmmeans that each term c1,j of the resulting matrix C1m corre-sponds to the AN D operation & of the products a1,i & bi,j

that are not null (with i being from 1 to n and j being from 1to m).The PTmatrix indicates the places that must have a token to

activate a transition.

Then, the matrix T specifying the transitions to be activatedis calculated

T = F& PT = F& CP TIt. (9)

After that, the FTImatrix is obtained

FTI= F TI. (10)

This matrix is used to obtain the PP staying matrix establish-

ing the conditions to be fulfilled so that the state of any markedplace remains unchanged

PP = CP & FTI. (11)

Now, the transition evolution matrix TTO is obtained

TTO = T TO. (12)

Then, the logic operation OR | between the TTO matrixand the PP matrix is carried out to obtain the next markingmatrixNP, taking into account that a certain place may alreadybe marked (PP) or newly marked (TTO)

NP = TTO |PP = (T TO)|CP & (F TI)

. (13)

The general equation, depending on the initial definitions in

Table I, is

NP =

(F& CP TIt) TO|CP & (F TI)

. (14)

Finally, the output equation corresponding to matrix A isgiven by the next marking and the output activation matrices

A = NPXA (15)

where the operator between two matrices A1n and Bnmmeans that each term c1,j of the resulting matrix C1m corre-

sponds to the OR operation | of the products a1,i & bi,j thatare not null.

Fig. 1. Processes implementing a PN.

Fig. 2. Block diagram of the logic controller hardwaresoftware platform.

Fig. 1 shows the process organization implementing the PN

from the aforementioned equations. The different processes are

the following.

1) ConditionsCalc: This is a combinational process (5) cal-

culating the logic conditions that activate the transitions.

2) StateCalc: This is a combinational process (14) calculat-ing the next marked state from the present one and taking

into account the logical functions of the transitions, which

were calculated in the previous process.

3) StateUpdate: This is a process being synchronized by

the clock, where the markings and outputs are updated.

The outputs are directly calculated from the NP signals(15) and are memorized at the same time as the CPones. Although this method of calculating the outputs

does not follow traditional solutions, it has the advantages

of saving one clock cycle and guaranteeing that all output

signals are activated at the same time, thereby preventing

intermediate output values because of the delays of thecombinational circuit of the logic equation (15).

C. RLC Implementation

To implement an RLC, a hardwaresoftware platform is

needed. In the implementation presented in this paper (Fig. 2),

the software includes a PN design tool called HPetriNets [27]

and the design tool of the particular FPGA being used in

the project. The most important task of the HPetriNets is the

translation of a PN into a VHDL description in a transparent

way. The hardware is an FPGA-based card and a set of digital

and analog I/O cards (Fig. 3). It not only implements the

automation task but is also combined with a software toolproviding simulation and monitoring capabilities.


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Fig. 3. RLC photography including the FPGA (left) and the I/O card (right).

TABLE IIIC P ROGRAM GENERATING THE VHDL COD E

FROM THE MATRIX MODEL

Using the HPetriNets graphic interface, the PN is defined and

translated into the matrix model in accordance with the method

previously described. The code generator converts the matrix

model into a VHDL description using the data flow modeling

and takes into account the hardware constraints. Table III

shows an example of a C language program generating the

VHDL code.

A synthesis using fewer resources can be obtained if a VHDL

structural description is used [28], [29], particularly if specific

components are designed, instead of directly implementingplaces and transitions of the PN [30]. However, nowadays, it

TABLE III(Continued.) C PROGRAM GENERATING THE VHDL COD E

FROM THE MATRIX MODEL


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Fig. 4. PN example.

is not worth making an effort to use component-based models

because there is no problem with the number of logic elements

(LEs) that are integrated into the FPGA.

When developing HPetriNets, it was taken into account

that the monitoring and testing of the hardware-configured

application is necessary. Therefore, a VHDL file describing a

monitor and communication software module is included in

the project. This module provides information to the graphic

interface about how the implemented controller is working.

Fig. 2 shows this module in addition to its connection with the

rest of the HPetriNets elements.

Using the VHDL PN file and the VHDL monitor file, theFPGA Design Tool creates a project taking into account the

device that has been selected. The project is compiled and

analyzed, and finally, the hardware is configured.

III. IMPLEMENTATION EXAMPLE

To demonstrate an actual application of the matrix model

method described in Section II, the PN in Fig. 4 is used. The

PN representation follows the PN Standard Graphical Notation

guidelines [31]. In this example, the number of places is n =5, the number of transitions is m = 4, and the TI and TO

matrices, given by (1) and (2), are, respectively

TI=

1 0 0 0 00 1 0 0 00 0 1 0 00 0 0 1 1

TO =

0 1 1 0 00 0 0 1 00 0 0 0 11 0 0 0 0

.

Then, the matrix T (9) specifying the transitions to beactivated is calculated

T= ( t1 t2 t3 t4 ) =F& PT=F& CP TIt

T= ( f1 f2 f3 f4 ) & ( cp1 cp2 cp3 cp4 & cp5 )

T= (f1 & cp1 f2 & cp2 f3 & cp3 f4 & cp4 & cp5 ).

After that, the FTI intermediate matrix (10) and the PPmatrix (11) are obtained

FTI=F TI= ( f1 f2 f3 f4 )

1 0 0 0 00 1 0 0 00 0 1 0 00 0 0 1 1

FTI= ( f1 f2 f3 f4 f4 )

PP = CP& FTI

PP= ( cp1 cp2 cp3 cp4 cp5 ) & ( f1 f2 f3 f4 f4 )

PP= (cp1 & f1 cp2 & f2 cp3 & f3 cp4 & f4 cp5 & f4).

Now, the transition evolution matrix (12) is obtained, as

shown in the equation at the bottom of the page.

Then, the logic operation OR | between the TTO matrixand the PP matrix is carried out to obtain the next markingmatrix NP (13)

NP = TTO |PP NPt =

t4 (cp1 & f1 )

t1 (cp2 & f2 )

t1 (cp3 & f3 )

t2 (cp4 & f4 )

t3 (cp5 & f4 )

.

Therefore, the final equations to the next marking for the PN

example in Fig. 4 are the following:

np1 = t4 (cp1 & f1 ) = (f4 & cp4 & cp5 )

(cp1 & f1 )np2 = t1

(cp2 & f2 ) = (f1 & cp1 ) (cp2 & f2 )

np3 = t1 (cp3 & f3 ) = (f1 & cp1 )

(cp3 & f3 )np4 = t2

(cp4 & f4 ) = (f2 & cp2 ) (cp4 & f4 )

np5 = t3 (cp5 & f4 ) = (f3 & cp3 )

(cp5 & f4 ).Finally, the output matrix A is given by the next marking and

the output activation matrices (15)

A=NPXA= (np1 np2 np3 np4 np5 )

0 01 11 00 00 1

A= (A1 A2 ) = (np2 |np3 np2 |np5 ) .

TTO = T TO = ( t1 t2 t3 t4 )

0 1 1 0 00 0 0 1 00 0 0 0 1

1 0 0 0 0

TTO = ( t4 t1 t1 t2 t3 )

TTO = ( f4 & cp4 & cp5 f1 & cp1 f1 & cp1 f2 & cp2 f3 & cp3 )


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TABLE IVVHDL DATAFLOW DESCRIPTION OF THE PN IN FIG . 4

Thus, following the diagram in Fig. 2, the code generator,

which is carried out by the general algorithm in Table III,

provides the specific VHDL description of the PN in Fig. 4

according to the hardware structure in Fig. 1. This VHDL code

is shown in Table IV, adding the sEsynchronized inputs in theStateUpdate process to minimize the risk of race conditions.

These inputs should be evaluated to prevent PN evolution after

an RST signal is applied. From (14), this value is obtained

F& CP TIt = 0 sE. (16)

Fig. 5 presents the simulation results using the Altera

Quartus II software [32] to implement the PN example in Fig. 4,

described in VHDL according to the previously described

method. A Cyclone FPGA has been used as a target device for

the synthesis. This example uses 14 LEs, which are the minimal

resources needed to carry out a synchronous implementation.

Despite the fact that this example is not very complex, it

demonstrates the correct performance of the model description

without output deadlocks, traps, and glitches. Notice that only

one clock cycle is needed to evaluate the firing transition

conditions, to activate the new places, and to establish the new

outputs, even if several places must concurrently be activated,

such as places 2 and 3. As just one clock is used, the timespent to update the whole net is constant and independent of

Fig. 5. Simulation result using the Altera Quartus II.

its complexity. Moreover, for the same reason, if the input

signal speed is similar to the clock one, the net performance

is guaranteed because of the correct synchronization of the

different VHDL processes with the same clock event.

This fact is demonstrated in Fig. 5, showing a particular sit-

uation where the conditions to simultaneously activate several

transitions are true. When places 3 and 4 are active (cp3 andcp4) and f3 (E2 & E3) is true, place 5 is activated (cp5). Dueto the fact that f4 (E1) and f1 (E1) are true, a firing sequencethrough the whole net occurs (places 1, 2, and 3) until place 5

is activated again. This way, any possible stability problems are

avoided. After the first rising edge of the clock system following

a reset deactivation, thesEi synchronization signals in Table IVare not valued Ei signals until a rising edge of the clock, andthus, fi signals are not updated. This is only in the interim

between the end of the reset and the rising edge.At this point, it is important to highlight that all of the pre-

vious characteristics (a high-speed response to the input vari-

ations in only one clock cycle with a correct synchronization

avoiding stability problems and output glitches) can be only

achieved if an RLC is implemented instead of a PLC. Thus, the

advantages of logic controllers based on an FPGA (RLCs) over

logic controllers based on a programmable processor (PLCs)

are clearly shown.

IV. TIMERS AND COUNTERS

Time events, which consist of timers and counters, are es-sential to allow the automation of any industrial process. Thus,

any implementation of a logic controller must facilitate their

utilization. To include timers and counters, the matrix model,

described in Section II, must be modified, and the matrices that

are defined in Table V must be added. To illustrate the imple-

mentation using an FPGA, the previous example is modified

to include a timer. Similarly, the same example is modified to

illustrate what changes must be incorporated to the VHDL code

implementing a counter.

Timers and counters are not included in the PN general

theory, so it must be extended. To achieve this, a model with

a control subsystem and a data subsystem including counters

and timers is used. It is important to point out that this modelis different from the theoretical model of timed PNs [5], [6].


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TABLE VDEFINITION OF THE NEW MATRICES

Fig. 6. PN example in Fig. 4 including the TM0 timer.

A data subsystem time can be used to specify timing relations

between places or transitions in any position and not solely

between adjacent ones.

In this paper, timers are used in a way similar to that in SFC;

however, they must explicitly be triggered by means of the PN

transition pulse outputs. In the SFC methodology, every step is

associated with an elapsed time variable that can be used within

the rest of the chart to monitor step activation [33]. Counters

are used in a way similar to that in SFC; however, they must be

initialized by means of the PN transition pulse outputs.

A. Timers

Timers are triggered by means of transition pulse outputs,

which are indicated by / characters [34], instead of by specialactions associated with places [6]. The PN in Fig. 6 uses the

retriggerable TM0 timer with the /TM0 := 5 s pulse. Thetiming end is checked with TM0, equivalent to TM = 0. Dueto the fact that the hardware main clock may have differ-

ent frequencies, an appropriate frequency divisor value must

be included in the hardware constraints before the automaticVHDL code is generated. Using this information, the system

Fig. 7. Processes implementing a PN with timers.

can generate a 1-ms and/or 1-s time base, depending on thetime scale implementing the different processes.

All timers used in the PN must be triggered in such a way

that the controller only uses the essential timers without any

subsequent optimization method. This characteristic of the PN

constitutes an important difference with the SFC [33].

The basic structure of the PN description in Fig. 1 is extended

to that in Fig. 7 using the same methodology but including the

processes carrying out the timing generation. The structure in

Fig. 1 has an independent process that tests fi signals of thetransition firing conditions. These signals are combined with

the transition input place states by means of the following

equation to generate the pulses that establish the timer initial

contain (LD):

TM_LD = TXTM_LD = (F& PT) XTM_LD. (17)

It must be highlighted that the TimersUpdate process that

implements (17) depends on the fi and cpi signals, in the sameway that the StateCalc process calculates npi.

Regarding the example in Fig. 6, the load condition of the

TM0 timer is obtained by substituting (9) and the timer loading

matrix XTM_LD in (17). The following timer equation isobtained in this way:

TM_LD = ( f1 & cp1 f2 & cp2 f3 & cp3 f4 & cp4 & cp5 )

00100

TM_LD = f3 & cp3. (18)

The transition logic equation matrix (5) is now converted

into the following to add the timer output as a new controller

input:

F =E1 E3 E2 & E3 E1 & TM0

. (19)


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Fig. 9. Processes implementing a PN with the CT0 counter.

Table VII contains the VHDL code describing the PN de-

picted in Fig. 8 according to the block diagram in Fig. 9. This

code comprises two new processes, as well as the three included

in Table IV (which are slightly modified).

1) The Counter_CT# process, Counter_CT0 in this case,

is automatically added to the code when a counter is

included in the project.

2) The CountersUpdate process establishes the counters

preset value (PV) and the counters up/down value(UD).

The CountersUpdate process includes the vCT# auxiliary

variable and a call to the TC_Load procedure with the global

signal CT#_LD. Any TC_Load can modify the vCT# variable,

but only the last value is taken into account when it is stored in

the CT#_PV preset value signal (# represents 0 in this case). It

must be highlighted that this process depends on the fi and cpisignals, in accordance with

CT_LD = TXCT_LD = (F& PT) XCT_LD. (20)

The application of this equation to the example in Fig. 8 is

carried out by substituting (9) and the counter loading matrix

XCT_LD in (20). This way, the load condition of the CT0

counter given by (21), shown at the bottom of the page, isobtained.

The CountersUpdate process also uses the vCT# auxiliary

variable and calls to the TC_UpDn procedure with the global

TABLE VIIVHDL DESCRIPTION OF THE CONTROLLER INCLUDING

THE CT0 COUNTER

signal CT#_UD. Any TC_UpDn can modify the vCT# vari-

able that it is stored in the CT#_UDV up/down value signal

(# represents 0 in this case). This process depends on the fi andcpi signals, in accordance with

CT_U/D= TXCT_U/D = (F&PT)XCT_U/D . (22)

CT_LD = ( f0 & cp0 f1 & cp1 f2 & cp2 f3 & cp3 f4 & cp4 & cp5 )

10000

0

CT_LD = f0 & cp0 (21)


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The application of this equation to the example in Fig. 8 is car-

ried out by substituting (9) and the counter up/down updating

matrix XCT_U/D in (22). This way, the up/down condition ofthe CT0 counter given by (23), shown at the bottom of the page,

is obtained.

Now, the transition logic equation matrix (5) is ex-

tended to

F = (E1 E3 E2 & E3 E1 & [CT0 < 4]) (24)

to incorporate the logic condition, which depends on the value

(an integer) of the counter output CT0. This means that the

value of the counter output is handled as an input

The ConditionsCal process in Table IV is modified to in-

clude the CT# signals generating the transition firing condi-

tions. The StateCalc and StateUpdate processes in Table IV

remain unchanged, except for the associate code to the f0condition and place 0 (Fig. 8).

Each time a new loading condition for the same counter

is included in the PN, a new TC_Load code line is gener-ated because, in general, different values must be loaded. The

auxiliary variable vCT# is used to reset the CT#_PV signal

(when vCT# is 0) and to make sure that only the last value is

taken into account (as the counter is undertaken in a parallel

process). With this method, the automatic code generation is

simplified, and a possible collision is avoided when several

transitions simultaneously try to load the same counter. This

way, the robustness of the result is guaranteed if a bad design is

carried out.

The same thing does not happen when increasing/decreasing

the counter content, since several simultaneous counting ac-

tions may have to be carried out on the same counter fromdifferent transitions, as in the example in Fig. 8. Thus, the

TC_UpDn procedure, shown in Table VII, accumulates the

value, which is passed as a parameter into vCT0. It must be

observed that an OR logic function is not suitable to solve

this problem, since it is not possible to distinguish between

an independent counting and a simultaneous one. Due to this,

(23) is separated, and each term of the OR logic function

is passed as a parameter to each line generated using the

TC_UpDn procedure, as the up/down values are generally

different.

V. EXPERIMENTAL RESULTS

To validate the simulation results of the logic matrix model

and its translation to VHDL code, as described in Section II,

Fig. 10. Performance test of the PN example in Fig. 6 configuring theFPGA.

Fig. 11. Performance test of the PN example in Fig. 8 configuring theFPGA.

an actual RLC based on a Cyclone FPGA has been used

(Fig. 3).

A logic analyzer has been used to test the signals involved

in the different examples described before. The practical results

depicted in Fig. 10 correspond to the PN in Fig. 6 including the

TM0 timer.

The system starts to operate after placing the RST signal at0. When the E1 input signal is placed at 1, the f1 firingoccurs, and places 2 and 3 are activated. Following on, when

E3 is valued 1, place 4 is activated, and place 2 is deactivated,which means that places 3 and 4 are active at this moment.

When E2 and E3 are worth 1, the TM0 timer is triggered,and the system has to wait for TM0 to end. When starting the

transition in the f3 condition, the firing sequence f3, f4, f1,f2, f3 cannot happen.

Fig. 11 shows how the CT0 counter in Fig. 8 works. The

CT0_UD signal has been connected to the A3 output, only fortesting. When this signal is active and several simultaneous fires

happen, all of the operations over the counter are accumulated.Notice that when the counter value is 3 and f2 and f3 are true,the counter final value is established at 6. This is due to the

fact that it takes into account two operations: transition with f2

CT_U/D = ( f0 & cp0 f1 & cp1 f2 & cp2 f3 & cp3 f4 & cp4 & cp5 )

00110

0

CT_U/D = (f2 & cp2)|(f3 & cp3) (23)


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Fig. 12. PN example including a subnet.

increases the content by 1 and transition with f3 increases itby 2.

VI. EXTENDING THE MATRIX MODEL

TO HIERARCHICAL PNs

The complexity of many industrial processes implies that, in

general, their behavior cannot be described with just one PN

because they would be too big to be handled and understood

[36], [37]. This problem can be solved using a top-down decom-

position methodology to develop a model including subnets.

In PN literature, top-down decomposition is usually referred

to as refinement and can be defined in static or dynamicform [38]. The PNs described in this section follow the static

integration mechanism where a PN can contain another PN

model (subnet). This integration is obtained by place substi-

tution, where a place is seen as a macroplace, which can also

include other macroplaces, supporting a multilevel hierarchical

integration schema.

In this section, the matrix model described in Section II is

extended to a hierarchical PN to integrate the matrix model of

a net into another one.

Fig. 12 shows a main PN including four transitions (mH =4) and four places plus a subnet (macroplace) named LOAD

(nH = 5). The subnet is also made up of three places (nL = 3)and two transitions (mL = 2).To achieve a matrix model from the two models (one of

the main net and another of the subnet), the general matrices

TI and TO must be obtained from the specific TI and TOmatrices of each net. Then, the general equations will be solved

by applying the method described in Section II. Moreover, it is

obvious that the matrices of each net are also built following the

same method but considering the subnet included in the main

net as if it was a place. In the PN example in Fig. 12, subnet 3

(LOAD) is considered to be place 3, but a different symbol and

the name r3 is used.The procedure to obtain the general matrices of the

whole design is described next by means of the example inFig. 12.

Fig. 13. Preincidence and postincidence matrices including a subnet.

As mentioned before, the procedure starts obtaining

p1 p2 r3 p4 p5

TIH =

1 0 0 0 00 1 0 0 00 0 1 0 00 0 0 1 1

t1

t2

t3

t4p1 p2 r3 p4 p5

TOH =

0 1 1 0 00 0 0 1 00 0 0 0 11 0 0 0 1

t1

t2

t3

t4

(25)

of the main net (high level H) and

of the subnet (low level L), which have already been defined.

The TIH and TOH matrices of the main net are now extendedwith the elements of the TIL and TOL subnet matrices toobtain TIand TO global matrices using the following steps.

1) The r3 column defining the output and input connectionsto the subnet is extracted from the TIH and TOH matri-ces, respectively, of the high-level net.

2) The TIL and TOLmatrices are added to TIH and TOH,respectively, at the end position (mH+1, nH). Now, thenew matrices TI and TO of the whole net have thesuitable dimensions [(mH + mL) (nH 1 + nL)].

3) The r3 column extracted from TIH is overwritten at thelast column of the extended matrix TI (Fig. 13, r3p3

r3). The same operation is carried out with the columnextracted from TOH to complete the column nH ofTO(Fig. 13, r3p1 r3).

4) The remaining elements of the general TIand TO matri-ces are padded with 0.

At this point, the final step is to extend the general matrices

E, A, F, CP, and NP by adding the subnet matrices to the netones as follows:

E= (EH EL ) (27)

A = (AH AL ) (28)

F = (f1, f2, . . . , f mH, rf1, rf2, . . . , r f mL) (29)

CP = (cp1, cp2, . . . , c pnH,rcp1,rcp2, . . . , rcpnL) (30)NP = (np1, np2, . . . ,npnH,rnp1,rnp2, . . . , rnpnL). (31)


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Consequently, when the general matrices are obtained, the

process to achieve the final equations is the same as that shown

in Section II. Although, in this method, subnets are used as

places, they cannot have any associated action in the main net.

This is due to the fact that when the subnet state is activated,

it really corresponds with the first place in the subnet, which is

the place specifying the action that must be carried out.It is important to highlight the fact that, as the two models are

mixed into only one, the process to obtain the VHDL code from

this global model is greatly simplified because this solution

follows the general scheme in Fig. 1.

VII. CONCLUSION

Due to the flexible hardware architecture of real FPGAs,

nowadays, it is worthwhile to implement FPGA-based logic

controllers. Nevertheless, useful, robust, and economical design

methods are necessary.

This paper has described a new logic controller design and

implementation method using CIPNs and FPGA reconfigurable

integrated circuits. The presented method has provided, from

the matrix structure defining the PN, controller state equa-

tions directly synthesizable with FPGA hardware. Due to the

hardware structure implementing the controller, an optimum

running speed has been achieved because only one clock cycle

is necessary to obtain the next PN state.

This method has utilized a generic algorithm to obtain the

specific VHDL code describing each PN. Thus, the use of

VHDL templates, hiding the automation method, has been

avoided. The method has been presented through several

examples of increasing complexity including important ele-

ments such as timers and counters, being used in many logiccontrollers.

To facilitate complex logic controller management, the ma-

trix model has also been generalized to incorporate subnets,

obtaining a unique global matrix model. The results have been

validated by simulation before their practical implementation,

and the VHDL code of each example has been used to configure

an RLC based on a Cyclone FPGA. Using this method, PLC

users can implement RLCs using the same design methods,

and they do not need an in-depth knowledge of the RLC

hardware.

REFERENCES[1] J. T. Welch and J. Carletta, A direct mapping FPGA architecture for

industrial process control applications, in Proc. IEEE Int. Conf. Comput.Des., 2000, vol. 1, pp. 595598.

[2] J. M. Fernandes, M. Adamski, and A. J. Proena, VHDL generationfrom hierarchical Petri net specifications of parallel controllers, Proc.

Inst. Elect. Eng.Comput. Digit. Tech., vol. 144, no. 2, pp. 127137,Mar. 1997.

[3] M. Adamski, SFC, Petri nets and application specific logic controllers,in Proc. IEEE Int. Conf. Syst., Man, Cybern. , 1998, pp. 728733.

[4] J. Pardey and M. Bolton, Logic synthesis of synchronous parallel con-trollers, in Proc. IEEE Int. Conf. Comput. Des., 1991, pp. 454457.

[5] T. Murata, Petri nets: Properties, analysis and applications, Proc. IEEE,vol. 77, no. 4, pp. 541580, Apr. 1989.

[6] R. David and H. Alla, Discrete, Continuous and Hybrid Petri Nets.Berlin, Germany: Springer-Verlag, 2005.

[7] R. Zurawski and M. Zhou, Petri nets and industrial applications: Atutorial, IEEE Trans. Ind. Electron., vol. 41, no. 6, pp. 567583,Dec. 1994.

[8] M. Wegrzyn, M. Adamski, and J. L. Monteiro, The application of recon-figurable logic to controller design, Control Eng. Pract., vol. 6, no. 7,pp. 879887, Jul. 1998.

[9] J. J. Rodriguez-Andina, M. J. Moure, and M. D. Valdes, Features, designtools, and application domains of FPGAs, IEEE Trans. Ind. Electron.,vol. 54, no. 4, pp. 18101823, Aug. 2007.

[10] E. Monmasson and M. N. Cirstea, FPGA design methodology for in-dustrial control systemsA review, IEEE Trans. Ind. Electron., vol. 54,

no. 4, pp. 18241842, Aug. 2007.[11] A. Wegrzyn and M. Wegrzyn, Petri net-based specification, analysis andsynthesis of logic controllers, in Proc. IEEE Int. Symp. Ind. Electron.,2000, pp. 2026.

[12] M. Adamski, Reconfigurable logic controller for embedded applica-tions, in Proc. 3rd IFAC Workshop Discrete-Event Syst. Des., 2006,pp. 147152.

[13] S. Ichikawa, M. Akinaka, R. Ikeda, and H. Yamamoto, Converting PLCinstruction sequence into logic circuit: A preliminary study, in Proc.

IEEE Int. Symp. Ind. Electron., 2006, pp. 29302935.[14] C. Johnson, M. Hales, and R. Harris, Programmable controller with sub-

phase clocking scheme, U.S. Patent 6 981 167 B2, Dec. 27, 2005.[15] C. F. Silva, C. Quintns, E. Mandado, and M. A. Castro, Methodology

to implement logic controllers with reconfigurable and programmablehardware, in Proc. IEEE Int. Symp. Ind. Electron., 2007, pp. 324328.

[16] IEEE Standard VHDL Language Reference Manual, IEEE Std. 1076-2002, 2002.

[17] J. Biesenack, M. Koster, A. Langmaier, S. Ledeux, S. Marz, M. Payer,M. Pilsl, S. Rumler, H. Soukup, N. Wehn, and P. Duzy, The Siemenshigh-level synthesis system CALLAS, IEEE Trans. Very Large Scale

Integr. (VLSI) Syst., vol. 1, no. 3, pp. 244252, Sep. 1993.[18] M. Adamski and J. L. Monteiro, From interpreted Petri net specification

to reprogrammable logic controller design, in Proc. IEEE Int. Symp. Ind.Electron., 2000, pp. 1319.

[19] C. Quintns, C. F. Silva, and E. Mandado, Synthesis of parallel con-trollers through a logic matrix model, in Proc. 3rd IFAC Workshop

Discrete-Event Syst. Des., 2006, pp. 179184.[20] T. Kozlowski, E. L. Dagless, J. M. Saul, M. Adamski, and J. Szajna,

Parallel controller synthesis using Petri nets, Proc. Inst. Elect. Eng.-Comput. Digit. Tech., vol. 142, no. 4, pp. 263271, Jul. 1995.

[21] D. A. Tacconi and F. L. Lewis, A new matrix model for discrete eventsystems: Application to simulation, IEEE Control Syst. Mag., vol. 17,no. 5, pp. 6271, Oct. 1997.

[22] Altera, Inc. (2005). Cyclone device handbook. San Jose, CA. [Online].Available: http://www.altera.com[23] L. Gomes, On conflict resolution in Petri nets models through

model structuring and composition, in Proc. 3rd IEEE Int. Conf. Ind.Electron., 2005, pp. 489494.

[24] L. Gomes, J. P. Barros, A. Costa, and R. Nunes, The input-outputplace-transition Petri net class, in Proc. IEEE Int. Conf. Ind. Informat.,Jun. 2007, vol. 1, pp. 509514.

[25] S. Klein, G. Frey, and M. Minas, PLC programming with signal in-terpreted Petri nets, in Proc. ICATPN, Eindhoven, The Netherlands,Jun. 2003, vol. 2679, pp. 440449.

[26] L. Gniewek and J. Kluska, Hardware implementation of fuzzy Petri netas a controller, IEEE Trans. Syst., Man, Cybern. B, Cybern., vol. 34,no. 3, pp. 13151324, Jun. 2004.

[27] C. F. Silva, C. Quintns, J. M. Lago, and E. Mandado, An integratedsystem for logic controller implementation using FPGAs, in Proc. IEEE

Ind. Electron. Conf., 2006, pp. 195200.

[28] E. Soto and S. Pereira, Implementing a Petri net specification in a FPGAusing VHDL, in Proc. DESDes, 2001, pp. 1924.

[29] D. Andreu, G. Souquet, and T. Gil, Petri net based rapid prototyping ofdigital complex system, in Proc. IEEE Comput. Soc. Annu. Symp. VLSI,2008, pp. 405410.

[30] M. Uzam, M. Avci, and M. K. Yalcin, Digital hardware implementationof Petri net based specifications: Direct translation from save automationPetri nets to circuit elements, in Proc. DESDes, 2001, pp. 2533.

[31] Software and systems engineeringHigh-level Petri nets, Part 1: Con-cepts, definitions and graphical notation, Int. Std. ISO/IEC 15909,Dec. 2004.

[32] Altera, Inc., Quartus-II Web Edition, San Jose, CA, 2006. [Online].Available: http://www.altera.com

[33] R. W. Lewis, Programming Industrial Control Systems Using IEC 1131-3.Stevenage, U.K.: Inst. Elect. Eng., 1998, ser. IEE Control EngineeringSeries.

[34] M. Silva and S. Velilla, Programmable logic controllers and Petri nets:A comparative study, in Proc. 3rd IFAC/IFIP Symp. Softw. Comput.Control, 1982, pp. 2934.


13/13


[35] M. Zamora, H. Wu, and M. P. Henry, An FPGA implementation offrequency output, IEEE Trans. Ind. Electron., vol. 56, no. 3, pp. 648653, Mar. 2009.

[36] M. Wegrzyn and M. Adamski, Hierarchical approach for design of appli-cation specific logic controller, in Proc. IEEE Int. Symp. Ind. Electron.,1999, pp. 13891394.

[37] R. J. Machado, J. M. Fernandes, and A. J. Proena, Specification ofindustrial digital controllers with object-oriented Petri nets, in Proc.

IEEE Int. Symp. Ind. Electron., 1997, pp. 7883.[38] L. Gomes and J. P. Barros, Structuring and composability issues inPetri nets modeling, IEEE Trans. Ind. Informat., vol. 1, no. 2, pp. 112123, May 2005.

Celso F. Silva received the Industrial Engineeringdegree from the University of Vigo, Vigo, Spain,in 1987.

Since 1987, he has been a Researcher and anElectrical and Computer Engineering Educator withthe Department of System Engineering and Automa-tion, University of Vigo. His research interests are inprogrammable control systems. He is a coauthor ofbooks about programmable logic controllers, includ-ing Autmatas Programables y Sistemas de Autom-atizacin (Barcelona, Spain: Marcombo, 2009) with

two editions.

Camilo Quintns (M05) received the B.S. degreein electrical engineering from the University of Vigo,Vigo, Spain, in 1997, the M.S. degree and the Ph.D.degree in electrical engineering from the SpanishUniversity for Distance Education (UNED), Madrid,Spain, in 2005 and 2008, respectively.

From 1997 to 2001, he was in the industrial elec-tronics field, particularly in electrical power gener-ation. Since 2000, he has been a Researcher andan Assistant Professor with the Department of Elec-tronic Technology, University of Vigo. His research

interests are in analog and digital mixed circuits applied to instrumentation andcontrol systems.

Antonio Colmenar received the Industrial Engineer-ing degree and the Dr.Eng. degree from the EscuelaTcnica Superior de Ingenieros Industriales/SpanishUniversity for Distance Education (UNED), Madrid,Spain.

He is an Electrical and Computer EngineeringEducator with the Electrical and Computer Engi-neering Department, Spanish University for DistanceEducation. He worked for 14 years in different levelsof education in Spain and Nicaragua. He was aResearcher on various projects, ranging from solar

power systems to distance learning systems. He has published various technicalbooks and articles in journals and conference proceedings.

Dr. Colmenar is a member of the Association for the Advancement of

Computing in Education (AAEC) and the Spanish group of the InternationalSolar Energy Society (ISES).

Manuel A. Castro (M87SM93F08) receivedthe Industrial Engineering degree and the Ph.D. de-gree in engineering from the Escuela Tcnica Su-perior de Ingenieros Industriales/Madrid PolytechnicUniversity, Madrid, Spain.

He is an Electrical and Computer EngineeringEducator with the Spanish University for DistanceEducation (UNED), Madrid, Spain. For five years,

he was with in the Digital Equipment Corporation,Madrid, Spain,as a SeniorSystems Engineer. He wasa Researcher in different projects, ranging from solar

power system and advanced microprocessor system simulation to telematicsand distance learning systems, acting now as a Senior Technical Coordinator.He served as UNEDs New Technologies Vice Rector, Information ServicesCenter Director, Research Vice Director, and Academic Affairs Vice Directorof the Engineering School, acting now as Head of the Electrical and ComputerEngineering Department. He has published various technical books and articlesin journals and conference proceedings. His research interests focus on sys-tem applications of simulation techniques, distance learning applications, andcomputer-aided electrical engineering.

Dr. Castro is a member of the IEEE Education Society AdministrativeCommittee (20052010) and the Founder of the Spanish Chapter of the IEEEEducation Society. He is a Board Member of the Spanish International SolarEnergy Society Committee.

Enrique Mandado (S68M69LM09) receivedthe B.S. degree in electronic engineering from thePolytechnic University of Madrid, Madrid, Spain,in 1969 and the Ph.D. degree from the PolytechnicUniversity of Barcelona, Barcelona, Spain, in 1976.

From 1969 to 1978, he was an Electronic Appli-cation Engineer with Miniwatt (Philips), Barcelona,Spain. In 1979, he joined the University of Vigo,Vigo, Spain, where he is currently a Full Professor ofelectronics with the Department of Electronic Tech-nology and the Director of the Institute for Applied

Electronics, developing electronic systems for control and measurement. Heis the author or a coauthor of ten books about electronics, including Pro-grammable Logic Controllers and Logic Devices (London, U.K.: Prentice-Hall,1996), Sistemas Electrnicos Digitales (Barcelona, Spain: Marcombo, 2008)

with nine editions, and Autmatas Programables y Sistemas de Automatizacin(Barcelona, Spain: Marcombo, 2009).

silva_2010_petri_net - a method based on petri nets and a matrix model to implement reconfigurable...

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