IEEE Communications Magazine • March 201372 0163-6804/13/$25.00 © 2013 IEEE

NEW TRENDS INSYSTEM COMPONENTS

Recently, the technique of system in package(SiP), in which a number of integrated circuitchips are enclosed in a single package, has beenused for reducing size and supporting multiplefunctions. This has brought a number of benefitssuch as the shortening of development periodsand the reduction of development costs com-pared to the technique of system on chip (SOC).Furthermore, using SiP, the integration of CPUswith various types of memory can easily be real-ized in one package, whereas with SOC tech-nologies it is difficult to integrate CPUs withflash memory or DRAM.

Similar to SiP, it is expected that on-chip serv-er technology will become a reality around 2020.Each component in the on-chip server willbecome progressively miniaturized and offerhigher performance than present ones. The cur-rent trend in electronic system components is adownsizing of their footprint by utilizing three-dimensional (3D) packages [1]. For example, 3D

technology by through silicon via (TSV) has beensuccessfully introduced for memories. In proces-sor technology, multicore technology has beenintroduced, and both many-core and 3D many-core technology will be introduced in the nearfuture. In storage technology, solid state drives(SSDs) are emerging as a key storage deviceinstead of hard disc drives (HDDs). SSDs will befurther enhanced in the future as 3D-SSDs. Ourultimate goal is to realize the on-chip server (aminiaturized sever-board in a single chip) in thenear future.

The required throughputs per distance ofvarious interconnects are shown in Fig. 1. Inthe figure, the current chip-to-chip intercon-nections are shown as solid line boxes; most ofthese interconnections are performed electron-ically. However, after the implementation ofthe various expected technological advances(challenges for semiconductors), the intercon-nections require much faster speeds (as shownin the dashed line box). These high-speed con-nections are required to realize an on-chipserver. In the following section we provide amore detailed discussion on each type of inter-connection.

In processor technology, core-to-core com-munication will be enhanced from multicore tomany-core communications (more than 16cores). Since each core operates at speeds ofseveral tens of gigabits per second, an intra-chipinterconnect will have to be able to handlespeeds of several hundred gigabits per second,or terabits per second in total (proportional tothe number of cores). The photonic interconnec-tion will achieve such ultra-high speeds becauseits signal propagation mechanism is completelydifferent from the electrical one and will notcause any signal interference (crosstalk) orpower consumption problems [2].

For memory technology, memories will bestacked in a 3D manner (3D-MEM). While 10Gb/s per each signal line is considered to be theupper bound for an electrical interconnect, amuch faster interconnect technology (propor-tional to the number of memory stacks in 3D-MEM) will be required for the advanced system.While each memory device may not achieve the

ABSTRACT

New semiconductor technologies such asmany-core processors and 3D memories arebeing researched in order to overcome the limi-tations of electronics in the near future. Here,we first discuss some drawbacks of current tech-nologies, and then show that silicon photonicswill solve those interconnection problems. Next,we describe our studies toward realizing a sys-tem integration platform based on photonics andelectronics convergence, and show that an opti-cal interposer is the most efficient way to copewith the various problems that a purely electron-ic system may encounter. Our recent advances insilicon photonic devices are also described, andtheir integration into the hybrid interposer isreported through an early prototyping result.Finally, a surface mounted components approachfor silicon photonics technology is discussed,which may prove useful in the computer andcommunication markets.

NEW PARADIGMS INOPTICAL COMMUNICATIONS AND NETWORKS

Yasuhiko Arakawa, The University of Tokyo

Takahiro Nakamura, Yutaka Urino and Tomoyuki Fujita, PETRA

Silicon Photonics for Next GenerationSystem Integration Platform

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IEEE Communications Magazine • March 2013 73

top speed, an advanced pipelining mechanismbased on photonic interconnection will achievethe expected performance for consecutive mem-ory access of large-volume data.

For storage technology, the change fromHDD to SSD will allow for the integration ofmuch smaller memory components, and furtherfacilitate substantially higher performance andmuch lower power consumption. Terabytes ofstorage will be mounted on a chip as a 3D-SSDin the near future.

For off-chip peripheral components, PCI-Express for data communication and DisplayPort for raw data communication are the keyinterfaces to the system. Both will require muchfaster interconnects to cope with, for example,increased image resolution provided by SuperHiVision class monitors and cameras. Peripheralinterfaces are similar to the memory interfaces,but operate at much longer connection dis-tances. If the various peripheral components canconnect via the same optical interface, the num-ber of interface cables will be reduced to a mini-mum.

Finally, for server-to-server communication,EXA-scale computing, where thousands of pro-cessors communicate with each other in a veryquick manner, will require terabit-per-secondclass interconnections.

From the above discussions, it is clear thatsuch 3D technologies will demand interconnect-ing throughputs almost proportional to the num-ber of stacks. Indeed, the throughput ofinterconnects will increase rapidly to speeds thatare several tens/hundreds of times as high as theones that are presently used.

The high throughputs of these interconnectswill further demand an increase in pin densityand data transfer rate. This will be very difficultto realize with electrical connections, due tolimitations imposed on speed, density, andpower. Therefore, in order to overcome thelimits of electronics, the interconnects forfuture on-chip servers will be achieved in anoptical manner.

Silicon photonics has recently become a sub-ject of intense interest because it offers variousinterconnect solutions for low cost, low powerconsumption, high bandwidth, and high density.Although there have been many optical linkdemonstrations [3–6], there are no high-densitysystems integrated with light sources on a singlesilicon chip without our activities [7].

PHOTONICS-ELECTRONICSCONVERGENCE SYSTEM FORINTERCHIP INTERCONNECTS

In order to develop the interconnects for futureon-chip servers, in Japan, Photonics and Elec-tronics Convergence System Technology(PECST) project was started in March 2010, asone of the 30 Funding Program for World Lead-ing Innovative R&D on Science and Technology(FIRST) projects supported by the Council forScience and Technology Policy in the CabinetOffice. This project is being carried out for fouryears, and involves the University of Tokyo,

PETRA, and Advanced Industrial Science andTechnology (AIST). PECST aims to establish achip-to-chip interconnect technology with abandwidth density of 10 Tb/s/cm2. In addition,innovative photonic devices based on nanotech-nology, such as quantum dot lasers on silicon,are explored.

Figure 2 shows our proposed on-chip serverthat may be realized in the 2020s. A many-coreCPU, 3D-memory, and 3D-SSD are integratedon a silicon optical interposer supporting terabit-per-second-class optical interconnects among thecomponents.

In this section, we describe the fabrication ofthe photonics-electronics convergence system forrealizing the on-chip servers. There are threemain points to be considered in order to opti-mally exploit the interface between electronicsand photonics:• The physical structure for combining pho-

tonics and electronics circuits• The laser source arrangement• The method of mounting the large-scale

integrations (LSIs) on the interposerBasically, these three issues will dominate theoperating speed, size, temperature dependence,and crosstalk of the device.

The cross-section of a silicon optical inter-poser is shown in Fig. 2. The silicon opticalinterposer is formed as follows. Optical splitters,optical modulators, and PDs are monolithicallyintegrated on a silicon substrate, arrayed laserdiodes (LDs) are integrated on the substrate asa hybrid structure, and these optical compo-nents are optically linked to each other via sili-con optical waveguides. A many-core CPU,3D-MEM, and 3D-SSD are mounted on theoptical interposer by flip-chip bonding, and areelectrically connected to the optical modulatorsand PDs.

As shown in Fig. 2, the on-chip server ismounted on a printed circuit board (PCB) forelectrical connection. High-speed optical signalsfor inter-server interconnects are directly trans-mitted to or received from the optical fibers.Low-speed electric interconnects to the PCB andelectric power supply are performed throughTSVs.

Figure 1. Trends of chip-to-chip throughput as afunction of interconnection distance in current(solid boxes) and future (dashed boxes).

1/Distance (m–1)

110–2

1

0.1

Band

wid

th (

Gb/

s)

10

100

10210–1 10–1 103

CPU-CPU(ManyCore)

CPU-CPU(MultiCore)

Inter-Chipconnection

Inter-Chip(high-speed)

3D-Meminterface

High-speedperipheralinterface

Memoryinterface

Peripheralinterface

Electricalinterconnection

Optical

interconnection

It is clear that such

3D technologies will

demand intercon-

necting throughputs

almost proportional

to the number of

stacks. Indeed, the

throughput of inter-

connects will

increase rapidly to

speeds that are sev-

eral tens/hundreds of

times as high as the

ones that are

presently used.

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IEEE Communications Magazine • March 201374

INTEGRATION STRUCTURE

Three types of layered sandwich structure arefeasible for the implementation of integratingphotonic and electronic circuits: front-end inte-gration, back-end integration, and flip-chipbonding. The first two are monolithic integra-tions, and the third is a hybrid integration. Thehybrid integration allows us to choose the mostsuitable technology nodes separately for bothphotonics and electronics circuits, which enablesus to design, fabricate, and test them separatelybefore combining them. On the other hand,monolithic integration, especially front-end inte-gration, is expected to provide higher speeds anda lower assembly cost than hybrid integration,but requires very strict complementary metaloxide semiconductor (CMOS) compatibilities interms of design, fabrication, and testing.

In our project, hybrid integration is applied toa SiP substrate, and monolithic integration isapplied to electrical-to-optical (E/O) or optical-to-electrical (O/E) conversion for an ultra-high-speedinterface to special devices such as the 3D-MEM.

LIGHT SOURCE INTEGRATIONIn order to minimize the total length (and hencelosses) of waveguide lines on the interposer, theon-chip sources can be located near the modula-tors, where all the modulators must be connect-ed to one of the light sources.

In our case, butt-coupled lasers are integrat-ed on silicon substrate of silicon-on-insulator(SOI) with a passive alignment technique [8] toprovide enough optical output power for powersplitting and facilitate heat dissipation for high-temperature operation.

MOUNTING LSIS ON AN INTERPOSER

The LSI mount stage on the surface of the inter-poser is designed as shown in Fig. 3 [7]. BareLSI chips are mounted on the interposer and areelectrically connected to the optical modulatorsand photo detectors (PDs) by flip-chip bonding.That is, electric circuits (the bare LSI chips) andphotonic circuits (the optical interposer) areintegrated as a hybrid structure.

The inter-chip interconnects/silicon opticalinterposers operate as follows. Arrayed LDs aredriven simultaneously by DC current, and thecontinuous waveform (CW) light from each LDis divided by an optical splitter and launchedinto an optical modulator. The optical modula-tors are directly driven by transmitter circuits inone LSI. The modulated optical signals propa-gate along inter-chip optical waveguides and aredetected by PDs under other LSIs. The electricalsignals from those PDs input to receiver circuitsin the LSI above the PDs.

This system enables us to replace the con-ventional electronic wires on a printed circuitboard (PCB) with the optical interconnects on asilicon substrate, which are 100th of the size(i.e., from a 30 ¥ 30 cm2 board to a 3 ¥ 3 cm2

chip). This silicon optical interposer has widebandwidth capabilities due to the properties ofthe optical signals. Since the silicon substratescan be fabricated using a CMOS-compatibleprocess, they have quite high density and arelow in cost to manufacture. Furthermore,because this system is optically complete andclosed without any optical inputs or outputs,users do not have to worry about any opticalissues, such as optical coupling, reflection, orpolarization dependence.

Figure 2. On-chip server.

Cross-sectional view

Processor interconnectionmulti-core ⇒ many-core

Memory interconnectionflat-mem ⇒ 3D-mem

Storage interconnectionHDD ⇒ 3D-SSD

Semiconductorchallenges

Peripheral interconnectionHDMI ⇒ super HiVision

Server interconnection⇒ EXA-scale computing

3D-SSD

3D-MEM

Arrayed LD Many-coreCPU

Gephotodetector

Si opticalmodulator

3D-MEM

On-chip server @ 2022

Siliconoptical

interposer

Si waveguide

TSV

PCB BGA

Cache

Many-core CPU

2 inch

19 inch

Server board @ 2012

Three types of lay-

ered sandwich struc-

ture are feasible for

the implementation

of integrating pho-

tonic and electronic

circuits: front-end

integration, back-end

integration, and flip-

chip bonding. The

first two are mono-

lithic integrations,

and the third is a

hybrid integration.

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IEEE Communications Magazine • March 2013 75

FABRICATION OFSILICON OPTICAL INTERPOSERS

The silicon optical interposers were fabricatedfrom SOI wafers by CMOS process technology.The silicon optical waveguides were formed byelectron beam lithography and dry etching, andthe epitaxial germanium mesas for the PDs wereselectively grown on the silicon waveguides bychemical vapor deposition. The waveguides,modulators, and PDs were then covered with theSiO2 upper cladding layer by chemical vapordeposition. The waveguide end faces and thepedestals for the LD mount were formed by dryetching before an arrayed LD chip was integrat-ed on the substrate with a passive alignmenttechnique [8].

Optical components for the interposer in SiPare required to be temperature independent dueto their positioning near the LSIs. Furthermore,for the small and highly efficient O/E or E/Oconverters, it is important to design the struc-tures that have strong interaction between theoptical field and electrical carriers.

For realizing optical modulators with bothsmall size and high efficiency, the interactionbetween the optical field and the electrical carri-ers is maximized by strong confinement of them.Therefore, we chose to implement a channelwaveguide with large optical confinement, andformed a side-wall grating along the waveguidefor carrier injection and confinement, as shown inFig. 4a [9]. This waveguide structure generally hasthe trade-off between waveguide loss and opera-tion speed. The grating pitch should be carefullydesigned so that the wavelength of the input lightwould be outside the stop-band formed on thespectrum. Furthermore, we applied a Mach-Zehnder interferometer for both temperature-and wavelength-independent operation.

For the Germanium (Ge) photodiodes, weused a PIN structure as shown in Fig. 4b [10].The thickness of Ge was optimized for effective-ly applying electric fields to carriers produced bylight absorption. This enabled us to realize effi-cient optical absorption with a small (less than30 mm long) Ge mesa.

Figure 4c shows a photograph of the fabricat-ed silicon optical interposer on a 5 mm ¥ 5 mmsubstrate. An SSC array, a 1 ¥ 4 optical splitter,an optical modulator array, and a PD array wereall monolithically integrated onto a single siliconsubstrate. A 13-channel arrayed LD chip was

Figure 3. Mounting LSIs on an interposer.

Silicon opticalwaveguides

LSI bare chip

LSI b

are

chipFlip-chip

padsfor LSI

LSI

LSILSI

Silicon optical interposer

8-ch opticaltransmitterarray

1 x 8-splitter

8-ch modulatorarray

: 8-ch PD array

Signals from neighbor LSI Signals to neighbor LSI

CW lightform LD

8-ch opticalreceiver array

Arrayed LD chip

ArrayedLD chip

LSI

Platform forLD mount

Figure 4. Fabrication of a silicon optical interposer: a) modulator; b) photo detector; c) photograph of asilicon optical interposer.

Aluminumelectrode

Siliconwaveguide

(c)

(a)

AI

SiO2

AI

n+ P+SiBox

MMIcoupler

(b)

Ge

n+-GeMetal

p-Si

Si

5 mm

5 m

m

1 x 4 splitter

Optical waveguide array

Arrayed LD Modulator array

SSC array

PD array

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IEEE Communications Magazine • March 201376

integrated onto the substrate as a hybrid struc-ture, and these optical components were optical-ly linked to each other via the silicon opticalwaveguide array.

The measured eye data of the PD output onthe silicon optical interposer at 12.5 Gb/s non-return to zero (NRZ) with a 27 – 1 pseudo-ran-dom binary sequence (PRBS) via the 1 ¥ 4optical splitter is shown in the inset of Fig. 5.The clear eye opening suggests that the opticallinks were capable of data transmission at 12.5Gb/s. The measured bit error rates (BERs) forthe 12.5 Gb/s PRBS are plotted in Fig. 5. Weconfirmed that the BER was less than 10–12

when the PD input power was more than –10.8dBm. Error-free transmission at 12.5 Gb/s viathe 1 ¥ 4 optical splitter was therefore success-fully achieved.

The total footprint was 0.19 mm2 per chan-nel, meaning that we could achieve a bandwidth

density of 6.6 Tb/s/cm2 with a channel line rateof 12.5 Gb/s. We note here that about two-thirdsof the total footprint was actually occupied bythe electrode pads, and we can expect to improvethe bandwidth density further by using smallerpads in the near future.

The overall inter-chip bandwidth for high-endservers is expected to reach around the 10 Tb/slevel by the late 2010s [2]. The typical CPU diesize will be about 1–2 cm2 (related to the yieldsor the costs), and therefore, a bandwidth densityof around 10 Tb/s/cm2 will be required by thelate 2010s for chip-to-chip interconnects.

Figure 6 shows the throughput of varioustypes of optical modules against their inversearea. In general, interconnects for shorter dis-tance have smaller footprints and wider band-widths (i.e., higher bandwidth densities). Fromthis figure, we can see that 10 Tb/s/cm2 is per-haps a reasonable target for chip-to-chip inter-connects in a high-end server application.

SILICON PHOTONICS AS SURFACEMOUNTED COMPONENTS

A set of surface mounted components has beenenvisaged and designed to be used by systemengineers without deep knowledge of photonicstechnology (Fig. 7). The three components aredesigned to provide photonic interconnectionseamlessly.

The first is a micro active optical cable(AOC), which will connect any point on theboard (with an electrical interface) to anotherpoint using a connector size of 5 mm2, muchsmaller than a conventional AOC. Inside theconnector, small high-speed silicon photonic cir-cuits, operating at 25 Gb/s to 40 Gb/s, provideE/O and O/E interfaces. The micro AOC willachieve throughputs of 200 Gb/s to 1 Tb/s percable.

Second, an LSI mounted hybrid AOC willprovide optical and electrical interconnection.The component provides high-frequency signallines through optical fiber ribbons as well aselectronic wiring connection in low speed. Whenwe apply a field programmable gate array(FPGA) or graphic processing unit (GPU) as anLSI, this approach will behave like a specialaccelerator for image processing, pattern recog-nition, object understanding, and so on.

Third, the on-chip server will provide highspeed, low power, and a very small footprint byutilizing both photonics and electronics. Thephotonics interconnection will reduce the totalpower consumption of the server by more than30 per cent as our target, since the photonicswiring will reduce the power consumption gener-ated by electrical wiring.

CONCLUSIONWe have discussed recent advances in semicon-ductor technology and the subsequent require-ments that future chip-to-chip interconnectionsshould exhibit speeds 10 times higher than thoseused today. To meet those requirements, a pho-tonics-electronics convergence system with a sili-con optical interposer has been proposed to

Figure 5. Bit error rates for 12.5 Gb/s NRZ PRBS with eye diagram.

PD input power (dBm)-15

10-12

10-13

Bit

erro

r ra

te

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-10 -5

12.5 Gb/s27-1 PRBS

Figure 6. Bandwidth per area for interconnection modules.

1/module area (cm-2)0.10.01

10

1

Band

wid

th (

Gb/

s)

100

1000

1 10

Packaging densityavailable to realizeinterposer

10 Tb/s interconnectionto LSI bare chip1 Gb/s/cm 2

10 Gb/s/cm 2

100 Gb/s/cm 2

1 Tb/s/cm 2

10 Tb/s/cm 2

Inter-boards

Chip-to-chip

Interposer

Commercially

available

Under R&D

LAN-WAN

Inter-racks

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IEEE Communications Magazine • March 2013 77

solve the bandwidth bottleneck problem thatchip-to-chip electronic interconnects have. Keytechnologies for the integration and develop-ment of the photonic devices are described.

A fabricated prototype device employing ahigh-density optical interposer using silicon pho-tonics integrated with these optical componentson a single silicon substrate was described andshown to demonstrate error-free data transmis-sion at 12.5 Gb/s and a bandwidth density of 6.6Tb/s/cm2.

Finally, a surface mounted componentsapproach was introduced so that a system engi-neer without special photonics knowledge couldutilize the system.

ACKNOWLEDGMENTSThis research is partly supported by the CabinetOffice through its Funding Program for World-Leading Innovative R&D on Science and Tech-nology (FIRST) Program, and partly supportedby the Ministry of Economy, Trade and Industrythrough its Future Pioneering Project.

REFERENCES[1] R. Jammy, “Evolution of Device Technologies and Revo-

lution needed in Manufacturing,” Int’l. Symp. Semicon-ductor Manufacturing ’12, Tokyo, Japan.

[2] I. A. Young et al., “Optical Technology for Energy Effi-cient I/O in High Performance Computing,” IEEE Com-mun. Mag., vol. 48, no. 10, Oct. 2010, pp.184-91.

[3] P. D. Dobbelaere et al., “Si Photonics Based High-SpeedOptical Transceivers,“ ECOC ’12, We.1.E.5, 2012.

[4] S. Assefa et al., “A 90 nm CMOS Integrated Nano-Pho-tonics Technology for 25 Gb/s WDM Optical Communi-cations Applications,” IEEE IEDM ’12, 33.8, 2012.

[5] X. Zheng et al., “2-pJ/bit (On-Chip) 10-Gb/s DigitalCMOS Silicon Photonic Link,” IEEE Photonics Technolo-gy Letters, vol. 24, no. 14, 2012, p. 1260.

[6] A. Alduino, “Demonstration of a High Speed 4-ChannelIntegrated Silicon Photonics WDM Link with Hybrid Sili-con Lasers,” Hot Chips 22, Session 3, 2010.

[7] Y. Urino et al., “First Demonstration of High Density OpticalInterconnects Integrated with Lasers, Optical Modulatorsand Photodetectors on Single Silicon substrate,” Opt. Exp.,vol.19, no.26, B159-B165, Dec. 2011.

[8] N. Fujioka, T. Chu, and M. Ishizaka, “Compact and LowPower Consumption Hybrid Integrated WavelengthTunable Laser Module Using Silicon Waveguide Res-onators,” IEEE J. Lightwave Tech., vol. 28, no. 21, Nov.2010, pp. 3115–20.

[9] S. Akiyama et al., “12.5-Gb/s Operation with 0.29-V•cmVpL Using Silicon Mach-Zehnder Modulator Based onForward-Biased Pin Diode,” Opt. Exp., vol. 20, no. 3,Jan. 2012, pp. 2911–23.

[10] J. Fujikata et al., “45 GHz Bandwidth of Si Waveguide-Integrated PIN Ge Photodiode, and Its Zero-Bias Volt-age Operation,” Proc. Int’l. Conf. Solid State Devicesand Materials, A-7-3, Sept. 2012.

BIOGRAPHIESYASUHIKO ARAKAWA [F] (arakawa@iis.u-tokyo.ac. jp)received his B.S., M.S., and Ph.D. degrees in electronicsand electrical engineering from the University of Tokyo in1975, 1977, and 1980, respectively. In 1980, he joinedthe University of Tokyo as an assistant professor andbecame a full professor in 1993. He is currently thedirector of the Center for Photonics Electronics Conver-gence (CPEC), Institute of Industrial Science, and also the

director of the Institute for Nano Quantum InformationElectronics (Nano Quine), University of Tokyo. He is amember of the Science Council of Japan, a Vice Presidentof ICO, the Asian Regional Editor in Chief of NJP, and amember of the Joint APL-JAP Editorial Board. He hasbeen made a Fellow of OSA, JSAP, and IEICE. His majorresearch fields include physics, growth, and photonicsapplications of the quantum dot. He is leading a nationalproject named Photonics and Electronics ConvergenceSystem Technology (PECST) of the FIRST program. He hasreceived several major awards including the Leo EsakiAward (2004), the IEEE/LEOS William Streifer Award(2004), the Fujiwara Award (2007), the Prime MinisterAward (2007), the Medal with Purple Ribbon (2009), theIEEE David Sarnoff Award (2009), the C&C Award (2010),the Welker Award (2011), and the OSA Nick Holonyak Jr.Award (2011).

TAKAHIRO NAKAMURA (t-nakamura@petra-jp.org) receivedB.E., M.E., and D.E. degrees in electrical engineering fromOsaka University, Japan in 1986, 1988, and 2005, respec-tively. He joined NEC Corporation in 1988, where he hasbeen engaged in the research and development of laserdiodes. He is currently a temorary chief manager in PETRA.He is a member of the IEICE.

YUTAKA URINO (y-urino@petra-jp.org) received his B.E.degree in communication engineering and M.E. degree inelectronic engineering from Tohoku University, Japan, in1985 and 1987, respectively. He joined NEC Corporation,where he has been engaged in the research and develop-ment of optical waveguide device subsystems. He is cur-rently a temporary chief researcher at PETRA. He is amember of the IEICE.

TOMOYUKI FUJITA [M] (t-fujita@petra-jp.org) received his B.E.and M.E. degrees in electronics and communication engi-neering from Waseda University, Japan, in 1976 and 1978,respectively. He joined NEC Corporation in 1978 as aresearcher of computer aided design and became aresearch manager in 1989. He was a visiting researcher atthe University of California at Berkeley in 1983 through1984. He was a director of the planning office at NEC Cen-tral Research Labs in 1999 and a deputy managing directorof NEC China Labs in Beijing in 2003. He has been an exec-utive director of PETRA since 2009. He is a member of theIEICE and IPSJ.

Figure 7. Surface mounted components for photonic interconnection.

μ-AOCActive optical cablewith small connectors(20 m ~ 10 cm)

LSI mounted hybrid AOCHigh speed signals are connected through optical cables (fiber ribbons)(50 cm ~ 5 cm)

On-chip serverPhotonics and electronics convergedSi interposer with many-core, 3D-MEM and 3D-SSD.(50 cm ~ 5 mm)

(Year)(2025)(2020)(2015)

1000100101

1/Distance (m-1)

100

10

1

0.1

0.01

Band

wid

th d

ensi

ty (

Tb/s

/cm

2 )

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