signal process in fpga.pdf

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Design and FPGA Implementation of Sequential

Digital FIR Filter using Microprogrammed Controller

Syed Manzoor Qasim, Mohammed S. BenSaleh, Mazen Bahaidarah, Hesham AlObaisi

King Abdulaziz City for Science and Technology

National Center for Electronics, Communications and

Photonics, Micro Sensors and Devices Division

Riyadh, Saudi Arabia

Tariq AlSharif, Mosab AlZahrani and Hani AlOnazi†

King Abdulaziz University/

†King Saud University

Department of Electrical and Computer Engineering†Department of Electrical Engineering

College of Engineering

Jeddah/†Riyadh, Saudi Arabia

Abstract —Digital finite impulse response (FIR) filters play a

very important role in digital signal processing (DSP)

applications ranging from image and video processing to

wireless communication. Digital FIR filter is primarily

composed of multipliers, adders and delay elements. Several

techniques have been reported in the open literature to

implement digital FIR filters using Field Programmable Gate

Array (FPGA). This paper also presents an FPGA

implementation of FIR filter but using a novel

microprogrammed controller based design approach. The

proposed controller controls the sequence of operation of the

filter. To demonstrate the technique, design of a sequential 4-tap

digital FIR filter based on the microprogrammed controller is

presented. The proposed FIR filter is coded in VHDL using

modular design approach and implemented in Spartan-3E

FPGA. Performance evaluation is done based on the

implementation results obtained through Xilinx ISE tool.

I. I NTRODUCTION

Digital finite impulse response (FIR) filters are the basic building block of many digital signal processing (DSP)systems. FIR Filters are used due to their stability and linear phase properties. The main objectives of digital FIR filter areto filter out undesirable parts of the signal, shape the spectrumof signals in communication channels, signal detection or analysis in radar applications. Adders, multipliers and delayelements are the main components used in the implementationof digital FIR filters. These components are arranged andinterconnected in different ways based on the architecture of the FIR filter [1].

FIR filter performs a linear convolution on a window of N data samples which can be mathematically expressed asfollows:

∑−

=

−⋅=

1

0

)()()( N

k

k n xk hn y (1)

A direct form implementation of an FIR filter can bereadily developed from the convolution sum as shown in fig.1.

Figure 1. Direct form FIR filter architecture

Direct form FIR filters are also known as tapped delay line or transversal filters. N-tap FIR filter consists of N delayelements, N multipliers and N-1 adders or accumulators. Theimpulse response of the FIR filter can be directly inferredfrom the tap coefficients hk .

Several techniques for the implementation of digital FIR using Field Programmable Gate Array (FPGA) have been

reported in the open literature [2-4]. The objective of this paper is to demonstrate a novel microprogrammed controller [5-7] based technique using an example of sequential 4-tapdigital FIR filter.

The rest of the paper is organized into four sections. Thedatapath and microprogrammed controller architecture of the

proposed FIR filter are discussed in section II and IIIrespectively. FPGA implementation and simulation results are

presented in section IV. Finally, section V presents theconcluding remarks and some recommendations for futurework.

II. DATAPATH ARCHITECTURE

The proposed FIR filter architecture comprises of twomain building blocks which are datapath unit and control unit.The block diagram of the 4-tap sequential FIR filter with theintegrated datapath and control unit is shown in fig. 2. Fig. 3illustrates the datapath design of 4-tap FIR filter. The datapatharchitecture consists of the following sub modules: four 8-bit

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Figure 2. Block Diagram of FIR filter

Figure 3. Datapath architecture

data registers, one 2-to-4 decoder, four 8-bit coefficientregisters (wo, w1, w2, w3), two 4:1 multiplexers which are usedas data selectors, single multiplier and 16-bit adder, one 2:1

multiplexer to control the flow of data from multiplier or accumulator, 16-bit accumulator and 16-bit register to latchthe output [8]. Each sub modules are coded in VHDL andfinally integrated to obtain the complete datapath. The controlsignals generated by the microprogrammed controller for thisdatapath are fed to different sub modules for proper operationof the FIR filter.

III. MICROPROGRAMMED CONTROLLER

There are several methods to design the controller, such ashardwired controller and microprogrammed controller. In this

Figure 4. Microprogrammed Controller

paper, we used microprogrammed controller to organize theoperation of FIR filter. The most important advantage of themicroprogrammed controller is its flexibility to add or modify

by simply changing the microprogram in the ROM basedcontrol memory [9-10]. This makes the design of larger tapFIR filter much easier.

As shown in fig. 4, microprogrammed controller consistsof two main parts. The first part is responsible for addressingmicroinstructions kept in the control memory and the second

part is used to hold and generate microinstructions for thedatapath unit. The sequence of operations listed in table I isfollowed to generate the output for the sequential FIR filter

architecture. The control signals generated by themicroprogrammed controller are listed in table I. The tapcoefficient registers (w0, w1, w2, w3) are loaded with data basedon load enable (LE) signal and the decoder output signals(Ld1 and Ld0). After loading the input data in the firstregister, the input data is multiplied and accumulated based onthe select signals (S1 and S0), product select (Ps) and loadaccumulator (lacc) signals.

TABLE I. CONTROL SIGNALS

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The filtered output data is available only after the outputlatch (YL) signal is asserted high. The process is continued for the remaining registers only after the data move (Dm) signal isasserted high.

IV. FPGA IMPLEMENTATION A ND SIMULATION R ESULTS

The sequential FIR filter is designed and simulated using

VHDL. To implement the proposed architecture, Spartan-3E(xc3s500e-4fg320) FPGA device is used. For the synthesis,translation, mapping and place-and-route processes, XilinxISE 12.2 webpack is used. Different reports are generated bythe tools. A summary of the results generated by the tool issummarized in FPGA device utilization table II. Themaximum operating frequency of the designed FIR filter is119.775 MHz and consumes a small area out of the entireFPGA real estate leaving plenty of room for implementingother parallel processors [11]. The RTL view generated by thetool is shown in fig. 5 which clearly shows the integration of the datapath with the control unit.

TABLE II. FPGA DEVICE UTILIZATION

Figure 5. Integration of Datapath and Control unit (RTL View)

TABLE III. SIMULATION TEST CASES FOR 4-TAP FIR FILTER

Test No. Tap Coefficients (W) Input Data (X) Output Data (Y)

1 {1, 2, 2, 1} {1, 2, 3, 3} {1, 4, 9, 14}

2 {3, 6, 6, 5} {2, 10, 3, 3} {6, 42, 81, 97}

3 {5, 4, 4, 1} {3, 9, 7, 7} {15, 57, 83, 102}

Figure 6. Simulation snapshot of datapath unit for test case no. 1



Three different test data are used for testing the designedcircuit. The filter taps are chosen randomly with an objectiveto provide something that is observable at the output. Thesetaps could be changed depending on the requirement of the

application [12]. The functionality of the FIR filter is verifiedthrough simulation using Xilinx ISE built-in simulator.

Fig. 6, 7 and 8 shows the simulation waveform of thedatapath which verifies the three test cases listed in table IIIrespectively. Fig. 9 presents a snapshot of simulation resultsfor the microprogrammed controller. Finally, the datapath andmicroprogrammed controller are integrated together todemonstrate the simulation results of 4 tap FIR filter for eachtest case. Fig. 10, 11 and 12 depicts the simulation waveformsof the top level FIR filter for each case respectively.

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Figure 9. Simulation snapshot of microprogrammed controller

Figure 10. Simulation snapshot of FIR filter for test case no. 1



V. CONCLUSIONS

In this paper, we have presented a design of 4-tap FIR filter using microprogrammed controller and its FPGAimplementation. The microprogrammed controller is used for controlling the operation of digital FIR filter. A sequentialarchitecture utilizing single multiplier and adder along withother building blocks are used to demonstrate the proposedtechnique. Performance evaluation is done by synthesizingand implementing the design in target Spartan-3E FPGA usingXilinx ISE XST synthesis tool.

The maximum operating frequency of the designed FIR filter is 119.775 MHz which is much greater than the systemclock frequency (50 MHz) of the used board and consumes asmall area out of the entire FPGA real estate leaving plenty of room for implementing other parallel processors. Since thesize of the FIR filter presented in the paper is small, the resultsare not that significant, however, for larger tap FIR filters,these results would be significant.

Future work would concentrate on developing anequivalent parallel architecture of the FIR filter, extending thetap size of the FIR filter architectures, applying optimizationtechniques such as pipelining and comparing both thearchitectures for speed, area and power.

ACKNOWLEDGMENT

The authors gratefully acknowledge the financial support provided by the National Center for Electronics,Communications and Photonics, King Abdulaziz City for Science and Technology (KACST) under the Ejaz project(IRU No. 31/513).

R EFERENCES

[1] S. A. Khan, Digital Design of Signal Processing Systems: A practical approach, John Wiley and Sons, United Kingdom, 2011.

[2] U. Meyer-Baese, G. Botella, D. E. T. Romero and Martin Kumm,“Optimization of high speed pipelining in FPGA-based FIR filter design using genetic algorithm,” Proc. of SPIE , Vol. 8401, 2012.

[3] Y. Zhou and P. Shi, “Distributed Arithmetic for FIR Filter implementation on FPGA,” Proc. of IEEE Intl. Conf. on MultimediaTechnology (ICMT’2011), Hangzhou, China, pp. 294-297, July 2011.

[4] F. Nekoei, Y. S. Kavian and O. Strobel, “Some schemes of realizationdigital FIR filters on FPGA for communication applications,” Proc. of 20th Intl. Crimean Conference on Microwave and TelecommunicationTechnology (CriMiCo’2010), Crimea, Ukraine, pp.616-619, Sept. 2010.

[5] B. W. Bomar, “Implementation of microprogrammed control in

FPGAs,” IEEE Transaction on Industrial Electronics, Vol. 49, No. 2, pp. 415-422, Apr. 2002.

[6] A. Barkalov and L. Titarenko, Logic synthesis for Compositonal Micro- program Control Units, Springer, Berlin: Germany, 2008.

[7] R. Wiśniewski, A. Barkalov, L. Titarenko and W. Halang, “Design of microprogrammed controllers to be implemented in FPGAs,” Intl.

Journal of Applied Mathematics and Computer Science, Vol. 21, No. 2, pp. 401-412, June 2011.

[8] M. Rafiquzzaman, Fundamentals of Digital Logic and Microcomputer Design, John Wiley and Sons Inc., 5th Edition, New Jersey: USA,2005.

[9] A. A. Barkalov, L. A. Titarenko and K. N. Efimenko, “Optimization of circuits of compositional microprogram control units implemented onFPGA,” Cybernetics and Systems Analysis,Vol. 47, No. 1, pp. 166-174,2011.

[10] R. Wisniewski, M. Wisniewska, M. Wegrzyn and N. Marranghello,

“Design of microprogrammed controllers with address converter implemented on programmable systems with embedded memories,”

Proc. of 9th IEEE East-West Design and Test Symposium(EWDTS’2011), Gora, Poland, pp.123-126, Sept. 2011.

[11] D. Amos, A. Lesea and R. Richter, FPGA-based prototyping methodology manual: Best practices in design-for-prototyping ,Synopsys Press, USA, Feb. 2011.

[12] N. Mukherjee, J. Rajski and J. Tyszer, “Testing schemes for FIR filter structures,” IEEE Transactions on Computers, Vol. 50, No. 7, pp. 674-688, July 2001.

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