Short Channel Effects in MOSFET

Defination

• A MOSFET device is considered to be short when the channel length is the same order of magnitude as the depletion-layer widths of the source and drain junction In general, visible when L ~ 1μm and below

• As the channel length L is reduced to increase both the operation speed and the number of components per chip, the so-called short-channel effects arise.

• The class of effects that alter device behavior that arise from device miniaturization - short-channel effects.

What happens as L is decreased……

• Threshold voltage variation with channel length• Drain-induced barrier lowering (DIBL)• Mobility degradation • Velocity saturation• Channel-length modulation• Hot carrier effects

– Impact ionization near the drain– Gate oxide charging– Punch-through

Thresold voltage variation

• Region under the gate is relatively small due to the area covered by the source and drain regions.

• Even with VGS=0, part of channel is already depleted

• The close proximity of the source and drain regions causes a fraction of the bulk charge density under the channel

• Both the gate and source–drain voltages share control of the bulk charge density below the gate - charge-sharing model.

• As the channel length decreases, a larger fraction of the bulk charge under the channel has field lines terminated at the source and the drain junctions.

• A lower gate voltage is required to attain threshold in a short-channel device.

• The total charge below the gate controlled by the gate voltage in a short-channel device is correspondingly less than that controlled by the gate in a long-channel device

• As channel length L decreases, threshold voltage decreases.

The smaller the L, the greater percentage of charge balanced by the S/D pn junctions

Less gate charge is required to reach inversioni.e. |VT | decreases

Drain-induced barrier lowering

• The current flow in the channel depends on creating and sustaining an inversion layer on the surface.

• If the gate bias voltage is not sufficient to invert the surface (VGS<VT0), the electrons in the channel face a potential barrier that blocks the flow.

• The potential barrier is controlled by both the gate-to-source voltage VGS and the drain-to-source voltage VDS.

• If the drain voltage is increased, the potential barrier in the channel decreases – DIBL

• The reduction of the potential barrier eventually allows electron flow between the source and the drain, even if the gate-to-source voltage is lower than the threshold voltage.

• The channel current that flows under this conditions (VGS<VT0) is called the sub-threshold current. Hence the subthreshold current increases.

• Raising the drain potential increases the drain junction depletion region, reducing threshold voltage furthermore.

Mobility degradation

• Inversion layer charge is induced by a vertical field.

• A positive gate voltage produces force on the electrons in the inversion layer towards the drain are attracted to the surface, but then are repelled by localized columbic forces - Surface scattering

• Surface scattering effect reduces mobility. As VGS increases, surface mobility decreases

• Increase in the gate control reduces the insulator layer thickness under the gate. – increase in the gate current

• As the channel length becomes smaller, the electric field component Ey increases, causes reduction of the mobility.

• The reduction in the surface mobility can be modeled as

• where is the mobility at the

threshold voltage and is the

mobility reduction factor.

Velocity saturation• As channel length is reduced, the electric field increases

(if voltage is constant)

• When a strong enough electric field is applied, the carrier velocity in the semiconductor reaches a maximum value. When this happens, the semiconductor is said to be in a state of velocity saturation. The Velocity is,

• At that point, the carrier velocity

no longer increases because the

carriers lose energy by emitting

photons as soon as the carrier

energy is large enough to do so.

cd EE

Ev

/1

• Electron drift velocity Vd is

proportional to electric field

is true only for values of ξ

less than 1.5V/μm.

• When the electric field reaches a critical value ΕC, (1.5×10-6 V/m for p-type silicon) the velocity of the carriers tends to saturate (105 m/s for silicon)

• IDsat is proportional to VGS-VTn rather than (VGS-VTn)2

• VDsat is lower than for long-channel MOSFET. VDsat < VGS-VT so the device enters saturation before VDS reaches VGS-VT and operates more often in saturation

Channel-length modulation• Channel-length modulation arises from the shortening of

the effective channel length of the transistor because of the increase in the drain depletion region as the drain voltage is increased.

• Pinch-off point for inversion channel moves to left with higher VDS shortening effective channel length.

• The effect of channel-length modulation on the drain current can be modeled as

• Where L is the original channel length, ▲L the difference in the channel length, and I0 the original drain current.

• As ▲L increases, the drain current increases. This results in an output conductance defined as the nonzero slope of the drain current versus drain voltage for the device.

• ID increases (slightly) with increasing VDS in the saturation region of operation.

Hot Carrier effects

• If the drain–source voltage is sufficiently high, impact ionization of the carriers near the drain can occur.

• When a high voltage applied at the drain, results in very high electric fields near the drain, which accelerate channel carriers into the drain's depletion region.

• The acceleration of the channel carriers causes them to collide with Si lattice atoms, creating dislodged electron-hole pairs in the process.  This phenomenon is known as Impact ionization.

• If the electric field strength near the drain exceeds the minimum needed to induce impact ionization, carrier multiplication can become appreciable.

• The generated electrons are swept into the drain region, increasing the drain–source current, while the generated holes are swept into the substrate – hot electrons.

• The injected holes within the substrate increase the net positive charge within the p-type substrate. Thus, creating a forward-biased p-n junction.

• The net result is a further increase in the drain current

• The very high source–drain electric field heats the carriers to very high kinetic energy near the drain.

• The electrons in an n-channel device, can be heated to sufficient kinetic energy such that they can transfer from the semiconductor channel into the gate oxide.

• Electrons trapped in the gate oxide creates a fixed charge that increases the threshold voltage of NMOS.

• For an electron to become hot an

electric field of 104 V/cm is necessary.

Gate oxide charging

Punch Through• Punch-through arises when the channel length is very

small.

• The source and drain depletion regions can touch, resulting in a large increase in the drain current.

• For very large Vds, the drain n+-p junction is reversed biased, resulting in an appreciable depletion region formed at the junction.

• The two depletion regions formed

at the source and drain contacts

will touch if the source-to-drain

separation is made small enough.

rj

Ws WD

L++V

De-rj

Punch through

• Linear dependence on VGS in short-channel device

• Short-channel device has ~ 40% less current at high VDS

Summary• List of short-channel effects:

– Threshold voltage variation with channel length– As channel length L decreases, threshold voltage decreases.

– Drain-induced barrier lowering (DIBL)– Drain voltage affects Vth

– Mobility degradation with vertical field– Large Vgs leads to more carrier scattering and reduced mobility

– Velocity saturation– Mobility of carriers begins to drop as electric fields increase above

1V/um

– Hot carrier effects– High lateral electric fields cause “hot” carriers which may hit Si

atoms near drain at high speeds creating impact ionisation (causing substrate and gate currents).

Thank You