September 2003September 2003

ODYSSEY:ODYSSEY:Toward Object-Oriented Toward Object-Oriented

System-Level DesignSystem-Level Design

Maziar GoudarziMaziar Goudarzi

Department of Computer EngineeringDepartment of Computer Engineering

Sharif University of Technology, I.R.IranSharif University of Technology, I.R.Iran

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OutlineOutline

• Part 1– The ConceptsPart 1– The Concepts– IntroductionIntroduction– MotivationMotivation– The ODYSSEY Thesis (The OO-ASIP)The ODYSSEY Thesis (The OO-ASIP)– OO-ASIP Life CycleOO-ASIP Life Cycle– The Approach & ConsequencesThe Approach & Consequences

• Part 2– The detailsPart 2– The details– OO-ASIP Design FlowOO-ASIP Design Flow– OO-ASIP ArchitectureOO-ASIP Architecture

33

IntroductionIntroduction

• The need to higher The need to higher abstraction levelsabstraction levels– The design The design

productivity gapproductivity gap– Tighter time-to-Tighter time-to-

marketmarketSource : Synopsys

44

Introduction (cont’d)Introduction (cont’d)

• Approaches to System-Level DesignApproaches to System-Level Design– Extend hardware design methodologiesExtend hardware design methodologies– Extend software design methodologiesExtend software design methodologies– Use HW/SW-neutral or mathematical modelsUse HW/SW-neutral or mathematical models

• Software accounts for 80% of embedded Software accounts for 80% of embedded system development cost. [ITRS-2001]system development cost. [ITRS-2001]

Object-Oriented Design MethodologyObject-Oriented Design Methodologyis one of the answersis one of the answers

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MotivationMotivation

• OO MethodologyOO Methodology– Incremental Incremental

evolution modelevolution model– Addresses Addresses

design-effort reusedesign-effort reuse

• ASIP is replacing ASIP is replacing ASICASIC– ASIP addresses ASIP addresses

hardware reusehardware reuse

We wish to correspondWe wish to correspondthe low-level reuse method (ASIP) to the low-level reuse method (ASIP) to

the high-level one (OO)the high-level one (OO)

66

Motivation Motivation

• ObservationObservation– The The class libraryclass library has the central role in has the central role in

an OO model an OO model – The methods of the class library are the The methods of the class library are the

only allowed operationsonly allowed operations

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The ODYSSEY ThesisThe ODYSSEY Thesis

We decide the We decide the instruction-setinstruction-set of the ASIPof the ASIPto be the to be the methodsmethods of the class library of the class library

We also implement We also implement polymorphismpolymorphism as an as anOO-specific abstraction OO-specific abstraction (but it means more than that)(but it means more than that)

ODYSSEYODYSSEY calls such an ASIP an calls such an ASIP an OO-ASIPOO-ASIP

88

The ODYSSEY Thesis The ODYSSEY Thesis (cont’d)(cont’d)

• OO-ASIP corresponding only to OO-ASIP corresponding only to int/float classes int/float classes A traditional A traditional processor processor – Advantage: Leverage processor design Advantage: Leverage processor design

knowledge to design efficient OO-ASIPsknowledge to design efficient OO-ASIPs– Disadvantage: basically sequentialDisadvantage: basically sequential

•VLIW, multithreading, superscalar, or other VLIW, multithreading, superscalar, or other known approaches could have been usedknown approaches could have been used

•We preferred multiprocessor architectureWe preferred multiprocessor architecture

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The ODYSSEY Thesis The ODYSSEY Thesis (cont’d)(cont’d)

• The OO-ASIP is the chip building The OO-ASIP is the chip building blockblock– Each OO-ASIP implements an arbitrary Each OO-ASIP implements an arbitrary

number of objects of the corresponding number of objects of the corresponding class library and their interactionsclass library and their interactions

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The ODYSSEY Thesis (cont’d)The ODYSSEY Thesis (cont’d)The ultimate goalThe ultimate goal

• The ODYSSEY target The ODYSSEY target chip: chip: FPGA-like array ofFPGA-like array ofOO-ASIPs OO-ASIPs

• Interconnection:Interconnection:– Packet-routing networkPacket-routing network– Motivation: Motivation:

• Network-on-Chip viewed Network-on-Chip viewed as future paradigm in as future paradigm in DSM technologiesDSM technologies

ODYSSEYSystem-Synthesiser

On-Chip network of OO-ASIPs

OO-ASIP1

OO-ASIP3

OO-ASIP2

Processor

router

router

OO-ASIP4 Processorrouter

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OO-ASIP Life CycleOO-ASIP Life Cycle

• Initial PhaseInitial Phase– Initial class library is givenInitial class library is given

• The OO-ASIP is synthesised The OO-ASIP is synthesised

• The OO-ASIP is programmedThe OO-ASIP is programmed

• Middle PhaseMiddle Phase– The class library growsThe class library grows

• New methods as software for the OO-ASIPNew methods as software for the OO-ASIP

• Final PhaseFinal Phase– Next-generation OO-ASIP is designedNext-generation OO-ASIP is designed

• New methods implemented as the OO-ASIP New methods implemented as the OO-ASIP instructionsinstructions

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Initial Phase:Initial Phase:Synthesising the OO-ASIPSynthesising the OO-ASIP

• Initial class library is givenInitial class library is given– The OO-ASIP design flow The OO-ASIP design flow – The OO-ASIP architectureThe OO-ASIP architecture– Both discussed in Part 2Both discussed in Part 2

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Middle Phase:Middle Phase:Augmenting the class libraryAugmenting the class library

• New classes introducedNew classes introduced– New attributesNew attributes

•Only more space in data memoryOnly more space in data memory

– New behavioursNew behaviours•Redefinition of old methods: e.g. E::f()Redefinition of old methods: e.g. E::f()

– Still use the old opcode of Still use the old opcode of A::fA::f– OO-ASIP despatches calls to either HW (old) or OO-ASIP despatches calls to either HW (old) or

SW (new) implementationsSW (new) implementations

•Brand-new methods: e.g. E::m()Brand-new methods: e.g. E::m()– Software (indirect) calls: Software (indirect) calls: call E::mcall E::m

A

D B

f()h()

f()g()

k()

E f()m()

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Final Phase:Final Phase:Next-Generation OO-ASIPNext-Generation OO-ASIP

• Software methods introduced in Middle Software methods introduced in Middle PhasePhase– Additional functionality with lower performanceAdditional functionality with lower performance

• New hardware manufacturing cycleNew hardware manufacturing cycle– Implement suitable extensions as hardware Implement suitable extensions as hardware

FUsFUs– Higher performanceHigher performance– Backward compatibilityBackward compatibility

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Direct Consequences of Direct Consequences of the OO-ASIP Approachthe OO-ASIP Approach

• HW Patching through SWHW Patching through SW– Dynamic binding supportedDynamic binding supported

•SW methods can override out-dated or buggy HW SW methods can override out-dated or buggy HW methodsmethods

• HW/SW Co-designHW/SW Co-design– Partitioning quantum is the class methodsPartitioning quantum is the class methods

•Partitioning hinted by the designer and his Partitioning hinted by the designer and his intuition intuition

– Rapid design-space exploration possible with Rapid design-space exploration possible with OO-ASIP synthesiser and programmer toolsOO-ASIP synthesiser and programmer tools

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The OO-ASIP ArchitectureThe OO-ASIP Architecture

• Each class method is expected to do a Each class method is expected to do a complex taskcomplex task– One One Functional Unit (FU)Functional Unit (FU) per OO-ASIP per OO-ASIP

instruction instruction – FU DesignFU Design

•Bottom-up: Enodia® Technology architectureBottom-up: Enodia® Technology architecture– Patent by “Silicon Infusion Co.” UK startup Patent by “Silicon Infusion Co.” UK startup

•Top-down: Synthesise FUs from method Top-down: Synthesise FUs from method definitionsdefinitions

– Our approach: leverage behavioural synthesis Our approach: leverage behavioural synthesis technologytechnology

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ConsequencesConsequences

• Results of FU-based OO-ASIP Results of FU-based OO-ASIP ArchitectureArchitecture– Dynamic Power ManagementDynamic Power Management

•Clock-gating for each FUClock-gating for each FU

•All FUs switched off unless invokedAll FUs switched off unless invoked

– Implementation on Reconfigurable Implementation on Reconfigurable Computing PlatformsComputing Platforms•All FUs off the platform unless invokedAll FUs off the platform unless invoked

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Consequences (cont’d)Consequences (cont’d)

• For a system of For a system of NN objects objects– One extreme point:One extreme point:

•One OO-ASIP per object One OO-ASIP per object ODETTE Approach ODETTE Approach

– Second extreme point:Second extreme point:•One OO-ASIP for all objects One OO-ASIP for all objects

To implement a system of To implement a system of NN objects, objects, the optimum point is (usually) somewhere the optimum point is (usually) somewhere

between the two extremes.between the two extremes.

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OutlineOutline

• Part 1– The ConceptsPart 1– The Concepts– IntroductionIntroduction– MotivationMotivation– The ODYSSEY Thesis (The OO-ASIP)The ODYSSEY Thesis (The OO-ASIP)– OO-ASIP Life CycleOO-ASIP Life Cycle– The Approach & ConsequencesThe Approach & Consequences

• Part 2– The detailsPart 2– The details– OO-ASIP Design FlowOO-ASIP Design Flow– OO-ASIP ArchitectureOO-ASIP Architecture

2020

OO-ASIP Design ElementsOO-ASIP Design Elements

Software

Application

SW Model Object

Instantiation

SystemClass Lib.

A

D B

f()h()

f()g()h()

k()

HardwareClass Lib.

DD BB

CSoftwareClass Lib.

ASIP Programming

Path

C++

Hardware

ASIP Hardware

ASIP Synthesis Path

SystemC (C++)

ASIP ISA: f, g, k

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OO-ASIP Design FlowOO-ASIP Design Flow

OO-ASIP Design Flow

Disciplined Benchmarking

Hardware Class lib.

OO-ASIP Synthesis

The OO-ASIP

(OO-ASIP, HW Class Lib.)

Database

OO-System Development Flow

Choose suitable class lib.

HW class lib.

Model+verify the App.

Compile toward the ASIPOO-ASIP

Data memory Instr. memory

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Inside Black Box 1:Inside Black Box 1:OO-ASIP SynthesisOO-ASIP Synthesis

HardwareClass lib.

HW Methods Definitions in C++

Functional-Unit (FU)

OO-ASIP

Invariant Templatesin SystemC

Customised OO-ASIP

Behavioural SynthesisSynopsys SystemC Compiler

Gate-level OO-ASIP

GNU C++ Compiler

Exec. modelto validate

Customised FUs

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Inside Black Box 2: Inside Black Box 2: Model & Verify the ApplicationModel & Verify the Application

HW class lib.C++

Augment to match application needs

Software class lib.

System class lib.C++

GNU C++ Compiler

Executable for functional validation

OO model of the application

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Inside Black Box 3: Inside Black Box 3: Compile toward the OO-ASIPCompile toward the OO-ASIP

• Software compilationSoftware compilation– Simply substituting method calls with Simply substituting method calls with

OO-ASIP instructionsOO-ASIP instructions– Retargettable compiler required for all OO-ASIPsRetargettable compiler required for all OO-ASIPs

class A {class A {

void f(int){…}void f(int){…}

}; };

main() {main() {

A a; A a; allocate space and id for ‘a’ allocate space and id for ‘a’

a.f(1); a.f(1); generate generate <A::f opcode, ‘a’ id, 1><A::f opcode, ‘a’ id, 1>

}}

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OutlineOutline

• Part 1– The ConceptsPart 1– The Concepts– IntroductionIntroduction– MotivationMotivation– The ODYSSEY Thesis (The OO-ASIP)The ODYSSEY Thesis (The OO-ASIP)– OO-ASIP Life CycleOO-ASIP Life Cycle– The Approach & ConsequencesThe Approach & Consequences

• Part 2– The detailsPart 2– The details– OO-ASIP Design FlowOO-ASIP Design Flow

– OO-ASIP ArchitectureOO-ASIP Architecture

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OO-ASIP ArchitectureOO-ASIP Architecture

• Just a sample architectureJust a sample architecture– Leverage processor architecture Leverage processor architecture

knowledge to propose other solutionsknowledge to propose other solutions

• The sample architectureThe sample architecture– One FU per OO-ASIP instructionOne FU per OO-ASIP instruction– Store objects data in memoryStore objects data in memory

•The The Object Management Unit (OMU)Object Management Unit (OMU) distributes them to FUsdistributes them to FUs

– Per FU coherent caches for accelerationPer FU coherent caches for acceleration

– A virtual-method dispatching solutionA virtual-method dispatching solution

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OO-ASIP Architecture:OO-ASIP Architecture:Centralised method dispatcher Centralised method dispatcher

• The (virtual) method dispatcherThe (virtual) method dispatcher– The The Method Invocation Unit (MIU)Method Invocation Unit (MIU)

•Reads instructions (method invocation Reads instructions (method invocation commands)commands)

•Resolves the called method to an FU or Resolves the called method to an FU or softwaresoftware

– Object-Type Table (OTT): shows class of all Object-Type Table (OTT): shows class of all objectsobjects

– Virtual-Method Table (VMT): the same as in C++Virtual-Method Table (VMT): the same as in C++

• Invokes the FU or calls the software routineInvokes the FU or calls the software routine

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OO-ASIP Architecture:OO-ASIP Architecture:Centralised method dispatcher Centralised method dispatcher (cont’d)(cont’d)

Data Memory

a

b1

d

aaa2

ddd1

b1b1b

Instruction Memory

ap->f()

a2.h()

d1.g()

A-introducedmethods

D-introduced methods

B-introduced methods

MIU

OTTVMT

A

D B

f()h()

f()g()

k()

OO-ASIP Hardware

OMU

cache

cache

cache

FunctionalUnits

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OO-ASIP Architecture:OO-ASIP Architecture:Distributed method dispatcherDistributed method dispatcher

• MIU is good, but MIU is good, but – CentralisedCentralised– Not scalableNot scalable– Area, time, and power overheadArea, time, and power overhead

• Need for a distributed, scalable, Need for a distributed, scalable, overhead free solutionoverhead free solution– Unify Unify method dispatchmethod dispatch with with inherent inherent

network routingnetwork routing in the NoC paradigm in the NoC paradigm

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OO-ASIP Architecture:OO-ASIP Architecture:Distributed method dispatcher Distributed method dispatcher (cont’d)(cont’d)• FU-identifier:FU-identifier:

FU=<method.class>FU=<method.class>

• Object-identifier:Object-identifier:object=<class.num>object=<class.num>

• Method call = invoke a Method call = invoke a methodmethod on an on an objectobject<method.object> = <method.<class.num>> <method.object> = <method.<class.num>> = <<method.class>.num> = <FU.num> = <<method.class>.num> = <FU.num> = = Packet destined to the node addressed Packet destined to the node addressed FUFU

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OO-ASIP Architecture:OO-ASIP Architecture:Distributed method dispatcher Distributed method dispatcher (cont’d)(cont’d)• To dynamically bind a method call To dynamically bind a method call

(e.g. (e.g. objp->method(params)objp->method(params) in C++) in C++)

1.1.Assemble a packet asAssemble a packet as<method, objp, params><method, objp, params>

2.2.Send it over the on-chip networkSend it over the on-chip network

3.3.The (probable) return value is sent back The (probable) return value is sent back as another packetas another packet

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OO-ASIP Architecture:OO-ASIP Architecture:Distributed method dispatcher Distributed method dispatcher (cont’d)(cont’d)

Data Memory

a

b1

d

aaa2

ddd1

b1b1b

Instruction Memory

bp->f()

b2.h()

d3.f()

A-introducedmethods

D-introduced methods

B-introduced methods

OO-ASIP Hardware

OMU

cache

cache

cache

FunctionalUnits

On-ch

ip

Netw

ork

Instruction Memory

ap->f()

a2.h()

d1.g()

Processor 2

Processor 1cache

cache

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Thanks + Q&AThanks + Q&A

• ODYSSEY web pageODYSSEY web page– http://www.cl.cam.ac.uk/users/mg342/odysseyhttp://www.cl.cam.ac.uk/users/mg342/odyssey

• Some Discussion TopicsSome Discussion Topics– What else needed in the ODYSSEY What else needed in the ODYSSEY

thesis?thesis?– Language for the concurrent OO model?Language for the concurrent OO model?– Interesting case studiesInteresting case studies– Suitable tool chainsSuitable tool chains