self biased high performance folded cascode cmos opamp

7/27/2019 Self Biased High Performance Folded Cascode Cmos Opamp

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A Self-Biased High Performance Folded Cascode CMOS Op-AmpPradip [email protected] .in

Electrical Comm. Engg. Dept.Indian Institute of ScienceBangalore-560012, India

AbstractCascode CMOS op-amps use a large number of ex-ternal bias voltages. This results in numerou s draw-backs, namely, an area and power overhead, suscepti-blity of the bias lines to noise and cross-talk and high

sensi tivity of the bias poin t to process variation s. Inthis paper we present a self-biasing technique fo r foldedcascode CMOS op-amps that uses no additional de-vices and no baas voltages other than the two supplyrails. The resulting self-biased op-amps are free fromthe above mentioned drawbacks and exhibit the sameperformance as existing folded casode op-amps, exceptfor a small d u c t i o n in s lew rate. This is achieved byfollowing trans istor sizing constraints derived throughdetailed circuit analysis. The technique i s applied to anexisting high performance op-amp. Simulation resultsshow that the high performance is maintained whilenine bias voltages are eliminated.

1. IntroductionIn a wide variety of applications such as A/D con-

verters [l] nd switched-capacitor filters [2], speed andaccuracy are determined by the settling behavior of th eopamps. The settling speed depends on the unity gainfrequency and a single pole settling behavior whereashigh settling accuracy requires high d.c. gain of theopamps.

Folded cascode opamps have the important prop-erty of single pole settling behavior yith a large unitygain frequency. But a simple folded cascode opampfails to provide high gain which is required for high set-tl ii g accuracy. To overcome this limitation, the gainboosting technique introduced by Hosticka [3]has beenapplied for a folded cascode opamp [4].But a majordrawback of this gain boosted o pa mp is that it needsa number of external bias voltages [5 ] .

V. [email protected] inSupercomputer Edn. and Res. CentreIndian Institute of ScienceBangalore- 560012 , India

In an andog circuit dif'ferent active devices should beproperly biased to get high performance. For instance,most of the transistors in a CMOS op-amp should bebiased in the saturation region of operation. Usually aseparate bias circuit is used to bias the transistors inan op-amp. The main disadvantage of using a separatebias circuit is that it requires long wires for broadcast-ing the bias voltages from the bias circuit to the mainopamp circuit. These wires not only consume a con-siderable amount of area but, what is worse, are alsosusceptible to noise and cross talk. As has been ob-served in [5], the requirement of a large number of biasvoltages m,ay limit the use of gain boosted folded cas-code opamps.

There have been some efforts to overcome this bi-asing problem of op-amps. In [6] self-biased CMOSop-amps are proposed. 13ut some of the transistors inthese self-biased opamps are biased in the linear regionof operation which causes drastic reduction of someimportant a.c. performances, like gain, CMRR andPSRR. n 171 a self-biased transistor like circuit block,called super MOS transistor, is introduced. This superMOS transistor can be u s e d to construct a folded cas-code op-amp to get very high performance. But eachone of the super MOS circuit blocks consists of asmanyas 12 transistors.

We propose a CMOS opamp self-biasing techniquewhich, witlhout any extra devices, keeps all the tran-sistors in tlhe saturation region of operation. This self-biasing technique is used to bias a very high perfor-mance folded cascode op-amp which has 100 dB gainand 100MHz unity gain frequency. The self-biased op-amp requires only the two supply rails, Vdd and Vs8.Thus, the area and power overhead of biasing is elimi-nated. Further, the operating point is less sensitive toprocess variations, since in this approach the bias pointis determined by size ratios only. While self-biasinghas a number of performance advantages, the cost is asmall sacrifice in slew rate. This slew rate reduction is

4290-8186-775549605.000 1996 EEE Idh ntemutionulConfierence on VLSI Design -January 1997


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Figure 1 . Externally biased folded cascodeop-amp

Figure 2. Self-biased folded cascode op-amp

analytically predicted and minimined.The paper is organized as follows. Section 2 deals

with a self-biased fully complementary folded cascodeopamp. In the same section we present the designanalysis of the op am p and we compare the perfor-mance of the o pa mp with an externally biased opamp.The analysis that is provided is used to pick the tran-sistor sizes so that all devices are biased in saturationand the slew rate is high. Section 3 discusses the self-biasing of a very high performance opamp. Simulationresults are given in Section4.Section 5 summarizes hework.2. Self-Biasing of Folded Cascode Op-

AmpsIn this section we describe the self-biasing technique

by applying it to the fully complementary folded cas-code opamp shown in Fig. 1[SI. However, the tech-nique can be applied to any folded cascode opamp.

The opamp circuit shown in Fig. 1has large com-mon mode range, high slew rate and, with appropriatetransistor sizes, symmetric transient response for risingand falling inputs. In this circuit, the two tail currentsource transistors M3 and MSa are externally biased.However, these two transistors can be biased by usingthe internal current source formed by the transistors

M ~ , M G , M ~nd M ~ o . n particular, nodes 6 and 10can provide the gate bias of M3 and M3a respectively.The resulting self-biased opamp circuit is shown inFig. 2.In the self-biased opamp the gate biases of the tran-sistors M3 and form two feedback paths. But be-cause of the diode connected transistors M4 and M IOthe two nodes 6 and 10 are a.c. attenuated. So ef-fectively no signal comes through the feedback paths.Hence, at a given design and bias point, except thetransient response, all other performances of the exter-nally biased and the self-biased opamps are the same.

Apart from the transient response the other differ-ence between the externally biased and the self-biasedopamp is the difference in the design technique neededto keep the transistors M3 and M3a in saturation. Inthe following subsection first, we find the potential de-sign variables and then we give a design guideline tokeep all the transistors in the opamps in saturation.In the subsequent subsection we compare the step r esponse of the two opamps.2.1. Design Analysis

We take L and /3 ( = k ' W / L )of the transistors as pri-mary design variables. The quiescent current througha transistor Mi is denoted by ID^ As is typical withopamps, all of the primary variables are not inde-pendent variables. There are a number of matched

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pair transistors in the op amps. They are the follow-M ~ o ,11 . Note that, any two matched devices havethe same quiescent current.

The fully complementaryopamps have a large com-mon mode range. Over some portion of the commonmode range only the input transistors MI and Ma areactive, while over some other portion only M1a andM2a are active. So to get uniform performance overthe common mode range and t o get symmetric step re-sponse for rising and falling inputs, the following equal-ities are taken:

ing: M2; M1a7M2a; M4, M s; M6, M7; &, Mg and

(4)Note that, this equality also gives

ID10 =1 0 4 - ( 5 )In the self-biased op-amp the current ratio ID3/ID4 canbe controlled by the size rat io of the transistors M3 andM4. Hence, we impose the following constraints:

L3a = L109L3 =L4 (6 )- 9nd,- = _ _3a P3P l O P 4 (7)

From the equalities ( 1 ) (2), ( 6 )and (7) we are left withL1 ,PI, L4,P 4 , Lo ,P6 and q as the design variables.Based on the matching information of the transistorsand from K C L ,

ID4 = D6 +ID312 ( 8 )It therefore follows that Io4 >1 0 3 1 2 . Hence, from (4 )the range of q is (0 ,2 ) .

To get high performanceall of the transistors in theopamp should be in saturation. Because of the diodeconnection of the transistors M4,Me,Ma and M IOallof the transistors M4-Mi1 are always in saturation. Inquiescent condition the node voltages VS and Vg areclose to zero. So the node voltages v6 and V7 are neg-ative (since th e transistors Mc and M7 re in satu-ration). Hence, the transistors M1a and M2a are insaturation. Similarly, the two transistors M I and M2are also in saturation.

In the externally biased opamp the gate voltagesof the transistors M3 and M3a can be easily chosen tobias them in saturation. However, in the self-biasedop am p the gate voltages of the two transistors dependon the sizes of the other transistors. In the self-biasedog am p, the design constraint,

(9)keeps the two transistois in saturation. This inequal-ity can be obtained by first expressing the gate and thedrain voltages of the two transistors in terms of differ-ent transistor sizes. Then, the node voltage inequalitiesfor keeping the transistors in saturation are imposed,resulting in the inequality (9).2.2. Performance Comparison

As previously mentioned, for performance compari-son we need only to compare the slew rate of the self-biased op-amp with tha t of the externally biased o pamp. The slew rate is dletermined by the load currentwhich charges or discharges the load capacitor. Thistransient load current can be increased at the cost ofthe total quiescent current drawn (hence, power dis-sipation). So to compare the performance of the twoopamps we have taken the ratio of the transient loadcurrent and the total quiescent current as the perfor-mance metric.It is important to note that the fully complementaryopamps have symmetric transient response for risingand falliig inputs. So for our comparison we consideronly the positive step rcesponse. Besides facilitating acomparison of the opamps , the analysis also providesthe value (of the parameter q at which the slew rate ismaximized.

The transient load current for both of the op-ampsis,

where i ~ jenotes the transient current through thetransistor M j . For the externally biased opamp thetransient load current c m be well approximated by,

io 1 = [ 1 +min{l, ( l / q - o . 5 ) } ] I D 3 (11)while for the self-biased o pamp the transient load cur-rent is,

i02 = 4[1+min{l/q, (1+a ) } ]X [ L m ] l I D 3-I- 2 d + (12)

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where 8= &/p6.op-amp circuit is,

Now the total quiescent current drawn by the main

= (7 )DFrom equations (11) and (13) the ratio of the transientload current of the externally biased opamp and itstotal quiescent current is,

- [ 1 + m i n ( 1, ( l / q - .5)}]- 14)01Itot (2 +!I)- -From equations (12) and (13) we get the ratio metricfor the self-biased op-amp as,

The ratio metric i o2 / I to t is maximum at q =0.618.This maximizer can be obtained by equating the twoparts of the min function in (15). The maximum valueof the ratio metric is quite insensitive to 8. On theother hand, the ratio metric i o a / I t o t reaches its max-imum value of 0.5 at q =213. For larger values of qthe ratio metric remain the same. So for simulationcomparison (given is Section 4) we took q=213. Withthis value of q and with 0 =1 the value of io2/I tot is0.45. In other words, with equal power dissipation (inthe main op-amp) the self-biased opam p has 10% lessslew rate than t ha t of the externally biased op-amp.This analytical prediction is well matched by simula-tion results as is shown in Section 4. Further, whenthe current in the bias circuit of the externally biasedop-amp is also accounted for, simulation measurementsshow that the performance metric is actually 12 % bet-ter for the self-biased op-amp.3. Self-Biasing of High Performance Op-

AmpIn this section we describe a self-biased folded cas-

code op-amp which has both high d.c. gain and highunity gain frequency. The self-biased folded cascodeop-amp discussed in the last section has high unity gainfrequency. To enhance its gain, the gain boosting tech-nique given in [4] an be applied to this opamp. Thegain boosting technique is shown in Fig. 3. The gain ofthe simple amplifier can be increased by the additional

CL

Figure 3. Gain boosted cascode amplifierstage

amplifier circuit A a d d by increasing the cascoding effectof th e transistor M 2 .

Fig. 4 shows the gain boosted self-biased fully com-plementary folded cascode op-amp. Because of the fullcomplementarity, this opamp has rail to rail commonmode range. It alsohas rail t o rail minus two thresholdvoltage of output swing. The gain boosting amplifiers,A1 and A2 are shown in Fig. 5. Note tha t th e two non-complementary boosting amplifiers are also self-biased.

v ddI 1

+CL-"I1

M 3 ;Jl M4r" 'I; 5- V d dFigure4. Gain boosted self-biased fully com-plementary folded cas cod e op-amp

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v dd

2.4/1.8

- V d d

v,9Vi-

+ +-+L - v d d

Figure5.Galn boo sting amplifiersSince the negative output of the gain boosted o p

amp (Fig. 4) is not used, the a.c. attenuated output(negative output) of the amplifiers A1 and A2 are usedto provide the gate bias of the transistors MS and M6respectively. In the gain boosted op-amp, the d.c. volt-ages at the nodes 6 and 7 are the same while the a.c.signals at the two nodes are in opposite phase. Hence,instead of using an external voltage for the referenceinput (positive input) of th e boosting amplifier AS (asin [4]),the input is connected to th e node 6. Similarly,the positive input of the amplifier A1 is connected tothe node 10. This completes the self-biasing of the highperformance op-amp. Note tha t, the gain boosted op-amp uses only the V d d and - V d d supply rails for bi-asing. This is in contrast to t he op-amp in [4] whichrequires 3 additional bias voltages for the main op-ampand for each of the gain boosting amplifiers.

The design guideline for stability given in [4]s validfor this op-amp also. For single pole settling behav-ior, the unity gain frequency of the boosting amplifiersshould be larger than the bandwidth of the closed loopop-amp and smaller than th e second pole of the origi-nal op-amp.

4. Simulation ResultsThe performances of both the self-biased and the

externally biased non-boosted opamps and the self-biased gain boosted op-amp are predicted throughSpice simulation. For this simulation, level-2 MOSmodel for a 1.6,~ rocess [9]was used. In Section 2

9Table 11 Value of thie d esign variables at t hesimu lation point

th e design variables of the fully complementary foldedcascode olpamps are given. For our simulation com-parison of self-biasing with external biasing we tookthe design point which is given in Table 1. The samedesign point was taken for the boosted op-amp also.The transistors in the gain boosting amplifiers are ap-propriately sized (as shown in Fig. 5 ) to satisfy thestability condition given in [4]. The load capacitancewas 1pF and the supply was f3 volts.

The sirnulation results are given in Table 2. Unitygain frequency (UGF) and phase margin (PM) are ef-fectively the same for all of the three op-amps. D.C.gain (A(0)) of the two non-boosted opamps are thesame while it is doubled (in dB) in the boosted o pamp. Because of the high gain, CMRR and PSRR ofthe gain boosted op-amp are better than those of thenon-boosted op-amps.

Slew rate (SR) of the self-biased opamps are 10%less than that of the externally biased opamp. For the

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Performance

Table 2. Spice simulation results

Self-BiasedExt.-Biased Self-Biased with GainBoosting

settling time measurement we used the feedback circuitconfiguration given in [4],with the feedback factor of0.5. Due to self-biasing, the power dissipation (PD) ofthe non-boosted op am p is reduced by 19%. The powerdissipation of the boosted opam p is also less than thatof the non-boosted externally biased op-amp.

Finally, the ratio i o / l t o t was measured to be 0.50and 0.46 for the externally biased and self-biased o pamps, respectively. This is very close to the the ore ti dprediction given by the equations (14)and (15).5 . Summary

A self-biasing technique for folded cascode CMOSopamps is presented. The biasing technique uses noadditional devices and no bias voltages other than thetwo supply rails. Nevertheless, all transistors are biasedin saturation and hence, the high performance of theop-amps is maintained. This s achieved by appropriateuse of a.c attenuated internal nodes to provide the gatebias of the transistors and following transistor sizingconstraints derived through detailed circuit analysis.Thus, self-biasing eliminates the area and the poweroverhead of the bias circuitry and it also removes thelong biasing wires which are susceptible to noise andcross-talk.

While self-biasing has a number of performance ad-vantages the cost is a small reduction in slew rate.Through detailed circuit analysis the slew rate is pre-dicted and with proper transistor sizing its reductionis minimized.

The self-biasing technique is applied to a gainboosted folded cascode op-amp which can provide 100dB gain and 100MH z unity gain frequency with singlepole settling behavior. Simulation results show thatthe high performances is maintained while nine biasvoltages are eliminated.

References[l] P. J. A. Naus et. al., A CMOS Stereo 16-bit D/Aconverter for digital audio, IEEE J1. of Solid sta tecircuits, Vol. SC-22, No. 3, pp. 390-395, June 1987.[2] F. W. Singor and W. M. Snelgrove, Switched-capacitor bandpass delta-sigma A/D modulationat 10.7 MHz, IEEE Jl . of Solid state circuits, Vol.30 , NO.3, pp. 184-192, March 1995.[3] B. J. Hosticka, Improvement of the gain of MOSampliiers, IEEE JL of Solid state circuits, Vol.SC-14, No. 6, pp. 1111-1114, Dec. 1979.[4] K. Bult and G. J. G. M. Geelen, A fast-settlingCMOS op amp for SC circuits with 90-dB dc gain,IEEE JL. of Solid state circuits, Vol. 25 , No. 6, pp.1379-1384, Dec. 1990.[5] K. Bult, Basic CMOS circuit techniques, in Ana-log VLSI Signal and Informa tion Processing M. Is-mail and T. Fiez, eds., McGraw-Hill, pp. 12-56,1994.[6] M. Bazes, Two novel fully complementary self-

biased CMOS differential amplifiers, IEEE Jl . ofSolid state circuits, Vol. 26, No. 2, pp. 165-168,Feb. 1990.[7] E. Sackiiger and W. Guggenbuhi, High-swing,high-impedance MOS cascode circuit, IEEE Jl .of Solid state circuits, Vol. 25, No. 1,pp. 289-298,Feb. 1990.[SI R. E. Vallee and E. I. El-Masry, A very high-frequency CMOS complementary folded cascodeamplifier, IEEE JL of Solid state circuits, Vol.29 , No. 2, pp. 130-133, Feb. 1994.[9] P. V. Wolf et. al., An ntroduction to the NELSIS

IC design system, Delft U niv. of Technology, TheNetherlands, 1990.

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self biased high performance folded cascode cmos opamp

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