self-biased, high-bandwidth, low- jitter 1-to-4096 multiplier clock generator pll based on a...
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![Page 1: Self-Biased, High-Bandwidth, Low- Jitter 1-to-4096 Multiplier Clock Generator PLL Based on a presentation by: John G. Maneatis 1, Jaeha Kim 1, Iain McClatchie](https://reader031.vdocuments.mx/reader031/viewer/2022032801/56649de45503460f94adaa13/html5/thumbnails/1.jpg)
Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock
Generator PLL
Based on a presentation by:
John G. Maneatis1, Jaeha Kim1, Iain McClatchie1,Jay Maxey2, Manjusha Shankaradas2
True Circuits, Los Altos, CA1
Texas Instruments, Dallas, TX2
PDF file of JSSC paper linked at class web page.
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2
Clock Generator PLLs for ASICs
Most ASICs PLLs for clock generation, but … Use different frequencies and multiplication
GraphicsProcessor
NetworkProcessor
I/OController
YourASIC
N
FREF FOUTPLL
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3
Optimal PLL Design
For each FOUT and N, one must adjust loop parameters for both minimum jitter and stability
For clock generators (track input clocks)(REF = 2·FOUT/N)
Loop bandwidth :N ~ REF/20
Damping ratio : ~ 1 Third-order pole :C ~ REF/2
Circuit parameters (e.g. ICH, R) must vary with FOUT
and N!
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4
Addressing Diverse Specifications
Designing a different PLL for each ASIC Easier to meet the specification, but … Verifying all designs is difficult and costly
Our Goal: One PLL design for all ASICs Only one design needs verification, but … Loop parameters must adjust automatically
to satisfy wide range of FOUT and N
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5
Challenges
Self-biased PLLs [Maneatis ‘96] adjust for FOUT
Achieve fixed N/REF and indep. of PVT
But, Self-Biased PLLs do NOT adjust for N N/REF and vary with N (want fixed)
C/REF varies with N (want fixed)
This talk extends Self-Biased PLLs for wide ranges of N with a new loop filter network
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Outline
Introduction Review of Self-Biased PLLs Pattern Jitter Issues Loop Filter Architecture Implementation of Key Circuits Measured Results Conclusions
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Second-Order PLLs
PFDCPICH VCTL
N
CKOUT
CKREF
CKFB
UP
DN
C1
RVCOKV
2NN
N
I
O
)/s()/s(21
)/s(21N
)s(P
)s(P
1CR21
N 1
VCH C1KI
N1
N
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Second-Order PLLs
PFDCPICH VCTL
N
CKOUT
CKREF
CKFB
UP
DN
C1
RVCOKV
)1
( RCS
IV CHCTL
Oscillation frequency is supposed to be controlled by VCTL, that is by ICH/CS + ICH*R.In Ring Oscillators, frequency is more easily controlled by current, through tail biasing voltage. want tail current to have two components: ICH/CS + ICH*R.
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Self-Biased PLLs
PFD
CPxID
CPxID
VCOKV
=k/CB
VCTL
VBN
N
CKOUT
CKREF
CKFB
UP
DN
VFF
Replica-FeedbackBiasing
C1
1/gm ID
mg/1R DCH IxI BmVCO CgF
)1
( RCS
ICH
VBN biases the tail current in Ring Oscillator buffer stages.
So want ID to have components:
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Self-Biased PLLs
PFD
CPxID
CPxID
VCOKV
=k/CB
VCTL
VBN
N
CKOUT
CKREF
CKFB
UP
DN
VFF
Replica-FeedbackBiasing
C1
1/gm ID
Op Amp adjust VBN so that NMOST ID matches currents in 1/gm and that from top charge pump.Notice: VCTL = VDD – ICH / sC1 dID = (VDD – VCTL)gm + ICH-ff = ICH (1/sC1 + 1)
Hence VBN will generate I-tail proportional to ICH (1/sC1 + 1)
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Maneatis self bias generator
From 1996 Maneatis paper, which is very widely reference.PDF file linked at web page.
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Self-Biased PLLs
With Self-Biased PLLs
N/REF and are constant with FOUT,
BUT not with N
Nx~CCNx21
1BREFN
Nx~CCNx41
B1
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Pattern Jitter / Spurious Noise
Phase corrections every rising reference edge can cause disruptions to nearby output cycles Periodic noise pattern repeats every ref. cycle
or N output cycles
Typical causes Charge pump imbalances or leakage Jitter in reference clock (aperiodic result)
CKREF
VCTL
CKOUT
SHORT
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Shunt Capacitor
Use third-order pole to extend disturbance with reduced amplitude over many output cycles
Problem with varying N using fixed capacitor Extended number of cycles NOT function of N Too few for large N Pattern jitter Too many for small N Instability
FILTERED
CKREF
VCTL
CKOUT
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Proposed Loop Filter
Use switched capacitor filter network to Output scaled amplitude error signal with N
output cycle duration [Maxim ’01]
Want a simple solution using this approach that is compatible with Self-Biased PLLs
FILTERED
CKREF
VCTL
CKOUT
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Original Filter Network
Only need to filter feed-forward path
VCTL
VBN
VFF
Replica-FeedbackBiasing
C1
CP
CP
UP
DN
1/gm
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Sampled Feed-Forward Network
Sample phase error and generate proportional current that is held constant for N·TOUT
Sampled error is reset at end of ref. cycle Need VRST = VCTL as zero bias level
gm
VCTL
VBN
VFF
Replica-FeedbackBiasing
C1
1/gmC2
CP
CP
UP
DN
VRST
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Complete Filter Network
Reset C2 to VCTL directly
Eliminates C1 charge pump
Equivalent feed-forward control gain
QO ~ N · QI
gm
VCTL
VBN
VFF
Replica-FeedbackBiasing
C1
1/gmC2
CPUP
DN
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Loop Dynamics
With this new loop filter network we achieve
Need to keep N/REF and constant with N
Just scale charge pump current with 1/N (=x)
More detailed analysis will show
Both are independent of FOUT, N, and PVT!
Nx~REFN Nx~NxQQ~ IO
1B CC21
REFN
21B CCC41
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Complete Self-Biased CGPLL
PFD
CP1
CP2
VCO
Charge Pump Bias Gen.(Prog. 1/N Current Mirror)
VFS1
VFS2
VCTL
VBN
VBC
VBC
ClockDivider
CKOUT
CKREF
CKFB
Divide Ratio(N=1...4096)
UP
DN
VBP
gm(VFS1+VFS2)
VFF 1/gm
Loop Filter
Replica-FeedbackVCO Bias Gen.
C2
C1
C2
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Self-Biased Filter Network
CP1
CP2
VFS1
VFS2
VFF
VCTL
C2
C1
C2
S1
S2
SelectControl
UP
DN
en
en
VBN
VBN
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Filter Network Reset Switches
Can switch to VCTL independent of voltage level
VBN
VBR VCTL
SEL_B SEL
VCTLVFS
VCTL
VDD+VCTL
sel_boosted
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Filter Network Reset Switches
When un-selected, sel = 0, sel_B = 1 (VDD). V_B = VDD, V_D = VDD + V_CTL, V_A = 0, V_C = V_BR = V_CTL.
V_CA charged to V_CTL
VBN
VBR VCTL
SEL_B SEL
VCTLVFS
VCTL
VDD+VCTL
sel_boosted
A B
C D
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Filter Network Reset Switches
When selected, sel_B = 0, sel = 1 (VDD). V_A = VDD, V_C = VDD + V_CTL, V_B = 0, V_D = V_BR.
V_DB charged to V_BR or V_CTL
VBN
VBR VCTL
SEL_B SEL
VCTLVFS
VCTL
VDD+VCTL
sel_boosted
A B
C D
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Inverse-Linear Current Mirror
Need to generate ICH = ID / N
Use switches to adjust device size on input side For N=1~4096, need 12 binary weighted legs Need size range of 2048:1 Too much area!
IOUTIIN
VBD
S0S1S2S3S4S5
x2x4 x1x8x16x32
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Multi-Stage Linear CM
Solution to size problem with LINEAR control Use multiple device groups operating at
different but ratioed current densities Can have large ranges using small devices
IOUTIIN
VBDS3S4S5
8:1
S0S1S2
x2x4 x1x2x4 x1
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Multi-Stage Inverse-Linear CM
Just diode connect multi-stage linear current source and use as input side of current mirror Can output gate bias of any device group Stable as long as gain blocks reduce currents
IOUTVBD
S3S4S5
8:1
S0S1S2
x2x4 x1x2x4 x1
IIN
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Complete Current Mirror
VBN
IOUT
VBC
8:18:18:1
S9S10S11 S6S7S8 S3S4S5
IIN
E3
E3
E2
E2
(N = 1 … 4096)
IOUT
IIN 1
N
S0S1S2
x2x4 x1 x1
VBD
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Voltage-Controlled Oscillator
VFF
VCTL
VBN VBN
VBP
VBP
VI-VI+VO+VO-
VTAIL
Buffer StageVCO Replica-Feedback Bias Generator
11-Stage Ring Oscillator
VBN
VBP
CK+
CK-
CK+
CK-
VREP
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V
VDS
Higher VDD
V
IL IHID
V
V
VTAIL
VREP
time
Buffer Tail Node Matching
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Modified VCO
VFF
VCTL
VBN VBN
VBP
VBP
VI-VI+VO+VO-
VTAIL(SHARED)
Buffer StageVCO Replica-Feedback Bias Generator
11-Stage Ring Oscillator
VBN
VBP
VTAIL
CK+
CK-
CK+
CK-
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Static Supply Sensitivity
32
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PLL Implementation
Process Technology 0.13m N-well CMOS
Nominal Supply Voltage 1.5V (designed for 1.2V)
Total Occupied Area 0.38 x 0.48mm2
VCO Frequency Range 30 ~ 650 MHz
Multiplication Factor Range N = 1 ~ 4096
Power Dissipation 7mW @ 240 MHz, 1.5V
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Measured Jitter vs N (240MHz)
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PLL Jitter Measurement Summary
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Conclusions
Proposed PLL achieves wide N and FOUT range
PLL is self-biased with constant loop dynamics (N/REF, ), independent of N, FOUT , and PVT
Sampled feed-forward network suppresses pattern jitter with effective C that tracks REF
Achieves relatively constant period jitter of less than 1.7% as N is scaled from 1 to 4096
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References J. Maneatis et al., “Self-biased high-bandwidth low-jitter 1-to-4096
multiplier clock generator PLL,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2003, pp. 424–425.
J. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723–1732, Nov. 1996.
A. Maxim et al., “A low-jitter 125–1250 MHz process-independent 0.18 m CMOS PLL based on a sample-reset loop filter,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2001, pp. 394–395.
T. C. Lee and B. Razavi, “A stabilization technique for phase-locked frequency synthesizers,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2001, pp. 39–42.
J. Maneatis and M. Horowitz, “Precise delay generation using coupled oscillators,” IEEE J. Solid-State Circuits, vol. 28, pp. 1273–1282, Dec. 1993.