sd 2.0 host controller ip - capital-micro.com

SD 2.0 Host Controller IP

User Guide

12/2014

Capital Microelectronics, Inc.

China

User Guide of SD 2.0 Host Controller IP

http://www.capital-micro.com 1

Contents

Contents ............................................................................................................................................................... 1

1 Introduction .................................................................................................................................................. 2

2 SD 2.0 Host Controller IP Overview .............................................................................................................. 3

2.1 Block Diagram and Description ........................................................................................................ 3

2.1.1 Block Diagram ....................................................................................................................... 3

2.1.2 Block Description .................................................................................................................. 3

2.2 Pin and Parameter Description ......................................................................................................... 4

2.2.1 EMIF Host interface .............................................................................................................. 4

2.2.2 AHB Host interface ............................................................................................................... 6

2.2.3 Parameters ........................................................................................................................... 7

2.3 Registers for Host ............................................................................................................................. 7

2.3.1 Register Memory Map .......................................................................................................... 7

2.3.2 Register and Field Descriptions ............................................................................................ 9

2.4 Host Interface Operation ................................................................................................................ 15

2.4.1 EMIF operation ................................................................................................................... 15

2.4.2 AHB Interface Operation .................................................................................................... 17

2.5 Interrupt operation ........................................................................................................................ 18

2.5.1 8051 external interrupt sources ......................................................................................... 19

2.5.2 ARM external interrupt sources ......................................................................................... 19

2.6 Resource Usage .............................................................................................................................. 20

3 SD Host Controller IP Usage ....................................................................................................................... 21

3.1 Internal Register Access .................................................................................................................. 21

3.1.1 AHB Interface Timing.......................................................................................................... 21

3.1.2 EMIF Interface Timing ........................................................................................................ 22

3.2 Initialization Process ....................................................................................................................... 22

3.2.1 Auto detect initialization .................................................................................................... 23

3.2.2 Forced initialization ............................................................................................................ 23

3.3 Data Transaction ............................................................................................................................. 23

3.3.1 Single/Multi-block Read ..................................................................................................... 23

3.3.2 Single/Multi-block Write .................................................................................................... 25

3.4 Explicit Command Transaction ....................................................................................................... 26

3.5 Primace Setting when this IP used ................................................................................................. 27

3.5.1 Timing Constraint setting ................................................................................................... 27

3.5.2 Fast I/O setting, recommand .............................................................................................. 27

4 Generate File Directory Structure .............................................................................................................. 29

4.1 File Directory Structure in M5 family device .................................................................................. 29

4.2 File Directory Structure in M7 family device .................................................................................. 30

Revision History .................................................................................................................................................. 31



1 Introduction

This document mainly describes the implementation of SD2.0 Host controller IP, which supports the Secured

Digital (SD) 2.0 memory technologies. This IP handles all of the timing and interface protocol requirements to

access the media as well as processing the commands. A host CPU or Microprocessor can easily utilize this IP

to access a SD memory card. The SD2.0 IP supports the following features:

Compliant with the following specification versions:

Part 1 Physical Layer Specification Version 2.00

Part A2 SD Host Controller Standard Specification version 2.00

Auto Card detect

Forced initialization on the inside of the controller IP

Supports SPI, SD 1-bit and SD 4-bit mode

Supports the normal mode of 25MHz and the optional high speed mode of 50MHz

Supports an 8KB Read/Write buffer for CPU/Microprocessor initiated writes and reads

Support both single and multiple block read/write operation

CRC7 and CRC16 support for CMD and DATA

With EMIF(External Memory Interface) and AHB interface for user application

Device family support:

CME-M5, CME-M7



2 SD 2.0 Host Controller IP Overview

2.1 Block Diagram and Description

The following sections describe the block diagrams of the design.

2.1.1 Block Diagram

SD 2.0 Host Controller IP application environment:

SD 2.0

Host

Controller

IP

CPU

or

Micro-

processor

SD CARD

Figure 2-1 Application block diagram

Detail structure of the SD 2.0 Host Controller IP design:

SD 2.0 Host Controller IP

CPU

or

Micro-

processorSD CARD

Slave

register

interface SD bus

interface

Controller Core

Regs

Clock

Initial &

Command

Control

FSM

DMAOutside

Memory

Slave

data

interface

Buffer

System clock in

Figure 2-2 Detail structure diagram

2.1.2 Block Description

Slave Register Interface:

The processor use this interface to configure the Host Controller IP by writing different configuration registers.

Support AHB and EMIF.



Slave Data Interface:

This is a slave memory interface, can be used to transfer data directly between the IP internal read-write

Buffer and outside memory or host processor. And this interface will only exist on port of this IP when

parameter SLAVE_DATA_IF_TO_PROCESSOR set to 0.

Regs:

Consisting of the SD Host Controller register set which can be used/controlled by the Host Driver running on

the CPU/Micro-processor.

DMA:

Used to moving data from/to the read-write Buffer to/from SD card.

Buffer:

The 8KB read-write Buffer, used for buffering the data to be read/written from/to SD Card through the Host

Controller. The internal controller will read/write this buffer only when host performs an explicit command, or

host starts a block data read or write operation, or during the initialization.

Initial & Command Control FSM:

Used for initialization and command posting mechanism.

Clock:

Generate the initialization clock 400KHz and data transfer clock 25MHz or 50MHz, based on the input 50MHz

system clock and control signals from Initial & Command Control FSM block.

SD Bus Interface:

For SD memory side physical interface that handles the SD data transfer modes (SPI Mode, SD 1-bit Mode, SD

4-bit Mode).

2.2 Pin and Parameter Description

Here two host interface will be supported to connect CPU or Micro-processor, that is, EMIF(external memory

interface) and AHB.

2.2.1 EMIF Host interface

Table 2-1 Pin Description of EMIF interface

Signal Type Signal Name Type Width Description

System interface

clk_i I 1 System clock input, 50MHz

rst_i I 1 Reset input, high active, all logic of IP core

will be reset when this port being high.



IP_core_clk_o O 1

IP core clock for output, which is the clock of

all the IP internal logic. At 400KHz during

initialization, and then at data transfer

frequency (25 or 50 MHz)

Slave reg interface

(EMIF, clock domain:

IP_core_clk_o)

s_memaddr_i I 23 8051 emif address

s_memwr_i I 1 8051 emif write enable

s_memrd_i I 1 8051 emif read enable

s_memdata_i I 8 8051 emif write data to IP

s_memdata_o O 8 8051 emif read data from IP

s_memack_o O 1 8051 emif acknowledge

s_ip_interrupt_o O 1 Interrupt output

Slave data interface

(clock domain:

IP_core_clk_o)

s_buf_wr_start_o O 1 High pulse signal, tell host to move the block

data into buffer

s_buf_wr_done_i I 1 High pulse signal, tell Controller that block

data in buffer has been ready for reading

s_buf_rd_start_o O 1 High pulse signal, tell host to move the block

data out of buffer

s_buf_rd_done_i I 1 High pulse signal, tell Controller that block

data in buffer has been read out

s_buf_cnt_size_o O 5 Real-time value of Block Count & Size

register

s_buf_ce_i I 1 Buffer Chip enable/select, high active

s_buf_we_i I 1 Buffer write enable, high write, low read

s_buf_addr_i I 11 Buffer address, 2K word(8KB) buffer size

s_buf_wdata_i I 32 Buffer write data

s_buf_rdata_o O 32 Buffer read data

SD Bus Interface

SD_clk_o O 1

SD card clock. At 400KHz during initialization,

and then at data transfer frequency (25 or 50

MHz)

SD_card_detectn_i I 1

Insertion detect of SD card, through the

physical switch connector in circuit board.

Low active. The internal FSM (not include

internal registers) of IP core will be reset

when this port being high(card disconnect).

SD_CMD_io I/O 1 The command/response of the SD interface

SD_DAT0_io I/O 1 The data line 0 of the SD interface




Note: The “Slave data interface” port field only exists when the parameter “SLAVE_DATA_IF_TO_PROCESSOR”

is set to 0, which means the slave data buffer does not connect to CPU/Micro-processor as its slave buffer but

connect to an outside-memory like SRAM or DRAM.



2.2.2 AHB Host interface

Table 2-2 Pin Description of AHB interface

Signal Type Signal Name Type Width Description

System interface

clk_i I 1 System clock input, 50MHz

rst_i I 1 Reset input, high active, all logic of IP core

will be reset when this port being high.

IP_core_clk_o O 1

IP core clock for output, which is the clock of

all the IP internal logic. At 400KHz during

initialization, and then at data transfer

frequency (25 or 50 MHz)

Slave reg interface

(AHB, clock domain:

IP_core_clk_o)

s_ahb_sel_i I 1 AHB slave select signal

s_ahb_addr_i I 32 AHB address

s_ahb_write_i I 1 AHB transfer direction, high means write,

low means read

s_ahb_trans_i I 2 AHB transfer type of the current transfer

s_ahb_wdata_i I 32 AHB write data from master to slave

s_ahb_readyout_o O 1 AHB ready out, when high, indicates a

transfer has finished

s_ahb_resp_o O 1 AHB transfer response, low means OKAY,

high means ERROR

s_ahb_rdata_o O 32 AHB read data from slave to master

s_ip_interrupt_o O 1 Interrupt output

Slave data interface

(clock domain:

IP_core_clk_o)

s_buf_wr_start_o O 1 High pulse signal, tell host to move the block

data into buffer

s_buf_wr_done_i I 1 High pulse signal, tell Controller that block

data in buffer has been ready for reading

s_buf_rd_start_o O 1 High pulse signal, tell host to move the block

data out of buffer

s_buf_rd_done_i I 1 High pulse signal, tell Controller that block

data in buffer has been read out

s_buf_cnt_size_o O 5 Real-time value of Block Count & Size

register

s_buf_ce_i I 1 Buffer Chip enable/select, high active

s_buf_we_i I 1 Buffer write enable, high write, low read

s_buf_addr_i I 11 Buffer address, 2K word(8KB) buffer size

s_buf_wdata_i I 32 Buffer write data

s_buf_rdata_o O 32 Buffer read data

SD Bus Interface SD_clk_o O 1

SD card clock. At 400KHz during initialization,

and then at data transfer frequency (25 or 50

MHz).



SD_card_detectn_i I 1

Insertion detect of SD card, through the

physical switch connector in circuit board.

Low active. The internal FSM (not include

internal registers) of IP core will be reset

when this port being high(card disconnect).

SD_CMD_io I/O 1 The command/response of the SD interface.

SD_DAT0_io I/O 1 The data line 0 of the SD interface.




Note: The “Slave data interface” port field only exists when the parameter “SLAVE_DATA_IF_TO_PROCESSOR”

is set to 0, which means the slave data buffer does not connect to CPU/Micro-processor as its slave buffer but

connect to an outside-memory like SRAM or DRAM.

2.2.3 Parameters

Table 2-3 SD Host Controller IP Parameters

Name Type Size Description

BASE_ADDR Int 23(emif)

32(ahb)

The base address of the SD Host Controller IP on bus

memory space of 8051 EMIF or ARM AHB.

SLAVE_DATA_IF_TO_PROCESSOR Int 1

When 1, this parameter indicates that the slave data

interface is combined with the slave register interface

to connect to Processor; when 0, the slave data

interface will exist in the IP interface, and data in the

read-write Buffer can only be accessed through the

slave data interface.

2.3 Registers for Host

2.3.1 Register Memory Map

The SD Host Controller IP has a 128Byte register memory space, and a 8KByte block data buffer. Table

2-4(AHB Host Interface) and 2-5(EMIF Host Interface) lists the all the internal registers and their address

mapping.

Table 2-4 SD Host Controller IP registers for AHB Host Interface

Address Registers Description Size Access Reset Value

0x00 Control Register 32bit RW 32’h0000_0010

0x04 Configuration Register 32bit RW 0

0x08 Status Register 32bit RO 0



0x0C Block Count & Size Register 32bit RW 0

0x10 Argument Register 32bit RW 0

0x14 Command Register 32bit RW 0

0x18 Response Register 128bit RO 0

0x28 Interrupt Status Register 32bit RO 0

0x2C Interrupt Enable Register 32bit RW 0

0x30~7F Reserved - - -

0x2000~3FFFF Block Data Buffer(The read-write Buffer in

Figure 2-2) 8KByte RW -

Note: The address space of Block Data Buffer exists only when parameter SLAVE_DATA_IF_TO_PROCESSOR is

set to 1, otherwise the Block Data Buffer is directly accessed through the slave data interface.

Table 2-5 SD Host Controller IP registers for EMIF Host Interface

Address Registers Description Size Access Reset Value

0x00 Control Register 8bit RW 8’h10

0x04 Configuration Register 8bit RW 0

0x08 Status Register

bit[7:0] 16bit RO 0

0x09 bit[15:8]

0x0C Block Count & Size Register 8bit RW 0

0x10

Argument Register

(bit[7:0])

32bit RW 0 0x11 (bit[15:8])

0x12 (bit[23:16])

0x13 (bit[31:24])

0x14 Command Register 8bit RW 0

0x18

Response Register

bit[7:0]

128bit RO 0

0x19 bit[15:8]

0x1A bit[23:16]

0x1B bit[31:24]

0x1C bit[39:32]

0x1D bit[47:40]

0x1E bit[55:48]

0x1F bit[63:56]

0x20 bit[71:64]

0x21 bit[79:72]

0x22 bit[87:80]

0x23 bit[95:88]

0x24 bit[103:96]

0x25 bit[111:104]

0x26 bit[119:112]

0x27 bit[127:120]

0x28 Interrupt Status Register 8bit RO 0

0x2C Interrupt Enable Register 8bit RW 0

0x30~7F Reserved - - -



0x2000~3FFFF Block Data Buffer(The read-write Buffer in

Figure 2-2) 8KByte RW -

Note: The address space of Block Data Buffer exists only when parameter SLAVE_DATA_IF_TO_PROCESSOR is

set to 1, otherwise the Block Data Buffer is directly accessed through the slave data interface.

2.3.2 Register and Field Descriptions

The following sections contain the field descriptions for the individual registers. The description of each

register size is based on AHB Host Interface; under EMIF Host Interface, the register valid size(exclude the

reserved bits) bigger than 8bit can be accessed 8bit by 8bit according to address offset listed in table 2-5.

2.3.2.1 Control Register

Address Offset: 0x00

Size: 32bits

Read/Write Access: Read/Write

The register is used to control the operation of the card. This register also specifies mode(single or multiple)

and direction(write or read) of the transfer.

Bit Access Reset Description

31:6 RO 0 Reserved.

5 R/W 0 Single/Multiple block transfer direction(write/read flag): this bit indicates the

write or read operation of single/multiple block transfer, 1 write, 0 read.

4 R/W 1 Single/Multiple block transfer mode: 1 mean single block access, 0 multiple.

3 R/W 0

Command Valid: Setting this bit indicates that the processor is posting a

explicit command whose index is indicated by the Command index section of

the Command Register. The processor must set this bit only after setting all

the command argument and command index sections of the register set. As

soon as the request bit is set, the controller frames a command and sends it to

the Card. The response is updated into the Response Register.

This bit will be automatically cleared when response received(command

done).

2 R/W 0

Single/Multiple block transfer trigger: when this bit is set, the operation of

single/multiple block data transfer will be started according to the length

specified in Block Count & Size Register. Before asserting this bit, the Block

Count & Size Register and Argument Register should be set for corresponding

value.

This bit will be automatically cleared 1 cycle after set.



1 R/W 0

Reset initialization Statistics: The bit is used as a soft reset for resetting any

initialization flags(internal FSM and some registers) that are set by the Host

controller when it was used to initialize any other speed and bus width

configuration. The processor is expected to set this bit at least once before a

second “Force initialization” is forced on the Host controller’s initialization

state machines.


0 R/W 0

Force initialization: This bit is used to control the initialization flow of the Host

controller. After this bit being asserted, the host controller will immediately

start the initialization process(send init-related commands to SD bus).


2.3.2.2 Configuration Register


Size: 32bits


The register is used for configuring the SD Host Controller operations.


31:4 RO 0 Reserved.

3 R/W 0

Auto detect, asserted if Auto detect is required. When set, this bit indicate

that initialization will be automatically issued 250ms(Power up time) after the

moment of this bit being asserted or after card insertion detected(input port

“SD_card_detectn_i” from 1 to 0). And initialization result can be found in

Status Register bit 1 and bit 0. (This bit can be asserted after power-up or

“Reset initialization Statistics” bit enabled, and value of this bit should be

kept unchanged before next time “Reset initialization Statistics” bit enabled.)

2 R/W 0 Speed Class, 0 for Standard mode(25MHz), 1 for High Speed mode(50MHz).

1:0 R/W 0 Bus width configuration on the PHY interface. 2’b00 means 1-bit mode, 2’b01

means 4-bit mode, 2’b11 means SPI mode of operation.

Note: The bit 2(Speed Class) and bit 1:0(Bus width) can only be active after “Force initialization” bit being

asserted, or be active in initialization step of hot-insertion(input port “SD_card_detectn_i” from 1 to 0) when

“Auto detect” bit of Configuration Register asserted. Value of this register will be reset to 0 when “Reset

initialization Statistics” bit being asserted. And value of bit [2:0] should be kept unchanged before next

time “Force initialization” or “Reset initialization Statistics”.

2.3.2.3 Status Register


Size: 32bits



Read/Write Access: Read Only(some bits will be cleared when writing the Control Register)

The register is used for identifying the Status of the SD Controller Initialization modules.


31:12 RO 0 Reserved.

11 RO 0 SD high capacity card: When set, this bit indicates that the card is a high

capacity card(over 2GB, up to and including 32GB).

10 RO 0 SD standard capacity card: When set, this bit indicates that the card is a

standard capacity card (up to and including 2GB).

9 RO 0 SD Legacy Card: When set, this bit indicates that the card is a legacy standard

capacity SD card(cards prior to SD version 2.0, that is Ver1.x SD memory card).

8 RO 0

Unusable card flag: This is an error bit and indicates that the card is unusable

for various reasons such as a voltage mismatch or continuous ERC error

observed during initialization.

7 RO 0 Card connect status: When set, this bit indicates that there is a card inserted

or existent. This bit real-time reflects the input “SD_card_detectn_i”.

6 RO, WCC 0

Block data in buffer has been read out into outside-memory. This bit is only

used/valid when parameter “SLAVE_DATA_IF_TO_PROCESSOR” be 0(that is

the Slave data interface does not connect to CPU but an outside-memory).

5 RO, WCC 0 Single/Multiple block transfer CRC error: the write or read data of the previous

Single/Multiple block transfer on SD bus have CRC error.

4 RO, WCC 0

Single/Multiple block transfer done success: When set, this bit indicates that

the operation of single/multiple block transfer is finished(if write operation, all

block data in buffer is transfer to sd card and CRC status response ok; if read

operation, all block data from sd card is loaded into buffer, and CRC check ok).

3 RO, WCC 0

CMD done with error/timeout: This bit indicate there are errors exist in Card

Status, VHS, VDD range or CRC check in the response of the previous explicit

command; or indicate timeout that no response received.

When some commands such as CMD0/CMD4/CMD15 under SD mode is

issued, this bit just indicate timeout when asserted. Other commands indicate

errors in response or timeout when asserted.

2 RO, WCC 0

CMD done success: This bit is an acknowledge bit indicating that the received

response is updated into the Response-Register after the explicit command is

sent by the Host controller. The processor may have to poll this bit at regular

intervals after posting a request for an explicit command to enquire the status

of the request.

1 RO 0 Error in Initialization: This bit indicates there are some errors during

initialization of the card. Also means the initialization was unsuccessful.

0 RO 0

Initialization Done success: When set, this bit indicates that the initialization

process is successful and all the status register bits are valid for the software

driver to inquire.

Note: WCC mean that the bit will be automatically cleared when writing the Control Register. And value of



bits 11:8 is valid only after initialization done success.

2.3.2.4 Block Count & Size Register

Address Offset: 0x0C

Size: 32bits


The register can be used to indicate the number of blocks, with the size of each block, that are to be

transferred to/from the processor from/to the Card.

The “Block Size” and “Block Count” fields are used for Single/Multi block transfer on the SD interface.


31:20 RO 0 Reserved.

4 R/W 0 Block Size: the size of each data block, 0 mean 512 byte, 1 mean 1024 byte.

3:0 R/W 0

Block Count: which indicates the number of data blocks for a read/write

transaction on the SD interface. Allowed Values are 0x00-0x0F, which means

1-16 blocks can be transmitted. This field only applicable when multiple mode

“Single/Multiple block transfer mode” (bit 4 of Control Register) is set.

Note: Value of this register will be reset to 0 when “Reset initialization Statistics” bit being asserted.

2.3.2.5 Argument Register


Size: 32bits


The Argument of the SD command shall be programmed in this register.


31:0 R/W 0 Content of the argument register.

The argument register can be used to send a processor intended command argument to the SD card without

the interference of the controller. The processor can use the command register for sending an explicit

command.

The argument register can also be used to specify the SD card data address of read/write single/multiple

block transfer (That is argument field of CMD17/CMD18/CMD24/CMD25). And data address is in byte units in

a Standard Capacity SD Memory Card and in block (512 Byte) units in a High Capacity SD Memory Card.



2.3.2.6 Command Register


Size: 32bits


The command register can be used to send a processor intended command index to the SD card without the

interference of the controller.


31:6 RO 0 Reserved.

5:0 R/W 0

Command Index Register: This section is the command index of the explicit

command that the processor intends to post to the card. The section is

evaluated only when the “Command Valid” bit of the Control Register is set.

Note: Here the supported commands exclude CMD17, CMD18, CMD24 and CMD25, which can be fulfilled

through the Single/Multi block transfer operation provided in this IP.

2.3.2.7 Response Register


Size: 128bits

Read/Write Access: Read Only

This register is the response register for an explicit command posted by the processor. And the Response

register can be read by the processor once the command is posted.

Please note that if the explicit command posted not only has response but also follows data block, like reading

CSD/CID/SCR register under SPI mode(CMD9, CMD10, ACMD51) or reading Status/SCR under SD

mode(ACMD13, ACMD51), then the response will be discarded, and only the data block be accepted into the

read-write Buffer(the bits mapping of data block of registers stored in the read-write Buffer follow the same

rules as the following response bit/byte).


127:0 RO 0 Response value.

Note: bit 127:96, address offset 0x24;

bit 95:64, address offset 0x20;

bit 63:32, address offset 0x1C;

bit 31: 0, address offset 0x18.

For SD 1bit/4bit mode:

Data stored in the response register is bit [39:8] of 48bits response and bit [127:8] of 136bits response under

SD mode(detail format of the 48bits/136bits response please see SD part1 Physical Layer Specification). And



the bit/byte map between the response and the register is as following(the first received byte will be stored

into lower byte position of the register):

Bit mapping of 48bits response:

Bit position of 48bits response under SD 1bit/4bit mode Bits of the response register

39:32 7:0

31:24 15:8

23:16 23:16

15:8 31:24

Bit mapping of 136bits response:

Bit position of 136bits response under SD 1bit/4bit mode Bits of the response register

127:120 7:0

119:112 15:8

111:104 23:16

… …

23:16 111:104

15:8 119: 112

For SPI mode:

The same with SD mode, that is, the first received byte of response will be stored into the lowest byte

position of the register (7:0), and the successive bytes(if exists) will be stored into the lower bytes position as

15:8, 23:16, … of the register.

2.3.2.8 Interrupt Status Register


Size: 32bits

Read/Write Access: Read Only

Detail meaning of this register interrupt bit can be found in Status Register. This register value is enabled only

when related bit field of Interrupt Enable Register is asserted.


31:5 RO 0 Reserved.

4 RO, WC 0 Card connect or disconnect interrupt. Poll Status Register bit[7] to check status

of connect or disconnect.

3 RO, WC 0

Block data in buffer has been read out into outside-memory. This bit is only

valid when parameter “SLAVE_DATA_IF_TO_PROCESSOR” be 0, see Status

Register bit[6].

2 RO, WC 0 Single/Multiple block transfer done success or CRC error. Detail see Status

Register bit[5:4].

1 RO, WC 0 CMD done success or error/timeout. Detail see Status Register bit[3:2].



0 RO, WC 0 Initialization Done success or error. Detail see Status Register bit[1:0].

Note: WC mean that the bit will be automatically cleared when writing any value to this register.

2.3.2.9 Interrupt Enable Register

Address Offset: 0x2C

Size: 32bits


This register is the interrupt enable register for interrupt processing. Writing 1 to related bit mean enable, 0

mean disable.


31:6 RO 0 Reserved.

5 R/W 0 All interrupts enable, when set, all interrupts in Interrupt Register are enabled,

otherwise disabled.

4 R/W 0 Card connect or disconnect interrupt enable.

3 R/W 0 Block data in buffer has been read out into outside-memory interrupt enable.

2 R/W 0 Single/Multiple block transfer done success or CRC error interrupt enable.

1 R/W 0 CMD done success or error/timeout interrupt enable.

0 R/W 0 Initialization Done success or error interrupt enable.

Note: In this register, bit[4:0] is valid only when bit[5] enabled.

2.4 Host Interface Operation

This section specifies the interface between Host(CPU/Micro-processor) and the Controller IP. Here two kind

of Host interfaces, External memory interface(EMIF) and AHB, are supported.

2.4.1 EMIF operation

2.4.1.1 EMIF Interface timing

EMIF is used to extend the MSS (MCU sub-system) memory, address 20000~7FFFFF, can be implemented with

Fabric.

The CME-M5 family provides synchronous and asynchronous EMIF for Fabric extended memory which has the

same data/address and control ports but have different timing waveforms. The synchronous or asynchronous

EMIF mode is selected by the parameter sync_mode_en.



Figure 2-3 EMIF read waveform

When reading, Fabric places the read data to memdatai bus and not outputs a valid “memack” after one or

several cycles until the fabric data is ready after the memrd is asserted.

Figure 2-4 EMIF write waveform

In write cycle, Fabric writes the memdatao to extended memory when the memwr is asserted and send a

valid “memack” to MSS on the next cycle.

2.4.1.2 EMIF data bank mapping



Figure 2-5 CME 8051 memory map

Figure 2-6 CME 8051 bank arrangement

As is shown in figure up, the common area starts at 0x0000H address and ends at 0x7FFFH. Bank 0 is not

available, it is physically the same memory spaces at the common area. While code/xdata memory banking

feature is enabled, the code/xdata memory address is composed of two parts:

15 bit address

8bits from a bank switching register SW_REGISTER:

PAGESEL for code memory

D_PAGESEL for xdata memory

Figure 2-7 code/xdata memory address with banking

For more information of EMIF interface, please refer to:

http://www.capital-micro.com/PDF/CME-M5_Family_FPGA_Data_Sheet_EN%20%281%29.pdf

or http://www.capital-micro.com/PDF/MSS_8051_Subsystem_User_Guide_EN.pdf

2.4.2 AHB Interface Operation

2.4.2.1 AHB interface timing

Following is the AHB interface timing of write and read operation. This AHB interface only support single burst

http://www.capital-micro.com/PDF/CME-M5_Family_FPGA_Data_Sheet_EN%20%281%29.pdf

http://www.capital-micro.com/PDF/MSS_8051_Subsystem_User_Guide_EN.pdf



transfer, and 32bit data transfer size.

Figure 2-8 AHB write and read waveform

2.4.2.2 AHB address mapping

FP0

bfff_ffff

a000_0000

FP1

dfff_ffff

c000_0000

Figure 2-9 CME M7 ARM AHB Address mapping

The ARM Core provides two groups of AHB Bus signals, AHB0 and AHB1, so there are two memory space for

user logic which are called as FP0 and FP1. It means that if you instantiate an ARM Core and choose the AHB0 ,

you must access your slaves on the address from a000_0000 to bfff_ffff, but if you connect the AHB interface

to AHB1, the slaves can be accessed on the address from c000_0000 to dfff_ffff.

2.5 Interrupt operation

For this SD Host controller IP, after each transmission and reception complete, interrupt request

(s_ip_interrupt_o) is generated. User can connect this interrupt request to any 8051/ARM’s external interrupt

input. And 8051/ARM will follow the normal interrupt handle procedure to handle this IP’s interrupt request.

Following are external interrupt sources of both 8051 and ARM.



2.5.1 8051 external interrupt sources

Table 2-6 8051 external interrupt sources

Vector

Number

Type Polarity Alternate Port Description

0 I Low/Fall Port3i[2] External interrupt 0

2 I Low/Fall Port3i[3] External interrupt 1

9 I Fall/Rise Port1i[4] External interrupt 2

10 I Fall/Rise Port1i[0] External interrupt 3

11 I Rise Port1i[1] External interrupt 4




2.5.2 ARM external interrupt sources

Table 2-7 ARM external interrupt sources

Interrupt Serve Function Type Alternate Port Description

Void FP0_IRQHandler(void) I fp_interrupt[0] External interrupt 0


















2.6 Resource Usage

Resource usage and performance of the USB IP on Primace.

Table 2-8 SD Host Controller IP resource usage and performance

Resource

Chip LUT4s REGs EMB5K Performace

M5/M7 2.4K 1.5K 16 60MHz



3 SD Host Controller IP Usage

3.1 Internal Register Access

This transaction can be used to access a single 32 bit word(AHB) or 8 bit byte(EMIF) from or to the SD

Controller for programming purpose. This transaction is mainly used for accessing the CPU register set for

reading response bytes, status registers, or writing control and configuration registers for forcing initialization

of the SD memory, for executing SD commands from processor if required, for clearing status registers using

soft resets.

3.1.1 AHB Interface Timing

When accessing internal registers through AHB interface, AHB single operation is used, and the timing

diagram is shown in Figure 3-1(Read operation will take 2 more clock cycle).

Figure 3-1 Internal register access of AHB(Single) on the host/processor interface

When parameter “SLAVE_DATA_IF_TO_PROCESSOR” is set to 1, then Block Data Buffer(the read-write Buffer)

can be accessed at offset 0x2000(See table 2-4 and 2-5), and the buffer can also be accessed using AHB burst

operation(INCR4,INCR8,INCR16). And following is the burst operation timing diagram in Figure 3-2(Read

operation will take 2 more clock cycle).



Figure 3-2 Internal Buffer access of AHB(Burst) on the host/processor interface

3.1.2 EMIF Interface Timing

The timing diagram of the EMIF interface is shown in Figure 3-3.

Figure 3-3 Internal register/Buffer access of EMIF on the host/processor interface

3.2 Initialization Process

Before performing a single/multiple block data transaction or explicit command transaction, an initialization

process should be issued.

There are 2 kinds of method to issue an initialization, one is auto detect initialization, the other one is forced

initialization.

After initialization successful, then one point should be noticed, that is one transaction(explicit command or

block read/write) should be issued until the previous transaction is finished.



3.2.1 Auto detect initialization

For an auto detect, there are 4 steps:

1. “Power up” or “Reset initialization statistics” bit being asserted or “Card insertion detect” (input

“SD_card_detectn_i” changes from 1 to 0, and the changes also reflect at Status Register bit 7 and

Interrupt Register bit 4) to make sure internal FSM of IP core is reset.

2. Set interrupt register if need(This register can be set at any time, whether before initialization or not ).

3. Set “Speed Class & Bus Width” (bit 2:0 of Configuration Register) to corresponding value, and the “Auto

detect” (bit 3 of Configuration Register) to ‘1’. Then the controller will automatically wait

250ms(Power up time) then automatically start the initialization.

4. Poll Status Register bit [1:0] or wait interrupt (Interrupt Register bit 0) to check whether initialization

finished.

3.2.2 Forced initialization

For a forced initialization, there are 5 steps:

1. First there should exist or connect a card(whether hot insertion or not), and then assert the “Reset

initialization statistics” bit to make sure internal FSM of IP core is reset(The “Reset initialization statistics

“ may not be issued the first time initialization after power up, but should be issued at least once before a

second or further forced initialization after power up).

2. Set interrupt register if need(This register can be set at any time, whether before initialization or not ).

And set “Speed Class & Bus Width” (bit 2:0 of Configuration Register) to corresponding value.

3. For the SD memory card have a 250ms power up time, so this time period should be met before issuing a

forced initialization. That is to say, time period between “card power-up/insertion” and “forced

initialization” should be at least 250ms.

4. Set “Force initialization” (bit 0 of Control Register) to start a forced initialization.

5. Poll Status Register bit [1:0] or wait interrupt (Interrupt Register bit 0) to check whether initialization

finished.

3.3 Data Transaction

After initialization successful, then data transaction can be issued. SD card data access is based on block, and

data transaction block size in this Controller IP can be set to 512 or 1024. But one point should be mentioned

when issuing data transaction, that is Standard Capacity Memory Card supports 512 or 1024 bytes size block,

but High Capacity Memory Card supports only 512 bytes size block.

3.3.1 Single/Multi-block Read

The Processor can transfer single or multiple blocks of data from the SD card via the Host Controller using this

transaction. The host Controller shall transfer the data from the SD card to the read-write Buffer(See figure

2-2), and then data in the Buffer can be fetched out by the processor.



The sequence of operation for a single/multi block read from the SD card is as follows(step 1 and 2 can be

exchanged):

1. Set the Block Count & Size Register with the number of blocks to be fetched, and size of each block. The

maximum Block Count can be 16(Register bit[3:0] be 0xF) for an 8KBytes read-write Buffer. By default,

the Block Count is configured to 0, which means 1 block, and the Block Size is configured to 512 byte.

2. Set the Argument Register with the data address of SD memory card, from which the SD Host Controller

shall read the blocks of data. Note that data address unit is different between Standard Capacity SD

Memory Card and High Capacity SD Memory Card.

3. Write 0 to “Single/Multiple block transfer direction” bit, proper value to “Single/Multiple block transfer

mode”, and 1 to “Single/Multiple block transfer trigger” bit of Control Register, to start reading of the

entire blocks of data that it configured, using the Single/Multi Block Read transaction, with data being

transferred into the read-write Buffer.

4. Poll Status Register bit[5:4] or wait interrupt (Interrupt Register bit 2) to check whether the transaction

finished. If the transfer success, then data in the Buffer is ready to be fetched out.

5. If IP parameter “SLAVE_DATA_IF_TO_PROCESSOR” is set to 1, then Processor can access the Buffer at

offset 0x2000(see table 2-4); If it is set to 0, then data in the Buffer will be fetched out directly into

Outside-memory(not by processor), and Processor can poll Status Register bit 6 or wait interrupt

(Interrupt Register bit 3) to check whether data in the Buffer is fetched out.

Figure 3-4 shows the timing of a single/multi block read transaction sequence on the interface when

parameter “SLAVE_DATA_IF_TO_PROCESSOR” is set to 1 (Slave data interface connects to the processor as a

slave buffer space).

Figure 3-4 Timing of block read transaction sequence (Slave data interface connect to processor)

Figure 3-5 shows the timing of a single/multi block read transaction sequence on the interface when

parameter “SLAVE_DATA_IF_TO_PROCESSOR” is set to 0 (Slave data interface connects to the

Outside-memory directly).

Figure 3-5 Timing of block read transaction sequence (Slave data interface connect to Outside-memory)



3.3.2 Single/Multi-block Write

The Processor can transfer single or multiple blocks of data to the SD card via the Host Controller using this

transaction. The host Controller shall transfer the data from the read-write Buffer to the SD card.

The sequence of operation for a single/multi block write to the SD card is as follows(step 1, 2 and 3 can be

exchanged):

1. Set the Block Count & Size Register with the number of blocks to be fetched, and size of each block. The

maximum Block Count can be 16(Register bit[3:0] be 0xF) for an 8Kbytes read-write Buffer. By default,

the Block Count is configured to 0, which means 1 block, the Block Size is configured to 512 byte.

2. Set the Argument Register with the data address of SD memory card, to which the SD Host Controller

shall write the blocks of data. Note that data address unit is different between Standard Capacity SD

Memory Card and High Capacity SD Memory Card.

3. If IP parameter “SLAVE_DATA_IF_TO_PROCESSOR” is set to 1, then the processor shall prepare the data

into the read-write Buffer for the SD Host Controller to fetch.

4. Write 1 to “Single/Multiple block transfer direction” bit, proper value to “Single/Multiple block transfer

mode”, and 1 to “Single/Multiple block transfer trigger” bit of Control Register, to start writing of the

entire blocks of data that it configured, using the Single/Multi Block Write transaction, and when

“SLAVE_DATA_IF_TO_PROCESSOR” be 1 then data in the read-write Buffer will be started to transfer out

immediately, or when “SLAVE_DATA_IF_TO_PROCESSOR” be 0 then data in the read-write Buffer will be

started to transfer out until “s_buf_wr_done_i” detected.

5. If IP parameter “SLAVE_DATA_IF_TO_PROCESSOR” is set to 0, then data in Outside-memory should be

fetched out into the read-write Buffer after detecting high pulse of “s_buf_wr_start_o”, and a high pulse

of “s_buf_wr_done_i” should be given to the SD Host Controller to indicate that data in the read-write

Buffer is ready to be fetched out for transfer.

6. Poll Status Register bit[5:4] or wait interrupt (Interrupt Register bit 2) to check whether the transaction

finished. If the transfer success, then data in the Buffer has been successfully written into the SD card.

Figure 3-6 shows the timing of a single/multi-block write transaction sequence on the interface when

parameter “SLAVE_DATA_IF_TO_PROCESSOR” is set to 1 (Slave data interface connects to the processor as a

slave buffer space).

Figure 3-6 Timing of block write transaction sequence (Slave data interface connect to processor)

Figure 3-7 shows the timing of a single/multi-block write transaction sequence on the interface when

parameter “SLAVE_DATA_IF_TO_PROCESSOR” is set to 0 (Slave data interface connects to the

Outside-memory directly).



Figure 3-7 Timing of block write transaction sequence (Slave data interface connect to Outside-memory)

3.4 Explicit Command Transaction

After initialization successful, then the explicit command transaction can also be issued.

The sequence of operation for an explicit command transaction to the SD card is as follows:

1. The processor shall configure the Command Register with the command index of the explicit command

the processor intends to post to the card.

2. The processor shall also program the argument value into the Argument Register. The detail content of

each command’s argument can be found in SD Physical Layer Spec.

3. The processor then write 1 to “Command Valid” bit of the Control Register, to start the command posting

to SD card.

4. The processor can then poll bit 2 or 3 of Status Register to wait/check the result of the transaction. Or

wait for interrupt when the command done. If the command finished, then the received response in the

Response Register can be fetched out.

Note that the supported explicit commands exclude CMD17, CMD18, CMD24 and CMD25, which can be

fulfilled through the Single/Multi block transfer operation provided in this IP.

And note that if the explicit command posted not only has response but also follows data block, like reading

CSD/CID/SCR register under SPI mode(CMD9, CMD10, ACMD51) or reading Status/SCR under SD

mode(ACMD13, ACMD51), then the response will be discarded, and only the data block be accepted into the

read-write Buffer.



3.5 Primace Setting when this IP used

3.5.1 Timing Constraint setting

After Synthesis flow of Primace, select Primace-->Tools-->Timing Constraints Editor-->Create a new SDC file:

Then under Clock-->Object-->Search Design, for this IP, search “*IP_core_clk*”(clock of internal logic of this IP,

which frequency can be 400KHz/25MHz/50MHz at different period) by “Pins”, as shown in following figure:

After selecting the clock needed constraint, the “Frequency(MHz)” item of the selected clock should be set as

50(MHz).

3.5.2 Fast I/O setting, recommand

There are 2 kinds of method to realize the fast I/O setting. User can use either or both kind of the 2 method

to do fast I/O setting.

3.5.2.1 Through Project Setting

Primace-->Project-->Project Settings-->Project-->Logic Flow-->”Pack I/O registers into IO”, this is fast I/O

setting for all used I/Os (Following is an example of fast I/O setting in Project Setting):



3.5.2.2 Through IO Editor

Primace-->Tools-->IO Editor, this is fast I/O setting for individual I/O (Following is an example of fast I/O

setting in IO Editor):



4 Generate File Directory Structure

The SD 2.0 Host Controller IP wizard generated file includes: source files(src), simulation files(sim) and

example design files(example). The detailed design directory structure is as below.

4.1 File Directory Structure in M5 family device

Table 4-1 Generated File Directory structure of M5

Directory Description

src\

Directory for project source code, including IP wizard generate

code, for example: ip_top.v, which instantiate the SD2.0 Host

Controller IP and define related parameters.

ip_core\ The directory specially for all IPs

\sd_host_ctrl_v1 Directory for SD2.0 Host Controller IP

\doc\

CME_SD20_Host_Controller_user_

guide _EN01.doc User guide for the IP

\src\

emif_SD_Host_Controller_top.v Top module (Encrypted)

emif_control_fsm.vhd FSM Controller module (Encrypted)

emif_dma_interface.vhd Internal DMA module (Encrypted)

emif_phy_interface.vhd PHY interface module (Encrypted)

emif_sd_IP_pkg.vhd Package of VHDL modules (Encrypted)

m5_device_related_module.v Specific hard-IP(like EMB) of M5 device used in design

\sim\

src_vp\* Encrypted source files for simulation in Modelsim

SD_model\* Simulation model of SD memory card

tb_m5\* Testbench related files of M5

\firmware\

sd_m5.c, sd_m5.h Functions for SD Host Controller IP usage, including internal

register/buffer access, initialize, disk read/write.



4.2 File Directory Structure in M7 family device

Table 4-1 Generated File Directory structure of M7

Directory Description

src\

Directory for project source code, including IP wizard generate

code, for example: ip_top.v, which instantiate the SD2.0 Host

Controller IP and define related parameters.

ip_core\ The directory specially for all IPs

\sd_host_ctrl_v1 Directory for SD2.0 Host Controller IP

\doc\CME_SD20_Host_Controller_user

_guide_EN01.doc User guide for the IP

\src\

ahb_SD_Host_Controller_top.v Top module (Encrypted)

ahb_control_fsm.vhd FSM Controller module (Encrypted)

ahb_dma_interface.vhd Internal DMA module (Encrypted)

ahb_phy_interface.vhd PHY interface module (Encrypted)

ahb_sd_IP_pkg.vhd Package of VHDL modules (Encrypted)

m7_device_related_module.v Specific hard-IP(like EMB) of M& device used in design

\sim\

src_vp\* Encrypted source files for simulation in Modelsim

SD_model\* Simulation model of SD memory card

tb_m7\* Testbench related files of M7

\example\

CME_SD20_Host_Controller_example

_user_guide_EN01.pdf Example user guide

sd_demo_ahb.zip The example RTL and firmware project

\firmware\

sd_m7.c, sd_m7.h Functions for SD Host Controller IP usage, including internal

register/buffer access, initialize, disk read/write.



Revision History

Revision Date Comments

1.0 2014-07-08 Initial release

sd 2.0 host controller ip - capital-micro.com

Documents