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CME3000-C FPGA Data Sheet v1.1

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CME3000-C FPGA

Data Sheet v1.1

Capital microelectronics Co., Ltd.



CME3000-C FPGA ........................................................................................................................... 1

1 General Description ..................................................................................................................... 5

2 FPGA............................................................................................................................................. 8

2.1 Programmable Logic Block (PLB) ..................................................................................... 8

2.1.1 LP .............................................................................................................................. 8

(1) Look-Up Table.................................................................................................... 9

(2) Register............................................................................................................... 9

(3) Carry, Cascade and Arithmetic Logic ............................................................... 10

2.2 LE ................................................................................................................................... 10

(1) LE Cascade ....................................................................................................... 10

(2) LE Carry and Skip ............................................................................................ 10

(3) LE Shift ............................................................................................................ 10

2.3 Embedded Memory Block ............................................................................................. 10

2.3.1 EMB5K Port Definitions .......................................................................................... 11

2.3.2 EMB5K Operations.................................................................................................. 12

2.3.3 EMB5K Operation Mode ......................................................................................... 13

EMB5K True Dual-port ............................................................................................... 13

EMB5K Simple Dual-port............................................................................................ 14

EMB5K Single-port ..................................................................................................... 15

2.4 DSP Block ....................................................................................................................... 16

2.4.1 DSP Primitive .......................................................................................................... 17

2.4.2 DSP Usage Mode .................................................................................................... 19

(1) Multiplier .......................................................................................................... 20

(2) Multiplier and adder ......................................................................................... 20

(3) Multiplier and Accumulator ............................................................................. 20

2.5 Input/output Blocks....................................................................................................... 21

2.5.1 Pull-Up Resistors ..................................................................................................... 23

2.5.2 ESD Protection ........................................................................................................ 23

2.5.3 Drive Strength ......................................................................................................... 23

2.5.4 The Organization of IOBs into Banks ...................................................................... 23

2.5.5 The I/Os During Power-On, Configuration, and User Mode ................................... 23

2.6 Interconnect .................................................................................................................. 24

2.7 PLL ................................................................................................................................. 25

2.7.1 PLL features ............................................................................................................ 25

2.7.2 CME3000 PLL Hardware Description ...................................................................... 25

2.7.3 PLL Primitive Port Signal Definitions ....................................................................... 26

2.7.4 Clock Feedback Modes ........................................................................................... 29

(1) Internal Feedback Mode (Frequency Synchronous Mode) ............................. 29

(2) External Feedback Mode ................................................................................. 29

2.7.5 Phase-shift Implementation ................................................................................... 30

2.8 Global Clock & Reset Resources .................................................................................... 32

2.8.1 External Crystal Input ............................................................................................. 32

2.8.2 Clocking Infrastructure ........................................................................................... 33

2.8.3 Clock Switch ............................................................................................................ 34



2.8.4 Reset Networks ....................................................................................................... 35

3 MSS Subsystem .......................................................................................................................... 35

3.1 8051 Instantiation ......................................................................................................... 37

3.1.1 8051 Macro Primitive Description .......................................................................... 37

3.2 MSS Clock Description ................................................................................................... 39

3.3 MSS Memory Map ......................................................................................................... 39

3.4 MSS External Memory Interface (EMIF) ........................................................................ 40

(1) Synchronous EMIF ........................................................................................... 40

(2) Asynchronous EMIF ......................................................................................... 41

3.5 Multiplex of P Port Pins ................................................................................................. 42

3.6 RTC ................................................................................................................................. 43

3.7 MSS in System Management ......................................................................................... 43

3.7.1 Device Register ....................................................................................................... 44

3.7.2 ISC Register Frame .................................................................................................. 44

3.7.3 Extended SFR .......................................................................................................... 45

3.7.4 MSS In System Configuration .................................................................................. 46

3.7.5 MSS in System Clock Configuration ........................................................................ 48

(1) PLL Configuration ............................................................................................. 48

(2) GCLK Dynamic Switch ...................................................................................... 48

(3) MSS Clock Dynamic Switch .............................................................................. 49

4 Configuration and Debug ........................................................................................................... 49

4.1 Configuration Mode ...................................................................................................... 49

4.1.1 AS Mode ................................................................................................................. 49

4.1.2 PS Mode.................................................................................................................. 50

4.1.3 JTAG Mode .............................................................................................................. 51

4.2 SPI Flash ......................................................................................................................... 51

(1) Using embedded SPI-Flash .............................................................................. 51

(2) Using External SPI-Flash ................................................................................... 52

4.3 ISC .................................................................................................................................. 52

4.4 Debug ............................................................................................................................ 52

4.5 Power-On-Reset (POR) .................................................................................................. 52

5 Security ...................................................................................................................................... 53

5.1 Bitstream Generation Security Level ............................................................................. 53

(1) prot_flagn ........................................................................................................ 53

(2) read_disable0 .................................................................................................. 54

(3) read_disable1 .................................................................................................. 54

5.2 On-Chip eFuse ............................................................................................................... 54

5.3 Embedded SPI-Flash Hidden Bitstream ......................................................................... 55

5.4 AES Security ................................................................................................................... 55

6 DC & Switching Characteristics .................................................................................................. 56

6.1 DC Electrical Characteristics .......................................................................................... 56

6.1.1 Absolute Maximum Ratings .................................................................................... 56

6.1.2 Power Supply Specifications ................................................................................... 57

6.1.3 General Recommended Operating Conditions ....................................................... 57



6.2 Switching Characteristics ............................................................................................... 61

6.2.1 Clock Performance .................................................................................................. 61

6.2.2 I/O Performance ..................................................................................................... 61

6.2.3 PLB Performance .................................................................................................... 61

6.2.4 EMB5K Performance ............................................................................................... 62

6.2.5 DSP Performance .................................................................................................... 62

7 Pins and Packaging..................................................................................................................... 62

7.1 Pins Definitions and Rules ............................................................................................. 62

7.2 Pin List ........................................................................................................................... 64

7.2.1 LQFP144 Package Pin List........................................................................................ 64

7.2.2 TQFP100 Package Pin List ....................................................................................... 66

7.3 Package Information ...................................................................................................... 66

8 Developer Kits ............................................................................................................................ 69

9 Ordering Information ................................................................................................................. 69

Number of Pins .................................................................................................................................. 70

10 Legend .................................................................................................................................. 71

11 Revision History .................................................................................................................... 72



1 General Description

CME3000-C FPGA is an intelligent device integrates enhanced 8051 MCU and high performance FPGA, which can fulfill customized system design and IP protection (128 bit AES). Embedded optimized RAM confers highest speed and performance on 8051 processor hardcore which is easy to use and debug.

Designers can design FPGA with CME’s Primace as well as embedded design with 3rd party EDA tool KeilTM conveniently and quickly. Based on CME3000 single chip, CAP (Configurable Application Platform on chip) is ideal for hardware and embedded designers who need a true system-on-chip (SoC) solution that gives

more flexibility than traditional fixed-function microcontrollers and is more cost-efficient than FPGAs—without the excessive cost of soft processor cores on traditional FPGAs. CME3000-C FPGA can be used widely in industry, medical, communication system and consumer electronics etc..

FPGA SRAM-based FPGA Fabric

- 6144 4-input Look-up Tables, 4096

DFF-based registers - Performance up to 250MHz

Embedded RAM Block Memory - 32 4.5Kbit programmable dual-port

DPRAM memory EMB5K blocks Embedded DSPs block

- 16 18x18 DSP (MAC) blocks also can be used as 32 12x9 DSPs

Clock Network - 8 de-skew global clocks - 2 PLLs support frequency multiplication,

frequency division, phase-shifting, de-skew

(input clock frequency: 5~427.5MHz, output clock frequency: 10~450MHz)

- 8 external input clocks, 1 external crystal clock input

I/O - 3.3/2.5/1.8V LVTTL, 3.3/2.5/1.8/1.5V

LVCMOS support - Tri-State Output Pad with Input and

Enable Controlled Pull-Up - Programmable driver strength

MSS Enhanced 8051 MCU

- Reduced instruction cycle time (up to 12 times in respect to standard 8051), frequency up to 200MHz

- Compatible to 8051 instruction system

- Support up to 8Mbit data/code memory extension

- Support hardware 32/16-bit MDU - On-chip debugger system (OCDS), support

JTAG online debugging - 4 channels DMA

Embedded SRAM Memory - 128KByte single-port SRAM - Data/code unified addressing, flexible

memory configuration Peripheral

- 3 16-bit Timers, Timer2 can be used as

CCU - 1 16-bit watch dog Timer - 1 I2C interface - 1 SPI interface - 2 Full Duplex Serial Interfaces - RTC

STOP, IDLE Mode Power Management In System Management

- ISC Control - Dynamic frequency switches in system

Configuration Configuration Mode

- JTAG Mode - AS Mode - PS Mode

JTAG Interface - JTAG Chip Configuration - JTAG 8051 Debugging - Chip Configuration and 8051 debugging

Share 1 JTAG Dynamic/Multi-configuration Image Support

Security Encrypted in-system programming (ISP) with

128-bit AES Decrypted in-system configuration (ISC) with

128-bit AES key stored in eFuse Efuse controls access to the security settings of

the device Protection against overbuilding with customer

programmable device key

Packaging TQFP-100, LQFP-144

CME3000-C FPGA Data Sheet


CME3000-C FPGA Feature Summary

Table 1-1 CME3000-C FPGA Feature Summary

Device(1) LUT

Programmable Logic

Block(PLB) (2)

Embedded Memory Block

SRAM (3)

DSP Block (4)

PLL Flash MCU Max User I/O LP Register 4.5Kb Max

CME3C03 3072 1024 2048 16 72Kb 64KB 8 2 - 1 204

CME3C06 6144 2048 4096 32 144Kb 128KB 16 2 - 1 204

CME3C03N 3072 1024 2048 16 72Kb 64KB 8 2 4Mb 1 204

CME3C06N 6144 2048 4096 32 144Kb 128KB 16 2 4Mb 1 204

Note:

1. C: FPGA + SRAM (used by MCU) + MCU. CME3xxxN: ‘N’ indicates configuration flash option.

2. Each CME3000 PLB contains 4 LPs (Logic parcel). Each LP contains 3 LUTs, 2 registers. 3. CME3CXX serial devices: SRAM could only be used by MCU. 4. Each DSP Block contains an 18 x 18 multiplier with 41 bits accumulator, an adder. Each DSP Block can also

support 2 independent 12 x 9 multiplier with 21 bits accumulator.

Table 1-2 CME3000-C FPGA Device-Package and Available I/Os Package TQFP100 LQFP144

Pitch(mm) 0.5 0.5

Body Size(mm) 16 x 16 22 x 22

Device User I/O User I/O

CME3C03 66 101

CME3C06 66 101

CME3C03N 66 101

CME3C06N 66 101

Architecture Overview

The CME3000-C FPGA architecture consists of five fundamental programmable functional tiles and

an enhanced 8051 MSS. The PLBs, IOBs, EMB, DSPs and PLLs made up the FPGA. The enhanced

8051 and SRAM made up the MSS. The EMB and DSP can be called as special function block (SFB).

Programmable Logic Blocks (PLBs) contain RAM-based Look-Up Tables (LUTs) to implement

logic and storage elements that can be used as flip-flops. PLBs can be programmed to perform

a wide variety of logical functions as well as to store data.

Embedded Memory Block provides data storage in the form of 4.5Kbit dual-port blocks.

DSPs accept two 18-bit binary numbers as inputs and calculate the product. The DSP block

includes special DSP multiply-accumulate blocks.

Phase (PLL) blocks provide self-calibrating, fully digital solutions for distributing, delaying,

multiplying, dividing, and phase shifting clock signals.

Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal



logic of the device. Each IOB supports bidirectional data flow plus 3-state operation.

The monocycle enhanced 8051 CPU is used as central processing unit, whose instruction set is

compatible with standard ASM51 completely. The embedded 128KB SRAM is used as the 8051

CPU memory.

These elements are organized as shown in Figure 1-1. A ring of IOBs surrounds a regular array of

PLBs. The CME3000-C FPGA has a single column of block EMB and DSP in the array. The PLLs and

GCLK_CTRL blocks are positioned at the top and bottom of right corner. The 8051 and SRAM

memory are layouted at the right side of the diagram. All these elements include the Xbars which

interconnect the functional elements, transmitting signals among them.

IO SEAM

SPI Config /JTAG

8051

64KB SRAM

64KB SRAM

PLL

GCLK_Ctrl

PLLGCLK_Ctrl

200um 300um

IO SEAM

RTC DigitalSEAM

SEAM

SEAM

SEAM

RT

C analog

Efuse E

SD

IOBs

IOBs

IOBs

EMB 18K

PLB

PLB

PLB

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EMB 18K

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IOBs

r1

r2

r3r4

r5

r6

r7

r8

r9

r10

r11

r12

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r20

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r26

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r32

r28

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r31

C1 C2 C3 C4 C7 C8 C9C10

C12

C13

C14

C15

C16

C17

C18

C19

C5 C6C11

Figure 1-1 CME3000 C FPGA Architecture



2 FPGA

The CME3000 FPGA consists of up to 512 PLBs, 32 EMB5K blocks, 16 18x18 DSPs and 2 PLLs. This

chapter describes the element blocks.

2.1 Programmable Logic Block (PLB)

The Programmable Logic Block (PLB) is the fabric basic logic tile which is composed of LE and Xbar.

The PLB is the basic tile of the Fabric. Their organization is shown as Figure 2-1. One LE contains

four interconnected Logic Parcels (LP). The LE constitutes the main logic resource for implementing

synchronous as well as combinatorial circuits.

The Xbar switches and passes the signals between the tile elements.

Xbar

LP3

LP2

LP1

LP0

LE

PLB

Figure 2-1 PLB Schematic Diagram

The PLBs are arranged in a regular array of rows and columns as shown in Figure 1-1.

The CME development software designates the location of a PLB according to its C and R

coordinates, starting in the bottom left corner, as shown in Figure 1-1. The letter ‘C’ followed by a

number identifies columns of PLBs, incrementing from the left side of the die to the right. The

letter ‘R’ followed by a number identifies the position of each PLB in the CLB row, incrementing

from the bottom of the die.

2.1.1 LP

LP is the basic programmable logic element. The LP has the following elements to provide logic,

arithmetic functions as shown in Figure 2-2:

• Three 4-input LUT function generators, lut0, lut40 and lut41

• Two registers, reg0 and reg1

• Carry, cascade and arithmetic logic



LUT4

4_1

LUT4

0

LUT4C

4_0

di

di

4

0

f0[8]

f1[8]f2[8]

byp[8]

byp[12]

f0[4]f1[4]f2[4]

fy[0]

byp[4]

f0[0]

f1[0]

f2[0]

dy[0]

qx[4]

dx[4]

qx[0]

dx[0]

byp[0]

fast cascade to next PLB

Lut5 cascades from next LP up

dx4bcarry output

din[0]

shift

a_sr

en

shift

a_sr

en

shift up/down

shift up/downfast cascade to next LP above

fast cascades from prev PLB

clk

fx4b

shift[1:0]

Ca

sca

de

Ge

n

Ca

sca

de

Ge

nL

UT

5

Ge

n

LUT5 Gen

din[1]

carry input

din[1:0]

Figure 2-2 LP Schematic Diagram

(1) Look-Up Table

The Look-Up Table or LUT is a RAM-based function generator and is the main resource for

implementing logic functions. Each of the three LUTs in a LP has four logic inputs (f0-f3) and a

single output (d). Any four-variable Boolean logic operation can be implemented in one LUT.

Functions with more inputs can be implemented by cascading LUTs which are in one LP or adjacent

LPs.

(2) Register

The register is a programmable D-type flip-flop. There are two level multiplexers on the D input

select of the registers. The first level multiplexer selects either the LUT combinatorial output or the

bypass signal byp[x]. The second level multiplexer selects either the first level multiplexer output

signal byp[x] or signal shift. The shift signal is from the next up/down relative register output qx.

The storage element output, qx, offers three possible paths:

1. Drives the interconnect line directly

2. Feedbacks to the LUT input

3. Cascade to the next up/down relative storage element signal shift



(3) Carry, Cascade and Arithmetic Logic

The vertical up cascading from near down LP feeds the LUT0 input, the LUT40 or LUT41 generates

the cascading output. Functions with more inputs can be implemented by cascading LUTs between

PLBs.

The carry chain, together with various dedicated arithmetic logic gates, support fast and efficient

implementations of math operations such as adders, counters, comparators, multipliers, wide logic

gates, and related functions. The carry logic is automatically used for most arithmetic functions in a

design. The gates and multiplexers of the carry and arithmetic logic can also be used for

general-purpose logic, including simple wide Boolean functions.

The carry input from LUT40 of the near down LP enters the LUT40 and the LUT40 generates the

carry out which can be cascaded to next up LUT40.

2.2 LE

The LE contains 4 LPs and Carry Ship, Register Control circuitry which make LE implement many

complex functions, such as cascading, Carry and Skip, LE Shift. These functions provide higher

performance and lower resources usage than normal LUT implemented because these

connections are hardware logic and connections.

(1) LE Cascade

The LEs can be cascaded vertically and horizontally to implement large and complex functions.

(2) LE Carry and Skip

The LEs can implement flexible carry function with skip 4 and skip 8 fast carry logic.

(3) LE Shift

The LE registers can be cascaded to implement the register shift up or down vertically with next up

LE register.

2.3 Embedded Memory Block

CME3000 device supports embedded memory block (EMB), which is organized as one column total 32

4.5Kbit EMB5K. EMB5K module is a true dual-port memory which permits independent access to the

common EMB block. Each port has its own dedicated set of data, control and clock lines for



synchronous read and write operations. EMB5K provides features as below:

4.5Kbits

Mixed clock mode

A, B data width configured independently

Support write data through output

Parity bit

The EMB5K blocks support a parity bit for each byte. The parity bit, along with internal LC, can

implement parity checking for error detection to ensure data integrity. Parity-sized data words can

be used to store user-specified control bits.

Initialization support

The format of initialization file is either .hex or .dat (a hexadecimal number each line, the number

of lines depends on depth of EMB5K). Initialization files initialize EMB5K memory during

configuration.

Two EMB5K cascade

Memory Mode

EMB5K can be configured into the following modes:

- emb_tdp

- emb_sdp

- emb_sp

2.3.1 EMB5K Port Definitions

The dual-port primitive EMB5K signals are defined in Table 2-1.

Table 2-1 EMB5K Port Definition

Port name Type Width Description

clka I 1 Input clock for port A

cea I 1 Chip enable for port A

wea I 1 Write enable for port A

aa I 12 Address line for port A

da I 18 Data input for port A

clkb I 1 Input clock for port B

ceb I 1 Chip enable for port B

web I 1 Wire enable for port B

ab I 12 Address line for port B

db I 18 Data input for port B

q O 18 Memory data q output

wq_in I 9 Input from paired EMB5K for wide true dual port mode

wq_out O 9 Output to paired EMB5K for wide true dual port mode



Table 2-2 EMB5K Parameters

Parameters Type Description

modea_sel string

Port a usage mode setting:

256x18, 512x9, 1kx4, 2kx2, 4kx1, wtdp(wide true dual port)

Default: 256x18

modeb_sel string

Port b usage mode setting:

256x18, 512x9, 1kx4, 2kx2, 4kx1, wtdp(wide true dual port)

Default: 256x18

porta_wr_through string

Bypassing of write data from write port to read port enable for

port a, true or false

Default: false

portb_wr_through string

Bypassing of write data from write port to read port enable for

port b, true or false

Default: false

init_file string EMB initial file

Default: “”

operation_mode string EMB working mode, just for simulation

true_dual_port, single_port, simple_dual_port

porta_data_width string EMB port a data width, just for simulation

portb_data_width string EMB port a data width, just for simulation

2.3.2 EMB5K Operations

Writing data to and accessing data from the EMB5K are synchronous operations that take place

independently on each of the two ports.

When the we and ce signals enable the active edge of clk, data at the d input bus is written to the

EMB5K location addressed by the a lines. There are two write actions which are selected by

wr_through parameter. The write data is also passed to q output bus if the wr_through is true

during the writing process. The q output bus value will be the previous read output value during

the writing process if the wr_through is false. The two operation waveforms are shown as in Figure

2-3 and Figure 2-4.



clk

ce

we

a

d

q

mem[bb] FFFF

men[ab]

FFFF

ab bb

0000

Figure 2-3 wr_through is false Waveform

1

1

clk

ce

we

a

d

q

mem[bb]

mem[ab]

FFFF

FFFF0000

ab bb

Figure 2-4 Write Through Waveform

2.3.3 EMB5K Operation Mode

EMB5K True Dual-port

EMB5K supports any combination of dual-port operation: two read ports, two write ports, or one

read and one write at different clock frequencies. Figure 2-5 shows true dual-port memory



configuration.

Port A Port B

da[]

cea

clka

qa[]

db[]

ceb

clkb

EM

B5K

qb[]

aa[] ab[]

wea web

Figure 2-5 True Dual-port Memory Mode Table 2-3 Port Descriptions of True Dual-port Memory Mode

Port name Type Description

aa (b) Input Port A (B) Address.

da (b) Input Port A (B) Data Input.

qa (b) Output Port A (B) Data Output.

wea (b) Input Port A (B) Write Enable. Data is written into the dual-port SRAM

upon the rising edge of the clock when both wea (b) and cea (b)

are high.

cea (b) Input Port A (B) Enable. When cea (b) is high and wea (a) is low, data

read from the dual-port SRAM address aa (b). If cea (b) is low, qa

(b) retains its value.

clka (b) Input Port Clock.

Table 2-4 True Dual-port Configurations

A Port B Port

4K×1 2K×2 1K×4 512×8 512×9 256×16 256×18

4K × 1 √ √ √ √ 2K × 2 √ √ √ √ 1K × 4 √ √ √ √ 512 × 8 √ √ √ √ 512 × 9 √ 256 × 16 256 × 18

EMB5K Simple Dual-port

EMB5K also supports simple dual-port memory mode: one read port while one write port. Figure

2-6 shows simple dual-port memory configuration.



dw[]

wew

aw[]

qr[]

ar[]

EM

B5K

cer

cew

clkw clkr

Figure 2-6 Simple Dual-port Memory Mode

Table 2-5 Pin Descriptions of Simple Dual-port Memory Mode


dw Input Write Data

aw Input Write Address.

wew Input Write Enable, Active high.

clkw Input Write Clock.

cew Input Write Port Enable. Active high.

qr Output Read Data

ar Input Read Address.

cer Input Read Enable. Active high

clkr Input Read Clock.

Table 2-6 Simple Dual-port Configurations

W Port Read Port

4K×1 2K×2 1K×4 512×8 512×9 256×16 256×18

4K × 1 √ √ √ √ √ 2K × 2 √ √ √ √ √ 1K × 4 √ √ √ √ √ 512 × 8 √ √ √ √ √ 512 × 9 √ 256 × 16 √ √ √ √ √ 256 × 18 √

EMB5K Single-port

EMB5K also supports single-port memory mode shown as Figure 2-7.



we

ce

clk

q[]EM

B5K

a[]

d[]

Figure 2-7 Single-port Memory Mode

Table 2-7 Pin Description of Single-port Memory Mode


d Input Write Data

a Input Write Address.

we Input Write Enable. Active high.

clk Input Write Clock.

ce Input Port Enable. Active high.

q Output Read Data

Table 2-8 Single-port Configuration

Port

4K×1 2K×2 1K×4 512×8 512×9 256×16 256×18

2.3.4 Conflict Avoidance

In the dual-port memory mode, both ports can access any memory address at any time. When

both ports access the same address, the read and write behaviour should observe certain clock

timing restrictions. These restrictions are adaptable to both synchronous and asynchronous clocks.

2.4 DSP Block

The CME3000 devices have one column of 8 DSP MAC tiles. Within the DSP column, a single DSP

tile is combined with extra logic and routing.

+

dinx

diny

dinz

mac_out

acc_endinz_en sload

Xdinx_input_mode

mac_output_mode

diny_input_mode

dinz_input_mode



Figure 2-8 DSP Block

DSP tile contains an 18 x 18 bit two’s complement multiplier and a 40-bit sign-extended

accumulator, a function that is widely used in digital signal processing (DSP). Programmable

pipelining of input operands, intermediate products, and accumulator outputs enhances

throughput.

DSP provides features as below:

18-bit x 18-bit, two's-complement multiplier with a full-precision 36-bit result

Two-input, flexible 40-bit post- accumulator with optional registered accumulation feedback

Dynamic user-controlled operating modes to adapt DSP functions from clock cycle to clock

cycle

Performance enhancing pipeline options for control and data signals are selectable by

configuration bits

Registers, ensuring maximum clock performance and highest possible sample rates with no

area cost

One DSP support 2 independent 12x9 multiplier with 21 bits accumulator

2.4.1 DSP Primitive

Figure 2-9 shows MAC block as below.

a_dinx[13:0]

a_sload

clk

MAC

a_diny[9:0]a_dinz[20:0]

a_acc_ena_dinz_en

rst_n

a_mac_out[20:0]a_over_flow

b_dinx[13:0]

b_sload

b_diny[9:0]b_dinz[20:0]

b_acc_enb_dinz_en

b_mac_out[20:0]b_over_flow

Figure 2-9 MAC Block



Table 2-9 Port Definition Port Direction Width Description

a_dinx[13:0] I 14 Multiplicand inputs from ixbar to mult A MSBs，6 bit

LSBs for usage in 18x18 mode.

b_dinx[13:0] I 14 Multiplicand inputs from ixbar to mult B MSBs.

a_diny[9:0] I 10 Multiplier input from ixbar to mult A, LSBs of multiplier

input in 18x18 mode.

b_diny[9:0] I 10 Multiplier input from ixbar to mult B, MSBs of

multiplier input in 18x18 mode.

a_dinz[20:0] I 21 Ixbar and bypass inputs to mult A post add and post

add LSBs in 18x18 mode.

b_dinz[20:0] I 21 Ixbar and bypass inputs to mult B post add and post

add MSBs in 18x18 mode.

a_sload I 1 sloadA, when asserted directly loads the post add input

into the accumulator.

b_sload I 1 sloadB, when asserted directly loads the post add input

into the accumulator.

a_acc_en I 1 Accumulator A enable.

a_dinz_en I 1 Post adder A enable.

b_acc_en I 1 Accumulator B enable.

b_dinz_en I 1 Post adder B enable.

a_mac_out[20:0] O 21 Outputs to oxbar mult A.

b_mac_out[20:0] O 21 Outputs to oxbar mult B.

a_overflow O 1 mulA Overflow flag.

b_overflow O 1 mulB Overflow flag.

clk I 1 Clock input/scan clock input.

rstn I 1 Reset input, Active low.

Table 2-10 Parameter Table


mode_sel string MAC working mode select, default: 000.

signed_sel string Set signed/unsigned multiplication, true or false, default: true.

adinx_input_mode string a_dinx input mode setting: bypass or register, default: bypass.

adiny_input_mode string a_diny input mode setting: bypass or register, default: bypass.

adinz_input_mode string a_dinz input mode setting: bypass or register, default: bypass.

amac_output_mode string a_mac_out output mode setting: bypass or register

default: bypass.

bdinx_input_mode string b_dinx input mode setting: bypass or register, default: bypass.

bdiny_input_mode string b_diny input mode setting: bypass or register, default: bypass.

bdinz_input_mode string b_dinz input mode setting: bypass or register, default: bypass.

bmac_output_mode string b_mac_out output mode setting: bypass or register,

default: bypass.



2.4.2 DSP Usage Mode

The DSP can be used as two dependent 12x9 A-MAC and B-MAC or one 18x18 MAC function.

These MACs have the same functions is shown as Figure 2-8. The CME Primace® deals with use

input width and maps to 12x9 A-MAC and B-MAC or one 18x18 MAC automatically.

Table 2-11 Port Description Port name Type Description

clk Input mac clock,posedge active.

rstn Input mac reset, active low.

dinx Input mac multiplier input(Range:2..18).

diny Input mac Multiplier input(Range:2..18).

dinz Input mac input(Range:2..40).

sload Input accumulate load.

acc_en Input accumulate enble ,high active.

dinz_en Input adder enble,high active.

mac_out Output mac output(Range:2..40).

overflow Output mac overflow. 1 overflow;0 not Active high.

Note: The acc_en and dinz_en both are not active if they are both high.

Table 2-12 Parameter Description

Parameter Type Description

signedx_sel string “true” dinx input type is signed

“false” dinx input type is unsigned

signedy_sel string “true” diny input type is signed

“false” diny input type is unsigned

signedz_sel string “true” dinz input type is signed

“false” dinz input type is unsigned

dinx_input_mode string " bypass " input directly to multiplier ;

" register " input via register

diny_input_mode string " bypass " input directly to multiplier ;


dinz_input_mode string " bypass " input directly;


mac_output_mode string " bypass " mac output directly ;

" register " mac output via register

The x * y multiplier output will be an unsigned result only when both the x and y are unsigned,

otherwise be a signed and two’s complement result. The mac_out will be an unsigned result only

when both the dinz and multiplier output are unsigned, otherwise be a signed and two’s

complement result.



(1) Multiplier

Function Figure 2-10 describes the DSP is used as a Multiplier which outputs the dinx * diny result.

+

dinx

diny mac_outXdinx_input_mode

mac_output_mode

diny_input_mode

Figure 2-10 Multiplier

(2) Multiplier and adder

Function Figure 2-11 describes the DSP is used as a Multiplier and Adder which output the dinx *

diny + dinz result.

+

dinx

diny

dinz

mac_out

acc_endinz_en

Xdinx_input_mode

mac_output_mode

diny_input_mode

dinz_input_mode

Figure 2-11 Multiplier and Adder

(3) Multiplier and Accumulator

Function describes the DSP is used as a Multiplier and Adder which output the dinx * diny +

mac_out(n-1) result.



+

dinx

diny

dinz

mac_out

acc_endinz_en sload

Xdinx_input_mode

mac_output_mode

diny_input_mode

dinz_input_mode

Figure 2-12 Multiplier and Accumulator

2.5 Input/output Blocks

The Input/output Block (IOB) provides a programmable, bidirectional interface between an I/O pin

and the FPGA’s internal logic. The IOC is the function for a I/O pin. A simplified diagram of the IOC’s

internal structure appears in Figure 2-13. There are three main signal paths within the IOC: the

output path, input path, and tri-state path. Each path has its own pair of registers that can act as

registers. The three main signal paths are as follows:

The input path carries data from the pad, which is bonded to a package pin, through an

optional programmable delay element directly to the id line. There are alternate routes

through a register to the id line. The id line is lead to the FPGA’s logic.

The output path, starting with od, carries data from the FPGA’s internal logic through a

multiplexer and then a tri-state driver to the IOC pad. In addition to this direct path, the

multiplexer provides the option to registers.

The tri-state path determines when the output driver is high impedance. The oen line carries

data from the FPGA’s internal logic through a multiplexer to the output driver. In addition to

this direct path, the multiplexer provides the option to insert a register. When oen line is

asserted High, the output driver is high-impedance (floating, Hi-Z). The output driver is

active-Low enabled.

The output and tri-state paths entering the IOC have an inverter option. Any inverter placed

on these paths is automatically absorbed into the IOC.



REN

I

OEN

PAD

C

od

01

D Q

CKQresetn

setn

clk

2310

od_setn

od_resetn

1

0 txd

0

1id rxd

Q D

CKQ

resetn

setn

clk

id_resetn

id_setn

oen

10

D Q

CKQresetn

setn

clk

2310

oen_setn

oen_resetn

1

0 txe

R

Figure 2-13 IOC

The IOC Symbol is shown in Figure 2-14.

IOC

clk

setnrstn

odid

pad

oen

clken

Figure 2-14 IOC Symbol Table 2-13 IOC Port Definition

Port Width Direction Description

clk 1 I IO input clock

rstn 1 I IO input reset, active low

setn 1 I IO input set, active low

clk_en 1 I IO clock enable

oen 1 I IO output enable, active low

od 1 I Output data from fabric

id 1 O Input data from IO

pad 1 IO IO pad

Parameters

is_en_used string Whether external enable is used. Default: false

reg_always_en string Register for id/od/oen enable setting. True or

false, default: false

is_rstn_inv string Reset input invert enable, true or false, default:

false

is_setn_inv string Set input invert enable, true or false, default:



false

is_clk_inv string Clock input invert enable, true or false, default:

false

is_od_inv string Input data from fabric invert enable, true or false,

default: false

is_oen_inv string Output enable invert enable, true or false,

default: false

oen_sel string

Output enable mux selection control from

bypass/register/vcc(1)/gnd(0)

Default:bypass

od_sel string IO input data mux selection control from

bypass/register/vcc(1)/gnd(0)

id_sel string

IO output to fabric mux selection from

bypass/register

Default:bypass

oen_setn_en string Output enable register set enable

oen_rstn_en string Output enable register reset enable

od_setn_en string IO input register set enable

od_rstn_en string IO input register reset enable

id_setn_en string IO output register set enable

id_rstn_en string IO output register reset enable

2.5.1 Pull-Up Resistors

The optional pull-up resistors are intended to establish logic High, at unused I/Os. The pull-up resistor

optionally connects each IOB pad to VCCIO. The resistors are about 50K~100KΩ.These resistors are used

in a design using the PULLUP attributes in Primace aoc file.

2.5.2 ESD Protection

The Electro-Static Discharge (ESD) protection circuitries protect all device pads against damage from

ESD as well as excessive voltage transients.

The VIN absolute maximum rating in Table6-1 specifies the voltage range that I/Os can tolerate.

2.5.3 Drive Strength

CME3000 I/O current drive strength is programmable 2, 4, 8, 12, 16, 24mA

2.5.4 The Organization of IOBs into Banks

IOBs are allocated among 4 banks, so that each side of the device has one bank, as shown in Figure 1-1.

For all packages, each bank has independent VCCIO lines. For example, the VCCIO Bank 1 lines are

separate from the VCCIO lines going to all other banks.

2.5.5 The I/Os During Power-On, Configuration, and User Mode

With no power applied to the FPGA, all I/Os are in a high-impedance state. The VCCINT (1.0V) and VCCIO



supplies may be applied in any order. Before power-on can finish, VCCINT, VCCIO must have reached their

respective minimum recommended operating levels (see Table6-3). At this time, all I/O drivers also will

be in a high-impedance state.

VCCIO and VCCINT serve as inputs to the internal Power-On Reset circuit (POR). As soon as power is

applied, the FPGA begins initializing its configuration memory. At the same time, the FPGA internally

asserts the Global Set-Reset (GSR), which asynchronously resets all IOB registers to a pull-up state. A

Low level applied to nCONFIG input also serves as a GSR.

At this point, the configuration data is loaded into the FPGA. The I/O drivers remain in a

high-impedance state (with pull-up resistors) throughout configuration. The signal is released during

Start-Up, marking the end of configuration and the beginning of design operation in the user mode. At

this point, those I/Os to which signals have been assigned go active while all unused I/Os remain in a

high-impedance state.

2.6 Interconnect

All the CME3000 device tile includes Xbar which is interconnect, also called routing resources and

function element. The Xbar passes signals among the various functional tiles of CME3000 devices.

There are four kinds of interconnect: Octal lines, Triple lines, Single lines, and Diagonal lines.

Octal lines span the die both horizontally and vertically and connect to one out of every 8 and 4 Xbars

(see Figure 2-15).

Triple lines connect to one out of every 3, 2 and 1 Xbars horizontally and vertically (see Figure 2-15).

The octal and triple lines are very useful for one driver fanouting several tiles which span different

tiles numbers.

The octal and triple lines are very useful for one driver fanouting several tiles which span different tiles

numbers.

xbar xbar xbar xbar xbar xbar xbar xbarxbar xbar xbar xbar xbar xbar xbar

triple

octaloctal

triple

xbarxbar

Figure 2-15 Octal and Triple Lines

Single and Diagonal lines directly connect lines route signals to neighboring tiles: vertically,

horizontally. These lines most often drive a signal from a "source" tile to an octal and triple line

and conversely from the longer interconnect back to a direct line accessing a "destination" tile.



xbar xbarxbar

xbar xbarxbar

xbar xbarxbar

diagonal single

Figure 2-16 Single and Diagonal Lines

2.7 PLL

2.7.1 PLL features

• Input frequency: 5~472.5MHz

• PFD input frequency: 5 ~ 325MHz

• Output frequency: 10 ~ 450MHz

• VCO operating rang: 600 ~ 1200MHz

• Fixed quadrant phase shift: 0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°

• Clock bypass mode: Allow bypass of input clock directly to PLL output

• Power supply: DVDD: 0.9 ~ 1.1V, AVDD: 0.9 ~ 1.1V

• Output clock duty-cycle: 45-55%

• Power current consumption: < 2mA

• Power down current: < 20uA (VDDA)

• < 10uA(DVDD)

• Operation junction temperature: -40 to 125 °C

• PLL outputs: CO0, CO1, CO2, CO3

• Lock detection output

2.7.2 CME3000 PLL Hardware Description

CME3000 devices contain 2 PLLs (PLL0 and PLL1) with advanced clock management features. The

main goal of a PLL is to synchronize the phase and frequency of an internal or external clock to an

input reference clock. The PFD produces an up or down signal that determines whether the

voltage-controlled oscillator (VCO) needs to operate at a higher or lower frequency. The output of

the PFD feeds the charge pump and loop filter, which produces a control voltage for setting the

VCO frequency. The loop filter also removes glitches from the charge pump and prevents voltage



overshoot, which filters the jitter on the VCO. A divide counter (m) is inserted in the feedback loop

to increase the VCO frequency above the input reference frequency. VCO frequency (fVCO) is

equal to (m+1) times the input reference clock (fIN). The input reference clock (fIN) to the PFD is

equal to the input clock (fIN) divided by the pre-scale counter (N+1). Therefore, the feedback clock

(fFB) applied to one input of the PFD is locked to the fIN that is applied to the other input of the

PFD. The VCO output can feed 4 post-scale counters (C[0..3]), while the corresponding VCO output

from Top/Bottom PLLs can feed ten post-scale counters (C[0..3]). These post-scale counters allow a

number of harmonically related frequencies to be produced by the PLL.

Figure 2-17 shows a simplified block diagram of the major components of the CME3000 PLL.

1/(n+1) PFD Charge Pump

Loop Filter VCO

1/(c0+1)

post-divider

8

fVC

O

pre-divider

fREF

fFB

fIN

operation_mode

fbclkin

clkin

1/(m+1)

Lock

DIV2

loop-divider

pll_lock

1/(c0+1)

1/(c0+1)

1/(c0+1)

8

vco_divide_modeclkout0

clkout1

clkout2

clkout3

Figure 2-17 PLL block diagram

The dedicated pin CLK0~CLK3, XIN and OSC (internal configuration oscillator) and FPGA logic feed

the Bottom PLL0 clkin as the PLL clock input. The external feedback fbclkin must comes from the

dedicated pin CLK0~CLK3 or internal clkout0 if the PLL used as external feedback mode. The PLL

generates four clock outputs.

The Top PLL1 is same as the PLL0 only the clkin and fbclkin are come from the dedicated pin

CLK4~CLK7.

2.7.3 PLL Primitive Port Signal Definitions

CME3000 PLLs primitive module port signal definition and parameter table are shown in Table

2-14. The CME3000 PLL can be generated using the Primace wizard.

Table 2-14 Port Definition Port name Type Description

clkin Input Write Data

fbclkin Input Feedback input to the PLL. Come from the

dedicated CLK pin or PLL clkout0.

clkout0 Output PLL output 0 driving to the global clocks.







locked Output

Lock output from lock detect circuit. Active

high

pwrdown Input

Power down control.

1: Power on PLL

0: Power down PLL (default)

Table 2-15 Parameter Definition Parameters Type Description

pwr_mode string

PLL power mode.

"always_off": make PLL always stay in power down status

"always_on": make PLL always stay in power on status

"mcu_ctrl":" MSS 8051 mcu control the PLL power"

"fp_ctrl":" FP control the PLL power"

default："always_off",

operation_mode string

PLL feedback source path.

"internal_feedback": select the internal PLL output as the

feedback source

"external_feedback": select the external dedicated CLK pin as the

source

default: "internal_feedback"

rst_mode string

PLL reset mode

"auto": chip power on to reset the PLL automally

"mcu_control":MSS 8051 mcu control the PLL reset

test_control: reserved for chip test

default: "auto"

bandwidth_type string

PLL bandwidth setting

"low": filters out reference clock jitter but increases lock time"

medium": default

"high": provides a fast lock time and tracks jitter on the reference

clock source

vco_phase_shift string

VCO phase shift setting

VCO phase select from

the"0","45","90","135","180","225","270","315" degree.

default: “0”

co0_enable string

PLL CO0 output enable

"true": PLL CO0 output enable

"false" PLL CO0 output disable

default : "true"



co1_enable string




default : "false"

co2_enable string




default : "false"

co3_enable string




default : "false"

multiply_by(M) decimal PLL loop-divider setting, range is from 1 to 256

divide_by(N) decimal PLL pre-divider setting, range is from 1 to 256

co0_divide_by(C

0) decimal PLL output 0 counter setting, range is from 1 to 256

co1_divide_by(C


co2_divide_by(C


co3_divide_by(C


co0_delay_by decimal PLL output 0 to counter delay the VCO cycles , range is from 0

to255

co1_delay_by decimal PLL output 1 to counter delay the VCO cycles , range is from 0 to

255


255


255

co0_phase_shift string PLL output 0 to counter phase shift to VCO, select from the 8

"0","45","90","135","180","225","270","315" degree phase


"0","45","90","135","180","225","270","315" degree phase


"0","45","90","135","180","225","270","315" degree phase


"0","45","90","135","180","225","270","315" degree phase

The CME3000 device is a SoC device, the 8051 of MSS can control the PLL parameter such as

loop-divider M and pre-divider N. Post-divider C0, C1, C2 and C3 also can be modified or

reconfigured by 8051 in system. For more details, please refer to 3.7.5 MSS in System Clock



Configuration.

2.7.4 Clock Feedback Modes

CME3000 PLLs support up to two feedback modes. Each mode allows clock multiplication and

division, phase shifting. The mode is controlled by the operation_mode parameter.

(1) Internal Feedback Mode (Frequency Synchronous Mode)

In Frequency synthesize mode which the feedback is from the internal VCO, the PLL does not

compensate for any clock networks. This provides better jitter performance because clock

feedback into the PFD does not pass through as much circuitry.


Loop Filter VCO

1/(c0+1)

post-divider

8

fVC

Opre-divider

fREF

fFB

fIN

clkin

1/(m+1)

Lock

DIV2

pll_lock

8

vco_divide_mode clkout0

clkout1

clkout2

clkout3

1/(c0+1)

1/(c0+1)

1/(c0+1)

Figure 2-18 Internal Feedback Mode

fpfd = fIN /(N+1) ; fVCO = fIN *DIV2*(M+1)/(N+1), DIV2 = 1 or 2 ;

fFB = fVCO / m;

fclkout0 = fIN * (M+1) / ((N+1) * (C0+1));

fclkout1 = fIN * (M+1) / ((N+1) * (C1+1));

fclkout2 = fIN * (M+1) / ((N+1) * (C2+1));

fclkout3 = fIN * (M+1) / ((N+1) * (C3+1));

(2) External Feedback Mode

In external feedback mode, the external feedback input pin (fbclkin) is phase-aligned with the

clock input pin. Aligning these clocks allows you to remove clock delay and skew between the

devices. This mode is supported on all CME3000 PLLs. The feedback signal fbclkin comes from

internal global clock PLL clkout0 as the Figure 2-19 or clock pin CLK0~3/CLK4-7 as the Figure 2-20.

The clock pin CLK0~3/CLK4-7 is connected with the pin which is driven by the clkout0 on the board.




Loop Filter VCO

1/(c0+1)

post-divider

clkout0

8

fVC

O

pre-divider

fREF

fFB

fIN

fbclkin

clkin

1/(m+1)

Lock

DIV2

loop-divider

pll_lock

1/(c0+1)

1/(c0+1)

1/(c0+1)

clkout1

clkout2

clkout3

8

vco_divide_mode

Figure 2-19 Feedback Signal From clkout0


Loop Filter VCO

1/(c0+1)

post-divider

clkout0

8

fVC

O

pre-divider

fRE

F

fFB

fIN

fbclkin

clkin

1/(m+1)

Lock

DIV2

loop-divider

pll_lock

1/(c0+1)

1/(c0+1)

1/(c0+1)

clkout1

clkout2

clkout3

8

vco_divide_modepin

clk pin

IC

Figure 2-20 Feedback Signal From Clock Pin clk0~3/clk4~7

fpfd = fIN /(N+1) ; fVCO = fIN *DIV2*(M+1)/( (C0+1) (N+1)), DIV2 = 1 or 2 ;

fFB = fVCO / m;

fclkout0 = fIN * (M+1) / (N+1);

fclkout1 = fIN * (M+1) (C0+1) / ((N+1) * (C1+1));

fclkout2 = fIN * (M+1) (C0+1) / ((N+1) * (C2+1));

fclkout3 = fIN * (M+1) (C0+1) / ((N+1) * (C3+1));

2.7.5 Phase-shift Implementation

Phase shift is used to implement a robust solution for clock delays in CME3000 devices. Phase shift

is implemented by using a combination of the VCO phase output and the counter starting time.

The VCO phase output and counter starting time is the most accurate method of inserting delays,

since it is based purely on counter settings, which are independent of process, voltage, and

temperature. You can phase-shift the output clocks from the CME3000 PLLs in either of these two

resolutions:



■ Fine resolution using VCO phase taps

■ Coarse resolution using counter starting time

Fine-resolution phase shifts are implemented by allowing any of the output counters (C[3..0]) or

the m counter to use any of the eight phases of the VCO as the reference clock. This allows you to

adjust the delay time with a fine resolution. The minimum delay time that you can insert using this

method is defined by Equation 2-1.

IN

VCOf

fMN

fT

VCO )1(81

81

81

ine

++

===Φ

Equation 2-1 Equation 1

where fIN is the input reference clock frequency. For example, if fIN is 100 MHz, n is 1, and m is 10,

then fVCO is 1000 MHz and the minimum fine equals 125 ps.

Coarse-resolution phase shifts are implemented by delaying the start of the counters for a

predetermined number of counter clocks. You can express coarse phase shift as shown in

Equation 2-2.

INVCOcoarse

fMNC

fC

)1()1)(1(1

++−

=−

=Φ

Equation 2-2 Equation 2

where co_delay_by is the count value set for the counter delay time. If the initial value is 1,

co_delay_by – 1 = 0° phase shift.

Figure 2-21 shows an example of phase-shift insertion with the fine resolution using the VCO

phase taps method. The eight phases from the VCO are shown and labeled for reference. For this

example, CLK0 is based off the 0 phase from the VCO and has the co_delay_by value for the

counter set to one. The CLK0 signal is divided by four, two VCO clocks for high time and two VCO

clocks for low time. CLK1 is based off the 135° phase tap from the VCO and also has the

co_delay_by value for the counter set to one. The CLK1 signal is also divided by 4. In this case, the

two clocks are offset by 3. CLK2 is based off the 0 phase from the VCO but has the co0_delay_by

value for the counter set to three. This arrangement creates a delay of 2 coarse (two complete

VCO periods).



0°

45°

90°

135°

180°

225°

270°

315°

CLK0

CLK1

CLK2

1/8 tVCOtVCO

td0-1

td0-2

Figure 2-21 Phase Shift

You can use the coarse- and fine-phase shifts to implement clock delays in CME3000 devices.

2.8 Global Clock & Reset Resources

CME3000 global clock resources, include the dedicated clock inputs, buffers, and routing. The clocking

infrastructure provides 8 low-capacitances, low-skew interconnect global clock lines well-suited to

carrying high-frequency signals throughout the FPGA, minimizing clock skew and improving

performance, and should be used for all clock signals. These resources also can be used for high-fanout

signals.

2.8.1 External Crystal Input

XIN and XOUT are external crystal input and output pins respectively, frequency ranges from 10 to

20 MHz. When XIN works as external clock input, input clock connects to global clock tree through

XIN; meanwhile XOUT floats or connects to GND. The external crystal as clock input connection is shown as in Figure 2-22.

CME3000

XOUT

XIN

1M

22P 22P

10K

10~20M

Figure 2-22 External Crystal Input



2.8.2 Clocking Infrastructure

The global clock resources consist of two connected components: two clock generators blocks and

Global Clock routing network. The CME3000 clock network infrastructure is shown in Figure 2-23.

The clock generator 0 is located in the right of the bottom edge. The clock generator selects from

the dedicated pins CLK0 – CLK3, XI, 4 PLL0 outputs and fabric logic signals source to generate four

global clocks to the GBUFs(global buf). The clock generator 1 is placed in the right of the top corner.

Its function is same as the clock generator 0, only the dedicated pin CLK4 - CLK7 replaced the CLK0

– CLK3. Each clock generators has four Multiplexers named as CFG_DYN_SWITCH which can

deglitch and hand off between pairs of clock sources, including a clock from the other clock and

generator 4 global clocks to GBUFs. Two clock generators generate 8 global clocks to GBUFs. GBUFs are located in the vertical spine, just to the right of the FP fabric, as shown schematically in

Figure 2-23. Clocks from the clock generators are distributed to the GBUFs in a skew-balanced tree.

Each GBUF selects from the 8 spine clocks, a set of Gclks to distribute along its respective

horizontal seam. There are six seams, four for Fabric and two for I/O blocks.

The 2 IO GBUFs each select 2 Gclks for their seams. One MSS GBUF and EMIF GBUF also select one

GCLK from the 8 spine clocks for the clock of the MSS and EMIF interface.

Each of the four FP GBUFs selects 6 Gclks. In addition to the 8 spine clocks, the FP GBUFs may also

select from logic inputs from the FP fabric to distribute as Gclks. The four GBUFs are designed not

as full cross-bars, but as sparsely-populated crossbars, in order to reduce circuitry while providing

a fully nonblocking network (every PLL clock can reach every seam without blocking any other

clock from reaching any seam). A special GBUF selects from the 8 spine clocks, two more Gclks to

distribute to all FP fabric seams in a lowskew, recombinant mesh. These two clocks are rebuffered

from this point all the way down to PLBs without further selection or regional gating before final,

LBUF muxes, so may be connected in recombinant grids wherever their logic levels match. This

provides a very low-structural-skew option for any two clocks throughout the entire FP array; the

remaining Gclks and Rclks have flexible selectability and hierarchical gating, so cannot be

recombined between seams.

All 8 Gclks in each FP fabric horizontal seam are distributed in a skew-balanced tree to each RBUF.

RBUFs select regional clocks to four rows of PLBs above and four below the seam, in two PLB

columns, or to one SFB above and one SFB below the seam. The two low-skew Gclks are simply

rebuffered into the low-skew Rclk grid; at the top and bottom of their columns, they connect to

matching Rclks arriving from the adjacent seam.

LBUFs are the last stage in the clock tree; they directly drive the flipflops. LBUFs provide local,

precise clock gating. Each two PLBs contain an LBUF, to select a local clock for its 8 registers from

the 6 Rclks; each SFB contains one or more LBUFs, one per clock domain, as needed.



PLL0XIN

PLL1 clk4-clk7

LogicInputs

6

6

6

4

4

4LogicInputs

4LogicInputs

4LogicInputs

2

2

2

IO

IO

2

2

2

……

6GCLK

GCLK

clk0-clk3

Clock generator

MSS

EMIF

4

4

4……

……

……

……

gclk to EMIF clock

gclk to MSS clock

Spine…

66

2

Gclk[4]~Gclk[7]

Gclk[0]~Gclk[3]

SEAM

…

FP input

FP input

LBUF

LBUF

……

LBUF

LBUF

……

Mux & deglitch

Mux & deglitch

GBUF

GBUF

Gbuf4:1*2

Gbuf4:1*2

gbuf2:1*6

gbuf2:1*6

gbuf2:1*6

gbuf2:1*6

Gbuf4:1*2

RBUF

RBUF

RBUF

RBUF

LBUF

LBUF

LBUF

LBUF

RBUF

RBUF

RBUF

RBUF

Figure 2-23 Clock Infrastructure

2.8.3 Clock Switch

The clock generator contains one PLL and a four deglitch CFG_DYN_SWITCH multiplexer. Each of

the four CFG_DYN_SWITCH multiplexer generates a gclk clock. The CFG_DYN_SWITCH multiplexer

not only can be used as a static clock path but also can provide seamless clock dynamic switchover

between two clock sources in system, for both startup sequencing and entering and exiting

low-power operating modes.

The primitive CFG_DYN_SWITCH h is used to implement the clock dynamic switching in system.

The CFG_DYN_SWITCH select and control is controlled by MSS. How to use the dynamic clock

switch function is described in 3 MSS Subsystem.

Table 2-16 CFG_DYN_SWITCH Port Definition


in0 Input gclk clock source 0 input.

in1 Input gclk clock source 1 input.

out Output global clock to GBUF.

Table 2-17 Parameter Descriptions of CFG_DYN_SWITCH Parameters name Type Description

gclk_mux digital define the CFG_DYN_SWITCH location.



Table 2-18 Clock Routability Table GCLK IN0 IN1

GCLK[0]/

gclk_mux 0

PLL0O0 PLL0O1 CLK0 CLK1 PLL0O2 PLL0O3 FP

GCLK[1]/

gclk_mux 1

PLL0O1 PLL0O3 CLK2 CLK3 PLL0O0 PLL0O2 GCLK[4] FP

GCLK[2]/

gclk_mux 2

PLL0O1 PLL0O2 CLK1 CLK2 PLL0O0 PLL0O3 XIN FP

GCLK[3]/

gclk_mux 3


GCLK[4]/

gclk_mux 4

PLL1O0 PLL1O1 CLK4 CLK5 PLL1O2 PLL1O3 FP

GCLK[5]/

gclk_mux 5

PLL1O1 PLL1O3 CLK6 CLK7 PLL1O0 PLL1O2 GCLK[0] FP

GCLK[6]/

gclk_mux 6


GCLK[7]/

gclk_mux 7


For each of the eight GCLK, the CFG_DYN_SWITCH input in0 and in1 only can be fed as the table.

The MSS control to select the in0 or kin1 in system via the special extended SFR. How to use the

dynamic clock switch function is described in MSS Subsystem chapter.

2.8.4 Reset Networks

The CME3000 device provides a special reset network for synchronous or asynchronous reset logic.

The reset network which contains eight global resets has the same infrastructure as the clock

network and is parallel with the clock network from the clock generator to LBUF. The special reset

network directly supports user design global resets which are synchronized once for each clock

domain that emerges from a clock generator. The global reset can assert asynchronously and

de-assert synchronously, the synchronized versions will remain associated with its respective clock

through all muxes, down to the RBUF level.

The Primace will deal with the synchronous or asynchronous reset and route it to the special reset

network automatically. The reset network resources can save the global clock resources usage.

3 MSS Subsystem

MSS Subsystem is composed of 200MHz enhanced 8051 processor, embedded peripherals, SRAM

and other components which are inte8051rconnected via the Xbar or hardware connection. The

chapter only describes the MSS system and functions which are special for the CME3000 device.

The enhanced r8051xc2 core and peripherals are described in 8051 User Guide.

The MSS features are as follow:



Enhanced 8051MCU

- Reduced instruction cycle, 12 times in respect of standard 8051 MIPS, up to 200MHz

- Compatible 8051 instruction system

- On-chip debugger system (OCDS), online JTAG debugging

- Up to 8M data/code memory

Embedded SRAM Memory

- 128KByte single port memory SRAM, up to 200MHz

- Data/code unified addressing, flexible memory configuration

- 4 channels DMA

Peripheral

- 1 MDU

- 3 16-bit Timers, Timer 2 can used as capture unit

- 1 16-bit Watch Dog Timer

- 1 I2C Interface

- 1 SPI Interface

- 2 Full Duplex Asynchronous Series Ports

- 1 RTC

Suspend, Idle Mode Power Management

Chip system management

- ISC control

- Dynamic clock management

Figure 3-1 describes the functions and connections of MSS and FPGA.

SFR

Peripheral

I2C

RTC

SPI

8051 MCU

SRAM

EMIF

SFR

MSS

USARTInterruptP0,1,2,3...

SFR

EMIF

IO Blocks

IO Blocks

IO B

locksIO B

lock

s

Fabric

PLB PLB PLB PLB

PLB PLB PLB PLB

PLB PLB PLB PLB

PLB PLB PLB PLB

PLB PLB PLB PLB

PLB PLB PLB PLB

PLB PLB PLB PLB

PLB PLB PLB PLB

gclk

ISC

FPGA

I2C

SPI

P Port

MA

CM

AC

MA

CM

AC

MA

CM

AC

MA

CM

AC

EMB

EMB

EMB

EMB

EMB

EMB

EMB

EMB

Figure 3-1 MSS Diagram



3.1 8051 Instantiation

In the view of a user design, the 8051 IP is considered to be a macro block as other SFBs, which

will be instantiated in the RTL code of the user design. The 8051 tile also contains Xbar which is

used to connect with other tiles.

3.1.1 8051 Macro Primitive Description

Table 3-1 8051 Port Definition Name Type Bus size Description

Global Interface

clkcpu I 1 MSS 8051 clock, come from MSS GBUF or internal

OSC.

clkcpuen O 1 is low when cpu is in STOP and IDLE mode.

clkperen O 1 is low when cpu is in IDLE mode.

resetn I 1 MSS reset，Low active.

ro O 1 MSS core reset output.

swd I 1

Start Watchdog Timer input.

High level on this pin during reset starts the

watchdog Timer immediately after reset is released.

SPI Interface

scki I 1 Serial clock input.

scko O 1 Serial clock output.

scktri O 1 Serial clock tri-state enable.

ssn I 1 Slave select input.

misoi I 1 “Master input / slave output” input pin.

misoo O 1 “Master input / slave output” output pin.

misotri O 1 “Master input / slave output” tri-state enable.

mosii I 1 “Master output / slave input” input pin.

mosio O 1 “Master output / slave input” output pin.

mositri O 1 “Master output / slave input” tri-state enable.

spssn O 8 Eight slave select output .

I2C Interface scli,

I 1 Serial clock input.

sdai,

I 1 Serial data input.

sclo,

O 1 Serial clock output.

sdao,

O 1 Serial data output.

General I/O



Name Type Bus size Description

port0i I 8 8-bit input port.

port0o O 8 8-bit output port.

port1i I 8 8-bit input port, combine with int2-7, ccu, t2, rxd1.

port1o O 8 8-bit output port, combine with ccu, txd1.

port2i I 8 8-bit input port.

port2o O 8 8-bit output port.

port3i I 8 8-bit input port, combine with int0-1, rxd0, t0, t1.

port3o O 8 8-bit output port, combine with txd0, rxd0o.

EMIF Interface

clkemif I 1 EMIF interface clock.

memack I 1 Memory acknowledge.

memdatai I 8 Memory data input.

memdatao O 8 Memory data output.

memaddr O 23 Memory address.

memwr O 1 Memory write enable.

memrd O 1 Memory read enable.

Hold Interface

hold,

I 1 Hold mode request, active high.

holda O 1 Hold mode acknowledge signal.

intoccur O 1 Interrupt occure in hold mode signal.

waitstaten O 1 Waitstate indicator, active low when 8051 performs

a wait cycle.

Table 3-2 Parameter Table


rtc_div_num String Mcu rtc divide number.

sync_mode_en String Mcu synchronous mode enable,

true: synchronous mode, false: asynchronous mode.

program_file String Mcu/8051 program file: *.hex.



3.2 MSS Clock Description

clkemif

clkcpu

8051

clk

SRAM

GCLK from EMIF GBUF

GCLK from MSS GBUF

Figure 3-2 MSS Clock

The clock signal gclk comes from the 8 global clocks, see Figure 2-23. The SRAM clock and clkcpu

use the same clock.

3.3 MSS Memory Map

CME3000 integrates 2 block of 64KByte total 64KByte SRAM. The 128KByte SRAM is only available

by MSS. 8051 accesses SRAM, up to 200MHz.

The 8051 MCU core can extend both Program Memory and External Data Memory (independently)

up to 8MB by means of dedicated page address register. But CME3000 ORs the 8051 write and

read program and external data signals to one write and read signals, this make the program and

external data memory share the memory space. The program memory is from address 0 up to

increase, the reset and interrupt vectors are stored in the low memory. The 128KB SRAM can be

used as or program or external data memory. Users must part program and external data memory

space not make them overlap.

The parameter program_file is used to locate the 8051 firmware *.hex file which will be the part of

the initialized data and add to configuration file.

Figure 3-3 describes the CME3000 MSS memory map which include the FP extend memory.

FP Expand

128K SRAM

7FFFFF

1FFFF

000000

20000

Figure 3-3 MSS Memory Map



3.4 MSS External Memory Interface (EMIF)

EMIF is used to extend the MSS memory, address 20000~7FFFFF, implemented with Fabric.

The CME3000 provides synchronous and asynchronous EMIF for Fabric extended memory which

has the same data/address and control ports but have different timing waveforms. The

synchronous or asynchronous EMIF mode is selected by the parameter sync_mode_en.

Table 3-2 EMIF Port Description

Port name Type Width Description

clkemif Input 1 Fabric EMIF clock. Posedge active.

memaddr Output 23 EMIF Address，MSS to Fabric.

memdatai Input 8 Read Data，Fabric to MSS.

memdatao Output 8 Write data，MSS to Fabric.

memrd Output 1 Read Enable. High active.

memwr Output 1 Write Enable. High active.

memack Input 1 Fabric to MSS operation acknowledge.

(1) Synchronous EMIF

The Fabric extend memory uses the same clkcpu as the 8051 clock, the signals are connected

directly to Fabric. See the MSS Subsystem User Guide for detailed description and waveform on

synchronous mode.

The synchronous EMIF connection with fabric is shown as in Figure 3-4:

8051 Fabric

clkcpu

clkcpu

memaddr

memdatao

memdatai

memwrmemrd

memack

clkcpu clkemif

Figure 3-4 sync_mode_en is “true”



(2) Asynchronous EMIF

The Fabric extend memory is in clkemif clock domain which is different with the 8051 clkcpu clock

domain. The hardware SyncBridge is used to synchronize the control signals from one side clock

domain to the other side clock domain during the memory accessing process. EMIF implemented

two-way synchronization between Fabric clock domain and MSS clock domain of Fabric operated

by EMIF bus. Each read/write operation of Fabric extending memory takes about 4 clkemif

cycles+3 8051 clock cycles.

The asynchronous EMIF connection with fabric is shown as in Figure 3-5:

SyncBrige

8051 Fabric

clkcpu

memwr_cpu

clkemif

memrd_cpu

memaddr

memdatao

memdatai

memack_cpu

memwrmemrd

clkcpu clkemif

Figure 3-5 sync_mode_en is “false”

Control signals of “memrd”, “memwr” and “memack” are in the clkemif domain and generated on

the posedge clkemif. The “memrd”, “memwr”, “memack” control signals and memaddr, memdatao

bus will be held if the memack valid is not sent to 8051 core.

When reading, Fabric places the read data to memdatai bus and not outputs a valid “memack”

after one or several cycles until the fabric data is ready after the memrd is asserted.

EMIF read waveform is shown below:

memaddr

clkemif

memrd

memack

memdatai

... ...

... ...

Figure 3-6 EMIF Read Waveform



In write cycle, Fabric writes the memdatao to extended memory when the memwr is asserted and

send a valid “memack” to MSS on the next cycle.

EMIF write waveform is shown below:

... ...

...

clkemif

memaddr

memwr

memack

memdatao

Figure 3-7 EMIF Write Waveform

3.5 Multiplex of P Port Pins

Some function pins, such as: external interrupt1, USART0, USART1, Timer 0~2, and Compare –

Capture Unit, share pins with port1 and port3. The following shows the details.

Table 3-3 Port Pin Multiplex

Name Type Polarity Bus size

Alternate Port Description

External Interrupts Inputs

int0 I Low/Fall port3i[2] External interrupt 0

int1 I Low/Fall port3i[3] External interrupt 1

int2 I Fall/Rise port1i[4] External interrupt 2

int3 I Fall/Rise port1i[0] External interrupt 3

int4 I Rise port1i[1] External interrupt 4




Serial 0 Interface

rxd0i I 1 port3i[0] Serial 0 receive data

rxd0o O 1 port3o[0] Serial 0 transmit data

txd0 O 1 port3o[1] Serial 0 transmit data or receive clock in mode 0

Serial 1 Interface

rxd1 I 1 port1i[0] Serial 1 receive data

txd1 O 1 port1o[1] Serial 1 transmit data

Timers Inputs

t0 I Fall port3i[4] Timer 0 external input



Name Type Polarity Bus size

Alternate Port Description



t2ex I Fall port1i[5] Timer 2 capture trigger

Compare – Capture Unit

cc(0) I Rise/Fall port1i[0] Compare/Capture 0 input

cc(1) I Rise port1i[1] Compare/Capture 1 input



Ccubus[0] O 1 port1o[0] Compare/Capture 0 Output




3.6 RTC

The RTC circuitry has analog and digital parts. The 8051 RTC SFRs and control signals are

partitioned to the CME3000 device core VCCINT power domain, while the internal time counters

relative circuitry is partitioned to RTC power domain. The RTC analog circuitry is in the RTC power

domain. The external battery supply the RTC power via the VCCRTC and GNDRTC pins and make

run whether the CME3000 device is power on or down. The circuitry partition make the battery

run long time.

The RTC crystal connection circuitry is shown as Figure 3-8.

CME3000

RTCXO

RTCXI

10M

100K

22P22P32.768K

Figure 3-8 RTC Crystal Connection Circuitry

3.7 MSS in System Management

The MSS can control some components of CME3000 such as special configuration register, PLL and

CFG_DYN_SWITCH Multiplexer registers in system via some special extended SFRs. The MSS does

the ISC, PLL reconfiguration and clock dynamic switch functions indirectly in system by operating

the extended SFRs.



3.7.1 Device Register

The device registers decide and control the device working functions and status directly. There are

two types of registers, one is the ISC register, the other is the PLL and gclk_switch multiplexer clock

registers.

Table 3-4 ISC Register Register Location Attribute Reset Value Description

ISCREG 1 R/W 0x00000000 [31:8]: Flash start address for read

access

[0]: Bit0 ISCEN: reconfiguration enable,

be used to trigger the reconfiguration

sequence, auto clear

0: disable 1:enable

Table 3-5 Global Clock Register

Register Location Attribute Reset

Value Description

DIVM 6 R/W 0 PLL 0/1 loop-divider M

DIVN 5 R/W 0 PLL 0/1 pre-divider N

DIVC0 4 R/W 0 PLL 0/1 post-divider C0




DYN_ TRL[7:0] 0

R/W 0 Dynamical control register

[7:6]: reserved

[5]: Pll 0/1 reset control bit

1:reset PLL, 0: PLL work

[4]: pll 0/1 power down control bit

0:Down PLL,1:On PLL

[3:0]:see Table 3-6 Clock Routability table

[3]: CFG_DYN_SWITCH 3/7 output select

0: gclk source is in0,1: gclk source is in1







3.7.2 ISC Register Frame

Accessing the ISC register should follow the frame below which first is a 32-bit header and follows



a 32-bit write or read data.

Table 3-7 ISC Header Format Bit[31:29] Bit[28] Bit[27] Bit[26] Bit[25] Bit[24] Bit[23:10] Bit[9:0]

3’h001 0 1 0 1: write

0: read

0 14’h1f 1

3.7.3 Extended SFR

There are three types of SFR, ISC SFR, RTC SFR, global clock SFR and direct switch SFR.

The ISC SFR is used to transform the data between the MSS and device register. The MSS uses the

RTC SFRs to access RTC internal registers. The MSS manages the clock functions via the clock SFR.

The MSS access and control the relative function directly via the direct switch SFR.

Table 3-8 Register Definition Register Location Attribute Reset Value Description

ISCDATD0 AC R/W 0x00 ISC data [7:0]

ISCDATD1 AD R/W 0x00 ISC data [15:8]

ISCDATD2 AE R/W 0x00 ISC data [23:16]

ISCDATD3 AF R/W 0x00 ISC data [31:24]

ISCCMD F2 R/W 0x00 [7]

[1] Head and Data write,

1:trigger to write, self clear when done

ISCHEADER0 F3 R/W 0x00 ISC header [7:0]




RTCCMD E5 R/W 0x00 [7]WRITE go

1: write serial command,

self cleared when done

[6:0] reserved

RTCSEL E6 R/W 0x00 [7:5]reserved

[4] 1:write operation,0: read operation

[3:0] Register Address defined in RTC

(see MSS 8051 Subsystem User Guide).

RTCDATA E7 R/W 0x00 write or read RTC data

GCLKCMD F8 R/W 0x00 [7]WRITE go

1: write serial command,

self cleared when done

[6:0] reserved

GCLKADDR F9 R/W 0x00 [7]reserved

[6:5]clock generator select



Register Location Attribute Reset Value Description

00: clock generator 0

01: clock generator 1

[4] WRITE/READN

1:write

0:read

[3:0] Register address defined in clock

register table

GCLKDATA FA R/W 0x00 write to or read from global clock data

ISMDIRCTRL FB R/W 0x00 [7] PLL 1 locked status, 1: locked ,0: not

locked

[6] PLL 0 locked status, 1: locked ,0: not

locked

[5:1] Reserved

[0] MSS clock switch

1:select the gclk

0: select the internal oscillator

3.7.4 MSS In System Configuration

The configuration Image of CME3000 consists of FPGA configuration data and MSS programming

code. FPGA configuration data sizes are substantially the same, while MSS code size changes with

the size of program. The configuration Image is stored In SPI FLASH. Sector is the smallest unit to

store Images, with a size as big as 0x30000. And one Image can take more than one Sectors. Figure

3-9 describes mapping of multi-Image stored in SPI FLASH, therein the Image size is smaller than

three sectors. Configuration packer in Primace can generate .mcf file with multi Images, while

Download can download Images of .mcf into SPI FLASH once. Utilizing ISC features, CME3000 can

make use of SPI FLASH space to expand the CME3000 device volume in return, and in other words,

CME3000 can fulfill several CME3000 FPGA if each of the multi image logic can be implemented by

CME3000.



0000000

0030000

ISCREG

Configuration

Jinshan

SPI Interface

ISCEN0060000

………

SPI-FLASH address

Image1bitstream

firmware

Image2bitstream

firmware

Image3bitstream

firmware

MSS

ISCCMD

ISCDATA

SFR

ISCHEADER

Figure 3-9 ISC

The following example describes that the 8051 program reconfigure the CME3000 device using the

Image2.

Write SPI-FLASH Image start address to device ISCREG[31:8], then set ISCREG[0] to trigger the

configuring process.

ISC steps are as follow:

//Switch the 8051 clock to internal osc

1) ISMDIRCTRL = 0;

//Write frame header, refer to Table 3-9 ISC Header Format

2) ISCHEADER0 = 0x01;

ISCHEADER1 = 0x7c;

ISCHEADER2 = 0x00;

ISCHEADER3 = 0x22;

//Write SPI-FLASH address and trigger the reconfiguration, refer to Table 3.3 ISC Register

3) ISCDATA0 = 1;

ISCDATA1 = 0x00;

ISCDATA2 = 0x00;

ISCDATA3 = 0x03;

//Write ISCCMD to enable data write to ISC register

4) ISCCMD = 0x1 //Switch the 8051 clock to gclk

5) ISMDIRCTRL = 1;



3.7.5 MSS in System Clock Configuration

The user must be familiar with the clock network path form the clock sources to the special gclk

and the mechanism if user want to use the in system clock configuration. See the Global clock

(1) PLL Configuration

MSS can reconfigure the PLL and make the PLL output another frequency. The following example is

to change the PLL0 clkout0 frequency from 100MHz to 50MHz. See the Table

fIN = 20MHz, m = 40, n =1, c0 =8;

fVCO = = fIN * (m / n) = 800MHz;

fclkout0 = fVCO / c0 = fIN * (m / (n * c0)) = 100MHz;

The steps are as follow:


1) ISMDIRCTRL = 0; 2) Select the PLL0 in PLL wizard of Primace.

//Write GCLKADDR to select PLL0, DIVC0(4)

3) GCLKADDR = 00010100B

//Write new c0 to GCLKDATA

4) GCLKDATA = 16 //Write new c0 to PLL C0 register from GCLKDATA

5) GCLKCMD = 0x80 //Switch the 8051 clock to gclk

6) ISMDIRCTRL = 1;

After the steps, the clkout0 of PLL0 will output a 50MHz clock.

(2) GCLK Dynamic Switch

MSS can switch the gclk from one clock to another clock dynamically. The following example is to switch the GCLK[5] from PLL1 clkout1 to PLL1 clkout0. The steps are as

follow:


1) ISMDIRCTRL = 0; 2) Select the PLL1 in PLL wizard of Primace.

3) Instantiate the CFG_DYN_SWITCH make the parameter gclk_mux is 5

4) Connect the PLL1 clkout0 to in1 and clkout1 to in0 of CFG_DYN_SWITCH

//Write GCLKADDR to select PLL1, DYN_ TRL[7:0] (0)

5) GCLKADDR = 00110000B

//Write new DYN_ TRL to GCLKDATA, select the clkin1 as the source of gclk[5]



6) GCLKDATA = 00010010 //Write new value to DYN_ TRL register from GCLKDATA

7) GCLKCMD = 0x80 //Switch the 8051 clock to gclk

8) ISMDIRCTRL = 1;

(3) MSS Clock Dynamic Switch

The MSS also can be switched dynamically using the CFG_DYN_SWITCH or between the gclk and

the internal OSC. All the above 8051 In System managements should switch the MSS clock to OSC

before the actions.

The switching between the gclk and OSC steps are shown below:

//MSS clock switch to gclk

1) ISMDIRCTRL = 0x1

//MSS clock switch to OSC

1) ISMDIRCTRL = 0x0

4 Configuration and Debug

4.1 Configuration Mode

There are 3 configuration modes: JTAG, AS and PS mode. AS, PS mode configuration are controlled

by a mode-select pin MSEL, as described in Table 4-1.

Note: CME3000 with FLASH only provides 2 modes, AS and JTAG, without MSEL pin.

Table 4-1 Configuration Mode Mode select pin

Mode Description MSEL

0 AS Active Serial mode. The chip will be configured

automatically. Configuration data is stored in the SPI flash.

1 PS Chip acts as slave.

External microcontroller feeds configuration data into the

chip.

0/1 JTAG JTAG-based configuration. This mode takes high privilege

over AS and PS modes

4.1.1 AS Mode

In AS configuration mode, CME3000 POR or pin nCONFIG reset reads configuration data from SPI



flash 0 address automatically, and configures FPGA and embedded RAM of MSS.

The following figure describes the AS mode of CME3000 without FLASH.

Pin 1 Pin 2

JTAG

VCCVCC

TMS

TDI

TCK

TDO

nCONFIG

10K

10K10K

nCSO

sclk

SDO

SDI

MSEL

SPI Flash

CS#

sclk

SI

SO

10K

Figure 4-1 AS Configuration Without Flash

Figure 4-2 describes the AS mode of CME3000 with FLASH.

Pin 1 Pin 2

JTAG

VCCVCC

TMS

TDI

TCK

TDO

nCONFIG

10K

10K10K

10K

MSEL

Figure 4-2 AS Configuration With Flash

4.1.2 PS Mode

In the PS mode, CME3000 works as slave device, receive configuration data from external master

controller passively. SPI Master cannot read configuration data from CME3000.

Figure 4-3 describes CME3000 in PS configuration.



Pin 1 Pin 2

JTAG

VCCVCC

TMS

TDI

TCK

TDO

nCONFIG

10K

10K10K

nCSO

sclk

SDO

SDI

MSEL

SPI Master

CS#

sclk

SI

SO

VCC

10K

Figure 4-3 PS Configuration

4.1.3 JTAG Mode

There are two JTAG devices inside CME3000, one is for fabric debugging and configuration,

another is for OCDS of MCU, in order to make it convenient and to decrease cost, these two JTAG

devices are cascaded into one according to the IEEE standard.

In JTAG mode, JTAG host computer configures and debugs both FPGA and MSS through CME3000

JTAG interface.

JTAG interface has higher priority than other configuration mode, and can access and debug

configuration prior in any mode.

4.2 SPI Flash

SPI-Flash used for configuring CME3000, no matter embedded or external configured can be

operated in user mode.

(1) Using embedded SPI-Flash

Invoke spi interface to in user design, to use SPI-FLASH in CME3000 device. For embedded

SPI-Flash datasheet, please refer to GD25QXX_Rev1.0.pdf.

Table 4-2 Embedded SPI Interface Port Port name Type Description

sclk Input spi flash input clock




sdo output spi flash serial output data

cson Input spi flash chip select，low active

sdi Input spi flash serial input data

(2) Using External SPI-Flash

When using external SPI-Flash, connections should follow Figure 4-1, and set corresponding IO as

user IO during user design, see SPI contents of 7.1 Pins Definitions and Rules and 7.2 Pin List .

4.3 ISC

ISC (In System Configuration) can make MSS re-configure CME3000 dynamically or statically. ISC

can only be achieved in AS mode.

Static re-configuration, MSS program writes addresses and instructions to ISC corresponding SFR

to make CME3000 re-load corresponding Image from certain SPI Flash address to reconfigure

CME3000 device.

Dynamic re-configuration, MSS program reads Image from external (USART or other interfaces),

and writes to corresponding Image space through SPI interface, updates the Image. Then MSS

writes addresses and instructions to corresponding ISC SFR to configure CME3000 with the

updated Image. More details see 3.7.4 MSS In System Configuration.

4.4 Debug

There are two JTAG devices inside CME3000, one is for fabric debugging and configuration,

another is for OCDS of MCU, the two JTAG devices are cascaded into one according to the IEEE

standard. The CME3000 device identifies the different device operations and transforms the data

to the right JTAG device automatically. Using the same JTAG interface can access the FPGA and

debug the MSS.

4.5 Power-On-Reset (POR)

CME3000 device has internal POR circuits to monitor VCCINT and VCCIO voltage levels during

power-up. The POR circuit keeps the device in reset state until VCCINT and VCCIO reach the trigger

point. After the device enters into user mode, the POR circuit continues monitoring the VCCINT

voltage levels but not VCCIO anymore. POR also be controlled by external manual reset control

signal.

The POR circuit has the following features:



Power up monitor, trigger point:

- VCCINT： 0.75V-1.08V

Power down monitor, trigger point:

- VCCINT: 0.65V-0.9V

Low level monitor VCCINT

Delay time: typical 4.9ms, range 3.3ms ~ 7.4ms

5 Security

The CME3000 devices have several security levels to help protect customer products and profits. - Configuration bitestream encryption using 128 bit AES

- Efuse based protection mechanism

- SPI based flash protection mechanism

5.1 Bitstream Generation Security Level

During the test and debug phase of a design, you can decide to leave the JTAG interface in the

design for possible maintenance or for random check-ups after the design goes into production. While this is handy for the designer, it can leave a potential security hole. The Bitstream Generator adds security information to configuration .acf file based on the security

setting in Primace. The Bitstream Generator has three settings; the first one is the default, and the

remaining two are optional and provide additional security. As shown in Table 1, JTAG can be

optionally disabled completely or disabled except to special configuration memory space via JTAG.

Table 1 Bitstream Generator Security Level Settings Security Level Description

None Default. JTAG unrestricted access to all configuration memory and functions Level1 Disable JTAG to access the SPI-FLASH, fabric configuration memory or MSS

memory Level2 Disable JTAG to access any memory completely

There are three settings such as prot_flagn, read_disable0, read_disable1 for Bitstream Generator

in Primace. The Bitstream Generator will add security bits to the configuration bitstream if the

settings are set. User decides the Bitstream Generator to use a 128 bit key set in Primace as the

AES algorithm input to encrypt the bitstream or not on all the three levels.

(1) prot_flagn

The prot_flagn security bit will be programmed to SPI-FLASH if the prot_flagn setting is set. The



security bit is employed to protect flash content, to prevent fabric and register reading/writing,

and to prevent accessing MCU memory space via OCDS. Once prot_flagn is asserted, only several

flash instructions can be sent to flash, e.g. WREN, BE, RDSR, WRSR. So The SPI-FLASH can’t be

accessed by JTAG except the erase operation.

An internal signal prot_flagn is employed to obtain value of the security bit and to control the

security protection. On power up, the prot_flagn security bit stored in the SPI-FLASH is not loaded

to the internal prot_flagn, so the internal prot_flagn is default LOW and active. User must send a

specified set of JTAG instruction to transfer the prot_flagn bit from SPI-FLASH to internal

prot_flagn signals which is then used to provide security control over the whole chip referring to

user setting.

(2) read_disable0

The security signal read_disable0 is stored in the internal register after the device is configured by

the bitstream. The signal read_disable0 which is high active is used to prevent fabric chain reading,

and to prevent accessing MCU memory space via OCDS.

On power up, read_disable0 is default 0 to enable JTAG read. The read_disable0 bit stored in the

internal register will load to the read_disable0. If it is written with 1, then it can’t be changed by

writing with 0.

(3) read_disable1

The security signal read_disable1 is generated by the SECU chain which contains many bits. The

signal read_disable1 is also used to prevent fabric chain reading, and to prevent accessing MCU

memory space via OCDS.

On power up, read_disable1 is 1, enable the security protection. If the SECU chain matches the

fixed data pattern then read_disable1 transits to 0 so that read_disable1 is de-asserted and JTAG

can read.

The JTAG can’t read the fabric chain and MCU memory space if anyone of the three security

signals is active.

5.2 On-Chip eFuse

The eFUSE is a macro that contains electrically programmable fuses which is One Time Program

memory. Read operation requires only standard core voltage supply and the programming voltage

for write operation is external supply.

The CME3000 device has two 128bit eFUSE. The eFUSE0 is used to store the 128 bit AES cipher key

which is used for Primace bitgen tool to generate the encrypted configuration bitstream. The

eFUSE1 is used to store the security protection bits and other reserved information.



The security bit Table

eFUSE1 Bit Description

[5]

Decryption flag:

1: the key stored in Efuse0 used to decrypt the bitstream, the key must matches

the key which is input for encryption by user in Primace.

0: do not require decrypt the bitstream.

[4] JTAG & OCDS disable:

1: disable the JTAG operation whether the Security Level Settings is set or not.

The cipher key and security bits can be programmed to eFUSE0/1 by Primace tool to prohibit the cloners, overbuilders, and reverse engineers from embezzling your design whether or not the embedded SPI-FLASH or external SPI-FLASH is used to configure the device. E-fuse 1 can be read out via JTAG at any time, E-fuse 0 can’t be read out via JTAG any way.

5.3 Embedded SPI-Flash Hidden Bitstream

The embedded SPI-Flash is used to store CME3000 configuration data. If your design does not

connect the Flash to the outside world and your design does not read the SPI-FLASH data to

outside, then the Flash cannot be read to outside.

The CME3000 device bitstream is hidden during configuration because the Flash is inside the FPGA.

This configuration provides a starting point for security in a design, where it cannot directly be

copied from the Flash.

5.4 AES Security

Advanced Encryption Standard (AES) is a specification for the encryption of electronic data. The

AES algorithm is adopted to encrypt the configuration bitstream using a 128-bit key. The CME3000

will decrypt the encrypted bitstream using the 128-bit key which is stored in Efuse0. The

configuration will success if the two 128-bit keys are matching, otherwise the configuration will fail

and the device can’t work.

The encryption and decryption process is shown in figure 5-1



Primace

Configuration Data

AESEncryptor

Memory Storage

Encrypted Configuration

Data

Volatile Key

Encryption Key Programming

File


Data

FPGA

AES Decryptor

Volatile Key Storage


Data

Volatile Key

Bitgenabc

Security Setting

Check with Expected Value

Yes/No

Efuse

Step 1. Generate the encrypted configuration data and store in configuration memory.

Step 3. Configure the device using encrypted configuration data.

Step 2. Program volatile key into Efuse.

Figure 5-1 Encryption and Decryption Process

6 DC & Switching Characteristics

All parameter limits are representative of worst-case supply voltage and junction temperature

conditions. The following applies unless otherwise noted: AC and DC characteristics are specified

using the same numbers for both commercial and industrial grades. All parameters representing

voltages are measured with respect to GND.

6.1 DC Electrical Characteristics

6.1.1 Absolute Maximum Ratings

Stresses beyond those listed under Table 6-1: Absolute Maximum Ratings may cause permanent

damage to the device. These are stress ratings only; functional operation of the device at these or

any other conditions beyond those listed under the Recommended Operating Conditions is not

implied. Exposure to absolute maximum conditions for extended periods of time adversely affects

device reliability.

Table 6-1 Absolute Maximum Ratings

Symbol Description Conditions Min Max Units

VCCINT Internal supply voltage -0.5 V

VCCIO I/O driver supply

voltage -0.5 V

VREF

Input reference

voltage relative to

GND

-0.5 VCCIO+0.5 V

VIN Voltage applied to all

User I/O pins and

Driver in a high-impedance

state -0.95 V



dual-purpose pins

Voltage applied to all

Dedicated pins -0.8 V

VESD Electrostatic Discharge

Voltage

Human body model 0 ±2000 V

Charged device model - ±500 V

Machine model - ±200 V

TJ Junction temperature -40 -85 °C

TSTG Storage temperature –65 150 °C

6.1.2 Power Supply Specifications

Table 6-2 Supply Voltage Thresshoulds for Power-On Reset Symbol Description Min Max Units VCCINTT Threshold for the VCCINT supply 0.7 V VCCIOT Threshold for the VCCIO supply 2.26 V

Table 6-3 Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data

Symbol Description Min Max Units

VDRINT

VCCINT level required to retain

CMOS Configuration Latch (CCL)

and RAM data

V

Table 6-4 Supply Voltage Ramp Rate Symbol Description Min Max Units

VCCINTR Ramp rate from GND to valid

VCCINT supply level 10 us

VCCIOR Ramp rate from GND to valid

VCCIO supply level 10 us

6.1.3 General Recommended Operating Conditions

Table 6-5 Recommended Basic Operating Conditions for Single I/O Symbol Parameter Min Norm Max

TJ Junction temperature -40°C 25°C 85°C

VCCINT core voltage 0.9V 1V 1.1V

VCCIO I/O supply voltage @ 3.3V 2.97V 3.3V 3.63V

@2.5V 2.25V 2.5V 2.75V



Symbol Parameter Min Norm Max

@1.8V 1.62V 1.8V 1.98V

@1.5V 1.35V 1.5V 1.65V

VIH Input High Voltage @3.3V LVCMOS 2V VCCIO +0.3

@2.5V LVCMOS 1.7V VCCIO +0.3

@1.8V LVCMOS 0.65*

VCCIO

VCCIO +0.3

VIL Input Low Voltage @3.3V LVCMOS -0.3 0.8V @2.5V LVCMOS -0.3 0.7V

@1.8V LVCMOS -0.3 0.35* VCCIO

VT+ Schmitt trig Low to High threshold point

@3.3V

0.6* VCCIO

@2.5V

0.6* VCCIO

@1.8V

0.6* VCCIO

VT- Schmitt trig High to Low threshold point

@3.3V

0.4* VCCIO

@2.5V

0.4* VCCIO

@1.8V

0.4* VCCIO

TJ Junction Temperature -40 ℃ 25℃ 125℃

IL Input Leakage Current ±1μA

VOL Output low voltage @IOL=2,4…16mA @3.3V 0.4V

@2.5V

0.7V

@1.8V

0.45V

VOH Output high voltage @ IOH=2,4…16mA @3.3V 2.9V

@2.5V

1.7V

@1.8V

VCCIO -0.45

IOL Low level output current @VOL=0.4V

VCCIO =3.3V

min typ max

4mA >4mA 6

8mA >8mA 16

12mA >12mA 19

16mA >16mA 25

Low level output current @VOL=0.7V

VCCIO =2.5V

min typ max

4mA >4mA 5



Symbol Parameter Min Norm Max

8mA >8mA 14

12mA >12mA 16.8

16mA >16mA 21


VCCIO =1.8V

min typ Max

4mA >4mA 4

8mA >8mA 10

12mA >12mA 13

16mA >16mA 16


VCCIO =1.5V

min typ Max

4mA 2.8

8mA 7

12mA 8.4

16mA 11

IOH High level output current @VOH=2.9V

VCCIO =3.3V

min typ max

4mA >4mA 6

8mA >8mA 17

12mA >12mA 18

16mA >16mA 25

High level output current @VOH=2.1V

VCCIO =2.5V

min typ Max

4mA >4mA 5.4

8mA >8mA 14

12mA >12m 16

16mA >16mA 19

High level output current @VOH= VCCIO -0.45

VCCIO =1.8V

min typ Max

4mA >4mA 4

8mA >8mA 11

12mA >12mA 13

16mA 15

High level output current @VOH= VCCIO

-0.375

VCCIO =1.5V

min typ Max

4mA 2.8

8mA 7.8

12mA 8.5

16mA 11



Table 6-6 Recommended Operating Conditions of Programmable Transmitter Features Supported Voltage and Current

Capabilities Attributes Value

Drive strength

IOH

4mA

8mA

12mA

16mA

IOL

4mA

8mA

12mA

16mA

Slew-rate control

Rising Slew

slow

nominal

fast

Falling Slew

slow

nominal

fast

TX impedance control

Pull up 10kΩ

Pull down keeper 5kΩ

Note: All IOs support single-ended IO standards, such as LVCMOS. Measured between 10% and

90% VCCIO

Quiescent Current Requirements Table 6-7 Quiescent Current Requirements

Symbol Description Device Typical(1) Maximum(2) Units

IFPINTQ Quiescent VCCINT supply current only for Fabric. mA

IMSSINTQ Quiescent VCCINT supply current only for MSS include the 8051 SRAM(128KB).

mA

IINTQ Quiescent VCCINT supply current for whole device. mA

Notes: 1. The numbers in this table are based on the conditions set forth in Table General Recommended

Operating Conditions.

2. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all

pull-up/pull-down resistors at the I/O pads disabled.

Typical values are characterized using typical devices at room temperature (TJ of 25°C at VCCINT

= 1.0V).The FPGA is programmed with a ""blank"" configuration data file (i.e., a design with no



functional elements instantiated).

The maximum limits are tested for each device at the respective maximum specified junction

temperature and at maximum voltage limits with MAX VCCINT and VCCIO .

3. The maximum numbers in this table indicate the minimum current each power rail requires in

order for the FPGA to power-on successfully.

6.2 Switching Characteristics

Timing parameters and their representative values are selected for inclusion below either because

they are important as general design requirements or they indicate fundamental device

performance characteristics.

6.2.1 Clock Performance

Table 6-8 Recommended Operating Frequency of Global Clock

Symbol Max Frequency Units

GCLK 500 MHz

6.2.2 I/O Performance

Table 6-8 Recommended Operating Frequency of I/O

IO Standard Primary Usage Max Frequency

LVCMOS 1.5v/1.8v/2.5v/3.3v general purpose 200 MHz

6.2.3 PLB Performance

Table 6-9 Recommended Operating Frequency of PLB

Symbol Description Speed Units

Min Max ns

ADD16 16 bit adder performance @

recommended operating condition.

ADD32 32 bit adder performance @


Add64 64 bit adder performance @


CNT8 8 bit counter performance @





CNT16 16 bit counter performance

@recommended operating condition.

CNT32 32 bit counter performance @


6.2.4 EMB5K Performance

Table 6-2 Recommended Operating Frequency of EMB5K


Min Max MHz

EMB5K EMB5K performance at


6.2.5 DSP Performance

Table 6-3 Recommended Operating Frequency of DSP


Min Max MHz

DSP

DSP using register path.

DSP not using the register path.

7 Pins and Packaging

7.1 Pins Definitions and Rules

Table 7-1 Pins Definitions and Rules Pin Name Direction Description

User I/O Pins

IOXX_# iout user I/O pin

Multi-Function Pins

IOXXX/ZZZ_#

Multi-function pins are labelled IOXXX/YYY_#, where YYY

represents one ormore of the following functions in

addition to being general purpose user I/O.

If not used for their special function, these pins can be user

I/O.

Multi-Function Pins: SPI serial configuraiton Pins



Pin Name Direction Description

SCLK input/output

In passive serial configuration mode , SCLK is a clock input

used to clock configuration data from external device

source into device.

In active serial configuration mode, SCLK is a clock output

from device.

The pin can be used as regular user I/Os after configuration.

SDI input

Dedicated configuration data input pin in AS mode.

The pin can be used as regular user I/Os after configuration

in AS mode

SDO output

Active serial data output from the device.

The pin can be used as regular user I/Os after configuration

in AS mode.

This pin is only user I/O pin when the device is in PS mode .

nCSO output

Chip select output to enabla/disable a serial configuration

device.

This output is used during AS mode.The pin can be used as

regular user I/Os after configuration in AS mode.

This pin is only user I/O pin when the device is in PS mode.

Multi-Function Pins: Configuraiton Pins

CONF_DONE output

This is a dedicated configuration status pin, the pin will

output high during configuraiton.The pin can be used as

regular user I/Os after configuration.

MSEL 0 :Active Serial mode , 1 Passive Serial mode.

The pin can be used as regular user I/Os after configuration.

Multi-Function Pins: Clock Pins

CLKX input

These clock pins connect to Global Clock Buffers.

These pins become regular user I/Os when not needed for

clocks.

Multi-Function Pins: Efuse clock

FUSE_CLK input Efuse program clock.

Dedicated Pins: JTAG

TCK input TCK Input Boundary-Scan Clock.

TDI input TDI Input Boundary-Scan Data Input.

TDO output TDO Output Boundary-Scan Data Output.

TMS input TMS Input Boundary-Scan Mode Select.

Dedicated Pins: JTAG

nCONFIG input Chip global reset input. Active low.

Dedicated Pins: Crystal Pins

XIN input External crystal input.



Pin Name Direction Description

XOUT output output to crystal.

Dedicated Pins: RTC Pins

RTCXI input External crystal input for RTC 32K clock.

RTCXOUT output 32K clock output to crystal.

RTCRSTN input RTC reset pin, low active.

VCCRTC N/A RTC power.

GNDRTC N/A RTC ground.

Dedicated Pins: Power

VCCIO N/A Digital power for IO.

VCCINT N/A Digital power for core 1.0V.

VCCA_PLL N/A Analog power for PLLs.

VDDQ N/A Efuse program power.

GND N/A Digital ground.

Caution! VCCIO_0 and VCCIO_2 MUST be powered 3.3V. Note:

VDDQ should connect to the pin6 of 10 pin header on CME JTAG cable and use a 1K resistor to

make the signal pulldown to GND for programming the Efuse.

FUSE_CLK should connect to CME JTAG cable 10 pin header pin8.

7.2 Pin List

7.2.1 LQFP144 Package Pin List

Table 7-3 LQFP144 Package Pin List No. LQFP144

1 VICCIO_0

2 GND

3 IO1_0

4 IO2_0

5 IO3_0

6 IO4_0

7 IO5_0

8 IO6_0

9 IO7_0

10 IO8/CSON_0

11 IO9_0

12 VCCINT

13 IO10_0

14 IO11/SDI_0

15 IO12_0

No. LQFP144

16 IO13_0

17 IO14_0

18 IO15_0

19 IO16_0

20 IO17_0

21 IO18_0

22 IO19_0

23 VCCIO_0

24 GND

25 IO20_0

26 IO21_0

27 IO22_0

28 IO23_0

29 IO24_0

30 VCCINT

No. LQFP144

31 IO25_0

32 IO26_0

33 IO27_0

34 IO28_0

35 GND

36 VCCIO_0

37 IO29_1

38 IO30_1

39 GND

40 IO31_1

41 VCCIO_1

42 IO32_1

43 IO33_1

44 VCCINT

45 IO34_1



No. LQFP144

46 IO35_1

47 GND

48 IO36_1

49 IO37_1

50 IO38_1

51 IO39_1

52 VCCIO_1

53 IO40_1

54 IO41_1

55 GND

56 IO42_1

57 IO43_1

58 IO44_1

59 IO45_1

60 IO46_1

61 IO47_1

62 IO48/CLK0_1

63 IO49/CLK1_1

64 VCCIO_1

65 IO50/CLK2_1

66 IO51/CLK3/FUSE_CLK_1

67 IO52_1

68 IO53_1

69 IO54_1

70 VDDQ_1

71 XIN_1

72 XOUT_1

73 VCCA_PLL _2

74 nCONFIG_2

75 TMS_2

76 TDI_2

77 TCK_2

78 TDO_2

79 IO55/CONF_DONE_2

80 IO56/MSEL_2

81 IO57/SDO_2

82 VCCIO_2

83 IO58/SCLK_2

84 IO59_2

85 GND

86 VCCINT

No. LQFP144

87 IO60_2

88 IO61_2

89 VCCIO_2

90 GND

91 IO62_2

92 IO63_2

93 IO64_2

94 VCCINT

95 IO65_2

96 IO66_2

97 GND

98 IO67_2

99 IO68_2

100 IO69_2

101 IO70_2

102 IO71_2

103 IO72_2

104 VCCIO_2

105 IO73_2

106 IO74_2

107 IO75_2

108 IO76_2

109 RTCXI_3

110 RTCXO_3

111 VCCRTC

112 GNDRTC

113 IO77_3

114 IO78/CLK4_3

115 IO79/CLK5_3

116 VCCIO_3

117 IO80/CLK6_3

118 IO81/CLK7_3

119 IO82_3

120 IO83_3

121 IO84_3

122 GND

123 IO85_3

124 IO86_3

125 IO87_3

126 IO88_3

127 IO89_3

No. LQFP144

128 VCCIO_3

129 IO90_3

130 IO91_3

131 IO92_3

132 IO93_3

133 IO94_3

134 IO95_3

135 GND

136 IO96_3

137 VCCINT

138 IO97_3

139 IO98_3

140 IO99_3

141 VCCIO_3

142 GND

143 IO100_3

144 IO101_3



7.2.2 TQFP100 Package Pin List

Table 7-4 TQFP-100 Package Pin List No. TQFP100

1 IO1_0

2 IO2_0

3 IO3_0

4 IO4_0

5 VICCIO_0

6 GND

7 IO5_0

8 IO6_0

9 IO7_0

10 IO8/CSON_0

11 IO9_0

12 VCCINT

13 IO10_0

14 IO11/SDI_0

15 IO12_0

16 IO13_0

17 IO14_0

18 IO15_0

19 GND

20 IO16_0

21 IO17_0

22 VCCINT

23 IO18_0

24 IO19_0

25 VCCIO_0

26 VCCINT

27 IO20_1

28 VCCIO_1

29 IO21_1

30 IO22_1

31 GND

32 IO23_1

33 IO24_1

34 IO25_1

No. TQFP100

35 IO26_1

36 IO27_1

37 IO28_1

38 IO29/CLK0_1

39 IO30/CLK1_1

40 VCCIO_1

41 IO31/CLK2_1

42 IO32/CLK3/FUSE_CLK_1

43 IO33_1

44 IO34_1

45 IO35_1

46 VDDQ_1

47 VCCINT

48 GND

49 XIN_1

50 XOUT_1

51 VCCA_PLL _2

52 nCONFIG_2

53 TMS_2

54 TDI_2

55 TCK_2

56 TDO_2

57 IO36/SDO_2

58 VCCIO_2

59 IO37/SCLK_2

60 GND

61 VCCINT

62 IO38_2

63 IO39_2

64 IO40_2

65 IO41_2

66 IO42_2

67 VCCINT

68 GND

No. TQFP100

69 IO43_2

70 IO44_2

71 IO45_2

72 IO46_2

73 IO47_2

74 VCCIO_2

75 IO48_2

76 GND

77 VCCINT

78 IO49_3

79 IO50/CLK4_3

80 IO51/CLK5_3

81 VCCIO_3

82 IO52/CLK6_3

83 IO53/CLK7_3

84 GND

85 IO54_3

86 IO55_3

87 IO56_3

88 IO57_3

89 IO58_3

90 VCCIO_3

91 IO59_3

92 IO60_3

93 IO61_3

94 IO62_3

95 GND

96 IO63_3

97 VCCINT

98 IO64_3

99 IO65_3

100 IO66_3

7.3 Package Information



LQFP144 Low-profile Quad Flat-Pack Package Specifications(0.5 mm Pitch)

PIN 1IDENTIFIER

1

144

37 72

73

108

109

D 1

D1 24

E1

E1

2

36

A A2

A1 6 e b 0.08 CC SEATING PLANE

θ2

θ3

S

θ1

R1

R2

L

L1

θ.25

GAGE PLANE

B

B

SECTION A-A

b 5 3

c5

c15

b1 5

SECTION B-B

WITH PLATING

BASE METAL

A A

SymbolDimension in mm

Min Nom MaxDimension in inchMin Nom Max

AA1

A2

b1

b

c1

c

DD1

EE1

eLL1

RR1

S

θ1

θ2

θ3

θ

1.600.051.35 1.40 1.450.17 0.22 0.27

0.20 REF0.12 0.20

0.13 REF21.85 22.00 22.1519.90 20.00 20.1021.85 22.00 22.1519.90 20.00 20.10

0.50 BSC0.45 0.60 0.75

1.00 REF0.15 REF0.15 REF0.19 REF

7° REF12° REF12° REF

0° 3.5° 7°

0.0630.0020.053 0.055 0.0570.007 0.009 0.011

0.008 REF0.005 0.008

0.005 REF0.860 0.866 0.8720.783 0.787 0.7910.860 0.866 0.8720.783 0.787 0.791

0.020 BSC0.018 0.024 0.030

0.039 REF0.006 REF0.006 REF0.007 REF

7° REF12° REF12° REF

0° 3.5° 7°

TO BE DETERMINED AT SEATING PLANE

DIMENSION D1 AND E1 DO NOT INCLUDE MOLD PROTRUSIOND1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONINCLUDING MOLD MISMATCH.

DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONDAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THEFOOT.

EXACT SHAPE OF EACH CORNER IS OPTIONAL.

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEADBETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP.

A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE

TO THE LOWEST POINT OF THE PACKAGE BODY.CONTROLLING DIMENSION : MILLIMETER.

REFERENCE DOCUMENT : JEDEC MS–026 , BFB

CME3C…-L144……

C

2

3

4

5

6

7

8

1

Figure 7-1 LQFP144 package



TQFP100 Thin Quad Flat-Pack Package Specifications(0.5 mm Pitch)

PIN 1IDENTIFIER

1

100

26 50

51

75

76

D 1

D1 24

E1

E1

2

25

A A2

A1 6 e b ccc CC SEATING PLANE

θ2

θ3

S

θ1

R1

R2

L

L1

θ.25

GAGE PLANE

B

B

SECTION A-A

b 5 3

c5

c15

b1 5

SECTION B-B

WITH PLATING

BASE METAL

SymbolDimension in mm

Min Nom MaxDimension in inchMin Nom Max

AA1

A2

b1

b

c1

c

DD1

EE1

eLL1

RR1

S

θ1

θ2

θ3

θ

1.200.050.95 1.00 1.050.17 0.22 0.27

0.09 0.20

0.50 BSC0.45 0.60 0.75

0° 3.5° 7°

0.0470.0020.037 0.039 0.0410.007 0.009 0.011

0.004 0.008

0.020 BSC0.018 0.024 0.030

0.039 REF

0° 3.5° 7°

CME3C…-T100……

SEE DETAIL A-A

(4x)

(4x)

0.15

0.17 0.20 0.23

0.09 0.16

14.00 BSC16.00 BSC14.00 BSC16.00 BSC

0.15 REF0.080.08 0.200.20

0°11° 12° 13°11° 12° 13°

ccc 0.08 0.003

0.006

0.007 0.008 0.009

0.004 0.006

0.551 BSC0.630 BSC0.551 BSC0.630 BSC

0.0030.003 0.0080.008

0°11° 12° 13°11° 12° 13° SPECIAL CHARACTERISTICS C CLASS : ccc

TO BE DETERMINED AT SEATING PLANE

DIMENSION D1 AND E1 DO NOT INCLUDE MOLD PROTRUSIOND1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONINCLUDING MOLD MISMATCH.

DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONDAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THEFOOT.

EXACT SHAPE OF EACH CORNER IS OPTIONAL.

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEADBETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP.

A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE

TO THE LOWEST POINT OF THE PACKAGE BODY.CONTROLLING DIMENSION : MILLIMETER.

REFERENCE DOCUMENT : JEDEC MS–026 , BFB

C

2

3

4

5

6

7

8

1

9

Figure 7-2 TQFP100 package



8 Developer Kits

Capital Microelectronics developer kits can achieve 2 designs for CME3000: FPGA design and

embedded software design.

Capital Microelectronics Primace Integrated Design Environment (IDE) supports all CME’S chips,

can implement synthesis, mapper, placement, routing, bitgen and simulation etc. Support 3rd-party

EDA tools: Leonardo Spectrum and Modelsim.

AGDI is developed by Keil (Keil is a part of ARM), as a general purposed debugger interface to

Keil-C IDE, with which designers can compile and debug 8051 firmware online. The CME3000

device has on-chip debug (OCDS) capability. It helps the user debug 8051 program easily. For more

information, please refer to “CME2000 8051 Debugger User Manual”.

Please purchase Keil-C software tool for the 8051 programming, compiling, debugging etc. For

more information, please refer to http://www.keil.com/c51 .

Currently, the CME3000 device does not support other 3rd-party development environment.

Please send your suggestions and requirement to us: [email protected] .

OCDS debugging interface of MSS share the same JTAG interface with FPGA. Downloading cable

offered by Capital Microelectronics and software can identify and operate OCDS or JTAG of FPGA

automatically, but they cannot perform at the same time.

9 Ordering Information

All part numbers have the following conventions:

Table 9-1 Part number conventions

Family

Signature

Device

Type

LUT

Density

Package

Type

Temperature

Range

Speed

Grade

CME3 P/M/C 06 L144 C 7

Figure 9-1 Part number conventions

Family Signature

CME3 CME3000 family

CME2 CME2000 family

CME1 CME1000 family

Device Type

P FPGA

M FPGA + SRAM

C FPGA + SRAM + MCU

http://www.keil.com/c51

mailto:[email protected]



LUT Density

06 6K LUTs

03 3K LUTs

01 1K LUTs

Configuration SPI-flash Option

None Without internal SPI-flash

N With internal SPI-flash

Package Type: <type><#>

T Thin Quad Flat Pack (TQFP)

L Low profile quad flat package (LQFP)

Q Plastic Quad Flat Pack (PQFP)

F Fineline BGA

# Pin number (208 for 208pin, 100 for 100pin…)

Temperature Range

C Commercial (0℃,+70℃)

I Industrial (-40℃, +85℃)

M Military (-55℃,+125℃)

Speed Grade

# Speed (7 for speed 7, 6 for speed 6, …)

Example: CME3C06N-L144C7

Device Type Speed Grade

Package Type Temperature Range:

L : LQFP C = Commercial (Tj = 0°C to +85°C )

T : TQFP I = Industrial (Tj = - 40°C to +100°C )

Number of Pins



10 Legend

AES Advanced Encryption Standard

ALU Arithmetic-Logic Unit

AS Active Serial

CAP Configurable Application Platform on Chip

CCU Compare Capture Unit

CMS Control Mux Switch

CPU Control Processor Unit

DPRAM Dual Port RAM

DC Direct Current

DSP Digital Signal Processor

EMB Embedded Memory Block

IAP In Application Programming

I2C Inter-IC – a serial interface designed by Philips Semiconductors

ISC In System Configuration

ISP In System Programming

ISR Interrupt Service Routine Unit

LE Logic Element

LP Logic Parcel

LSB Least Significant Bit

MAC Multiply Accumulate Counter

MDU Multiplication-Division Unit

MOVC Move Program Memory

MOVX Move External Memory

MSB Most Significant Bit

MSS Microcontroller Subsystem

OCDS On-Chip Debug Support

OCI On-Chip Instrumentations

PLB Programmable Logic Block

PMU Power Management Unit

PS Passive Serial

RTC Real Time Clock

SFR Special Function Register

SPI Serial Peripheral Interface



11 Revision History

Table below shows the revision history for this document.

Date Version Revision

2012-6-14 1.0 Initial release.

2012-7-24 1.1 First updated.

· cme3000-c fpga data sheet v1.1 web: . capital-micro.com page 2 of 72 cme3000-c fpga

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