schem,mlb kepler 2phase,j31€¦ · 76 81 kepler core/fb power 01/18/2012 j31_sree 75 80 kepler...

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

TABLE_TABLEOFCONTENTS_HEAD

DRAWING











































































































2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PROPRIETARY PROPERTY OF APPLE INC.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISION

CKAPPD

2 1

1245678

B

D

6 5 4 3

C

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

THE INFORMATION CONTAINED HEREIN IS THE

C

A

D

DATE

R

SHEET

Apple Inc.

THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING TITLE

DSIZE

REVISION

DRAWING NUMBER

BRANCH

REV ECN

7

B

3

II NOT TO REPRODUCE OR COPY IT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

IV ALL RIGHTS RESERVEDIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

Schematic / PCB #’s

SCHEM,MLB_KEPLER_2PHASE,J31FRB & RISK RAMP 02/15/12

1 OF 105

2012-02-15

1 OF 132

3.0.0

051-9585

LAST_MODIFIED=Wed Feb 15 20:30:03 2012

CPU DMI/PEG/FDI/RSVD

Functional / ICT Test

Signal Aliases

CPU CLOCK/MISC/JTAG

SMC4549 12/19/2011

J31_YONAS

Front Flex Support4448 04/27/2010

K18_MLB

External B USB3 Connector4347 08/04/2011

J30_MLB

External A USB3 Connector4246 09/21/2011

J31_LINDA

SATA Redriver/Conn, IR, SIL4145 11/17/2011

J31_YONAS

FireWire Connector4043 06/10/2010

T27_REF

FireWire Port & PHY Power3942 06/17/2011

K91_MLB

FireWire LLC/PHY (FW643)3841 04/27/2010

K18_MLB

Ethernet Connector3740 05/26/2010

K91_TRINHNI

ETHERNET PHY (CAESAR IV)3639 10/11/2010

K91_ERIC

Thunderbolt Power Support3538 06/22/2011

T29_REF

Thunderbolt Host (2 of 2)3437 06/14/2011

T29_REF

Thunderbolt Host (1 of 2)3336 06/14/2011

T29_REF

X19/ALS/CAMERA CONNECTOR3235 11/11/2011

J30_MLB

DDR3/FRAMEBUF VREF MARGINING3134 06/09/2011

J31_ANNE

SD Card Connector3033 10/25/2011

J31_YONAS

DDR3 SO-DIMM Connector B2931 06/23/2010

K92_SUMA

DDR3 Byte/Bit Swaps2830 05/10/2010

K92_SUMA

DDR3 SO-DIMM Connector A2729 06/23/2010

K92_SUMA

CPU Memory S3 Support2628 04/27/2010

K18_MLB

USB HUB & MUX2527 09/16/2011

J31_LINDA

Chipset Support2426 07/06/2010

K92_MLB

CPU & PCH XDP2325 06/09/2011

J31_ANNE

PCH DECOUPLING2224 05/26/2011

J5_MLB

PCH GROUNDS2123 03/21/2011

J5_MLB

PCH POWER2022 03/21/2011

J5_MLB

PCH GPIO/MISC/NCTF1921 06/02/2011

J31_ANNE

PCH PCI/USB/TP/RSVD1820 06/02/2011

J31_ANNE

PCH DMI/FDI/PM/Graphics1719 05/26/2011

J5_MLB

PCH SATA/PCIe/CLK/LPC/SPI1618 06/02/2011

J31_ANNE

CPU DECOUPLING-II1517 08/19/2010

K92_MLB

CPU DECOUPLING-I1416 08/19/2010

K92_MLB

CPU POWER AND GND1314 06/15/2010

K92_SUMA

CPU POWER1213 08/03/2010

K92_MLB

CPU DDR3 INTERFACES1112 06/15/2010

K92_SUMA

1011 08/03/2010

K92_MLB

910 03/11/2011

J5_MLB

89 04/27/2010

K18_MLB

Power Aliases78 08/29/2011

J31_MLB

67 04/27/2010

K18_MLB

BOM Configuration55 05/28/2009

K17_REF

Revision History44 MASTER

MASTER

Power Block Diagram33 06/30/2009

K17_REF

Revision History22 04/19/2011

J31_MLB

J31_KIRAN

03/21/201197

90 LCD Backlight Driver

K91_MARY

08/03/201096

89 Graphics MUX (GMUX)

T29_REF

06/14/201194

88 Thunderbolt Connector A

J31_WILL

06/20/201193

87 Thunderbolt MUXing A

K92_MLB

11/21/201092

86 Muxed Graphics Support

K18_MLB

04/27/201090

85 LVDS Display Connector

D2_MLB_2P

01/18/201289

84 GFX IMVP VCore Regulator

J31_SREE

10/31/201188

83 KEPLER PEX PWR/GNDS

J31_SREE

11/16/201187

82 KEPLER GPIOS,CLK & STRAPS

J31_SREE

10/25/201186

81 KEPLER LVDS/DP/GPIO

J31_SREE

10/25/201185

80 GDDR5 Frame Buffer B

J31_SREE

10/25/201184

79 GDDR5 Frame Buffer A

J31_JACK

11/16/201183

78 1V05 GPU / 1V35 FB POWER SUPPLY

J31_SREE

10/25/201182

77 KEPLER FRAME BUFFER I/F

D2_MLB_2P

01/18/201281

76 KEPLER CORE/FB POWER

J31_SREE

10/25/201180

75 KEPLER PCI-E

J31_MARY

06/06/201179

74 Power Control 1/ENABLE

J31_MARY

05/05/201178

73 Power FETs

J31_JACK

06/10/201177

72 Misc Power Supplies

J31_JACK

09/19/201176

71 CPU VCCIO (1V0R1V05 S0) POWER SUPPLY

J31_JACK

11/11/201175

70 CPU IMVP7 & AXG VCore Output

J31_JACK

11/11/201174

69 CPU IMVP7 & AXG VCore Regulator

J31_JACK

07/07/201173

68 1.5V DDR3 Supply

J31_JACK

11/09/201172

67 5V / 3.3V Power Supply

J31_JACK

09/14/201171

66 System Agent Supply

J31_JACK

11/14/201170

65 PBus Supply & Battery Charger

J31_JACK

09/02/201169

64 DC-In & Battery Connectors

J31_AUDIO

10/26/201168

63 AUDIO: JACK TRANSLATORS

J31_AUDIO

10/26/201167

62 AUDIO: JACKS

J31_AUDIO

10/26/201166

61 AUDIO: SPEAKER AMP

J31_AUDIO

10/26/201165

60 AUDIO: HEADPHONE FILTER

J31_AUDIO

10/26/201164

AUDIO: DETECT/MIC BIAS

J31_AUDIO

10/26/201163

58J31_AUDIO

10/26/201162

57K91_BEN

06/08/201061

56 SPI ROM

J31_YONAS

08/11/201159

55 Digital Accelerometer

J31_LINDA

07/01/201158

54 WELLSPRING 2

J30_MLB

06/10/201157

53 WELLSPRING 1

K18_MLB

04/27/201056

52 Fan Connectors

J31_YONAS

09/08/201155

51 Thermal Sensors

J31_YONAS

10/25/201154

50 Power Sensors: High Side, CPU, AXG

J31_YONAS

01/19/201253

49 Power Sensors: Load Side

K18_MLB

04/27/201052

48 SMBus Connections

J5_MLB

05/26/201151

47 LPC+SPI Debug Connector

J31_YONAS

08/24/2011132

Power Sensors: CPU Ripple105J31_YONAS

09/12/2011131

Power Sensors: Debug ADC104J31_YONAS

09/12/2011130

Power Sensors: SMC Extended103K18_MLB

04/27/2010109

PCB Rule Definitions102K18_MLB

04/27/2010108

Project Specific Constraints101K92_MLB

08/09/2010107

GPU (Kepler) CONSTRAINTS100J31_YONAS

08/11/2011106

SMC Constraints99T29_REF

06/14/2011105

Thunderbolt Constraints98K91_ERIC

08/03/2010104

Ethernet/FW Constraints97J31_YONAS

05/05/2011103

PCH Constraints 296K92_MLB

08/09/2010102

PCH Constraints 195K91_MLB

06/25/2011101

Memory Constraints94K92_MLB

08/09/2010100

CPU Constraints93J31_SREE

09/19/201199

Power Sequencing EG/PCH S092

(.csa) Date

SyncTable of Contents1

1 MASTER

MASTER J31_JACK

09/16/201198

PCH VCCIO (1.05V) POWER SUPPLY91

Contents SyncDate(.csa)

PageJ31_YONAS

01/19/201250

46 SMC Support

TITLE=MLBABBREV=DRAWING

SCHEM,MLB_KEPLER_2PHASE,J31051-9585 1 SCH CRITICAL

Page ContentsDate(.csa)

Sync

PCBF,MLB_KEPLER_2PHASE,J31820-3330 1 PCB CRITICAL

SCHEM,MLB_KEPLER,J31

59

Page

AUDIO: LINE INPUT FILTER

AUDIO: CODEC/REGULATOR

Contents

www.qdzbwx.com

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

124578

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IV ALL RIGHTS RESERVED

R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

IVY BRIDGE

DDR3-1067/1333MHZ

J5650,5660

FAN CONN AND CONTROL

PG 51

PG 48 POWER SENSE

THERMAL SENSORPG 50

EXTERNAL B

PG 42

PG 42

PG 52

PG 41/43USB HUB

IR

PG 32BLUETOOTH

TRACKPAD/KEYBOARD

SMC DEBUG PORT

EXTERNAL APG 42

J3300

U4100

J4000

SDCARD READER

PG 36

BCM57765B0

ETHERNET

PG 16

PCI-E

U1800

MOBILE

PANTHER-POINT

INTEL

RTC

J2900

J2500,J2550

INTEL CPU

2.X GHZ

POWER SUPPLY

J4500

U3600

DP/T29

MUX

CONN

HDD SATA

CONN

ODD SATA

J4501

PG 41

PG 56

CONNECTION

SMBUS

12

CTRL

PWR

XDP CONN

PG 27,29

LVDS DDC MUX

J6700,J6750

FILTER

LINE INPUT

J4600

SMS SENSOR

ALS SENSOR

Misc

LPC + SPI CONN

PG 46

(UP TO 14 DEVICES)

PG 17

MINI DP PORT

U9270

PG 73

PG 84

J9000

PG 83

LVDS CONN

ETHERNET

J3501

PG 32

PG 30

PG 38

PG 40 PG 37

J6781,J6782

PG 57 PG 58 PG 59

PG 60PG 60

PG 44

PG 63

PG 32

PG 50

DIMM

J3100

SMC

Prt

Ser

U4900

Port80,serial

J5100

PG 17

11

13

GMUX

PG 86

U9600

PG 84

AirPort

SMB

PG 16 PG 16

JTAG

PG 18

6

5

PG 17

U3900

CONNCONN

HDA

SPEATKER

U6610,6620,6630

SPEATKER

AMP

HEADPHONE

FILTER

2

0

3

1

5

PG 16

4

3

12

0

BUFFER

AUDIO

AUDIO

CODEC

U6201

PG 16

PG 16

PG 16

PG 16

PG 16

USB

U6100

Boot ROM

SPI

PG 55

PG 19

PG 18

GPIO

PG 47

LPC

7

CONN

CONN

FIREWIRE

FW643

B,0 BSB

CLK

DMI

89

J4310

SPI

U8000

PG 9

2 DIMMS

PG 23

DC/BATT

J6950

U5920

FanADCI2C I2C

U2700

J4610

J4600

J3501

J5713/U5701

J4501/U4800

10

PG 25

DIMM

PEG

PCI

PG 27,29

LVDS

J9400

U9220

PG 84

PG 16

PG 33/34

T29

DP DDC MUX

PG 19 PG 17

FDI

SATA

4

PG 41

(UP TO 16 LINES)

PG 85

GRAPHICS

NVIDIA KEPLER

Revision History

SYNC_MASTER=J31_MLB SYNC_DATE=04/19/2011

051-9585

3.0.0

2 OF 132

2 OF 105

www.qdzbwx.com

Apple Inc.


124578

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PAGE TITLE

SHEET


R

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REVISION

BRANCH

6 3



SMC_RESET_L

CPU_PWRGD

PLT RESET L

SMC_ADAPTER_EN

PM_PWRBTN_L

PM_SYSRST_L

PM_DSW_PWRGD

PM_MEM_PWRGD

PM_RSMRST_L

PM_MEM_PWRGD

CPU_PWRGD

SMC_ADAPTER_EN

PP3V3_S5_AVREF_SMC

PM_DSW_PWRGD

PM_SYSRST_L

PM_PWRBTN_L

CPU_RESET_L

(B9)

SMC_RESET_LRESET

SMC RESET

SMC AVREF SUPPLY

VIN

MR1

SMC_TPAD_RST_LENABLE

PP3V3_S5_AVREF_SMCPP3V42_G3H3.425V G3HOT SN0903048

PM_PCH_SYS_PWROK

PM_S0_PGOOD

DPWROK

SYS_RERST#

PWRBTN#

(E20)

(K3)

(C6)

(H20)

(C21)

(E22)

(AY11)

RSMRST#

PLTRST#

U1800

COUGAR_POINT

(PAGE 16~21)

ACPRESENT/GPIQ31

SYS_PWROK

PROCPWRGD

DRAMPWROK

U9950

CPUIMVP_VR_ON

PM_PCH_PWROK

PCHVCCIOS0_PGOOD

CPUVCCIOS0_PGOOD

P5VS3_PGOOD

P1V5S0_PGOOD

P1V8S0_PGOOD

PP1V05_T29_FET

TBT_PWR_EN

VOUT

EN

U9950

PP1V0_FW_FET_R

(PAGE 35)

FW_PWR_EN

1V05 T29

U3815 & U3816

SWITCHVIN

REFOUT

VOUT

TPS22924

SMC_CPU_VSENSE

(PAGE 39)

U4202

EN

PPVCORE_S0_CPU

VIN

PPVCORE_S0_AXG_REG

SMC_AXG_VSENSE

PP1V5_S3

(PAGE 73)

UNCOREPWRGOOD

SM_DRAMPWROK

RESET

(AY25)

CPU

U7930

(C60)

(M3)SSIOFSS/PA3

T1CCP1/PJ1

(K51)RESET*

SMC

(PAGE 9~13)

U1000

3V3 SUS DETECT

WT2CCP0/PH0(K3)ALL_SYS_PWRGD

S5_PWRGD

S5_PWRGD(L9)

(H4)

(J3)

(D2)VREFA+

WT3CCP1/PH5

WT3CCP0/PH4

RST*(G10)

(PAGE 44)

LM4FSXAH5BBU4900

PQ6/IRQ130(M6)

PQ4/IRQ128(N6)

PQ5/IRQ129(K5)

PQ7/IRQ131(L6)

SMC_ONOFF_L

PM_SLP_S4_L

PM_SLP_S5_L

PM_SLP_S3_L

PVCCSA_PGOOD

ALL_SYS_PWRGD_R

RST*

WHISTLER PCI-E

(PAGE 74)U8000

PWRGOOD

(PAGE 88)

GRAPHICS MUX

U9600

VCC

U7960

TRST = 200mS

(PAGE 73)

ISL88042IRTEZ

V2MON

V3MON

V4MON

PP3V3_S0_VMON

PP1V5_S3RS0_VMON

PPVCCSA_S0_REG

PP5V_S0_VMON

PP1V0_S0GPU_REG

PP1V05_S0_VMON

(AH16)

(N1)PL25A

PM_ALL_GPU_PGOOD

R9990

PP3V3_S0_PWRCTL

ALL_EG_PGOOD

PP1V5_GPU_REG

GPUVCORE_PGOOD

P1V5FB_PGOOD

P1V0GPU_PGOOD

PPCPUVCCIO_S0_REG

(R7350)

SMC_DDR3_ISENSE

U5360

SMC_GPU_1V0_ISENSE

P1V5FB_PGOOD

P1V0GPU_PGOOD

UD141(RD145)

A

SMC_CPUVCCSA_ISENSE

(PAGE 46)

U5010

SMC_CPUVCCIO_ISENSE

PVCCSA_PGOOD

CPUVCCIOS0_PGOOD

(R7140)

MR2

A

U5310

(R7640)

VU5450

A

SMC_ONOFF_L

VOUT

PGOOD

1V0 /

CPU VCCIO

VIN

(PAGE 70)

1.05V

CPU/AXG VCORE

ISL95870

U7600EN

CPU VOUT

V

CPUIMVP_PGOOD

U5460

A

U5360

A

PPDDR_S3_REG

SMC_CPU_ISENSE

CPUIMVP_AXG_PGOOD

SMC_AXG_ISENSE

PPVTT_S0_DDR_LDO

PGOKA

PGOKB

U7400

MAX15119GTM

EN

VIN

(PAGE 68)

VOUT1

VOUT2

VLDOINVIN1.5V

0.75V

(PAGE 63)

CPUVCCIOS0_EN

CPUIMVP_VR_ON

S3

PP5V_S3_DDRREG

S5

PP5V_S0_CPUVCCIOS0

U6990

PM6640

PPBUS_G3H

A

U5410

U5400

PPBUS_G3H

SMC_GPU_HI_ISENSE

A

DDRREG_EN

DDRVTT_EN

VOUT

PGOOD

SYSTEM AGENT

(PAGE 65)

ISL95870A

U7100

AVOUT1VIN

DDRREG_PGOOD

PPVDDCI_S0_REG

PVDDCI_PGOOD

VIN

EN

EN1

PGOODU7300

PVCCSA_EN

TPS51916

(PAGE 67)

VOUTGPU VDDCI0V9~1V15ISL95870A

P1V0GPU_EN

(PAGE 90) PGOOD

U9800

1V0GPU/1V5 FB

VOUT2

POK2

POK1

U8300

1.503V(R/H)

1.003V(L/H)

(PAGE 77)

ISL6236

EN2P1V5FB_EN

VIN

PPVOUT_SW_LCDBKLT

SMC_LCDBKLT_VSENSE

ENPVDDCI_EN

PP15V_T29_REG

PPBUS_FW_FET

VOUT

VOUT

FIREWIRE PORT

EN

PPBUS_SW_BKL

A

UD120

V

SMC_LCDBKLT_ISENSE

VIN

VOUT

Q9706

LCD_BKLT_EN

BKLT_PLT_RST_L

&&

U9701

LP8550

EN

(PAGE 89)

PP5V_S3_RTUSB_A_ILIM

PP5V_S3_RTUSB_B_ILIM

PP4V5_AUDIO_ANALOG

U4260

EN

3A 32V FUSE

F9700

PPBUS_SW_LCDBKLT_PWR

(PAGE 35)U3890

SMC_PBUS_VSENSE

SMC_CPU_HI_ISENSE

(PAGE 39)

LT3957

POWER SWITCH

T29 15V BOOST

D6990

R6990

J31 POWER SYSTEM ARCHITECTURE

6A FUSE

F6905J6900

AC

Q5300

VPPBUS_G3H

PP5V_SUS_FET

PPBUS_G3H

F7040

8A FUSE

A

Q7840

EN2

VOUT2

VOUT15V

EN1

LED

(PAGE 54)U5850LT3491KB_BL

VINCTRL

VOUT

U4600

4.5V AUDIO

P5VSUS_EN

SMC_SYS_KBDLED

MAX8840

U6200

PP1V5_S3RS0_FET

POWER SWITCH USB PORT

(PAGE 42)

VIN

USB_PWR_EN

Q7801

VIN

PP5V_S0_FET

PPDDR_S3_REG

PP18V5_S4

Q7860

PP3V3_S0_AUDIO

SMC_DCIN_VSENSE

SMC_BMON_ISENSE

PP5V_S5_P5VSUSFET

P5VS0_EN

P1V5S3RS0FET_GATE

Q5310

R7050

V

PPVBUS_G3HVOUT

BATTERY CHARGER

PPVBAT_G3H_CHGR_R

SMB_RST_N

ISL6259HRTZ

PBUS SUPPLY/

U7000

VIN

(PAGE 64)

PP5V_S5_LDO

G

TPS61045

(PAGE 72)

U5805

VOUT

SLG5AP020U7801

VINON

VIN

(PAGE 54)

PP3V3_S0GPU_FET

P1V5CPU_EN

PP5V_S5_LDO

P3V3GPU_EN

PP3V3_S5

Q7870

(PAGE 57)

VIN

VIN

T29_A_HV_EN

FWPORT_PWR_EN

PP3V3_S4_FET

PP3V3_SW_LCD_UF

P3V3S4_EN

SHND

PP3V3_T29_FET

VOUT

Q7800

U9000

PP1V05_SUS_LDO

PP1V5_S0_REG

VOUT

VOUT

PP1V2_S0_REG

(PAGE 71)

TPS62201

EN

VIN

VOUT

U7710

U7740

TPS720105

(PAGE 71)

VIN

EN

PM_SLP_S3_L & WOL_EN & SMC_ADAPTER_EN

PP3V3_ENET_FET

VOUT

(PAGE 35)

(PAGE 84)

FPF1009

PP3V3_SUS_P1V05SUSLDO

VIN

PP3V3_SUS_FET

(PAGE 71)U7760

TPS622011V2_S0(GMUX)

T29 SWITCH

PP3V3_FW_FET

TPS22924 3.3V

Q7922

EN

U3810

VOUT

TPS22924

(PAGE 39)

VIN

U4201

EN

FW_PWR_EN

VIN

PP3V3_S0_FET

PP3V3_S3_FET

P3V3S3_EN

P3V3S0_EN

Q7810

Q7830

TBT_PWR_EN

EN

VIN

ENP1V2S0_EN

LCD_PWR_EN

P1V5S0_EN

P3V3SUS_EN

Q7820

R7978

P1V8S0_EN

PM_SLP_S3_R_L

P1V2S0_EN

PVCCSA_EN

CPUVCCIOS0_EN

P1V5S0_EN

(Y1)

FW_PWR_EN

DELAY

DELAY

DELAY

PP5V_S3_REG

PP3V3_S5_REG

PP18V5_DCIN_CONN

SMC_RESET_L

(PAGE 24)

A

R7020

SMC_DCIN_ISENSE

CHGR_BGATE

PPVBAT_G3H_CONN

Q7055

VOUT1

VREG5

VOUT2

P3V3S5_PGOODPGOOD2

(L/H)

(R/H)

TPS51980U7201

(PAGE 66)

P5VS3_PGOOD

P3V3S5_EN

5V

VIN

EN1

EN2 3.3VP3V3S5_EN

P5VS3_EN

PGOOD1

DELAY

RC

SMC_BATLOW_L

SMC_PM_G2_EN

H10

M2

(PAGE 45)

J6950

DCIN(18.5V)

IN

ADAPTER3S2P

(9 TO 12.6V)

SMC

DDRREG_EN

P3V3S3_EN

WOL_EN

U2152

P3V3S4_EN

(Y2)

(A2)

(PAGE 24)

U2150

R2526

(A2)

PM_SLP_S4_L

XDP_DB2_WOL_EN

P5VS3_EN

FW_PWR_EN_PCH

PM_SLP_S5_LR7916

AUD_IPHS_SWITCH_EN_PCH

RC

DELAY

RC

DELAY

SLP_SUS

(D14)

(V13)

(U2)

PM_SLP_S3_L

RCDELAY

RC

RC

RC

RC

P3V3GPU_EN

T29_A_HV_EN

GPUVCORE_EN

P3V3SUS_EN

P5VSUS_EN

P1V0GPU_EN

R9334

T29_A_HV_EN_R

LCD_PWR_EN

LCD_BKLT_EN

(PAGE 73)

3.3V/5.0V

EG_RAIL3_EN

EG_RAIL2_EN

U7940SUS ENABLE

(Y)

EG_RAIL1_EN

(A)

(C)

(N8)

(PAGE 16~21)

SLP_S5*(D10)

SLP_S4#(H4)

MOBILE

U1800

SLP_S3#(F4)

COUGAR-POINT

(PAGE 88)

(PAGE 86)

PB7A

PORT A MCU

(18)

SMC_BATLOW_L

PB17B

PB17A

PB16B

GMUXU9600

U9330

PM_SLP_SUS_L

GMUX

XP25-5

U9600

DELAY

PPVCORE_GPU_REG

SMC_GPU_VSENSE

V

U5310

GPUVCORE_PGOOD

SMC_GPU_ISENSE

AVOUT

PGOOD

GPU VCORE

VIN

ISL6263C

U8900

(PAGE 83)

R5388/U5388

VDD/PVCC

VR_ONGPUVCORE_EN

PP5V_S3_GPUVCORE

PP1V8_S0GPU_ISNS

UD180(RD186)

A

SMC_GPU_1V8_ISENSE

PP1V8_GPU_FET1V8GPU FET

VOUT

P1V8S0_PGOOD

PP1V8_S0_REG

U7880

VIN

(PAGE 72)

VOUT

PGOOD

NCP4543IMN5RG-A

EN

U7720

(PAGE 71)

ISL8014A

P1V8GPU_EN

VIN

EN

P1V8S0_EN

PCHVCCIOS0_EN

P5VS0_EN

P3V3S0_EN

PBUSVSENS_EN

DELAY

P1V5CPU_EN

MEM_RESET_L

RC

MEMVTT_EN

PM_ALL_GPU_PGOOD

P1V5FB_EN

P1V8GPU_EN

PM_SLP_S4_L

PM_SLP_S3_L

ALL_EG_PGOOD

EG_RAIL4_EN

PL25A

PB18A

CPU_MEM_RESET_L

ISOLATE_CPU_MEM_L

(PAGE 88)

PM_SLP_S3_L

PLT_RST_L

TBT_PWR_EN

PM_SLP_SUS_L

U4900

$CDS_IMAGE|O_0.jpg|416|272

$CDS_IMAGE|O_1.jpg|416|272

$CDS_IMAGE|O.jpg|416|272

$CDS_IMAGE|R.jpg|272|166



SYNC_DATE=06/30/2009SYNC_MASTER=K17_REF

Power Block Diagram

051-9585

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Revision History

SYNC_MASTER=MASTER SYNC_DATE=MASTER

051-9585

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4 OF 132

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TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

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BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM


TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM


TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM


TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

BOM GROUPS

BOM VARIANTS - FSB

SUB BOMS

/ EEEE #’sBar Code Labels

(Primary)

Alternate Parts

-

|

PSOC

Programmables - All Builds

(Alternate)

PD Parts

SMC

ETHERNET ROM

Module Parts

EFI ROM

DEVEL

J31_DEVEL:PVT

IVB_PPT_XDP

J31_DEVEL:FSB

J31_DEVEL:ENG

J31_PVT

J31_PROGPARTS1

J31_PROGPARTS

J31_COMMON

J31_COMMON2

J31_COMMON1

PCBA,MLB_2P,FSB,2.3,FOX,512_HYN,REN,J31,F327

J31 MLB_KEP_2P DEVELOPMENT BOM

IC,PCH,PPT,C1,SLJ8C,PRQ,BD82HM77

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

IC,CPU,IVB,S,R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA

J3100

CRITICAL

VREF:ENG_LDO

337S4267

CRITICAL FB_1G_SAMSUNG

376S1053

376S0958

157S0055

376S0761

155S0559

335S0777

155S0367

138S0638

138S0673

376S0953

197S0431

U8400,U8450,U8500,U8550

U9390

U3600

U1000

353S1658

ALLIC,TP PSOC,FSB,J31

Fairchild wafer option

128S0303

ALL

IC,SMC,EXTERNAL,PIB,V2.1A83,A3,J31 SMC_PROG:A3_PIB1 CRITICALU4900

SMC_PROG:PROTO3CRITICALU49001

U4900 SMC_PROG:PROTO11 CRITICAL

CRITICALIC,SMC,DEVELOPMENT-PROTO0,J31 SMC_PROG:PROTO01

IC,SMC,HS8/2117,9MMX9MM,TLP SMC_BLANK1 CRITICALU4900

U6100

CRITICAL

CRITICAL

SYNC_DATE=05/28/2009

ALL

138S0673

335S0550

341S3454

341S3510

341S3476 BOOTROM_PROG:FSB

SYNC_MASTER=K17_REF

BOOTROM_PROG:PIB2

BOOTROM_PROG:PROTO3

1 U6100

U6100IC,EFI,ROM,POST-PIB,J31

1

64 MBIT SPI SERIAL DUAL I/O FLASH

RADAR 10670230

ALL

353S3199

376S0977

IC,CPU,IVB,S,R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA

CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,MOLEX

CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,FOXCONN

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,FOXCONN

IC,ASSP,LIGHTRIDGE,PRQ,S LJJY,FCBGA,15X15MM,C1

IC,GPU,NV GK107-GTX-QS-A2

U4100

U1000

1

1

J31_CMNPTS,SODIMM:MOLEX,CPU:2_3GHZ,FB_512_SAMSUNG,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F32C CRITICAL

EEEE:F324

EEEE:F325

EEEE:F32C

EEEE:F327

CRITICAL

CRITICAL

CRITICAL

[EEEE_F329]

[EEEE_F328]

[EEEE_F324]

[EEEE_F325]

[EEEE_F32C]

[EEEE_F327]

LBL,P/N LABEL,PCB,28MM X 6 MM

J31_CMNPTS,SODIMM:FOXCONN,CPU:2_6GHZ,FB_1G_SAMSUNG,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F324

085-4620

639-3864

1 CPU:2_3GHZCRITICALU1000

CRITICAL353S3055 1

CRITICAL1338S0753

CRITICAL1

CPU:2_6GHZ1

U18001337S4269 CRITICAL

337S4268 1 CRITICAL

FB_512_HYNIXCRITICALU8400,U8450,U8500,U8550333S0620 4

333S0631 4

BOM Configuration

ALL197S0343197S0435 RADAR 10739227

ALL197S0343197S0434 RADAR 10739227

197S0432 ALL

ALL127S0134 Radar 10360888127S0111

ALL Radar 10257464128S0329128S0311

NXP alternate to Pericom DP muxALL

ALL155S0625

Tayo Yuden alt to Samsung caps138S0681

ALL Diodes alt for Rohm376S0859

Murata alt to Samsung cap138S0676 138S0691

376S0855 ALL

ALL353S3085 ST Micro alt to LT

157S0055 ALL Delta alt to TDK Magnetics

Acon (with liteon) alt to AconALL

ALL TDK alternate for ethernet transformer157S0084

ALL376S0604

371S0713 Radar 10562508371S0558

Tayo Yuden alt to Murata caps138S0671

ALL371S0709 NXP alternate for pin diodes

ALL

U6201 AUDIO CODEC OLD REV IS ALTERNATE FOR NEW REVALL353S2592

152S0796152S0685

138S0681 ALL

Samsung / Murata alt for Taiyo Yuden138S0652 138S0648 ALL

SODIMM_SCREW3,SODIMM_SCREW42 CRITICALSCR,M1.6X0.35X6.0,D4,HO.3,BLK,M97452-1708

CRITICAL2452-1708 SCR,M1.6X0.35X6.0,D4,HO.3,BLK,M97

1

CRITICALU8400,U8450,U8500,U85504333S0619

FB_1G_HYNIX_A_DIE4 U8400,U8450,U8500,U8550 CRITICAL333S0630 IC,SGRAM,GDDR5,64MX32,5GBPS,A-DIE,HF

CRITICAL UVGLUE_J311 UV_GLUE_J31725-1479 MLB LOCTITE UV EB CPU,PCH,T29,GPU,K91

SODIMM:FOXCONNJ29001516-0246

CRITICAL1 J2900 SODIMM:MOLEX516-0245

353S2603 ALL353S2805

ALL Sanyo alt to Kemet128S0257128S0264

376S0972 376S0612

U39901 CRITICAL341S3492

CRITICAL1

CRITICAL1335S0663

IC,TP PSOC,PROTO1,J31 TPAD_PROG:PROTO1CRITICALU5701341S3351 1

ALL Tayo Yuden alt to Murata inductors

138S0671 ALL

BOOTROM_BLANKU6100 CRITICAL

BOOTROM_PROG:PROTO1CRITICALU6100

IC,EFI,ROM,PROTO0, J31 BOOTROM_PROG:PROTO0CRITICAL1

BOOTROM_PROG:PROTO2CRITICALU6100

CRITICAL826-4393 LBL,P/N LABEL,PCB,28MM X 6 MM1

1 LBL,P/N LABEL,PCB,28MM X 6 MM

1826-4393 LBL,P/N LABEL,PCB,28MM X 6 MM

1 LBL,P/N LABEL,PCB,28MM X 6 MM826-4393

826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL1826-4393

1 TPAD_PROG:PROTO0CRITICALU5701IC,TP PSOC,K9x,DVT,PVT,J31

1 U5701341S3227 CRITICAL TPAD_PROG:PROTO3

1 SODIMM:MOLEXCRITICAL516S0805 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX

516S0806 CRITICALJ31001 SODIMM:FOXCONN

FB_1G_HYNIX_M_DIECRITICAL4333S0609 U8400,U8450,U8500,U8550IC,SGRAM,GDDR5,64MX32,4.2GBPS,M-DIE,HF

2376S0979 FDMC0225 Q7330,Q8360 FET:FAIRCRITICAL

376S0874 CRITICAL FET:FAIR2 Q7335,Q8361FDMC0202S

FET,N-CH,30V,3.6MOHM,LF,HF,RJK0332DPB FET:RENCRITICALQ70301376S0826

FET:REN376S0964 RJK02252 Q7330,Q8360 CRITICAL

CRITICAL SODIMM:HYBRIDCONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,FOXCONN J29001516-0246

376S0617 FET,N-CH,30V,30A,6.7MOHM,RJK0305DPB FET:RENCRITICALQ70351

FET,N-CH,30V,14A,13MOHM,FDMS0349 FET:FAIRQ70351 CRITICAL376S1018

FET,N-CH,30V,3.6MOHM,LF,HF,FDMS0355S FET:FAIRCRITICALQ70301376S0917

128S0282 ALL Panasonic alt to Sanyo

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX516S0805 CRITICAL SODIMM:HYBRID1 J3100

152S0518 ALL MAG LAYERS ALT TO CYNTEC

376S0777

MAG LAYERS ALT TO MURATAALL155S0329155S0457

GPU_INSULATOR1725-1607 INSULATOR,GPU,J31 CRITICAL

2 RJK0225 Q7335,Q8361376S0965 CRITICAL FET:REN

CRITICAL1 U6100

ALL127S0090127S0127 Radar 10382328

SODIMM_SCREW1,SODIMM_SCREW2

152S0896

ROHM alt to Toshiba N-FET

Diodes alt to Toshiba dual N-FET

add 4K byte as alternative to 2K

639-3861

639-3863

639-3862

639-3860

639-3865

J31_COMMON

J31_CMNPTS,SODIMM:FOXCONN,CPU:2_3GHZ,FB_512_HYNIX,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F327

J31_CMNPTS,SODIMM:FOXCONN,CPU:2_7GHZ,FB_1G_HYNIX_A_DIE,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F328

EEEE:F328

EEEE:F329

826-4393

085-4620 DEVEL_BOM

J31_CMNPTS607-9557 CRITICAL

PCBA,MLB_2P,FSB,2.6,MOL,1G_HY,FAIR,J31,F325

J31 MLB_KEP_2P DEVELOPMENT BOM

J31_CMNPTS,SODIMM:MOLEX,CPU:2_6GHZ,FB_1G_HYNIX_A_DIE,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F325

J31_CMNPTS,SODIMM:MOLEX,CPU:2_7GHZ,FB_1G_SAMSUNG,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F329

CMNPTS

157S0058

IC,EFI,ROM,FSB,J31

Radar 10562726

CRITICAL

CRITICAL

T29:YES

FB_512_SAMSUNG

1

IC,EFI,ROM,PROTO3,J31

337S4266

337S4239

338S1072

VREF:PROD

Murata alt to TDK cm mode filter

IC,EXTERNAL,PROTO2,PROTO3,J31

IC,SMC,DEVELOPMENT-PROTO1,J31

1

341S3099

IC,CPLD,LATTICE,GMUX,K91/K91F,J311 GMUX_PROGCRITICAL341S2830

IC,PLD,LATTICE,LFXP2-5E-5,132 BALL CSBGA GMUX_BLANKCRITICAL

CRITICAL T29ROM:PROG1

IR,ENCORE II,CY7C63833-LFXC341S2384 1 IR_PROGCRITICAL

335S0777 CRITICAL1 T29ROM:BLANK

T29MCU:BLANKCRITICAL337S3997 1

341S3365 T29MCU:PROG1

335S0852 CRITICAL GPUROM:BLANK1

1 TPAD_PROG:PIBCRITICAL341S3489 U5701IC,TP PSOC,PIB,J31

U5701 CRITICAL1341S3522 TPAD_PROG:FSB

ALL

376S0613

138S0638

ALL Dale/Vishay/TDK alt for Cyntec

341S3430 U3690

U3690

U9330

U9330

U4800

CRITICAL

ENETROM_BLANK

ENETROM_PROG:PROTO3

ENETROM_PROG:FSB

Taiyo Yuden alt for Murata 10 uF caps

371S0652

514-0788

155S0578

514-0671

1

IC,T29 EEPROM,LR,J30/J31

U8701

IC,TP PSOC,PROTO2,PROTO3-Z2,J31

U9600

U9600

IC,FLASH,SERIAL,SPI,1MBIT,2V7,8P,SOIC

IC,ENET ROM,1MBIT,DVT,PVT,K90i/K91x,J31

336S0042

U8000

IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN

IC,SGRAM,GDDR5,32MX32.1.25GHz,G-DIE,HF

IC,SDRAM,GDDR5,32MX32,1.5GHz,VEGA 44NM,B-DIE

IC,SGRAM,GDDR5,64MX32,5GBPS,D-DIE,HF

IC,CPU,IVB,S,R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA

VREF:ENG_M3

J31_DEVEL:PVT

607-9557

CMN PTS,PCBA,MLB_KEP_2P,J31

GMUX_PROG,IR_PROG,TPAD_PROG:FSB,ENETROM_PROG:FSB,T29ROM:PROG,T29MCU:PROG

CPUMEM_S0,RAMCFG_SLOT,USBHUB2513B,HUB_3NONREM,SMC_PACKAGE:PROD,MOJO:YES,TBTHV:P15V,SKIP_5V3V3:AUDIBLE

CMN PTS,PCBA,MLB_KEPLER,J31

PCBA,MLB_2P,FSB,2.7,FOX,1G_HY,REN,J31,F328

PCBA,MLB_2P,FSB,2.7,MOL,1G_SAM,FAIR,J31,F329

CRITICAL

PCBA,MLB_2P,FSB,2.6,FOX,1G_SAM,REN,J31,F324

PCBA,MLB_2P,FSB,2.3,MOL,512_SAM,FAIR,J31,F32C

BTPWR:S4,TPAD:Z2,T29:YES,TBTBST:Y,SDRV_PD,SDRVI2C:MCU,T29_DP_HPD:ALL_OR,LPCPLUS_R:YES,MEM_VDD_SEL:GPIO15,GPU:2P

ALTERNATE,COMMON,J31_COMMON1,J31_COMMON2,J31_PROGPARTS,J31_PROGPARTS1,UVGLUE_J31,J31_PVT

IC,EEPROM,SERIAL,8KB,SOIC

IC,PROGRMD,LPC1112A,T29 PORT MCU,PVT,HVQFN25,J31

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

Taiyo Yuden alt for Samsung

IC,EFI,ROM,PROTO2,J31

IC,EFI,ROM,PROTO1, J31

AON alternate to SiliconixALL

1

341S3419

341S3344

341S3257

338S0895

1 CRITICALU4900341S3296 IC,SMC,EXTERNAL,FSB,V2.1A143,J31 SMC_PROG:FSB

U49001

335S0740

341S3401

341S3481

341S3258

341S3294

341S3297 CRITICALIC,SMC,EXTERNAL,RISKRAMP,J31

For Q7260, Fairchild alt to Ren.ALL

353S3055353S3312

CPU:2_7GHZ

VREFDQ:M1_DAC,VREFCA:LDO_DAC

VREFDQ:M1_M3,VREFCA:LDO_DAC

VREFDQ:M1_M3,VREFCA:LDO

XDP,XDP_CONN_PCH,XDP_CONN_CPU,XDP_CPU:BPM,XDP_PCH

SMC_PROG:RR

VREF:PROD,XDP,XDP_CPU:BPM,BKLT:PROD,LOADISNS:NO,XWLOADISNS:NO

DDRVREF_DAC,VREF:ENG_M3,IVB_PPT_XDP,GMUX_JTAG_CONN,LPCPLUS_CONN:YES,BKLT:ENG,S0PGOOD_ISL,CPURIPPLE_ENG,LOADISNS:YES,XWLOADISNS:YES,DEBUG_ADC

DDRVREF_DAC,VREF:ENG_M3,IVB_PPT_XDP,LPCPLUS_CONN:YES,BKLT:PROD,S0PGOOD_ISL,LOADISNS:YES,XWLOADISNS:NO

LPCPLUS_CONN:YES,XDP_CONN_CPU

SMC_PROG:RR,BOOTROM_PROG:FSB

IC,GPUROM,J31,BLANK

U3990

U3990

U4900

IC,PRGRMD,ENET,SPI ROM,FSB,J30/J31

341S3096

051-9585

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J9000 (LVDS CONN)

FUNC_TEST

J5800 (IPD FLEX CONN)

3 TPs

7 TPs

7 TPs

J6900 (DC POWER CONN)

J5815 (KBD BACKLIGHT CONN)

Functional Test Points

NO_TEST

J5660 (RIGHT FAN CONN)

J6780 (MIC CONN)

2 TP needed

NO_TEST=TRUE

J3501 & J3502 (AIRPORT/BT/CAMERA CONN)

6 TPs

POWER RAILS

J6950 (BIL CABLE CONN)

J6781 & J6782 (SPEAKERS CONN)

4 TPs

3 TP needed

NC NO_TESTs2 TPs

NO_TEST4 TPs

J6950 (MAIN BATT CONN)

2 TPs

J4501 (SATA HDD CONN)

J4500 (SATA ODD CONN)

6 TPs

8 TPs

4 TPs

8 TPs

J6955 (BAT LED CONN)

3 TPs

2 TPs needed

FUNC_TEST

J5100

2 TPs

NO_TEST

NC NO_TESTs

J6950 (BAT CONN)

NO_TEST

NO_TEST

NC NO_TESTsFUNC_TEST

PCH ALIASES

ICT Test Points

CPU NO_TESTsJ5650 (LEFT FAN CONN)

NO_TEST=TRUE

7 TPs

2 TPs

10 TPs

J5713 (KEY BOARD CONN)

I1000

I1001

I1002

I1003

I1004

I1005

I1006

I1007

I1008

I1009

I1010

I1011

I1012

I1013

I1014

I1015

I1016

I1017

I1018

I1019

I1020

I1021

I1022

I1024

I1025

I1026

I1027

I1028

I1029

I1031

I1032

I1033

I1034

I1035

I1052

I1053

I1054

I1055

I1056

I1057

I1058

I1059

I1060

I1061

I1062

I1063

I1064

I1086

I1088

I1089

I1090

I1092

I1093

I1094

I1095

I1096

I1097

I1098

I1099

I1100

I1101

I1102

I1103

I1104

I1105

I1106

I1107

I1108

I1109

I1110

I1111

I1112

I1113

I1114

I1115

I1116

I1117

I1118

I1119

I1120

I1121

I1122

I1123

I1124

I1125

I1126

I1127

I1128

I1129

I1130

I1131

I1132

I1134

I1135

I1136

I1140

I1141

I1142

I1143I1145

I1146

I1149

I1150

I1151

I1152

I1160

I1161

I1273

I1288

I1292

I1297

I1436

I1437

I1438

I1439

I1440

I1441

I1442

I1443

I1464

I1481

I1483

I1485

I1486

I1487

I1488

I1489

I1490

I1491

I1492

I1493

I1496

I1508

I1509

I1510

I1513

I1514

I1515

I1516

I1517

I1518

I1519

I1520

I1521

I1522

I1523

I1524

I1525

I1526

I1527

I1528

I1529

I1530

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SYNC_MASTER=K18_MLB SYNC_DATE=04/27/2010

Functional / ICT Test

TRUE WS_KBD1

WS_KBD2TRUE

WS_KBD7TRUE

WS_KBD11TRUE

TRUE WS_KBD10

TRUE WS_KBD9

TRUE WS_KBD14

TRUE WS_KBD18

WS_KBD15_CAPTRUE

SMC_TDITRUE

TRUE SMC_TDO

SMC_TMSTRUE

SMC_ROMBOOTTRUE

SMC_RX_LTRUE

TRUE PM_CLKRUN_L

WS_KBD6TRUE

WS_KBD20TRUE

WS_KBD23TRUE

TRUE PP3V42_G3H

SMC_RESET_LTRUE

TP_CRT_IG_DDC_CLK

TP_CRT_IG_RED

TRUE SMC_TX_L

PP3V42_G3HTRUE

TRUE PM_SLP_S3_L

WS_KBD17TRUE

Z2_BOOST_ENTRUE

TRUE PP3V3_S5

PPBUS_G3HTRUE

TRUE PPVCORE_GPU

TRUE PP5V_S3_IR_R

IR_RX_OUTTRUE

MAKE_BASE=TRUETRUE NC_PCH_LVDS_VBG

NC_TBT_PCIE_RESET3_LTRUEMAKE_BASE=TRUE

TRUE TP_AUD_GPIO_1

TRUE DP_TBTSNK1_ML_P<3..0>

TRUE DP_TBTSNK1_ML_N<3..0>

TP_DP_TBTSRC_AUXCH_CNTRUE

SMBUS_SMC_2_S3_SCLTRUE

TRUE PP3V3_S5_AVREF_SMC

TRUE PP3V3_S0

TRUE WS_KBD21

TRUE WS_KBD22

DP_TBTSNK0_ML_C_P<3..0>TRUE

PP5V_S0TRUE

TRUE PCHVCCIOS0_OCSET

TRUE USB3_EXTB_TX_F_P

TRUE USB3_EXTB_TX_C_P

TRUE USB3_EXTB_TX_P

TRUE USB3_EXTB_TX_F_NTRUE USB3_EXTB_TX_C_NTRUE USB3_EXTB_TX_NTRUE USB3_EXTB_RX_F_PTRUE USB3_EXTB_RX_F_NTRUE USB3_EXTB_RX_PTRUE USB3_EXTB_RX_N

TRUE USB3_EXTA_TX_F_P

TRUE USB3_EXTA_TX_C_P

TRUE USB3_EXTA_TX_P

TRUE USB3_EXTA_RX_PTRUE USB3_EXTA_RX_N

TRUE USB3_EXTA_TX_F_NTRUE USB3_EXTA_TX_C_NTRUE USB3_EXTA_TX_N

TRUE USB3_EXTA_RX_F_N

TRUE USB3_EXTA_RX_F_P

TRUE P5VS3_SNUBR

TRUE P5VS3_VFB1

PCHVCCIOS0_VBSTTRUE

MEM_B_BA<2..0>TRUE

MEM_B_CKE<1..0>TRUE

MEM_B_CLK_N<1..0>TRUE

MEM_B_CLK_P<1..0>TRUE

MEM_B_CS_L<1..0>TRUE

FB_B1_A<8..0>TRUE

VCCSAS0_VBSTTRUE

PPVCORE_S0_CPU_PH2_LTRUE

TRUE PPVCORE_S0_CPU_PH1_L

VCCSAS0_LLTRUE

VCCSAS0_DRVLTRUE

PPVCORE_S0_CPU_PH3_LTRUE

VCCSAS0_B00T_RCTRUE

TRUE PCHVCCIOS0_DRVL

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_MLP<3..0>

TP_DP_IG_D_AUXN

TP_SDVO_TVCLKINNMAKE_BASE=TRUETRUE NC_SDVO_TVCLKINN

P5VS3_VBSTTRUE

TRUE P5VS3_DRVL

TRUE P5VS3_DRVH

DDRREG_FBTRUE

CPUVCCIOS0_VBSTTRUE

CPUIMVP_VSWG1TRUE

CHGR_BOOTTRUE

NC_DP_IG_C_MLP<3..0>MAKE_BASE=TRUETRUE

MAKE_BASE=TRUETRUE NC_DP_IG_D_MLN<3..0>

TP_SDVO_STALLP

TP_SDVO_INTP

TP_AUD_GPIO_2TRUE

TRUE BI_MIC_N

LVDS_CONN_A_CLK_F_PTRUE

TRUE LVDS_CONN_B_DATA_P<2>

LED_RETURN_1TRUE

TP_SATA_B_D2RP

TP_PSOC_P1_3

P3V3S5_VFB2TRUE

TRUE CPUIMVP_VSWG2

CPUVCCIOS0_DRVLTRUE

TRUE CPUVCCIOS0_OCSET

TRUE DDRREG_DRVL

DDRREG_LLTRUE

DC_TEST_B3_C2TRUE

CPUVCCIOS0_FBTRUE

TRUE CPUVCCIOS0_LL

TRUE P3V3S5_DRVH

TRUE P3V3S5_DRVL

P5V5G3H_BOOSTTRUE

P5V5G3H_SWTRUE

DMI_S2N_N<3>TRUE

DMI_S2N_P<3>TRUE

DMI_S2N_N<1..0>TRUE

TRUE DMI_N2S_P<3..1>

DMI_N2S_N<3..1>TRUE

DMI_S2N_P<1..0>TRUE

P3V3S5_LLTRUE

CPUVCCIOS0_DRVHTRUE

P3V3S5_TGTRUE

CPUIMVP_SLEWTRUE

TRUE CPUIMVP_PHASE3

TRUE CPUIMVP_TONA

TRUE P5VS3_CSP1_R

P1V8S0_SWTRUE

TRUE P3V3S5_CSP2_R

P3V3S5_SNUBRTRUE

TRUE GFXIMVP_VBST

GPUFB_BOOT_RCTRUE

TRUE GPUFB_LL

TRUE GPUFB_DRVL

TRUE GPUFB_DRVH

GFXIMVP_VBST_RTRUE

GFXIMVP_PHASETRUE

CPUIMVP_UGATE2GTRUE

TRUE CPUIMVP_BOOT1_RC

CPUIMVP_PH3_SNUBTRUE

CPUVCCIOS0_RTNTRUE

DDRREG_DRVHTRUE

TRUE PCHVCCIOS0_LL

PCHVCCIOS0_FBTRUE

TRUE PCHVCCIOS0_DRVH

TRUE PCHVCCIOS0_BOOT_RC

P3V3S5_VBSTTRUE

TRUE P3V42G3H_SW

TRUE P5VS3_LL

P1V05_GPU_DRVHTRUE

P1V05_GPU_LLTRUE

P1V05_GPU_VBSTTRUE

P1V8S0_FBTRUE

P1V05_GPU_BOOT_RCTRUE

CPUIMVP_BOOT1TRUE

P1V05_GPU_DRVLTRUE

GFXIMVP_PHASE_LTRUE

TRUE CPUIMVP_PH1_SNUB

CPUIMVP_LGATE1GTRUE

GPUFB_VBSTTRUE

CPUIMVP_PHASE2GTRUE

CPUIMVP_PHASE2TRUE

TRUE CPUIMVP_PHASE1

CPUIMVP_UGATE3TRUE

TRUE GFXIMVP_UGATE_R

GFXIMVP_LGATETRUE

TRUE DDRREG_TRIP

TRUE GFXIMVP_LL_RC

GFXIMVP_UGATETRUE

CPUIMVP_PHASE1GTRUE

CPUIMVP_PH2_SNUBTRUE

CPUIMVP_SKIPTRUE

CPUIMVP_TONBTRUE

CPUVCCIOS0_BOOT_RCTRUE

CPUIMVP_UGATE1TRUE

TRUE CPUIMVP_UGATE1G

CPUIMVP_UGATE2TRUE

CPUIMVP_LGATE3TRUE

CPUIMVP_LGATE2GTRUE

TRUE CPUIMVP_LGATE2

CPUIMVP_LGATE1TRUE

CHGR_PHASETRUE

TRUE CPUIMVP_BOOT1G_R

TRUE CPUIMVP_BOOT1G

TRUE CPUIMVP_AXG2_SNUB

CHGR_VCOMPTRUE

CPUIMVP_BOOT3TRUE

TRUE CPUIMVP_BOOT2G_RCTRUE CPUIMVP_BOOT2GTRUE CPUIMVP_BOOT2_RCTRUE CPUIMVP_BOOT2

CPUIMVP_AXG1_SNUBTRUE

CPU_VCCSASENSE_DIVTRUE

CHGR_UGATETRUE

TRUE CPUIMVP_BOOT3_RC

CHGR_LGATETRUE

CHGR_ICOMP_RCTRUE

TRUE DP_TBTSNK1_AUXCH_C_P

DP_SDRVA_ML_C_P<0>TRUE

TP_DP_TBTSRC_ML_CN<3..0>TRUE

TP_DP_TBTSRC_ML_CP<3..0>TRUE

TRUE DP_SDRVA_ML_C_N<2>

TRUE DP_SDRVA_ML_C_P<2>

TP_TBT_PCIE_RESET0_L

TRUE WS_KBD5

WS_KBD16_NUMTRUE

WS_KBD19TRUE

TRUE LVDS_CONN_A_DATA_P<2>

TRUE LVDS_CONN_B_DATA_N<0>

LVDS_CONN_A_CLK_F_NTRUE

TRUE Z2_RESET

Z2_KEY_ACT_LTRUE

TRUE PP3V3_S4

WS_KBD3TRUE

TRUE WS_KBD4

TP_DP_IG_D_MLN<3..0>

TP_DP_IG_D_AUXP

TP_SATA_E_R2D_CN

TP_SATA_F_D2RN

TRUE TP_FW643_SE

TRUE MEM_A_CLK_N<1..0>

TRUE MEM_A_ODT<1..0>

TRUE MEM_A_SA<1..0>

TRUE MEM_A_DQ<63..0>

MEM_A_DQS_P<7..0>TRUE

FB_A0_WCLK_N<1..0>TRUE

TRUE FB_A0_WCLK_P<1..0>

FB_A0_DBI_L<3..0>TRUE

FB_A1_DQ<31..0>TRUE

FB_A1_ABI_LTRUE

MAKE_BASE=TRUETRUE NC_SATA_E_D2RP

MAKE_BASE=TRUETRUE NC_SATA_E_R2D_CP

TP_SATA_F_R2D_CN


TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_B_R2D_CN

TP_SATA_B_D2RN

NC_TBT_MONDC0MAKE_BASE=TRUETRUE

TP_PCIE_CLK100M_PE6P

TP_SATA_F_R2D_CP TRUEMAKE_BASE=TRUE

NC_SATA_F_R2D_CP

MAKE_BASE=TRUETRUE NC_SATA_F_D2RN

TRUE NC_SATA_F_R2D_CNMAKE_BASE=TRUE

TP_SATA_F_D2RP TRUEMAKE_BASE=TRUE

NC_SATA_F_D2RP

MAKE_BASE=TRUETRUE NC_SATA_E_R2D_CN

TP_SATA_E_R2D_CP

TRUEMAKE_BASE=TRUE

NC_SATA_D_R2D_CP

TP_SATA_E_D2RP

NC_SATA_D_R2D_CNMAKE_BASE=TRUETRUE

TRUE NC_SATA_B_R2D_CPMAKE_BASE=TRUE


TP_PCIE_CLK100M_PE7N

MAKE_BASE=TRUETRUE NC_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE4PMAKE_BASE=TRUETRUE

NC_PCIE_CLK100M_PE4NMAKE_BASE=TRUETRUE

TRUEMAKE_BASE=TRUE

NC_SMC_P41

MAKE_BASE=TRUENC_LPC_DREQ0_L

TP_CRT_IG_HSYNC

TRUEMAKE_BASE=TRUE

NC_CRT_IG_GREEN

TRUEMAKE_BASE=TRUE

NC_CRT_IG_BLUE

BKLT_ENTRUE

TRUE ISSP_SDATA_P1_0

LCD_BKLT_PWMTRUE

LPC_FRAME_LTRUE

LPC_PWRDWN_LTRUE

TRUE TP_FW643_CE

DC_TEST_BH3_BJ2TRUE

TRUE TP_FW643_TCK

TP_CLINK_CLK

FB_A1_WCLK_P<1..0>TRUE

TRUE MEM_A_RAS_L

TRUE MEM_A_CAS_L

TRUE MEM_A_A<15..0>

TRUE FB_B0_EDC<3..0>

FB_B0_WCLK_N<1..0>TRUE

FB_B0_WCLK_P<1..0>TRUE

FB_B1_DQ<31..0>TRUE

FB_B1_EDC<3..0>TRUEFB_A1_EDC<3..0>TRUE

TRUE FB_A1_A<8..0>

TRUE NC_DP_IG_D_MLP<3..0>MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_GPU_BUFRST_LTRUE

NC_DP_IG_D_HPDTRUEMAKE_BASE=TRUE

TP_DP_IG_C_MLN<3..0>

TP_DP_IG_C_AUXN

TP_DP_IG_D_HPD

TP_SDVO_INTN

NC_GPU_GSTATE<0>TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUETRUE NC_CRT_IG_DDC_DATA

MAKE_BASE=TRUETRUE NC_DP_IG_D_AUXP

MAKE_BASE=TRUENC_DP_IG_D_AUXNTRUE

NC_DP_IG_D_CTRL_CLKTRUEMAKE_BASE=TRUE

NC_FW0_TPBNTRUE

NC_FW0_TPAPTRUE

NC_ALS_GAINTRUE

NC_DP_IG_C_MLN<3..0>TRUEMAKE_BASE=TRUE

NC_DP_IG_C_AUXNTRUEMAKE_BASE=TRUE

MAKE_BASE=TRUETRUE NC_PCIE_CLK100M_PEBN

TP_CLINK_RESET_L

TP_CLINK_DATA

TP_SDVO_TVCLKINP

TRUEMAKE_BASE=TRUE

NC_TP_CPU_RSVD_NCTF<8..5>

TP_DP_IG_C_CTRL_CLK

TP_DP_IG_C_CTRL_DATA

NC_DP_IG_C_AUXPTRUEMAKE_BASE=TRUE

NC_CRT_IG_VSYNCTRUEMAKE_BASE=TRUE

MAKE_BASE=TRUETRUE NC_CRT_IG_RED

MAKE_BASE=TRUETRUE NC_TP_CPU_RSVD<24..15>

TP_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUENC_CLINK_DATATRUE

NC_CLINK_CLKMAKE_BASE=TRUETRUE

NC_TP_CPU_RSVD<2..1>MAKE_BASE=TRUETRUE

TP_CPU_RSVD_NCTF<8..5>

TP_CRT_IG_DDC_DATA

TRUE LPCPLUS_GPIO

TP_CPU_RSVD<24..15>

TP_CPU_RSVD<43..32>

TP_CPU_RSVD<58..45>

TRUE NC_SMC_FAN_2_TACH

TRUE NC_SMC_FAN_2_CTL

TRUE NC_FW2_TPBN

NC_FW2_TPBPTRUE

NC_FW2_TPAPTRUE

NC_ESTARLDO_ENTRUE

NC_FW643_AVREGMAKE_BASE=TRUETRUE

TRUEMAKE_BASE=TRUE

NC_DP_IG_C_CTRL_DATA

TRUEMAKE_BASE=TRUE

NC_CRT_IG_DDC_CLK

NC_TP_CPU_RSVD<43..32>MAKE_BASE=TRUETRUE

MAKE_BASE=TRUETRUE NC_TP_CPU_RSVD<65..62>

NC_SMC_FAN_3_CTLTRUE

TRUE NC_SMC_FAN_3_TACH

NC_CRT_IG_HSYNCTRUEMAKE_BASE=TRUE

TP_CPU_RSVD<27..26>

TP_CPU_RSVD<2..1>

TP_GPU_MIOA_D<9..0>

ISSP_SCLK_P1_1TRUE

LPC_AD<0..3>TRUE

TRUE MEM_B_WE_L

TRUE MEM_B_CAS_L

TRUE MEM_B_RAS_L

MEM_B_DQ<63..0>TRUE

MEM_B_SA<1..0>TRUE

TRUE MEM_A_BA<2..0>

TRUE MEM_A_CLK_P<1..0>

FB_B0_DQ<31..0>TRUE

TRUE MEM_B_A<15..0>

TRUE FB_B1_ABI_L

FB_B1_WCLK_N<1..0>TRUE

FB_A0_ABI_LTRUE

FB_A0_EDC<3..0>TRUE

FB_A0_A<8..0>TRUE

TRUE FB_B1_WCLK_P<1..0>

FB_B1_DBI_L<3..0>TRUE

TP_CRT_IG_VSYNC

TRUE LPC_CLK33M_LPCPLUS

LPCPLUS_RESET_LTRUE

TRUE TP_SMC_P24

TRUE DC_TEST_BH1_BG2

MAKE_BASE=TRUENC_LVDS_IG_B_CLKNTRUE

TP_GPU_GSTATE<1>

NC_DP_TBTSRC_ML_CP<0..3>TRUEMAKE_BASE=TRUE

TP_LVDS_IG_CTRL_DATA

TRUEMAKE_BASE=TRUE

NC_HDA_SDIN2

TRUE NC_LVDS_IG_CTRL_DATAMAKE_BASE=TRUE


TRUE TP_BKL_FAULT

PP5V_S0TRUE

TRUE PP3V3_S0

TP_CRT_IG_BLUE

TP_CRT_IG_GREEN

TRUE LVDS_CONN_A_DATA_N<1>

LVDS_DDC_CLKTRUE

LVDS_CONN_A_DATA_N<2>TRUE

LVDS_CONN_A_DATA_P<0>TRUE

FB_A1_WCLK_N<1..0>TRUE

TRUE FB_B0_ABI_L

FB_B0_A<8..0>TRUE

TRUE MEM_B_DQS_P<7..0>

MEM_B_DQS_N<7..0>TRUE

MEM_B_ODT<1..0>TRUE

TRUE FB_A0_DQ<31..0>

MAKE_BASE=TRUETRUE NC_PCIE_CLK100M_PE7NMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6PTRUE

NC_SATA_B_D2RPTRUEMAKE_BASE=TRUE NC_SATA_B_R2D_CNMAKE_BASE=TRUETRUE

TRUEMAKE_BASE=TRUE

NC_SATA_D_D2RN

TP_SATA_D_D2RP

TP_SATA_B_R2D_CP

MEM_A_CS_L<1..0>TRUE

TRUE TP_SPI_DESCRIPTOR_OVERRIDE_L

TRUE Z2_MISO


TRUE PP18V5_DCIN_FUSE

LPC_SERIRQTRUE

TRUE SMC_ONOFF_L

TRUE SPKRCONN_R_OUT_N

LVDS_CONN_B_DATA_P<1>TRUE

TRUE LVDS_DDC_DATA

LVDS_CONN_B_DATA_P<0>TRUE

TRUE BI_MIC_PTRUE BI_MIC_SHIELD

LED_RETURN_5TRUE

LVDS_CONN_A_DATA_N<0>TRUE

LVDS_CONN_B_DATA_N<1>TRUE

TRUE SMBUS_SMC_5_G3_SDA

TRUE SYS_DETECT_L

TRUE SMBUS_SMC_5_G3_SCL

TRUE PP3V42_G3H

TRUE SMBUS_SMC_5_G3_SDA

TRUE LED_RETURN_3

LVDS_CONN_B_CLK_F_PTRUE

TRUE SMBUS_SMC_5_G3_SCL

TRUE SMC_BIL_BUTTON_L

TRUE SMC_LID_R

ADAPTER_SENSETRUE

TRUE SMBUS_SMC_2_S3_SDA

TRUE PSOC_SCLK

TRUE PSOC_MISO

PICKB_LTRUE

TRUE PSOC_F_CS_L

TRUE Z2_CLKIN

TRUE SPKRCONN_S_OUT_N

PPVOUT_S0_LCDBKLTTRUE

LVDS_CONN_B_DATA_N<2>TRUE

LED_RETURN_2TRUE

LED_RETURN_4TRUE

TRUE PP5V_SW_ODD

TRUE SATA_ODD_R2D_N

LVDS_CONN_B_CLK_F_NTRUE

LED_RETURN_6TRUE

SATA_ODD_R2D_PTRUE

SATA_ODD_D2R_C_NTRUE

SATA_ODD_D2R_C_PTRUE

SMC_ODD_DETECTTRUE

KBDLED_ANODETRUE

TRUE SMC_KDBLED_PRESENT_L

SATA_HDD_D2R_C_NTRUE

SATA_HDD_R2D_NTRUE

TRUE SATA_HDD_D2R_C_P

TRUE SATA_HDD_R2D_P

TRUE PP5V_S0_HDD_FLT

TRUE PP5V_S3_IR_R

TRUE IR_RX_OUT

TRUE SSD_OOBR2D_LTRUE SSD_OOBD2R_L

MAKE_BASE=TRUETRUE NC_LVDS_IG_CTRL_CLK

MAKE_BASE=TRUETRUE NC_TBT_PCIE_RESET0_L

TRUEMAKE_BASE=TRUE

NC_LVDS_IG_BKL_PWM

TRUEMAKE_BASE=TRUE

NC_SDVO_INTN

NC_SDVO_STALLNTRUEMAKE_BASE=TRUE

NC_SDVO_TVCLKINPMAKE_BASE=TRUETRUE

TP_SDVO_STALLN

TP_DP_TBTSRC_ML_CN<0..3>

Z2_CS_LTRUE

Z2_MOSITRUE

TRUE Z2_HOST_INTN

TRUE PP5V_S5_CUMULUS

PP18V5_Z2TRUE

TP_LVDS_IG_BKL_PWM

TRUE MEM_A_CKE<1..0>

MEM_A_DQS_N<7..0>TRUE

NC_SATA_D_D2RPTRUEMAKE_BASE=TRUE

NC_SATA_E_D2RNMAKE_BASE=TRUETRUE

TP_LPC_DREQ0_L

NC_CLINK_RESET_LMAKE_BASE=TRUETRUE

TP_PCIE_CLK100M_PEBN

TP_PCIE_CLK100M_PEBP

TRUE MEM_A_WE_L

FB_A1_DBI_L<3..0>TRUE

FB_B0_DBI_L<3..0>TRUE

NC_DP_IG_C_HPDTRUEMAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_FW643_TDITRUE

NC_FW0_TPBPTRUE

TRUE NC_FW2_TPAN

NC_FW2_TPBIASTRUE

P5VS3_TGTRUE

MAKE_BASE=TRUENC_DP_IG_D_CTRL_DATATRUE

NC_DP_IG_C_CTRL_CLKMAKE_BASE=TRUETRUE

TP_DP_IG_C_HPD

TP_FW643_TDI

TP_FW643_AVREG

TP_DP_IG_C_AUXP

TP_AUD_LO1_L_PTRUE

TP_AUD_LO1_L_NTRUE

SMC_TCKTRUE

TRUE PM_SYSRST_L

DP_TBTSNK0_AUXCH_C_NTRUE

TRUE DP_TBTSNK0_ML_N<3..0>

TRUE TP_DP_TBTSRC_AUXCH_CP

TRUE DP_SDRVA_ML_C_N<0>

TRUE TP_TBT_PCIE_RESET2_L

TP_LVDS_IG_B_CLKP

TP_TBT_PCIE_RESET0_LTRUE


TRUE SPIROM_USE_MLB

SPI_ALT_CLKTRUE

TRUE SPI_ALT_CS_L

TRUE SPI_ALT_MOSI

TP_LVDS_IG_CTRL_CLK

TP_PCH_LVDS_VBG

TP_HDA_SDIN2

TP_TBT_MONOBSN


TP_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6NMAKE_BASE=TRUETRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5PTRUE

TRUE TP_GMUX_PL6B

TRUE TP_XDPPCH_HOOK2

TRUE TP_XDPPCH_HOOK3

PP3V3_S3TRUE

TRUE DP_SDRVA_ML_P<2>

DP_SDRVA_ML_P<0>TRUE

DP_SDRVA_ML_N<0>TRUE

TP_PCI_CLK33M_OUT3MAKE_BASE=TRUETRUE NC_PCI_CLK33M_OUT3

NC_LVDS_IG_B_CLKPTRUE

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

TP_LVDS_EG_BKL_PWM

TP_SATA_D_D2RN

TP_PSOC_SDATRUE

TRUE TP_FW643_TMS

TRUE TP_FW643_VBUF

TRUE TP_FW643_VAUX_ENABLE

TRUE DP_SDRVA_ML_N<2>

DP_TBTSNK1_ML_C_N<3..0>TRUE

DP_TBTSNK1_ML_C_P<3..0>TRUE

PEG_R2D_P<7..0>TRUE


PEG_D2R_C_P<7..0>TRUE

TRUE PEG_R2D_N<7..0>

TRUE PEG_D2R_C_N<7..0>

TRUE PP1V5_S3

PPDCIN_G3HTRUE

TRUE PPVP_FW

TRUE PPVTTDDR_S3

TRUE PPVCORE_S0_CPU

TRUE PSOC_MOSI

TRUE Z2_SCLK

TP_HDA_SDIN3

SPI_ALT_MISOTRUE

TRUE PP3V42_G3H

TRUE PP5V_S0

PP5V_S3TRUE

TRUE TP_FW643_SCIFMC

TRUE TP_FW643_SCIFDAIN

TRUE TP_FW643_SM

TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7P

MAKE_BASE=TRUENC_SATA_B_D2RNTRUE

TRUEMAKE_BASE=TRUE

NC_PSOC_P1_3

CPUIMVP_UGATE2TRUE

TRUEMAKE_BASE=TRUE

NC_PCI_PME_L

TP_1V05_S0_PCH_VCCAPLLEXPTRUE

CPUIMVP_BOOT2TRUE

TRUE CPUIMVP_BOOT1

TP_PCI_PME_L


TRUE DP_TBTSNK1_AUXCH_P

TRUE DP_TBTSNK1_AUXCH_N

TRUE PP1V8_S0

TRUE PP3V3_ENET

TRUE PP3V3_FW_FWPHY

TRUE PP1V2_S0

TRUE TP_FW643_TDO

TRUE TP_SMC_P10

TP_P7_7TRUE

TRUE TP_PSOC_SCL

TP_SMC_P41

TRUE NC_PCIE_CLK100M_PEBPMAKE_BASE=TRUE

TRUE PPVBAT_G3H_CONN

TRUE TP_FW643_SDA

TRUE TP_FW643_SCIFDOUT

TRUE TP_FW643_SCIFCLK

TRUE TP_FW643_FW620_L

TRUE TP_FW643_JASI_EN

TP_USB_HUB1_PRTPWR1TRUE

TRUE TP_USB_HUB1_OCS1

TRUE TP_USB_HUB2_OCS1

TRUE TP_DC_TEST_A62

TRUE TP_USB_HUB2_PRTPWR1

TRUE Z2_DEBUG3

TRUE PP3V3_S4

TRUE SPKRCONN_S_OUT_P

TRUE SPKRCONN_R_OUT_P

SPKRCONN_L_OUT_NTRUE

TRUE SPKRCONN_L_OUT_P

TP_TBT_MONDC0

MAKE_BASE=TRUETRUE NC_TBT_MONDC1

TP_GPU_GSTATE<0>

TP_GPU_BUFRST_L

NC_TBT_PCIE_RESET2_LMAKE_BASE=TRUETRUE

NC_TBT_PCIE_RESET1_LMAKE_BASE=TRUETRUE

MAKE_BASE=TRUETP_DP_TBTSRC_AUXCH_CNTRUE

MAKE_BASE=TRUETRUE TP_DP_TBTSRC_AUXCH_CPTP_DP_TBTSRC_AUXCH_CP

TRUE WS_KBD12

WS_KBD8TRUE NC_TP_CPU_RSVD<27..26>TRUEMAKE_BASE=TRUE

NC_TP_CPU_RSVD<58..45>TRUEMAKE_BASE=TRUE

TRUE WS_KBD13

TRUE SMC_LID_R

SYS_LED_ANODETRUE


TP_DP_TBTSRC_AUXCH_CN

TRUE SYS_LED_ANODE_R

TRUE DP_TBTSNK0_AUXCH_N

TBT_R2D_C_N<1..0>TRUE

DP_TBTSNK0_AUXCH_C_PTRUE

TRUE WS_KBD_ONOFF_L

WS_LEFT_SHIFT_KBDTRUE

TRUE WS_LEFT_OPTION_KBD

TBTDPA_ML_N<3..0>TRUE

TBTDPA_ML_P<3..0>TRUE

TBT_R2D_C_P<1..0>TRUE

TRUE PP1V05_S0GPU

TRUE FAN_LT_PWM

FAN_LT_TACHTRUE

TP_DP_TBTSRC_ML_CP<0..3>

NC_DP_TBTSRC_ML_CN<0..3>MAKE_BASE=TRUETRUE

TP_GPU_MIOA_DENC_TBT_MONOBSNMAKE_BASE=TRUETRUE

NC_TBT_MONOBSPMAKE_BASE=TRUETRUE

TP_TBT_MONDC1

TP_TBT_MONOBSP

DP_TBTSNK0_AUXCH_PTRUEPP0V75_S0_DDRVTTTRUE

TRUE PCIE_CLK100M_AP_CONN_N

TRUE FAN_RT_TACH

TRUE WIFI_EVENT_L

TRUE AP_CLKREQ_Q_L

TRUE PCIE_AP_R2D_P

PCIE_CLK100M_AP_CONN_PTRUE

TRUE PP3V3_S3RS4_BT_F

LVDS_CONN_A_DATA_P<1>TRUE

AP_RESET_CONN_LTRUE

PP5V_S3_ALSCAMERA_FTRUE

TRUE PP5V_S0

PP3V3_WLANTRUE

TRUE USB_CAMERA_CONN_N

SMBUS_SMC_2_S3_SCLTRUE

SMBUS_SMC_2_S3_SDATRUE

USB_CAMERA_CONN_PTRUE

TRUE FAN_RT_PWM

PP3V3_SW_LCDTRUE

MAKE_BASE=TRUETRUE NC_GPU_GSTATE<1>

MAKE_BASE=TRUETRUE NC_GPU_MIOA_D<9..0>

TRUEMAKE_BASE=TRUE

NC_GPU_MIOA_DE

MAKE_BASE=TRUE

NC_LVDS_EG_BKL_PWMTRUETRUE DP_TBTSNK0_ML_P<3..0>

TRUE DP_TBTSNK0_ML_C_N<3..0>PP1V0_FW_FWPHYTRUE

TRUE PP1V2_ENET

PP1V05_S0TRUE

TRUE USB_BT_CONN_N

WS_CONTROL_KBDTRUE

TP_HDA_SDIN1 NC_HDA_SDIN1TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUETRUE NC_HDA_SDIN3

TRUE NC_SDVO_STALLPMAKE_BASE=TRUE

MAKE_BASE=TRUETRUE NC_SDVO_INTP

TP_SATA_E_D2RN

TP_CPU_RSVD<65..62>

PCIE_AP_R2D_NTRUE

TRUE PCIE_WAKE_L

TP_DC_TEST_D65TRUETRUE FDI_LSYNC<1..0>

TRUE FDI_FSYNC<1..0>

DMI_S2N_P<1>TRUE

TRUE DMI_S2N_N<1>

TRUE FDI_DATA_P<1>

FDI_DATA_N<1>TRUE

TRUE FDI_DATA_N<7..4>

FDI_INTTRUE

TRUE FDI_DATA_P<7..4>

TRUE DP_TBTSNK1_AUXCH_C_N

TRUE SYS_DETECT_L

TRUE USB_BT_CONN_P

GNDTRUE

TRUE GND

TRUE GND

TRUE GND

GNDTRUE

GNDTRUE

GNDTRUE

GNDTRUETRUE GND

TRUE GND

TRUE GND

TRUE GND

GNDTRUE

TRUE GND

GNDTRUE

GNDTRUE

051-9585

3.0.0

7 OF 132

6 OF 105

53

53

53

53

53

53

53

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53

45 46 47

45 46 47

45 46 47

46 47

45 46 47

17 45 47

53

53

53

6 7

45 46 47 65

17

17

45 46 47

6 7

17 26 45 74

53

54

7 101

7

7

6 41

6 41 44

33 98

33 98

6 33

6 45 48 99

45 46

6 7 101

53

53

33 81 98

6 7

11 29 94

11 29 94

11 29 94

11 29 94

11 29 94

77 80 100

17

17

17

17

17

17

17

62 63 101

85 100

85 86 100

85 90

53

33 81 98

87 98

6 33

6 33

87 98

87 98

6 33

53

53

53

85 86 100

85 86 100

85 100

53 54

53 54

6 7

53

53

17

17

16

16

38

11 27 94

11 27 94

27

11 28 94

11 28 94

77 79 100

77 79 100

77 79 100

77 79 100

77 79 100

16

6 33

16

16

16

16

16

16

16

17

8

89 90

16 45 47 89 96

17 45 47

38

12

38

16

77 79 100

11 27 94

11 27 94

11 27 94

77 80 100

77 80 100

77 80 100

77 80 100

77 80 100 77 79 100

77 79 100

17

17

17

40

40

16

16

17

17

17

19 47

40

40

40

8

16 45 47 89 96

11 29 94

11 29 94

11 29 94

11 28 94

29

11 27 94

11 27 94

77 80 100

11 29 94

77 80 100

77 80 100

77 79 100

77 79 100

77 79 100

77 80 100

77 80 100

17

24 47 96

24 47

12

17

6 33

90

6 7

6 7 101

17

17

85 86 100

85 86

85 86 100

85 86 100

77 79 100

77 80 100

77 80 100

11 28 94

11 28 94

11 29 94

77 79 100

16

11 27 94

53 54

16

64

16 45 47

45 46 53

61 62 101

85 86 100

85 86

85 86 100

62 63 101

62 63

85 90

85 86 100

85 86 100

6 45 48 99

6 64

6 45 48 99

6 7

6 45 48 99

85 90

85 100

6 45 48 99

45 46 64

6 64

64

6 45 48 99

53 54

53 54

53 54

53 54

53 54

61 62 101

8 85 104

85 86 100

85 90

85 90

41

41 95

85 100

85 90

41 95

41 95

41 95

41 45

54

54

41 95

41 95

41 95

41 95

41

6 41

6 41 44

41

41

17

6 33

53 54

53 54

53 54

54

54

8

11 27 94

11 28 94

16

16

16

11 27 94

77 79 100

77 80 100

40

40

40

38

38 45 46 47

17 24 45

33 81 98

33 98

6 33

87 98

6 33

8

6 33

6 33

19 47 56

47

47

47

17

17

16

33

16

89

23

23

7

87 98

87 98

87 98

18

8

16

53

38

38

38

87 98

33 81 98

33 81 98

75 92 93

6 33

75 93

75 92 93

75 93

7

7

7

7

7

53 54

53 54

16

47

6 7

6 7

7

38

38

38

6 69 70

20

6 69 70

6 69 70

18

16

33 98

33 98

7

7

7

7

38

53

53

64 65

38

38

38

38

38

12

53 54

6 7

61 62 101

61 62 101

61 62 101

61 62 101

33

6 33

6 33 6 33

53

53

53

6 64

41 46

6 33

6 33

41

33 98

33 81 98

53

53

53

7

52

52

6 33

33

33

33 98 7

32 101

52

32 45 46

32

32 96

32 101

32

85 86 100

32

32

6 7

32 46

32 95

6 45 48 99

6 45 48 99

32 95

52

85

33 98

33 81 98 7

7

7

32 95

53

16

16

32 96

17 24 32

12 9 17

93

9 17 93

6 9 17

93

9 17 93

9 17 93

9 17 93

9 17 93

33 81 98

6 64

32 95

Apple Inc.


124578

B

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A


PAGE

12

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



G3H Rails

T29 Rails

5V Rails

Backlight Rails

1.8V/1.5V/1.2V/1.05V Rails

Chipset "VCore" Rails

"GPU" Rails

FireWire Rails

2A max supply

For PCH RTC Power

ENET Rails

TBT Rails

3.3V Rails

I1658


Power Aliases

=PP3V3_S4_SD_HPD

=PP3V3_S4_BT

=PP3V3_S4_FET

=PP3V3_S4_SMC

=PP3V3_S4_TPAD

=PP5V_S0_AUDIO_XW

VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_SUS

=PP3V3_SUS_P1V05SUSLDO

=PP3V3_SUS_PCH_GPIO

=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_SUS_CNTRL

=PP3V3_SUS_ROM

=PP3V3_SUS_PCH_VCC_SPI

=PPVIN_S0_PCHVCCIOS0

=PPVCCIO_S0_XDP

=PP3V3_S0_TBT_HPD_GPU

PP15V_TBTMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM

VOLTAGE=15VMAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

PPVTTDDR_S3

VOLTAGE=0.75V

PP1V2_S0

MAKE_BASE=TRUEVOLTAGE=1.2V

MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM

=PPBUS_SW_BKL

=PP1V2_S3_ENET_PHY

PPVIN_SW_TBTBSTVOLTAGE=12.8V

MIN_LINE_WIDTH=0.6 MMPP1V05_TBT_RTR

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

=PP3V3_SUS_PCH_VCCSUS

=PPBUS_G3H

VOLTAGE=12.8V MAKE_BASE=TRUEMIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

PPVIN_S5_HS_COMPUTING_ISNS

=PPVIN_S0GPU_P1V05

=PPVIN_S0_CPUIMVP

=PPVIN_S5_HS_GPU_ISNS_R

=PP1V8_S0_GMUX

=PP1V5_S3_MEM_B

=PP1V5_S3_MEM_A

=PP3V3_S0_GFX3V3BIAS

=PP1V8_GPU_IFPAB_IOVDD

=PPVCORE_GPU

=PPVCORE_GPU_REG

PPVCORE_GPU



=PP3V3_GPU_OSC

=PP3V3_GPU_VDD33

=PP3V3_GPU_IFPX_PLLVDD

=PP3V3_GPU_LVDS_DDC

=PP3V3_S0GPU_ISNS_R

PP3V3_S0GPUMIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.10MM


MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.10MMVOLTAGE=3.3V


PP3V3_S0GPU_FET

PP1V8_S0GPUMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.15 MMVOLTAGE=1.8VMAKE_BASE=TRUE

=PPVCCSA_S0_CPU

=PPVIN_S0_DDRREG_LDO

=PP1V5_S3_DDR_ISNS

=PP1V5_S3_ISNS

=PP1V5_S3RS0_FET

=PPDDR_S3_REG


PP1V05_S0_CPU_VCCPQEVOLTAGE=1.05VMAKE_BASE=TRUE


MIN_LINE_WIDTH=0.6 MMPP1V2_ENET

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUEVOLTAGE=1.2V

=PP1V2_S0_REG

=PP3V3_S5_SYSCLK

=PP3V3_FW_P3V3FWFET


VOLTAGE=0.9VMAKE_BASE=TRUE

PPVCCSA_S0_REG

=PPVTT_S0_DDR_LDO

PP1V0_FW_FWPHY

MAKE_BASE=TRUEVOLTAGE=1.0VMIN_LINE_WIDTH=0.4 MM


=PP3V3_FW_FWPHY

=PP1V0_FW_FET_R

=PP1V0_FW_FWPHY


PP3V3_FW_FWPHYMIN_LINE_WIDTH=0.4 MM


=PP3V3_S5_PCH

=PP3V3_SUS_FET=PP3V3_TBT_FET

=PP3V3_S0_T29I2C

=PP3V3_T29_JTAG

=PPHV_SW_TBTAPWRSW

=PP1V05_TBT_FET

=PPVCORE_S0_CPU

=PP3V3_ENET_PHY

=PP3V3_ENET_SYSCLK

=PPVIN_S3_DDRREG

=PP3V3_S0_SMBUS_SMC_1_S0

=PP15V_TBT_REG

MIN_LINE_WIDTH=0.4 MMMAKE_BASE=TRUEVOLTAGE=1.05V


PP1V05_TBT

=PP1V05_TBT_RTR_R

=PP3V3_TBT_RTR

=PPVDDIO_T29_CLK

=PP1V05_TBT_RTR

=PP1V2_ENET_PHY

=PPVDDIO_ENET_CLK

=PP3V3_S0_P3V3S0FETMAKE_BASE=TRUE

PP1V8_S0MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.5V

=PPVP_FW_PORT1

=PPBUS_S5_FWPWRSW

=PP3V3_ENET_FET

=PPVDDIO_S0_SBCLK

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM VOLTAGE=1.8V

MAKE_BASE=TRUE

PP1V8_S0_CPU_VCCPLL_R

=PPDDR_S3_MEMVREF

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V5_S0_RDRVR

=PP1V2_S0_GMUX

PPVCORE_S0_CPU



MIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3VPP3V3_ENET

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

=PP1V8_S0_CPU_VCCPLL_R

=PP1V5_S3_MEMRESET

=PP3V3_S5_LCD

=PP3V3_S5_REG

=PPVIN_S5_HS_OTHER_ISNS_R

=PPVIN_S5_HS_COMPUTING_ISNS_R

=PPVIN_S5_HS_COMPUTING_ISNS

=PP1V05_SUS_PCH_JTAG

MIN_NECK_WIDTH=0.1 MM MAKE_BASE=TRUE

PP1V5_S3_REGMIN_LINE_WIDTH=0.8 MM VOLTAGE=1.5V

=PP1V8_S0_REG

MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

VOLTAGE=1.5V

PPGPUFB_S0

=PP1V35_GPU_S0_FB

=PP1V35_GPU_FBVDDQ

=PP1V8_S0_PCH_VCCTX_LVDS

MIN_LINE_WIDTH=0.8 MM VOLTAGE=1.5VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.1 MM

PP1V5_S3

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_GPUFET

=PP3V3_S0GPU_FET

=PP3V3_S0GPU_ISNS

=PP1V8_GPU_FET

PP1V5_S3_DDR

MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.5VMAKE_BASE=TRUE


=PP1V5_S0_AUDIO

MIN_NECK_WIDTH=0.17 mmMIN_LINE_WIDTH=2 mm


PP0V75_S0_DDRVTT

=PP1V5R1V35_GPU_REG

=PP1V5_S3_CPU_VCCDDRMIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PP1V5_S3RS0MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.5V

=PPVIN_S3_P1V5S3RS0_FET

=PP1V5_S3_DDR_ISNS_R

=PP1V5_S3_ISNS_R

=PPVCCSA_S0_REG

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PPVCORE_S0_AXG_REGMAKE_BASE=TRUEVOLTAGE=1.05V

PPVCORE_S0_AXG


MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V

PP1V5_S3_CPU_VCCDQMAKE_BASE=TRUE

=PPVCORE_S0_CPU_VCCAXG

=PPVCORE_S0_CPU_REG

=PPBUS_FW_FET

=PPVP_FW_PHY_CPS_FET

MIN_LINE_WIDTH=0.4 MM VOLTAGE=12.8VMIN_NECK_WIDTH=0.2 MM

PPVP_FW

MAKE_BASE=TRUE

=PP1V5_S0_VMON

=PP3V3R1V5_S0_PCH_VCCSUSHDA


MAKE_BASE=TRUE


PP1V5_S0

VOLTAGE=1.5V

=PPVTT_S3_DDR_BUF

=PPVIN_S0_CPUVCCIOS0

MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUEVOLTAGE=12.8V

PPBUS_G3HMIN_LINE_WIDTH=0.6 mm

=PPVIN_S0_CPUAXG

=PP3V3_SUS_SMC

=PP3V3_S0_PCH_VCC3_3_SATA

=PP1V05_SUS_LDO

=PPVCORE_S0_GFX_REG

=PP3V3_FW_FET

=PP1V05_S0_CPU_VCCPQE

=PP1V5_S3_CPU_VCCDQ

=PP1V05_S0_FWPWRCTL

=PP1V05_S0_VMON

=PPCPUVCCIO_S0_REG

=PP1V05_S0_P1V05TBTFET

=PP1V05_S0_PCH_VCCIO_PLLPCIE

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCCIO_USB


=PP1V05_S0_PCH_VCCIO_PLLUSB

=PP3V3_S4_P3V3S4FET

=PP3V3_S3_P3V3S3FET

MIN_LINE_WIDTH=0.4 MMPP1V05_SUS

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

=PP1V05_S0_CPU_VCCIO

=PPVCCIO_S0_CPUIMVP

=PPVCCIO_S0_SMC

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH

=PP1V05_S0_PCH_VCCSSC

MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V

PPBUS_SW_BKLMIN_LINE_WIDTH=0.6 mm MAKE_BASE=TRUE

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH_VCCIO_PLLFDI

=PP1V05_S0_PCH_VCCDMI_FDI

=PP3V3_T29_PCH_GPIO

PP3V3_TBTMIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V

=PPPCHVCCIO_S0_REG

=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_VCCDIFFCLK

=PP3V3_GPU_P3V3GPUFET

=PPVIN_S0_VCCSAS0

=PPBUS_S0_VSENSE

=PPVIN_SW_TBTBST

=PP1V05_S0_PCH_VCCIO_SATA

=PP0V75_S0_MEM_VTT_A

=PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP

=PP1V05_FW_P1V0FWFET


PP1V05_S0GPU



=PP1V05_S0GPU_REG

=PP1V05_GPU_PEX_PLLVDD

=PP1V05_GPU_PEX_IOVDD

=PP1V05_GPU_IFPEF_IOVDD

=PP1V05_GPU_IFPCD_IOVDD

=PP1V05_GPU_IFPAB_PLLVDD

=PP3V3_S0_IMVPISNS

=PPSPD_S0_MEM_B

=PP3V3_S0_TPAD

=PP3V3_S0_SMC

=PP3V3_S0_SB_PM

=PP3V3_S0_PWRCTL

=PP3V3_S0_SDCARD

=PP3V3_S0_SMBUS_PCH


=PP3V3_S0_VMON

=PPSPD_S0_MEM_A

=PP3V3_S0_P1V8GPUFET=PP3V3_S0_HDD

=PP1V5_S0_REG

=PPVIN_S0_GFXIMVP

=PP3V3_S0_PCH_VCC3_3_CLK

=PP1V05_S0_RMC

VOLTAGE=1.05VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

PP1V05_S0MIN_LINE_WIDTH=0.6 MM

=PP3V3_S5_P1V5S0

=PP3V3_S5_PCH_VCCDSW

=PP3V3_S5_P3V3SUSFET

=PP3V3_S5_PWRCTL

=PP3V3_S5_SMCBATLOW

=PP3V3_S5_P1V2P1V8

=PP3V3_S5_PCHPWRGD

=PP3V3_S5_PCH_GPIO

=PP3V3_S5_CPU_VCCDDR

=PP3V3_S5_MEMVDDSEL

=PP3V3_S5_VMON

=PP3V3_S5_XDP

=PP3V3_S0_RSTBUF

=PP3V3_S0_PCH_VCCA_LVDS

=PP3V3_S0_PCH_VCCADAC

=PP3V3_S0_PCH_VCC3_3_PCI

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP3V3_S0_PCH_VCC3_3_GPIO

=PPVIN_S0GPU_P1V5

MAKE_BASE=TRUEVOLTAGE=12.8VMIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.25 mm

PPVIN_S5_HS_GPU_ISNS

=PP18V5_DCIN_CONN

=PP3V42_G3H_REG

=PP5V_S3_REG

=PP5V_S5_LDO

=PPVRTC_G3_OUT

=PP5V_S3_USB


PPDCIN_G3H



PP5V_S5VOLTAGE=5VMAKE_BASE=TRUE

=PP5V_S3_SYSLED

=PP5V_S3_P5VS0FET

=PP3V42_G3H_AUDIO

=PP3V42_G3H_ONEWIREPROT

=PP3V42_G3H_BIL

=PP3V42_G3H_SMCUSBMUX


PPVRTC_G3HVOLTAGE=3.42VMAKE_BASE=TRUE

=PPDCIN_S5_VSENSE

=PP3V42_G3H_TPAD

=PPVBAT_G3_SYSCLK

=PPVRTC_G3_PCH

=PP5V_SUS_PCH

VOLTAGE=5VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

PP5V_SUS

MAKE_BASE=TRUE

=PP5V_S5_P1V5S3RS0FET

=PP5V_S3_ODD

=PP5V_S3_MEMRESET

=PP5V_S3_IR


PP3V42_G3HVOLTAGE=3.42VMAKE_BASE=TRUE


=PP3V3_S5_LPCPLUS

=PP3V3_S5_SMC

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_SMBUS_SMC_5

=PP5V_S3_ALSCAMERA=PP5V_S3_DDRREG

=PP5V_S5_DEBUG_ADC_AVDD

=PP5V_S5_DEBUG_ADC_DVDD

=PP5V_S3_AUDIO

=PP3V3_S3_ISNS

=PP3V3_S0_FET

=PPVIN_S5_HS_OTHER_ISNS

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm


PPVIN_S5_HS_OTHER_ISNS=PP3V3_S3_FET

MAKE_BASE=TRUEMIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3VPP3V3_S5


=PP3V3_S3_ISNS

=PP3V3_S0_GPUTHMSNS



=PP3V3_S0_PCH

=PP3V3_S0_GMUX

=PP3V3_S0_ENETPHY

=PP3V3_S0_BKL_VDDIO

=PP3V3_S3_P3V3ENETFET

=PP3V3_S0_HS_ISNS

=PP3V3_S0_AUDIO

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_FAN_RT

=PP3V3_S0_FWPWRCTL

=PP3V3_S0_ISNS

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_DPSDRVA

=PP3V3_S3_SDBUF

=PP3V3_S0_FWLATEVG

=PP3V3_S3_SMS

=PP3V3_S3_SMBUS_SMC_3

=PP3V3_S3_GMUX

PP3V3_S3_FETMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM


=PP3V3_S3_VREFMRGN

=PP3V3_S3_USB_HUB

=PP3V3_S4_TBTAPWRSW

=PP3V3_S3_ISNS_R

=PP3V3_S3_BT

=PP3V3_S3_MEMRESET

=PP3V3_S3_USB_RESET

=PP3V3_S3_USBMUX

=PP3V3_S3_PCH_GPIO

=PP3V3_S0_XDP

=PP3V3_S0_DDC_LCD

=PP3V3_S0_TBTPWRCTL

=PP3V3_S0_ODD

=PP3V3_S0_FAN_LT

=PP3V3_S0_CPU_VCCIO_SEL

=PP3V3_S0_DPMUX


PP3V3_S0MIN_LINE_WIDTH=0.5 MM


=PP3V3_S0_LVDSDDCMUX

=PPVIN_S5_SMCVREF

=PP3V42_G3H_CHGR

=PPDCIN_S5_CHGR

=PPVIN_S5_HS_GPU_ISNS

=PPVIN_S5_P5VP3V3

=PP5V_S0_LPCPLUS

=PP5V_S0_VCCSAS0

=PP5V_S0_CPUIMVP

=PP5V_S3_P5VS0SW

=PP5V_S3_P3V3S0SW

=PP5V_S0_FAN_LT

=PP5V_S0_KBDLED

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mm

PP5V_S3VOLTAGE=5VMAKE_BASE=TRUE

=PP5V_S5_TPAD

=PP5V_S5_P5VSUSFET

=PP5V_SUS_FET

=PP5V_S0_ISNS

=PP5V_S0_FET

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MMPP3V3_S3


=PP3V3_S3_WLAN

=PPBUS_S0_LCDBKLT

=PP5V_S5_ISNS

=PP5V_S3_GFXIMVP

=PP5V_S0_BKL

=PP5V_S0_CPUVCCIOS0

=PP5V_S0_FAN_RT

=PP5V_S0_VMON

=PP5V_S0_HDD

=PP5V_S0_PCH

=PP5V_S0GPU_P1V05

=PP5V_S0_RMC

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

PP3V3_S4MIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3V

=PP5V_S0GPU_P1V5

MAKE_BASE=TRUEVOLTAGE=5V

PP5V_S0


051-9585

3.0.0

8 OF 132

7 OF 105

30

32

73

46

53 54

8

72

16 17 18 19

20 22

74

56

20 22

23

6

6

90 104

72

35

20 22

64 65

78

69 70

50

89

29

27

84

81

76 83

49

6

75 81 82 83

81

86

104

12 15

68

49

103

73

68

6

72

24

39

68

6

38 39 40

39

38 39

6

17

73 35

48

89

88

35

12 14 49 105

24 36 72

24

68

48

8 35

35

104

33 34 35

24

34 104

36

24

73

6

40

39

74

24

31

19 20 22

41

89

6

6

12 14

26

85

67

50

50

50

23

72

77

76 79 80

22

6

20

14

73

73

104

73

57

6

78 103

10 13 15 26

101

73

49

103

49 66

20 22

49 70

12 13 15

70

39

40

6

74

20 22 24

31 68

71

6

70

46

20 22

72

84

39

8 12 14

12 15

39

74

71

35

20

22

7 20 22

20 22

7 20 22

20

73

73

9 10 12 13 14

69

46

20 22

17

20 22

20 22

16 22

20 22

20 22

20

20

16 19

91

20 22

16 20 22

73

66

49

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16 20 22

27

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81 83

77 83

81

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74 92

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74

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20 22

20 22

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64

64

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67

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64

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53

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16 17 20

22

73

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6

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45 46 82

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32

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104

104

7 49 103 104

73

50

73

6 101

7 49 103 104

51

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48

16 22

86 89

36

90

74

57 62 63

16 17 18 19 30

52

39

49 50 103 104

51

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24

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31

25

88

104

26

25

25

18 24

23

85

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6 101

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65 74

65

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73

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84

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71

52

74

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78

105

6

78

6

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Unused T29 Ports

TALL POGO PINS for BT NF

Frame Holes

GPU signals

Unused eDP signals

Keyboard / IPD Conn Protect

Unused eDP CLK

Fan Holes

Digital Ground

GMUX ALIASES

T29 / GMUX JTAG SignalsUSB Signals

T29 Signals Through PEG

Unused PEG signals

Left Speaker Holes

Thermal Module Holes

CPU signals

Short (IO Row) EMI pogo pins

Tall EMI pogo pins

SM

SM

SM

5%

0

805MF-LF1/8W

TBTBST:N

0.01UF10%

201

10VX5R

5%1/20W

51

MF201

201

10%10VX5R

0.01UF

0.01UF

10V

201

10%

X5R

51

5%1/20WMF201

201

10%0.01UF

X5R10V

1/20WMF201

51

5%

10V10%

201X5R

0.01UF1/20W5%

51

201MF

201

10%10VX5R

0.01UF1/20WMF

5%

201

51

X5R201

0.01UF

10V10%

1/20WMF

5%

201

51

0.01UF

X5R

10%10V

201

SM

NOSTUFF

POGO-2.0OD-3.5H-K86-K87

SM

POGO-2.0OD-3.5H-K86-K87

NOSTUFF

SM

POGO-2.0OD-3.5H-K86-K87

NOSTUFF

SM

NOSTUFF

POGO-2.0OD-3.5H-K86-K87

SM

POGO-2.0OD-3.5H-K86-K87

NOSTUFF

SMNOSTUFF

POGO-2.0OD-3.5H-K86-K87

SM

POGO-2.0OD-3.5H-K86-K87

POGO-2.0OD-3.5H-K86-K87SM

NOSTUFF

SM

NOSTUFF

POGO-2.0OD-3.5H-K86-K87

5%

402MF-LF1/16W

1K

MF-LF

5%1K

402

1/16W

201

51

5%

MF1/20W

PLACE_NEAR=C9361.1:2 mm

51

1/20WMF

5%

201


6.3V

0.1UF

201X5R

10%PLACE_NEAR=C9490.1:2 mm

1/20W

51

MF

5%

201

SM

1.4DIA-SHORT-SILVER-K99

SM

POGO-2.0OD-3.5H-K86-K87

SM

POGO-2.0OD-3.5H-K86-K87SM

POGO-2.0OD-3.5H-K86-K87

SM

POGO-2.0OD-3.5H-K86-K87

STDOFF-4.5OD.98H-1.1-3.48-TH

3R2P5

3R2P5

TH

SL-3.1X2.7-6CIR-NSP

3R2P5

3R2P5

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

SM


SM


SM


SM

1.4DIA-SHORT-SILVER-K99SM


SM


SM

POGO-2.0OD-3.5H-K86-K87

SM

POGO-2.0OD-3.5H-K86-K87

SM

POGO-2.0OD-3.5H-K86-K87

SM

POGO-2.0OD-3.5H-K86-K87

SM

POGO-2.0OD-3.5H-K86-K87

SM


STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

4.0OD1.85H-M1.6X0.35

4.0OD1.85H-M1.6X0.35

STDOFF-4.0OD3.0H-TH

STDOFF-4.0OD3.0H-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

MF-LF402

1/16W

4.7K5%

Signal Aliases

SYNC_DATE=04/27/2010SYNC_MASTER=K18_MLB

MIN_NECK_WIDTH=0.095 mmVOLTAGE=0V

MIN_LINE_WIDTH=0.6 mmGND

MAKE_BASE=TRUEUSB_SMC_N

ADC_CH6NO_TEST=TRUE

NC_ADC_CH6MAKE_BASE=TRUE

MAKE_BASE=TRUEUSB_SMC_P

MAKE_BASE=TRUEUSB_IR_P USBHUB_DN2_P

USBHUB_DN4_N

USBHUB_DN4_P

USBHUB_DN2_NUSB_IR_NMAKE_BASE=TRUE

USB_TPAD_NMAKE_BASE=TRUE

MAKE_BASE=TRUEUSB_TPAD_P

ADC_CH7

LVDS_IG_B_CLK_P

LVDS_IG_B_CLK_N

=FW_PME_L

NC_PCIE_EXCARD_D2RNTRUEMAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_N

T29_A_BIAS_R

GND_CHASSIS_FAN

GND_CHASSIS_LVDS

TP_PCIECLKRQ4_L_GPIO26

GND_CHASSIS_BATTCONN

GND_CHASSIS_SATA

DP_EG_AUX_CH_P

DPB_EG_DDC_CLK

DPB_EG_DDC_DATA

NC_DPB_EG_AUX_CHPNO_TEST=TRUEMAKE_BASE=TRUE

DP_EG_AUX_CH_N

TBT_D2R_P<3..2>

NO_TEST=TRUEMAKE_BASE=TRUEPCIE_TBT_R2D_C_P<3..0>

GPU_RESET_LEG_RESET_LMAKE_BASE=TRUE

PM_ENET_ENMAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_CNMAKE_BASE=TRUETRUE

MAKE_BASE=TRUELVDS_IG_BKL_ON

PCIE_TBT_R2D_C_N<3..0>MAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUE

NC_T29_R2D_CP<3..2>


NC_T29_R2D_CN<3..2>

NO_TEST=TRUE

NC_USB3_EXTC_TXPMAKE_BASE=TRUE

PCIE_TBT_D2R_N<3..0>MAKE_BASE=TRUE NO_TEST=TRUE

=PEG_R2D_C_N<7..0>

NC_PEG_D2RP<15..12>MAKE_BASE=TRUE NO_TEST=TRUE

=PEG_D2R_P<15..12>

NO_TEST=TRUE

NC_PEG_D2RN<15..12>MAKE_BASE=TRUE


NC_PEG_R2D_CP<15..12>

=PEG_D2R_P<7..0>

MAKE_BASE=TRUENC_PEG_R2D_CN<15..12>

NO_TEST=TRUE

DP_EG_AUXCH_PMAKE_BASE=TRUE

TBT_LSEO<3>

USB_EXTD_EHCI_N

DP_INT_IG_AUX_P

TBT_A_BIAS2P

JTAG_GMUX_TCK

JTAG_TBT_TDI

=PEG_R2D_C_P<11..8>

NO_TEST=TRUE

NC_USB_EXTD_EHCIPMAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTC_RXPMAKE_BASE=TRUE

=PEG_D2R_N<15..12>

=PEG_R2D_C_P<15..12>

JTAG_ISP_TCKMAKE_BASE=TRUE

MAKE_BASE=TRUENC_DP_INT_IG_MLN<3..0>

NO_TEST=TRUE

MEMVTT_ENMAKE_BASE=TRUE

NC_DPB_EG_MLN<3..0>NO_TEST=TRUEMAKE_BASE=TRUE

NC_DPB_EG_DDC_CLKNO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUENC_LVDS_IG_A_DATAN<3>

NO_TEST=TRUE

USB3_EXTD_TX_P


NC_LVDS_IG_A_DATAP<3>

TP_LVDS_IG_B_CLKNMAKE_BASE=TRUE

MAKE_BASE=TRUETP_LVDS_IG_B_CLKP

USB3_EXTD_TX_NNC_USB3_EXTD_TXNNO_TEST=TRUEMAKE_BASE=TRUE

NC_USB3_EXTC_RXNNO_TEST=TRUEMAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_P

MAKE_BASE=TRUEPCIE_TBT_D2R_P<3..0>

NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_T29_D2RP<3..2>

FW_PME_L

MAKE_BASE=TRUEPPVOUT_S0_LCDBKLT

PEX_CLKREQ_LMAKE_BASE=TRUE

PEG_CLKREQ_LMAKE_BASE=TRUE

SMC_EXCARD_PWR_EN

PCIE_EXCARD_D2R_P

PM_ALL_GPU_PGOODMAKE_BASE=TRUE

EG_CLKREQ_OUT_L

TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARDP

NO_TEST=TRUE

NC_FSB_CLK133M_PCHPMAKE_BASE=TRUE

LCD_BKLT_EN

DPB_EG_ML_P<3..0>

ISSP_SDATA_P1_0

JTAG_TBT_TDO

JTAG_TBT_TCK

JTAG_ISP_TDOMAKE_BASE=TRUE

TBT_LSOE<2>

NC_DPB_IG_HPDTRUEMAKE_BASE=TRUE

MAKE_BASE=TRUE TRUENC_DPB_IG_DDC_DATA

DPB_IG_DDC_CLK

NC_DPB_IG_AUX_CHNMAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

FW643_WAKE_L

TP_PCH_CLKOUT_DPP

T29_A_BIAS_R

MAKE_BASE=TRUE

JTAG_ISP_TDI

TRUEMAKE_BASE=TRUENC_DPB_IG_DDC_CLK

FW_PLUG_DET_LMAKE_BASE=TRUE

IG_LCD_PWR_EN

GMUX_INTMAKE_BASE=TRUE

=PPVIN_SW_TBTBST


NC_DP_INT_IG_HPD

DP_INT_IG_ML_P<3..0>

NO_TEST=TRUEMAKE_BASE=TRUENC_T29_D2RN<3..2>

NO_TEST=TRUE

NC_GPU_XTALOUTMAKE_BASE=TRUE

LVDS_IG_BKL_PWM

LVDS_IG_A_DATA_N<3>

LVDS_IG_B_DATA_P<3>NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<3>MAKE_BASE=TRUE

LVDS_IG_B_DATA_N<3>

DPB_EG_AUX_CH_N

TP_LVDS_MUX_SEL_EGMAKE_BASE=TRUE NO_TEST=TRUE

LVDS_IG_PANEL_PWRMAKE_BASE=TRUE

DP_INT_IG_ML_N<3..0>

=PEG_R2D_C_N<11..8>

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<3>MAKE_BASE=TRUE

=PEG_D2R_P<11..8>

LVDS_IG_A_DATA_P<3>

NO_TEST=TRUE

NC_USB_EXTD_EHCINMAKE_BASE=TRUE

USB_EXTD_EHCI_P

NO_TEST=TRUE

NC_USB3_EXTC_TXNMAKE_BASE=TRUE

T29_A_BIAS_R

=DDRVTT_EN

PPVOUT_SW_LCDBKLT

ALL_EG_PGOOD

T29_LSEO_LSOE3NO_TEST=TRUEMAKE_BASE=TRUE

DPA_IG_HPD

EG_CLKREQ_IN_L

NC_DPB_EG_DDC_DATANO_TEST=TRUEMAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_N

=PP5V_S0_AUDIO

GND_CHASSIS_AUDIO_JACK

=TBT_A_BIAS

NC_PCH_GPIO67_CLKOUTFLEX3TRUEMAKE_BASE=TRUE

LT_GAIN_TP

RT_GAIN_TP

TP_GMUX_PT32B

T29_A_BIAS_R

TP_DP_IG_B_MLP<3..0>

DPB_IG_HPD

MAKE_BASE=TRUET29_A_BIAS

FSB_CLK133M_PCH_N

NO_TEST=TRUE

NC_DP_IG_MLN<3..0>MAKE_BASE=TRUE

=DP_A_BIAS

DPA_IG_AUX_CH_N

DPA_IG_AUX_CH_P

DP_A_BIAS2

DPB_EG_ML_N<3..0>

NC_PCIECLKRQ4_L_GPIO26MAKE_BASE=TRUETRUE

DPA_IG_DDC_CLK

MAKE_BASE=TRUETP_ISSP_SDATA_P1_0

TP_GMUX_PT20B

TP_GMUX_PT20A

TBT_A_BIAS0P

T29_A_BIAS_R

T29_A_BIAS_R TBT_A_BIAS0NMAKE_BASE=TRUETP_ISSP_SCLK_P1_1

NO_TEST=TRUE

NC_DP_IG_MLP<3..0>MAKE_BASE=TRUE

DPB_IG_AUX_CH_P

DPB_IG_AUX_CH_N

DP_A_BIAS0

TP_DP_IG_B_MLN<3..0>

DP_IG_HPDMAKE_BASE=TRUE

DPB_IG_DDC_DATA

MAKE_BASE=TRUEDP_A_BIAS

TBT_A_BIAS1P TBT_A_BIAS1N

TBT_LSOE<3>

NC_PCH_GPIO66_CLKOUTFLEX2MAKE_BASE=TRUETRUE

DP_IG_DDC_DATAMAKE_BASE=TRUE

MAKE_BASE=TRUEDP_IG_DDC_CLK

NC_PCH_GPIO65_CLKOUTFLEX1TRUEMAKE_BASE=TRUE

TRUE NC_PCH_GPIO64_CLKOUTFLEX0MAKE_BASE=TRUE

MAKE_BASE=TRUENC_PCH_CLKOUT_DPPTRUE

ISSP_SCLK_P1_1

DPA_IG_DDC_DATA

MAKE_BASE=TRUETRUE NC_PCH_CLKOUT_DPNTP_PCH_CLKOUT_DPN

TP_GMUX_PT32A

MAKE_BASE=TRUENC_PEG_B_CLKRQ_L_GPIO56TRUE


NC_DP_INT_IG_AUXP

NC_DP_INT_IG_AUXNMAKE_BASE=TRUE NO_TEST=TRUE

=P1V2ENET_EN

NC_DP_INT_IG_MLP<3..0>MAKE_BASE=TRUE NO_TEST=TRUE

TP_LVDS_IG_BKL_PWMMAKE_BASE=TRUE

NC_ADC_CH7NO_TEST=TRUEMAKE_BASE=TRUE

USB3_EXTC_TX_P

NC_USB3_EXTD_TXPNO_TEST=TRUEMAKE_BASE=TRUE

=PEG_R2D_C_P<7..0>


=PP5V_S0_AUDIO_XW

FSB_CLK133M_PCH_P

TP_PCH_GPIO67_CLKOUTFLEX3


NO_TEST=TRUE

NC_FSB_CLK133M_PCHNMAKE_BASE=TRUE

NC_LT_GAIN_TPNO_TEST=TRUEMAKE_BASE=TRUE

=PP15V_TBT_REG

NC_RT_GAIN_TPNO_TEST=TRUEMAKE_BASE=TRUE

SW_GAIN_TPDPLL_REF_CLKP

MAKE_BASE=TRUE

DPLL_REF_CLK_P

NO_TEST=TRUE

NC_SW_GAIN_TPMAKE_BASE=TRUE

T29_A_BIAS_RVOLTAGE=3.3V

DPLL_REF_CLKNMAKE_BASE=TRUE



PCIE_EXCARD_D2R_N

PCIE_EXCARD_R2D_C_P

=PP1V05_S0M_PCH_VCC_LAN

TBT_A_BIAS2N

DPLL_REF_CLK_N

PP5V_S0_AUDIO_AMP_RMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.30MMVOLTAGE=5V

VOLTAGE=5V

MIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.30MM

PP5V_S0_AUDIO_AMP_L

PP5V_S0_AUDIOMAKE_BASE=TRUE

TP_PEG_B_CLKRQ_L_GPIO56

MAKE_BASE=TRUEUSB_BT_N

USBHUB_DN3_N

MAKE_BASE=TRUETP_SMC_EXCARD_PWR_EN

NC_DPB_EG_MLP<3..0>NO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUEDP_IG_AUX_CH_N

DP_INT_IG_HPD

DP_INT_IG_AUX_N

GPU_XTALOUT

USB3_EXTC_TX_N

TBT_LSEO<2>

DPMUX_UC_IRQ

NO_TEST=TRUEMAKE_BASE=TRUET29_LSEO_LSOE2

USB3_EXTD_RX_N

USB3_EXTD_RX_P

=PEG_D2R_N<11..8>

NC_USB3_EXTD_RXNNO_TEST=TRUEMAKE_BASE=TRUE

NC_USB3_EXTD_RXPNO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTCPMAKE_BASE=TRUE

USB_EXTC_P

USB_EXTC_NNO_TEST=TRUE

NC_USB_EXTCNMAKE_BASE=TRUE

IG_BKLT_EN

LVDS_MUX_SEL_EG

NC_PCIE_EXCARD_D2RPMAKE_BASE=TRUETRUE

=PEG_D2R_N<7..0>

TBT_R2D_C_P<3..2>

NO_TEST=TRUE

NC_DPB_EG_AUX_CHNMAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARDNTRUEMAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_CPTRUEMAKE_BASE=TRUE

MAKE_BASE=TRUEDP_EG_AUXCH_N

TBT_R2D_C_N<3..2>

TBT_D2R_N<3..2>


PEG_R2D_C_P<7..0>


PEG_R2D_C_N<7..0>

MAKE_BASE=TRUEPEG_D2R_N<7..0>

NO_TEST=TRUE

GND_BATT_CHGND

DPB_EG_AUX_CH_P

NO_TEST=TRUEMAKE_BASE=TRUEPEG_D2R_P<7..0>

NC_DPB_IG_AUX_CHPTRUEMAKE_BASE=TRUE

DP_IG_AUX_CH_PMAKE_BASE=TRUE

USBHUB_DN1_N

USBHUB_DN1_P

=PEG_R2D_C_N<15..12>

USBHUB_DN3_P

MAKE_BASE=TRUEUSB_BT_P

USB3_EXTC_RX_P

USB3_EXTC_RX_N

ZT0984

1

ZT0990

1

ZT0960

1

ZT09501

ZT0940

1

ZT0915

1

ZT0986

1

ZT0981

1

ZT0985

1

SH0917

1

SH0901

1

SH0912

1

SH0910

1

SH0911

1

SH0913

1

SH0903

1

SH0916

1

SH0902

1

SH0900

1

SH0904

1

SH0914

1

ZT0991

1

ZT0988

1

ZT0989

1

ZT0987

1

ZT0980

1

ZT0952

1

ZT0953

1

ZT0934

1

ZT0935

1

ZT0930

1

R09011

2

XW0901

1 2

XW0902

1 2

XW0903

1 2

R09501 2

C09051

2

R09211 2

C09011

2

C09021

2

R09221 2

C09031

2

R09231 2

C09041

2

R09241 2

C09061

2

R09261 2

C09071

2

R09271 2

C09081

2

SH0933

1

SH0932

1

SH0937

1

SH0935

1

SH0934

1

SH0931

1

SH0930

1

SH0936

1

SH0938

1

R09411

2

R09401

2

R936312

R936212

C94901

2

R94901 2

SH0918

1

SH0942

1

SH0941

1

SH0939

1

SH0940

1

051-9585

3.0.0

9 OF 132

8 OF 105

95

104

95

44 95 25

25

25

25 44 95

53 95

53 95

104

17

17

38 39

16

8

81 86 100

81 86 100

33 98

33 96

75 82 89

17

33 96

33 96

9

9

9

33

18

9 93

87

89

19 33

9

9

9

19 23

26

18

6

6

18

16 96

33 96

19 39

6 85 104

16

16

92

89

89 90

6

33

33

19 89

33

17

39

16

8

19 89

89

89

7 35

9 93

17

17 95

17

17

17

9 93

9

9

17 95

18

8

26 68

90

89

17

82 89

16 96

57

62

87

89

8

17

17

87

17

17

87

17

53

89

89

87

8

8 87

53

17

17

87

17

86

17

88 88

33

86

86

6

17

16

89

6

18

9

7 12

14

7

16

16

7 35

93

10

8

93

16

16

16

16

87

10

61

61

32 95

25

86 95

9

9 93

18

33

19

18

18

9

18 95

18 95

89

89

9

33 98

33 98

33 98

75 93

75 93

75 93

75 93

86 95

25

25

9

25

32 95

18

18

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

NCNCNCNCNC

NC

NCNC

NCNC

NC

NCNC

NCNC

NC

NCNCNCNCNC

NCNCNCNC

NC

NCNCNCNC

NCNCNCNC

NC

NCNC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

IN

NCNC

NCNCNC

NCNCNC

NCNC

NCNCNC

NCNCNCNC

NCNC

NCNC

NCNCNC

NCNC

NCNC

NCNCNC

NCNCNCNCNCNC

NC

NCNCNCNC

NC

NCNCNCNC

NC

S

D

G

NC

NC

DMI

(1 OF 11)

PCI EXPRESS BASED INTERFACE SIGNALS

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

FDI0_FSYNC

FDI1_FSYNC

FDI0_LSYNC

EDP_TX0*

EDP_TX2*

PEG_TX8

EDP_TX3*

FDI1_TX3

FDI_INT

FDI1_LSYNC

EDP_TX1*

EDP_TX0

EDP_TX1

EDP_TX2

EDP_TX3

FDI1_TX3*

FDI1_TX2*

PEG_RX7*

PEG_RX6*

PEG_RX8*

PEG_RX10*

DMI_TX1*

DMI_TX0*

DMI_RX3

DMI_TX3*

PEG_RX0

DMI_TX2

DMI_TX1

DMI_TX0

FDI0_TX2

FDI1_TX0

FDI1_TX2

PEG_TX10

PEG_TX9

PEG_TX7

PEG_TX6

PEG_TX14*

PEG_TX15*

PEG_TX13

PEG_TX12

EDP_AUX*

DMI_RX1

DMI_RX2

DMI_TX3

FDI0_TX0*

FDI0_TX1*

FDI1_TX1*

FDI0_TX0

FDI0_TX1

FDI0_TX3

FDI1_TX1

EDP_AUX

EDP_ICOMPO

EDP_COMPIO

EDP_HPD*

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX0*

PEG_RX1*

PEG_RX2*

PEG_RX5*

PEG_RX9*

PEG_RX15*

PEG_RX1

PEG_RX2

PEG_RX3

PEG_RX4

PEG_RX5

PEG_RX6

PEG_RX7

PEG_RX8

PEG_RX9

PEG_RX10

PEG_RX11

PEG_RX12

PEG_RX13

PEG_RX14

PEG_RX15

PEG_TX0*

PEG_TX1*

PEG_TX2*

PEG_TX3*

PEG_TX4*

PEG_TX5*

PEG_TX6*

PEG_TX7*

PEG_TX8*

PEG_TX9*

PEG_TX10*

PEG_TX11*

PEG_TX12*

PEG_TX13*

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX11

PEG_TX14

PEG_TX15

DMI_RX0

DMI_RX3*

DMI_RX1*

DMI_RX0*

DMI_RX2*

DMI_TX2*

FDI0_TX2*

FDI0_TX3*

FDI1_TX0*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX3*

PEG_RX4*

RSVD

RSVD

CFG

(5 OF 11)RESERVED


Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



CPU_CFG<4> should be pulled down to enable EDP

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

(THERMDC)

(THERMDA)

This connection is to support the same.

These can be Placed close to J2500 and Only for debug access

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

(DDR_VREF1)

(DDR_VREF0)

NOTE:

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

Intel is investigating processor driven VREF_DQ generation.

(IPU)

6 17 93

6 17 93

17 93

6 17 93

17 93

6 17 93

6 17 93

6 17 93

17 93

17 93

6 17 93

6 17 93

6 17 93

6 17 93

6 17 93

6 17 93

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

1%

MF-LF402

1/16W

24.9

17 93

6 17 93

17 93

17 93

6 17 93

6 17 93

6 17 93

6 17 93

17 93

6 17 93

17 93

17 93

6 17 93

6 17 93

6 17 93

6 17 93

6 17 93

6 17 93

6 17 93

6 17 93

6 17 93

24.9

402

PLACE_NEAR=U1000.AB1:12.7mm

MF-LF1/16W1%

NOSTUFF

1K

402

5%

MF-LF

1/16W

1K

1/16W

MF-LF

402

5%

NOSTUFF

1/16W

5%

MF-LF

1K

402402

1/16W

5%

1K

MF-LF

EDP:YESNOSTUFF

1K

1/16W

MF-LF

5%

402

1K

NOSTUFF

402

5%

MF-LF

1/16W

NOSTUFF

1K

402

5%

MF-LF

1/16W

NOSTUFF

1K

402

5%

MF-LF

1/16W

5%

MF-LF

NOSTUFF

1K

402

1/16W

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

OMIT_TABLE

1/16W

1K

MF-LF

402

5%

8 2N7002TXGSOT-523-3

EDP:YES

OMIT_TABLEBGA

IVY-BRIDGE

BGA OMIT_TABLE

IVY-BRIDGE

CPU DMI/PEG/FDI/RSVD

116S0066 RES,MTL FILM,1/16W,1K,0402,SMD,LF1 EDP:YESR1031

116S0090 RES,MTL FILM,1/16W,10K,0402,SMD,LF EDP:NOR10311

PPCPU_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm


VOLTAGE=0.75V

=PEG_D2R_P<9>

=PEG_D2R_P<8>

FDI_DATA_N<3>

FDI_DATA_N<2>

FDI_DATA_N<1>

DP_INT_IG_ML_P<0>

DMI_N2S_N<2>

DMI_N2S_N<3>

DMI_N2S_P<0>

DMI_N2S_P<1>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<9>

=PEG_R2D_C_P<3>

=PEG_D2R_N<1>

=PEG_D2R_N<2>

=PEG_D2R_N<3>

=PEG_D2R_N<4>

=PEG_D2R_N<0>

DMI_S2N_N<1>

DMI_S2N_N<0> CPU_PEG_COMP

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<3>

CPU_CFG<1>

CPU_CFG<2>

CPU_CFG<4>

CPU_CFG<5>

CPU_CFG<6>

CPU_CFG<9>

CPU_CFG<10>

CPU_CFG<11>

CPU_CFG<12>

CPU_CFG<13>

CPU_CFG<14>

CPU_CFG<15>

CPU_CFG<16>

CPU_CFG<17>


VOLTAGE=0.75V


PPCPU_MEM_VREFDQ_A

CPU_CFG<0>

FDI_FSYNC<0>

FDI_FSYNC<1>

FDI_LSYNC<0>

DP_INT_IG_ML_N<0>

DP_INT_IG_ML_N<2>

=PEG_R2D_C_P<8>

DP_INT_IG_ML_N<3>

FDI_DATA_P<7>

FDI_INT

FDI_LSYNC<1>

DP_INT_IG_ML_N<1>

DP_INT_IG_ML_P<1>

DP_INT_IG_ML_P<2>

DP_INT_IG_ML_P<3>

FDI_DATA_N<7>

FDI_DATA_N<6>

=PEG_D2R_N<7>

=PEG_D2R_N<6>

=PEG_D2R_N<8>

=PEG_D2R_N<10>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_S2N_P<3>

=PEG_D2R_P<0>

DMI_N2S_P<2>

FDI_DATA_P<2>

FDI_DATA_P<4>

FDI_DATA_P<6>

=PEG_R2D_C_P<10>

=PEG_R2D_C_P<9>

=PEG_R2D_C_P<7>

=PEG_R2D_C_P<6>

=PEG_R2D_C_N<14>

=PEG_R2D_C_N<15>

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<12>

DP_INT_IG_AUX_N

DMI_S2N_P<1>

DMI_S2N_P<2>

DMI_N2S_P<3>

FDI_DATA_N<0>

FDI_DATA_N<5>

FDI_DATA_P<0>

FDI_DATA_P<1>

FDI_DATA_P<3>

FDI_DATA_P<5>

DP_INT_IG_AUX_P

CPU_EDP_COMP

DP_INT_IG_HPD_L

=PEG_D2R_N<5>

=PEG_D2R_N<9>

=PEG_D2R_N<15>

=PEG_D2R_P<1>

=PEG_D2R_P<2>

=PEG_D2R_P<3>

=PEG_D2R_P<4>

=PEG_D2R_P<5>

=PEG_D2R_P<6>

=PEG_D2R_P<7>

=PEG_D2R_P<10>

=PEG_D2R_P<11>

=PEG_D2R_P<12>

=PEG_D2R_P<13>

=PEG_D2R_P<14>

=PEG_D2R_P<15>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<1>

=PEG_R2D_C_N<2>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<6>

=PEG_R2D_C_N<7>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<11>

=PEG_R2D_C_N<12>

=PEG_R2D_C_N<13>

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<5>

=PEG_R2D_C_P<11>

=PEG_R2D_C_P<14>

=PEG_R2D_C_P<15>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<2>

FDI_DATA_N<4>

=PEG_D2R_N<14>

=PEG_D2R_N<13>

=PEG_D2R_N<12>

=PEG_D2R_N<11>

CPU_CFG<7>

CPU_CFG<6>

CPU_CFG<5>

DP_INT_IG_HPD

CPU_CFG<4>

CPU_CFG<16>



CPU_CFG<0>CPU_CFG<2>

CPU_CFG<1>

CPU_CFG<3>

R10101

2

R10301

2

R10471

2

R10461

2

R10451

2

R10441

2

R10421

2

R10401

2

R10411

2

R10431

2

R10491

2

R10311

2

Q1031

3

1

2

U1000

N8

N10

T9

R10

R6

R8

U8

U10

N2

N4

R2

R4

P3

P1

T5

U6

AE4

AE2

AC2

AE8

AB1

AG4

AG2

AF3

AF1

AF7

AE6

AG8

AG6

AC8

AB7

W6

V7

W10

W8

Y9

AA8

AA10

AC10

AA2

AB3

U2

U4

W4

W2

V3

V1

AA6

Y5

AD9

G2

H1

F3

G22

F23

K23

H23

F11

H11

K11

J12

F9

E8

H9

G10

H7

J8

G6

F7

K21

H21

F19

H19

K19

J20

H17

G18

K15

K17

G14

F15

J16

H15

K13

H13

C22

A22

D23

B23

B13

D13

C10

A10

D11

B11

B9

D9

D7

B7

F13

E12

A18

C18

B21

D21

D19

B19

F21

E20

C14

A14

B17

D17

D15

B15

F17

E16

U1000B57

D57

F55

K55

F57

E58

H57

H55

D53

K57

B55

A54

A58

D55

C56

E54

J54

G56

G64

BJ42

BG62

BG34

BG26

BG22

BG4

BF63

BF43

BF41

BF35

BF25

BJ34

BF23

BF21

BF19

BF3

BE32

BE16

BE6

BD33

BD29

BD19

BJ22

BD15

BD13

BC42

BC30

BC14

BB57

BB43

BB25

BB17

BB15

BH43

BB13

BA48

BA16

AY45

AY41

AY17

AY15

AY13

AW50

AW46

BH35

AW42

AW14

AJ10

AJ6

AH5

AD5

AC6

AC4

AA4

P7

BH25 N6

M9

M5

L10

L6

L4

L2

K49

K47

K9

BH23

K7

K5

J50

J4

J2

H49

H47

H5

G52

G48

BH21

G4

F5

D49

D25

D3

C52

C24

C4

B53

B25

BH19

051-9585

3.0.0

10 OF 132

9 OF 105

31 93

93

23 93

9 23 93

9 23 93

9 23 93

9 23 93

9 23 93

9 23 93

9 23 93

23 93

23 93

23 93

23 93

23 93

23 93

23 93

9 23 93

23 93

31 93

9 23 93

93

9 23 93

9 23 93

9 23 93

9 23 93

9 23 93

7 9 10 12 13 14

7 9 10 12 13 14

9 23 93 9 23 93

9 23 93

9 23 93

BI

BI

BI

BI

BI

IN

IN

OUT

IN

IN

OUT

OUT

BI

NC

OUTBI

IN

IN(2 OF 11)

CLOCKS

PWR MGMT

JTAG & BPM

DDR3 MISC

THERMALPECI

PROCHOT*

THERMTRIP*

RESET*

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

SM_DRAMRST*

SM_VREF

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

DPLL_REF_CLK

DPLL_REF_CLK*

BCLK_ITP

BCLK_ITP*

BCLK

BCLK*

PRDY*

PREQ*

TCK

TMS

TRST*

TDI

TDO

DBR*

BPM0*

BPM1*

BPM2*

BPM3*

BPM4*

BPM5*

BPM6*

BPM7*

CATERR*

PROC_SELECT*

PROC_DETECT*

IN

OUT

IN

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

BI

BI

BI

Apple Inc.


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(IPU)

(IPU)

(IPU)

(IPD)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

R1120 and R1121 are Intel recommended values

23 93

23 93

23 93

23 93

23 93

10K5%

1/16W

402

MF-LF

PLACE_NEAR=U1800.AY11:157mm

17 26 93

19 23 93

26

16 93

16 93

19 93

19 46 93

19 46 93

402

1%75

1/16WMF-LF

1/16W

2001% PLACE_NEAR=U1000.BF45:12.7mm

402

MF-LF

402

1/16W

MF-LF

PLACE_NEAR=U1000.BG46:12.7mm

1%

25.5

402

1/16W

MF-LF

1401%

PLACE_NEAR=U1000.BJ46:12.7mm

45 93

1/16W

402

5%

MF-LF

68

402

MF-LF

1/16W

1K5%PLACE_NEAR=U1000.BJ44:2.54mm

1K5%

1/16W

MF-LF

402


402X5R

10%16V

0.1UF


56

5%1/16WMF-LF402

45 46 69 93

8

8

IVY-BRIDGEOMIT_TABLEBGA

MF

1/20W

5%

1K

201

NOSTUFF

23 93

23 93

23 93

23 93

23 93

23 93

23 93

1/16WMF-LF

1%

402

200

PLACE_NEAR=R1121.2:1mm

1/16WMF-LF

1%

402

130

PLACE_NEAR=U1000.AY25:51.562mm

16 93

16 93

17 93

5%

NOSTUFF

402

MF-LF

1/16W

51

MF-LF

1%

43.2

402

1/16W

23 24

1/20W

201

MF

1K5%

NOSTUFF

23 24 93

23 93

23 93

23 93

CPU CLOCK/MISC/JTAG

PM_MEM_PWRGD


CPU_RESET_L


CPU_PROCHOT_L




XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TRST_L

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_PREQ_L

XDP_CPU_PRDY_L

DMI_CLK100M_CPU_N

DMI_CLK100M_CPU_P

ITPCPU_CLK100M_N

ITPCPU_CLK100M_P

DPLL_REF_CLK_N

DPLL_REF_CLK_P

CPU_SM_RCOMP<2>

CPU_SM_RCOMP<1>

CPU_SM_RCOMP<0>

CPU_DDR_VREF

=MEM_RESET_L

PM_MEM_PWRGD_R

PM_SYNC

PLT_RESET_LS1V1_L

CPU_PROCHOT_R_L

CPU_PECI

XDP_BPM_L<7>

CPU_PWRGD

PM_THRMTRIP_L

CPU_CATERR_L

CPU_PROC_SEL_L

R11001

2

R11201

2R1121

12

R11041

2

R112512

R11021

2

R11111

2

R11261

2

R11141

2

R11131

2

R11121

2

R11011

2

R11301

2

R11311

2

C11301

2

R110312

U1000

D5

C6

K63

K65

C62

D61

E62

F63

D59

F61

F59

G60

H53

H61

AJ4

AJ2

F53

K53

J62

H65

B59

AH9

H51

K51

AY25

BE24

BJ46

BG46

BF45

BJ44

J58

K61

K59

F51

H59

H63

C60

051-9585

3.0.0

11 OF 132

10 OF 105

7 9 10 12 13 14

7 9 10 12 13 14

7 10 13 15 26

7 10 13 15 26

7 9 10 12 13 14

93

93

93

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

SA_CLK0

SA_CLK1*

SA_DQ30

SA_DQ0

SA_DQ1

SA_DQ2

SA_DQ9

SA_DQ11

SA_DQ12

SA_DQ13

SA_DQ14

SA_DQ15

SA_DQ16

SA_DQ17

SA_DQ18

SA_DQ19

SA_DQ20

SA_DQ21

SA_DQ22

SA_DQ23

SA_DQ24

SA_DQ25

SA_DQ26

SA_DQ27

SA_DQ28

SA_DQ29

SA_DQ31

SA_DQ32

SA_DQ33

SA_DQ34

SA_DQ35

SA_DQ36

SA_DQ37

SA_DQ38

SA_DQ39

SA_DQ40

SA_DQ41

SA_DQ42

SA_DQ43

SA_DQ44

SA_DQ48

SA_DQ49

SA_DQ50

SA_DQ51

SA_DQ52

SA_DQ53

SA_DQ54

SA_DQ55

SA_DQ56

SA_DQ57

SA_DQ58

SA_DQ59

SA_DQ60

SA_DQ61

SA_DQ62

SA_DQ63

SA_BS0

SA_BS1

SA_BS2

SA_RAS*

SA_WE*

SA_CS0*

SA_CS1*

SA_ODT0

SA_ODT1

SA_DQS0*

SA_DQS1*

SA_DQS2*

SA_DQS3*

SA_DQS4*

SA_DQS5*

SA_DQS6*

SA_DQS7*

SA_DQS0

SA_DQS1

SA_DQS2

SA_DQS3

SA_DQS4

SA_DQS5

SA_DQS6

SA_DQS7

SA_MA0

SA_MA1

SA_MA2

SA_MA3

SA_MA4

SA_MA5

SA_MA6

SA_MA7

SA_MA8

SA_MA9

SA_MA10

SA_MA11

SA_MA12

SA_MA13

SA_MA14

SA_MA15

SA_DQ4

SA_DQ3

SA_DQ10

SA_DQ8

SA_DQ7

SA_DQ5

SA_DQ6

SA_CAS*

SA_DQ47

SA_DQ46

SA_DQ45

SA_CKE1

SA_CLK0*

SA_CKE0

SA_CLK1

(3 OF 11)

MEMORY CHANNEL A

SB_MA15

SB_MA14

SB_BS0

SB_DQ51

SB_DQ52

SB_DQ53

SB_DQ54

SB_DQ55

SB_DQ56

SB_DQ57

SB_DQ18

SB_DQ19

SB_DQ20

SB_DQ21

SB_DQ22

SB_DQ23

SB_DQ24

SB_DQ14

SB_DQ2

SB_DQ5

SB_DQ7

SB_DQ8

SB_DQ6

SB_DQ10

SB_DQ9

SB_DQS0

SB_DQS4

SB_DQS5

SB_DQS6

SB_DQS7

SB_MA1

SB_MA2

SB_DQ0

SB_DQ12

SB_DQ11

SB_DQ13

SB_DQ15

SB_DQ16

SB_DQ17

SB_MA13

SB_MA12

SB_MA11

SB_MA10

SB_MA9

SB_MA8

SB_MA7

SB_MA6

SB_MA5

SB_MA4

SB_MA3

SB_MA0

SB_DQS3

SB_DQS2

SB_DQS1

SB_DQS7*

SB_DQS6*

SB_DQS5*

SB_DQS4*

SB_DQS2*

SB_DQS1*

SB_DQS0*

SB_ODT1

SB_ODT0

SB_CS1*

SB_CS0*

SB_WE*

SB_RAS*

SB_CAS*

SB_BS2

SB_BS1

SB_DQ63

SB_DQ62

SB_DQ61

SB_DQ60

SB_DQ59

SB_DQ58

SB_DQ50

SB_DQ49

SB_DQ48

SB_DQ47

SB_DQ46

SB_DQ45

SB_DQ44

SB_DQ43

SB_DQ42

SB_DQ41

SB_DQ40

SB_DQ39

SB_DQ38

SB_DQ37

SB_DQ36

SB_DQ35

SB_DQ34

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQ30

SB_DQ29

SB_DQ28

SB_DQ27

SB_DQ26

SB_DQ25

SB_DQS3*

SB_CLK1*

SB_DQ3

SB_CKE1

SB_CKE0

SB_CLK0

SB_CLK0*SB_DQ1

SB_DQ4

SB_CLK1

(4 OF 11)

MEMORY CHANNEL B

Apple Inc.


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6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 27 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 28 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

6 29 94

BGA OMIT_TABLE

IVY-BRIDGE IVY-BRIDGEOMIT_TABLEBGA


CPU DDR3 INTERFACES

MEM_A_CLK_P<1>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_CKE<1>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_CAS_L

MEM_A_DQ<6>

MEM_A_DQ<5>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<10>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<9>

MEM_A_DQ<2>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DQ<30>

MEM_A_CLK_N<1>

MEM_A_CLK_P<0>

MEM_A_DQ<13>

MEM_A_DQS_N<0>

MEM_B_CLK_P<1>

MEM_B_DQ<4>

MEM_B_DQ<1> MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_DQ<3>

MEM_B_CLK_N<1>

MEM_B_DQS_N<3>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CAS_L

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_DQS_N<0>

MEM_B_DQS_N<1>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4>

MEM_B_DQS_N<5>

MEM_B_DQS_N<6>

MEM_B_DQS_N<7>

MEM_B_DQS_P<1>

MEM_B_DQS_P<2>

MEM_B_DQS_P<3>

MEM_B_A<0>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<13>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<0>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<0>

MEM_B_DQ<9>

MEM_B_DQ<10>

MEM_B_DQ<6>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<5>

MEM_B_DQ<2>

MEM_B_DQ<14>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_BA<0>

MEM_B_A<14>

MEM_B_A<15>

U1000

BA36

BC38

BB19

BE44

BC18

BD17

BB31

BA32

AW34

AY33

BD41

BD45

AL6

AL8

AV7

AY5

AT5

AR6

AW6

AT9

BA6

BA8

BG6

AY9

AP7

AW8

BB7

BC8

BE4

AW12

AV11

BB11

BA12

BE8

BA10

AM5

BD11

BE12

BB49

AY49

BE52

BD51

BD49

BE48

BA52

AY51

AK7

BC54

AY53

AW54

AY55

BD53

BB53

BE56

BA56

BD57

BF61

AL10

BA60

BB61

BE60

BD63

BB59

BC58

AW58

AY59

AL60

AP61

AN10

AW60

AY57

AN60

AR60

AM9

AR10

AR8

AN6

AN8

AU8

AU6

BD5

BC6

BC10

BD9

BB51

BC50

BD55

BB55

BD61

BD59

AV61

AU60

BD27

BA28

AW38

AW22

BA20

BB45

BE20

AW18

BB27

AW26

BB23

BA24

AY21

BD21

BC22

BB21

BB41

BC46

BE36

BA44

U1000

BJ38

BD37

AY29

BH39

BD25

BJ26

BF33

BH33

BF37

BH37

BE40

BH41

AL4

AK3

BA4

BB1

AV1

AU2

BA2

BB3

BC2

BF7

BF11

BJ10

AP3

BC4

BH7

BH11

BG10

BJ14

BG14

BF17

BJ18

BF13

BH13

AR2

BH17

BG18

BH49

BF47

BH53

BG50

BF49

BH47

BF53

BJ50

AL2

BF55

BH55

BJ58

BH59

BJ54

BG54

BG58

BF59

BA64

BC62

AK1

AU62

AW64

BA62

BC64

AU64

AW62

AR64

AT65

AL64

AM65

AP1

AR62

AT63

AL62

AM63

AR4

AV3

AU4

AN2

AN4

AW4

AW2

BF9

BH9

BH15

BF15

BH51

BF51

BF57

BH57

AY65

AY63

AN64

AN62

BF31

BH31

AY37

BJ30

AW30

BA40

BB29

BE28

BB37

BC34

BF27

BB33

BH27

BG30

BH29

BF29

BG42

BH45

BG38

BF39

051-9585

3.0.0

12 OF 132

11 OF 105

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

IN

OUT

OUT

VCC VCC

(6 OF 11)CORE POWER

VIDALERT*

VIDSCLK

VCCSA

VIDSOUT

VCCSA_VID0

VCCSA_VID1

VCC_SENSE

VSS_SENSE

VAXG_SENSE

VSSAXG_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCC_DIE_SENSE

VCC_VAL_SENSE

VSS_VAL_SENSE

VAXG_VAL_SENSE

VSSAXG_VAL_SENSE

VCCIO_SEL

VCCDQ

VCCPLL

VCCPQE

VSS_NCTF

DC_TEST_A4

DC_TEST_A62

DC_TEST_A64

DC_TEST_B3

DC_TEST_B63

DC_TEST_B65

DC_TEST_BF1

DC_TEST_BF65

DC_TEST_BG2

DC_TEST_BG64

DC_TEST_BH1

DC_TEST_BH3

DC_TEST_BH63

DC_TEST_BH65

DC_TEST_BJ2

DC_TEST_BJ4

DC_TEST_BJ62

DC_TEST_BJ64

DC_TEST_C2

DC_TEST_C64

DC_TEST_D1

DC_TEST_D65

(9 OF 11)

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Pullup for SNB

NOTE: Intel validation sense lines per doc 439028 rev1.0

HR_PPDG sections 6.2.1 and 6.3.1.

(IPU)

69 93

69 93

69 93

69 93

71 93

71 93

66 93

MF-LF

402

10K5%

CPU:SNB

1/16W

402 1/16W 0 5% MF-LF69 93

130

MF-LF

1/16W

402

1%

PLACE_NEAR=U1000.A50:2.54mm

0 MF-LF1/16W402 5%69 93

1/16W402

43

MF-LF5%

PLACE_NEAR=U1000.B51:38mm

69 93

1/16W

MF-LF

751%

402

PLACE_NEAR=R1310.1:2.54mm

5%

402

10K

MF-LF

1/16W

100

402

1/16W

NOSTUFF

PLACE_NEAR=U1000.AU10:50.8mmPLACE_SIDE=BOTTOM

MF-LF

1%

1001%

1/16W

MF-LF

NOSTUFF

402

PLACE_NEAR=U1000.AW10:50.8mmPLACE_SIDE=BOTTOM

201

1%

MF

1/20W

49.9

PLACE_SIDE=BOTTOM

NOSTUFF

PLACE_SIDE=BOTTOM49.9

NOSTUFF1%

MF

1/20W

201

201

49.9

1/20W

1%

MF

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

NOSTUFF49.9

1%

1/20W

201

MF

1%

100

NOSTUFF

1/16W

MF-LF

402

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.B47:50.8mm

1/16W

1001%

MF-LF

PLACE_SIDE=BOTTOM

NOSTUFF

402


5%

402

10K

1/16W

MF-LF

MF-LF

NOSTUFF1/16W

1%

100

402

PLACE_SIDE=BOTTOMPLACE_NEAR=U1000.F49:50.8mm

1/16W

1%

MF-LF

402

100

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.E50:50.8mm

402

MF-LF

1%

1/16W

100

66 93

66 93

IVY-BRIDGEOMIT_TABLE

BGA

IVY-BRIDGEOMIT_TABLE

BGA

SYNC_MASTER=K92_MLB

CPU POWER


=PPVCCSA_S0_CPU

CPU_VIDALERT_L_R

CPU_VIDSCLK_R

CPU_VIDSOUT_R

CPU_VCCSA_VID<0>

CPU_VCCSA_VID<1>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPU_AXG_SENSE_P

CPU_AXG_SENSE_N

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

TP_CPU_VDDQSENSEP

TP_CPU_VDDQSENSEN

CPU_VCCSASENSE

TP_CPU_DIE_SENSE

CPU_VCC_VALSENSE_P

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P

CPU_AXG_VALSENSE_N

CPU_VCCIO_SEL

=PP1V5_S3_CPU_VCCDQ



TP_DC_TEST_A4

TP_DC_TEST_A62

DC_TEST_B63_A64

DC_TEST_B3_C2

DC_TEST_B65_C64

TP_DC_TEST_BF1

TP_DC_TEST_BF65

DC_TEST_BH1_BG2

DC_TEST_BG64_BH65

DC_TEST_BH3_BJ2

DC_TEST_BJ64_BH63

TP_DC_TEST_BJ4

TP_DC_TEST_BJ62

TP_DC_TEST_D1

TP_DC_TEST_D65

=PPVCORE_S0_CPU

=PPVCORE_S0_CPU

=PPVCORE_S0_CPU



CPU_VIDALERT_L

CPU_VIDSOUT

=PPVCORE_S0_CPU_VCCAXG=PPVCORE_S0_CPU_VCCAXG


=PPVCORE_S0_CPU

CPU_VIDSCLK

=PPVCCSA_S0_CPU

=PP3V3_S0_CPU_VCCIO_SEL

R13201

2

R13121 2

R13021

2

R13111 2

R13101 2

R13001

2

R13131

2

R13631

2

R13621

2

R13701

2

R13711

2

R13641

2

R13651

2

R13601

2

R13611

2

R13141

2

R13661

2

R13671

2

R13681

2

U1000R46

R42

N43

B29

A44

A40

A38

A34

A32

A28

A26

N39

N37

N33

N30

N26

N24

N20

M46

M42

R40

M40

M36

M34

M29

M27

M23

M21

L44

L40

L38

R36

L34

L32

L28

L26

L22

K45

K43

K41

K37

K35

R34

K31

K29

K25

J44

J40

J38

J34

J32

J28

J26

R29

H45

H43

H41

H37

H35

H31

H29

H25

G44

G40

R27 G38

G34

G32

G28

G26

F45

F43

F41

F37

F35

R23

F31

F29

F25

E44

E40

E38

E34

E32

E28

E26

R21

D45

D43

D41

D37

D35

D31

D29

C44

C40

C38

N45

C34

C32

C28

C26

B45

B43

B41

B37

B35

B31

U1000

A4

A62

A64

B3

B63

B65

BF1

BF65

BG2

BG64

BH1

BH3

BH63

BH65

BJ2

BJ4

BJ62

BJ64

C2

C64

D1

D65

F49

B49

F47

B47

D47

AV23

AT23

AP23

AL23

AJ8

AW10

AK65

AK63

AK61

AV21

AT21

AP21

AL21

W17

W15

N16

N14

M17

M15

M12

M11

L18

L14

W12

U17

U15

U12

T16

T14

T11

N18

K3

AE10

AG10

AY19

B51

D51

A50

BJ60

BJ6

E64

E2

B61

B5

A60

A6

BH61

BH5

BE64

BE2

BD65

BD1

F65

F1

A46

AU10

AW20

C48

E50

A48

051-9585

3.0.0

13 OF 132

12 OF 105

7 12 15

7 15

7 14

7 8 14

6

6

6

6

6

7 12 14 49 105

7 12 14 49 105

7 12 14 49 105

7 9 10 12 13 14

7 9 10 12 13 14

7 12 13 15 7 12 13 15

7 9 10 12 13 14

7 12 14 49 105

7 12 15

7

VSSVSS

(10 OF 11)

VSSVSS

(11 OF 11)

VDDQ

VAXG

(8 OF 11)

IO POWER DDR3

GRAPHIC CORE POWER

VCCIOVCCIO

(7 OF11)IO POWER

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BGA OMIT_TABLE

IVY-BRIDGEBGA OMIT_TABLE

IVY-BRIDGE

BGA OMIT_TABLE

IVY-BRIDGE

BGAOMIT_TABLE

IVY-BRIDGE

CPU POWER AND GND

=PP1V05_S0_CPU_VCCIO=PP1V05_S0_CPU_VCCIO

=PP1V5_S3_CPU_VCCDDR=PPVCORE_S0_CPU_VCCAXG

U1000BJ56

BJ52

BG60

AU47

AU41

AU35

AU28

AU22

AU16

AU14

AT61

AT57

AT50

BG56

AT44

AT38

AT31

AT25

AT19

AT11

AT7

AT3

AT1

AR54

BG52

AR47

AR41

AR35

AR28

AR22

AP65

AP63

AP57

AP50

AP44

BG48

AP38

AP31

AP25

AP19

AP17

AP15

AP12

AP11

AP9

AP5

BG44

AN54

AN47

AN41

AN35

AN28

AN22

AM61

AM7

AM3

AM1

BG36

AL57

AL50

AL44

AL38

AL31

AL25

AL19

AK16

AK14

AK11

BG28

AK9

AK5

AJ64

AJ62

AJ60

AJ57

AH7

AH3

AH1

AG57

BG24

AG17

AG15

BG20

BG16

BJ48

BG12

BG8

BF5

BE62

BE58

BE54

BE50

BE46

BE42

BE38

BJ40

BE34

BE30

BE26

BE22

BE18

BE14

BE10

BD35

BD7

BD3

BJ32

BC60

BC56

BC52

BC48

BC44

BC40

BC36

BC32

BC28

BC26

BJ24

BC24

BC20

BC16

BC12

BB65

BB63

BB47

BB39

BB9

BB5

BJ20

BA58

BA54

BA50

BA46

BA42

BA38

BA34

BA30

BA26

BA22

BJ16

BA18

BA14

AY61

AY11

AY7

AY3

AY1

AW56

AW52

AW48

BJ12

AW44

AW40

AW36

AW32

AW28

AW24

AW16

AV65

AV63

AV59

BJ8

AV57

AV50

AV44

AV38

AV31

AV25

AV19

AV9

AV5

AU54

U1000AG12

AF65

AF63

AF61

AF11

AF9

AF5

AE57

AD16

AD14

AD7

AD3

AD1

AC64

AC62

AC60

AC57

AB11

AB9

AB5

AA57

AA17

AA15

AA12

Y65

Y63

Y61

Y7

Y3

Y1

W57

V16

V14

V11

V9

V5

U64

U62

U60

U57

T7

T3

T1

R57

R50

R44

R38

R31

R25

R19

R17

R15

R12

P65

P63

P61

P11

P9

P5

N54

N47

N41

N35

N28

N22

M57

M50

M44

M38

M31

M25

M19

M7

M3

M1

L64

L62

L60

L58

L54

L50

L46

L42

L36

L30

L24

L20

L16

L12

L8

K39

K33

K27

K1

J64

J60

J56

J52

J48

J46

J42

J36

J30

J24

J22

J18

J14

J10

J6

H39

H33

H27

H3

G62

G58

G54

G50

G46

G42

G36

G30

G24

G20

G16

G12

G8

F39

F33

F27

E60

E56

E52

E48

E46

E42

E36

E30

E24

E22

E18

E14

E10

E6

E4

D63

D39

D33

D27

C58

C54

C50

C46

C42

C36

C30

C20

C16

C12

C8

B39

B33

B27

A56

A52

A42

A36

A30

A24

A20

A16

A12

A8

U1000AH65

AH63

AE64

AE62

AE60

AD65

AD63

AD61

AD58

AD56

AB65

AB63

AH61

AB61

AB58

AB56

AA64

AA62

AA60

Y58

Y56

W64

W62

AH58

W60

V65

V63

V61

V58

V56

T65

T63

T61

T58

AH56

T56

R64

R62

R60

R55

R53

R48

N64

N62

N60

AG64

N58

N56

N52

N49

M65

M63

M61

M59

M55

M53

AG62

M48

L56

L52

L48

AG60

AF58

AF56

BJ36

BJ28

AY47

AY43

AY39

AY35

AY31

AY27

AY23

AV46

AV42

AV40

BG40

AV36

AV34

AV29

AV27

AU45

AU43

AU39

AU37

AU33

AU30

BG32

AU26

AU24

AT46

AT42

AT40

AT36

AT34

AT29

AT27

AR45

BD47

AR43

AR39

AR37

AR33

AR30

AR26

AR24

AP46

AP42

AP40

BD43

AP36

AP34

AP29

AP27

AN45

AN43

AN39

AN37

AN33

AN30

BD39

AN26

AN24

AL46

AL42

AL40

AL36

AL34

AL29

AL27

BD31

BD23

BB35

U1000AV55

AV53

AU20

AU18

AT55

AT53

AT48

AT17

AT15

AT12

AR58

AR56

AV48

AR52

AR49

AR20

AR18

AR16

AR14

AP55

AP53

AP48

AN58

AV17

AN56

AN52

AN49

AN20

AN18

AN16

AN14

AM11

AL55

AL53

AV15

AL48

AL17

AL15

AL12

AK58

AK56

AJ17

AJ15

AJ12

AH16

AV12

AH14

AH11

AF16

AF14

AE17

AE15

AE12

AD11

AC17

AC15

AU58

AC12

AB16

AB14

Y16

Y14

Y11

AU56

AU52

AU49

051-9585

3.0.0

14 OF 132

13 OF 105

7 9 10 12 13 14 7 9 10 12 13 14

7 10 15 26 7 12 15

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CPU VCCIO/VCCPQ DECOUPLINGIntel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

PLACEMENT_NOTE (C1620-C1623):

PLACEMENT_NOTE (C1624-C16D5):

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402



CPU VCCPLL Low pass filter

CPU VCCPLL DECOUPLING

Intel recommendation: 4x 470uF 4mOhm, 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 8x 1uF 0402 (NOSTUFF)

Apple Implementation: 4x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 16x 22uF 0603, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0603 (NOSTUFF)

PLACEMENT_NOTE (C1600-C16C7):

CPU VCORE DECOUPLING


402

10VX5R

10%1UF

10%

X5R402

1UF

10VX5R10V

402

1UF10%

20%6.3VX5R

NOSTUFF

0201

1UF

NOSTUFF

20%

0201

6.3VX5R

1UF

402X5R10V10%1UF

20%

NOSTUFF

0201X5R

1UF

6.3V

10%10VX5R402

1UF

X5R10V

1UF

402

10%

20%6.3V

NOSTUFF

X5R0201

1UF

6.3V

0201

20%

X5R

1UF

NOSTUFF

22UF20%6.3V

CRITICAL

Place near inductors on bottom side.

X5R-CERM10603

10V10%

402

1UF

X5R402X5R10V10%1UF1UF

10%10V

402X5R

402

10%10VX5R

1UF

10VX5R

10%1UF

402 402X5R10V10%1UF

402X5R

10%10V

1UF

Place on bottom side of U1000

1UF10%

X5R402


10V

402X5R10V10%1UF

402X5R10V10%1UF

10%

Place on bottom side of U100.

10V

1UF

402X5R

10%10VX5R402

1UF

402

10VX5R

10%


1UF

402X5R10V10%1UF

6.3V


20%22UF

X5R-CERM10603

CRITICAL

6.3V20%


22UF

CRITICAL

X5R-CERM10603

6.3V20%


22UF

CRITICAL

X5R-CERM10603

6.3V

22UF


20%

CRITICAL

X5R-CERM10603


D2T-SM

20%2.0VPOLY-TANT

470UF-4MOHM

NOSTUFF

0201

20%

X5R

NOSTUFF

1UF

6.3V

NOSTUFF

6.3V

1UF

X5R0201

20%

20%

0402-1

10UF

6.3VCERM-X5R

CRITICAL

Place near U1000 on bottom sidePlace near U1000 on bottom side

CRITICAL

20%6.3VCERM-X5R0402-1

10UF

6.3V

Place near U1000 on bottom side

0402-1

CRITICAL

10UF20%

CERM-X5R


20%

CERM-X5R

10UF

0402-1

CRITICAL

6.3V

CRITICAL

22UF


6.3V20%

X5R-CERM10603


20%

CRITICAL

0603X5R-CERM16.3V

22UF 22UF


CRITICAL

X5R-CERM1

20%6.3V

0603


6.3V20%22UF

CRITICAL

X5R-CERM10603


20%6.3V

22UF

CRITICAL

X5R-CERM10603

CRITICAL


22UF20%6.3VX5R-CERM10603

CRITICAL

20%6.3V

22UF


X5R-CERM10603

CRITICAL

22UF20%6.3V


X5R-CERM10603


6.3V20%

CRITICAL

22UF

X5R-CERM10603

20%

CRITICAL

6.3V

22UF


X5R-CERM10603

20%


6.3V

22UF

0603

CRITICAL

X5R-CERM1

402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

X5R10V10%1UF

0

402

MF-LF

1/16W

5%

10%1UF

10VX5R

402PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

10%10VX5R

402

1UF

402X5R

1UF

10V10%

1UF10%10VX5R402

10V10%

X5R402

1UF

402X5R10V10%1UF

402

10V

1UF

X5R

10%1UF

X5R10V10%

402402X5R

1UF10%10V

X5R10V10%1UF

402

10%

X5R402

1UF

10VX5R

10%


10V

402

1UF

402

10VX5R

10%1UF


10%

X5R402


10V

1UF1UF


10%

X5R10V

402

402X5R10V10%1UF

402

10%10VX5R

1UF10%

402X5R10V

1UF

402

1UF

X5R10V10%

402X5R10V10%1UF

10%10VX5R402

1UF10%

402

1UF

X5R10V

1UF

402

10%10VX5R

402X5R10V10%1UF

402

10V10%1UF

X5RX5R402

10%1UF

10V

402

10%10VX5R

1UF

402X5R10V10%1UF


10UF

6.3V20%

X5R603

CRITICAL


6.3V

10UF20%

X5R603

CRITICAL

6.3V20%


10UF

X5R603

CRITICAL

6.3V

10UF


20%

X5R603

CRITICAL

10UF20%6.3V


X5R

CRITICAL

603

10UF20%6.3V


X5R603

CRITICAL

6.3V

10UF20%


X5R603

CRITICAL

6.3V20%


10UF

X5R603

CRITICAL

20%6.3V


X5R603

10UF

CRITICAL

6.3V20%10UF


X5R603

CRITICAL

20%

2VPOLY

CASE-D2-SM

Place near inductors on bottom side

330UF-0.006OHM

CRITICAL

0603MF1/4W1%

0.010

1UF

X5R

20%6.3V

0201

NOSTUFF NOSTUFF

1UF

X5R

20%

0201

6.3V

NOSTUFF

1UF

X5R

20%6.3V

0201

NOSTUFF

1UF

X5R

20%6.3V

0201

NOSTUFF

1UF

X5R

20%

0201

6.3V

NOSTUFF

1UF

X5R

20%

0201

6.3V

NOSTUFF

1UF

X5R

20%

0201

6.3V

NOSTUFF

1UF

X5R

20%

0201

6.3V

NOSTUFF

X5R0201

1UF20%6.3V

NOSTUFF

1UF

X5R

20%

0201

6.3V

NOSTUFF

1UF

X5R

20%

0201

6.3V

NOSTUFF

1UF

X5R

20%

0201

6.3V

NOSTUFF

1UF

X5R

20%

0201

6.3V

6.3V

NOSTUFF

0201X5R

20%1UF

NOSTUFF

6.3VX5R0201

1UF20%

X5R

20%

0201

1UF

NOSTUFF

6.3V

0201

20%

NOSTUFF

X5R6.3V

1UF1UF20%6.3V

NOSTUFF

X5R0201

1UF20%

0201

6.3VX5R

NOSTUFFNOSTUFF

1UF

X5R0201

6.3V20%

1UF

X5R

20%

0201

6.3V

NOSTUFF

NOSTUFF

22UF20%6.3V


X5R-CERM10603


20%22UF

6.3V

NOSTUFF

X5R-CERM10603


22UF20%

NOSTUFF

6.3VX5R-CERM10603


20%6.3V

22UF

NOSTUFF

X5R-CERM10603

CASE-D2-SM


POLY

20%

2V

330UF-0.006OHM

CRITICAL

330UF-0.006OHM

2V

20%

POLY

PLACE_NEAR=U1000.AK61:5 mm

CASE-D2-SM

CRITICAL

NOSTUFF

22UF20%6.3V


X5R-CERM10603

6.3V20%22UF

NOSTUFF

X5R-CERM10603


POLY-TANT2.0V20%470UF-4MOHM

D2T-SM1

CRITICAL CRITICAL

20%2.0V

470UF-4MOHM

D2T-SM1POLY-TANT

D2T-SM1

470UF-4MOHM20%2.0VPOLY-TANT

CRITICAL

POLY-TANT2.0V20%470UF-4MOHM

D2T-SM1

CRITICAL


CPU DECOUPLING-I

=PPVCORE_S0_CPU



=PP1V8_S0_CPU_VCCPLL


C16121

2

C16111

2

C16101

2

C16A41

2

C16A31

2

C16091

2

C16A21

2

C16081

2

C16071

2

C16A11

2

C16A01

2

C16311

2

C16061

2

C16191

2

C16051

2

C16181

2

C16041

2

C16171

2

C16031

2

C16021

2

C16161

2

C16151

2

C16011

2

C16141

2

C16001

2

C16131

2

C16301

2

C16291

2

C16271

2

C16261

2

C16401

23

C16A61

2

C16A51

2

C16201

2

C16211

2

C16221

2

C16231

2

C16251

2

C16241

2

C16281

2

C16321

2

C16331

2

C16391

2

C16381

2

C16371

2

C16361

2

C16351

2

C16341

2

C16861

2

R1600

1 2

C16851

2

C16841

2

C16581

2

C16571

2

C16561

2

C16551

2

C16541

2

C16531

2

C16521

2

C16511

2

C16501

2

C16491

2

C16481

2

C16471

2

C16461

2

C16641

2

C16631

2

C16621

2

C16611

2

C16601

2

C16591

2

C16711

2

C16701

2

C16691

2

C16681

2

C16671

2

C16661

2

C16651

2

C16751

2

C16741

2

C16731

2

C16721

2

C16791

2

C16781

2

C16771

2

C16761

2

C16811

2

C16801

2

C16821

2

R16011 2

C16A71

2

C16A81

2

C16A91

2

C16B01

2

C16B11

2

C16B21

2

C16B31

2

C16B41

2

C16B51

2

C16B61

2

C16B71

2

C16B81

2

C16B91

2

C16C01

2

C16C71

2

C16C61

2

C16C51

2

C16C41

2

C16C31

2

C16C11

2

C16C21

2

C16D31

2

C16D21

2

C16D11

2

C16D01

2

C16831

2

C16871

2

C16D41

2

C16D51

2

C16411

23

C16421

23

C16431

23

C16441

23

051-9585

3.0.0

16 OF 132

14 OF 105

7 12 49 105

7 12

7 8 12

7

7 9 10 12 13

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



CPU VDDQ/VCCDQ DECOUPLING


Intel recommendation: 2x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 6x 22uF 0805, 2x 22uF 0805 (NOSTUFF), 8x 10uF 0603, 2x 10uF 0603 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)

CPU VCCSA DECOUPLING



Apple Implementation: 2x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 6x 22uF 0603, 2x 22uF 0603 (NOSTUFF), 6x 10uF 0402, 2x 10uF 0402 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)

VAXG DECOUPLING


Intel recommendation: 1x 330uF, 3x 10uF 0603, 3x 1uF 0402


Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402


Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402



1UF10%

X5R402

10V

NOSTUFF

1UF

X5R10V10%

NOSTUFF

402

1UF

402X5R10V10%

NOSTUFF

1UF10%10VX5R402

NOSTUFF

1UF10%10VX5R402

NOSTUFF

X5R

10%

402

NOSTUFF

1UF

10VX5R

NOSTUFF

402

10V10%1UF

10V

NOSTUFF

1UF

402X5R

10%10V

402X5R

10%1UF

NOSTUFF

X5R10V10%1UF

402

1UF10%10V

402X5R

402

10V10%1UF

X5R

0402-1

20%

NOSTUFF

10UF

6.3VCERM-X5R

Place close to U1000 on bottom side

NOSTUFF

10UF20%6.3V


CERM-X5R0402-1


0603X5R-CERM16.3V20%22UF

NOSTUFF

0603X5R-CERM1

NOSTUFF


6.3V20%22UF

1UF

402

10%10VX5R

10UF

6.3V20%


0402-1CERM-X5R

1UF

402X5R10V10%

0402-1

20%6.3VCERM-X5R

10UF


402

10V

1UF10%

X5R


0402-1

20%10UF


6.3VCERM-X5R

0603X5R-CERM1


20%6.3V

22UF

0603X5R-CERM1

22UF20%6.3V


X5R-CERM16.3V


20%22UF

0603

1UF

X5R402

10V10%


10V

402


X5R

10%1UF

0402-1

10UF20%


6.3VCERM-X5R

0402-1

6.3V20%


10UF

CERM-X5R

1UF

402

10V10%


X5R

20%

CERM-X5R0402-1

10UF

6.3V


0603X5R-CERM16.3V

22UF20%


0603X5R-CERM1

20%


6.3V

22UF

0603X5R-CERM1


6.3V20%22UF

402

10V

1UF10%

X5R

1UF10%

402

10VX5RX5R

402

1UF

10V10%

1UF10%10VX5R402402

10V10%1UF

X5R

10%1UF

10V

402X5R

1UF10%

X5R10V

402


402

1UF

10V10%

X5R

1UF

10V10%


402X5R

1UF

10V


X5R

10%

402

1UF

402X5R

10%


10V

603


X5R6.3V

10UF20%

603X5R


6.3V20%10UF

20%6.3V

10UF

603X5R


603X5R


20%6.3V

10UF

603X5R

10UF


20%6.3V

603X5R


20%6.3V

10UF

603X5R6.3V20%


10UF

603X5R

10UF


20%6.3V

1UF

402

10%

X5R10V

X5R


1UF

10V

402

10%

603X5R

20%10UF

6.3V

603X5R

10UF

6.3V20%


402

10V10%1UF

X5R


1UF

10V10%

X5R402

603X5R6.3V

10UF20%

603X5R

10UF20%6.3V

402

10V10%1UF


X5R

X5R

10UF20%6.3V

603

0.010

1%1/4WMF0603


CASE-D2-SM

330UF-0.006OHM

2V

20%

POLY

CASE-D2-SM

330UF-0.006OHM20%2VPOLY

470UF-4MOHM

CRITICALNOSTUFF

POLY-TANT2.0V20%

D2T-SM1POLY-TANT2.0V20%470UF-4MOHM

D2T-SM1

CRITICAL

D2T-SM1

20%2.0VPOLY-TANT

CRITICAL

470UF-4MOHM


CPU DECOUPLING-II

SYNC_MASTER=K92_MLB

=PPVCCSA_S0_CPU=PP1V5_S3_CPU_VCCDDR

=PP1V5_S3_CPU_VCCDQ

=PPVCORE_S0_CPU_VCCAXG

C17171

2

C17161

2

C17151

2

C17141

2

C17131

2

C17121

2

C17111

2

C17101

2

C17091

2

C17081

2

C17071

2

C17061

2

C17251

2

C17241

2

C17331

2

C17321

2

C17051

2

C17231

2

C17041

2

C17221

2

C17031

2

C17211

2

C17311

2

C17301

2

C17291

2

C17021

2

C17011

2

C17201

2

C17191

2

C17001

2

C17181

2

C17281

2

C17271

2

C17261

2

C17571

2

C17471

2

C17461

2

C17451

2

C17441

2

C17431

2

C17421

2

C17411

2

C17401

2

C17391

2

C17381

2

C17551

2

C17541

2

C17531

2

C17521

2

C17511

2

C17501

2

C17491

2

C17481

2

C17621

2

C17611

2

C17671

2

C17661

2

C17601

2

C17591

2

C17651

2

C17641

2

C17581

2

C17631

2

R17001 2

C17561

2C17681

2

C17371

23

C17341

23

C17351

23

051-9585

3.0.0

17 OF 132

15 OF 105

7 12 7 10 13 26

7 12

7 12 13

IN

IN

OUT

OUT

OUT

IN

BI

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

IN

IN

OUT

OUT

OUT

BI

OUT

SATA3COMPI

SATA3RCOMPO

SATA0GP/GPIO21

SATA1GP/GPIO19

SATALED*

SATA3RBIAS

SATAICOMPO

SATA1RXN

SATA0TXP

SATA0TXN

SATA2RXN

SATA2RXP

SATA5RXP

SATA0RXP

LDRQ0*

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

HDA_RST*

SPKR

HDA_SDIN0

HDA_SDIN1

HDA_SDIN3

HDA_SDIN2

HDA_SDO

HDA_DOCK_EN*/GPIO33

HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CS0*

SPI_CLK

SPI_CS1*

SPI_MOSI

SPI_MISO

FWH0/LAD0RTCX1

RTCX2

SATA1TXP

SATA0RXN

SERIRQ

LDRQ1*/GPIO23

FWH1/LAD1

FWH2/LAD2

FWH3/LAD3

FWH4/LFRAME*

SATA1RXP

SATA1TXN

SATA2TXN

SATA2TXP

SATA3RXN

SATA3RXP

SATA3TXN

SATA3TXP

SATA4RXN

SATA4RXP

SATA4TXN

SATA4TXP

SATA5RXN

SATA5TXN

SATA5TXP

SATAICOMPI

JTAG

SPI

SATA

LPC

IHDA

RTC

(1 OF 10)

PEG_B_CLKRQ*/GPIO56

CLKOUT_PEG_B_N

PCIECLKRQ4*/GPIO26

PCIECLKRQ3*/GPIO25

CLKOUT_PCIE4P

CLKOUT_PCIE4N

CLKOUT_PCIE3P

CLKOUT_PCIE3N

PCIECLKRQ1*/GPIO18

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE2P

CLKOUT_PCIE2N

PCIECLKRQ0*/GPIO73

CLKOUT_PCIE1N

CLKOUT_PCIE1P

CLKOUT_PCIE0N

CLKOUT_PCIE0P

PERN3

PETP2

PETN2

PERP1

PETN1

PERN1

SMBCLK

SMBALERT*/GPIO11

PETP8

PERP8

PETN8

PETP7

PERN8

PETN7

PERP7

PERN7

PETN6

PETP6

PERP6

PERN6

PETP5

PETN5

PERP5

PETP4

PERN5

PETN4

PERP4

PETP3

PERN4

PETN3

PERP3

PERN2

PERP2

PETP1SMBDATA

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE5P

CLKOUT_PCIE5N

CLKOUT_PEG_B_P

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE6N

CLKOUT_PCIE6P

CLKOUT_PCIE7N

CLKOUT_PCIE7P

PCIECLKRQ7*/GPIO46

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_DP_P

CLKOUT_DP_N

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_P

CLKIN_SATA_N

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XTAL25_IN

XCLK_RCOMP

CLKOUT_PEG_A_N

PEG_A_CLKRQ*/GPIO47

CLKOUT_PEG_A_P

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML1DATA/GPIO75

CL_CLK1

CL_DATA1

CL_RST1*C-LINK

PCI-E*

CLOCKS

CLOCKS

FLEX

SMBUS

(2 OF 10)

IN

IN

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

BI

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

OUT

BI

BI

OUT

OUT

NC

NC

Apple Inc.


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6 3


III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY ITConnect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.

(IPD-BOOT)

(IPD)

(IPD)

(IPD)

Controlled by PCIECLKRQ5#

DOES THIS NEED LENGTH MATCH???

(IPU/IPD)

(IPU)

(IPU)

(IPD-BOOT)

(IPU)

(IPU)

(IPD-PWROK)

(IPU/IPD)

(IPD-PWROK)

(IPD-PWROK)

(IPU)

(IPU)

(IPU-RSMRST#)

1.8V -> 1.1V

(IPD)

(IPU-RSMRST#)

(IPD-PWROK)

(IPD-PLTRST#)

Unused clock terminations for FCIM Mode

(IPU)

(IPD)

(IPD-BOOT)

VSel strap not functional (VCCVRM = 1.8V)

If HDA = S0, must also ensure that signal cannot be high in S3.

24

57 96

47 96

47 96

47 96

47 96

6 45 47

41 95

41 95

41 95

41 95

36 96

36 96

32 96

32 96

38 96

38 96

36 96

36 96

32 96

32 96

38 96

38 96

48 96

48 96

8

8

8

8

1/20W5%

201MF

330K

1/20W5%

201MF

1M

1/20W5%

201MF

20K

1/20W5%

201MF

20K

10%

402X5R

1UF

10V10V10%

402X5R

1UF

1/20W1%

201MF

37.4

PLACE_NEAR=U1800.Y11:2.54mm

1/20W5%

201MF

10K

1/20W1%

201MF

90.9

PLACE_NEAR=U1800.Y47:2.54mm

48 96

48 96

16 33

OMIT_TABLE

FCBGA

MOBILE

PANTHERPOINT

FCBGA

MOBILE

PANTHERPOINT

OMIT_TABLE

16 24

23

23

23

23

MF201

NO STUFF

1/20W5%

0

NO STUFF

201MF

1/20W5%

0

1/16W1%

402MF-LF

604

1/20W1%

201MF

1K

24

24

750

MF201

5%1/20W

PLACE_NEAR=U1800.AH1:2.54mm

1/20W1%

201MF

49.9


23

23

38 96

38 96

32 96

32 96

8 96

16 32

8 96

16 39

16

16

48 96

48 96

10 93

10 93

8

8

16 96

16 96

16 96

16 96

16 96

16 96

16 96

24 96

8 16

41 95

41 95

41 95

41 95

16 36

75 96

75 96

33 96

33 96

16 35 1/20W 201MF

10K5%

1/20W5% 201MF

4.7K

MF 2015% 1/20W

10K

5% MF

10K1/20W 201

1/20W5% 201MF

10K

1/20W5% 201MF

10K

1/20W5% 201MF

10K

1/20W5% 201MF

10K

1/20W5% 201MF

10K

1/20W5% 201MF

10K

1/20W5% 201MF

10K

201MF1/20W5%

10K

1/20W5% 201MF

10K

10KMF 2015% 1/20W

5% 1/20W 201MF

10K

2011/20W5% MF

10KGPU:1P

MF 2011/20W5%

10K

16 25

16

5% 201

10KMF1/20W

201MF

10K5% 1/20W

PLACE_NEAR=U1800.K34:1.27mm 1/20W5% 201MF

33

1/20W5% 201MF

33PLACE_NEAR=U1800.A36:1.27mm

5%PLACE_NEAR=U1800.N34:1.27mm 1/20W 201MF

33

1/20W5% 201MF

33PLACE_NEAR=U1800.L34:1.27mm

57 96

57 96

57 96

57 96

6 45 47 89 96

6 45 47 89 96

6 45 47 89 96

6 45 47 89 96

331/20W5% 201MF

1/20W5% 201MF

33

1/20W5% 201

33MF

5% 1/20W 201MF

33

6 45 47 89 96 5% 201MF

331/20W

1/20W5% 201MF

10K

1/20W5% 201MF

10K

MF1/20W5% 201

10K

1/20W5% 201MF

10K

1/20W5% 201MF

10K

1/20W5% 201MF

10K

1/20W5% 201MF

10K

1/20W5% 201MF

10K

1/20W5% 201MF

10K

36 96

36 96

GPU:2P

5% 201

10KMF1/20W

PCH SATA/PCIe/CLK/LPC/SPI

SYNC_DATE=06/02/2011SYNC_MASTER=J31_ANNE

PCH_SATALED_L

FW_CLKREQ_L

PEGCLKRQB_L_GPIO56

PCIECLKRQ0_L_GPIO73

=PP3V3_SUS_PCH_GPIO

PEGCLKRQA_L_GPIO47

AP_CLKREQ_L

PCH_GPIO11

USB_EXTB_SEL_XHCI

TBT_CLKREQ_L

ENET_CLKREQ_L

JTAG_DPMUXUC_TRST_L

EXCARD_CLKREQ_L

PEGCLKRQB_L_GPIO56

=PP3V3_S0_PCH_GPIO

LPC_AD_R<1>

TP_SATA_F_D2RP

TP_SATA_D_D2RN

TP_SATA_C_R2D_CP

TP_SATA_C_R2D_CN

TP_SATA_C_D2RP

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

HDA_SYNC_R

LPC_AD<2>

ITPCPU_CLK100M_N

SYSCLK_CLK32K_RTC

TP_LPC_DREQ0_L

SATA_ODD_R2D_C_P

XDP_PCH_TCK

HDA_RST_R_L

TP_SATA_D_D2RP

HDA_BIT_CLK_R

LPC_AD_R<0>

HDA_SYNC_R

PCIE_CLK100M_PCH_N

PCH_XCLK_RCOMP

PCH_CLK100M_SATA_N

PCIE_ENET_R2D_C_NLPC_AD_R<2>

HDA_SDOUT_R

XDP_PCH_TDI

PCH_SATAICOMP

ITPXDP_CLK100M_P

SYSCLK_CLK25M_SB SYSCLK_CLK25M_SB_R

PCH_INTVRMEN_L

PCH_INTRUDER_L

PCH_SRTCRST_L

TP_SATA_F_R2D_CN

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

TBT_PWR_EN_PCH

TP_SATA_D_R2D_CP

LPC_AD_R<0>

HDA_SDOUT

HDA_RST_LHDA_RST_R_L

HDA_SYNC

HDA_BIT_CLK_R

LPC_FRAME_L

LPC_AD<0>

TBT_CLKREQ_L

PCIE_CLK100M_FW_P

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R_N

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_FW_D2R_P

PCIE_FW_D2R_N

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_ENET_D2R_P

PCH_CLK33M_PCIIN

PCH_CLK14P3M_REFCLK

PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_N

PCIE_CLK100M_PCH_P

PCIE_CLK100M_PCH_N

TP_PCH_CLKOUT_DPP

TP_PCH_CLKOUT_DPN

DMI_CLK100M_CPU_P

DMI_CLK100M_CPU_N

USB_EXTD_SEL_XHCI

SML_PCH_0_DATA

SML_PCH_0_CLK

USB_EXTB_SEL_XHCI

SMBUS_PCH_DATA

SMBUS_PCH_CLK

TP_CLINK_RESET_L

TP_CLINK_DATA

TP_CLINK_CLK

TP_PCIE_CLK100M_PEGAP

PEGCLKRQA_L_GPIO47

TP_PCIE_CLK100M_PEGAN

PCH_CLKIN_GNDP1

PCH_CLKIN_GNDN1





NC_PCIE_5_D2RN

NC_PCIE_5_D2RP

NC_PCIE_5_R2D_CN

NC_PCIE_5_R2D_CP

NC_PCIE_6_D2RN

NC_PCIE_6_D2RP

NC_PCIE_6_R2D_CP

NC_PCIE_6_R2D_CN

NC_PCIE_7_D2RN

NC_PCIE_7_D2RP

NC_PCIE_7_R2D_CN

NC_PCIE_8_D2RP

NC_PCIE_8_R2D_CP

PCH_GPIO11

=PP3V3_S0_PCH

=PPVRTC_G3_PCH

PCH_SRTCRST_L

RTC_RESET_L

PCH_INTRUDER_L


=PP1V05_S0_PCH

XDP_PCH_TDO

SPI_CLK_R

TP_HDA_SDIN1

HDA_SDIN0

PCH_SPKR

JTAG_TBT_TMS

TP_HDA_SDIN3

TP_HDA_SDIN2

TP_SATA_C_D2RN

TP_SATA_E_D2RN

PCH_SATA3COMP

HDA_BIT_CLK

LPC_AD_R<3>

LPC_FRAME_R_L

PCH_INTVRMEN_L

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_N

NC_PCIE_7_R2D_CP

NC_PCIE_8_D2RN

NC_PCIE_8_R2D_CN

TP_SATA_D_R2D_CN

XDP_PCH_TMS

SPI_MISO

TP_SPI_CS1_L

SPI_CS0_R_L

ENET_MEDIA_SENSE_RDIV

ENET_CLKREQ_L

ITPCPU_CLK100M_P

SML_PCH_1_DATA

SML_PCH_1_CLK


PCH_CLK96M_DOT_P

SPI_MOSI_R

=PP3V3_T29_PCH_GPIO

PCH_SPKR


SYSCLK_CLK25M_SB_R

PCH_CLKIN_GNDN1

PCH_CLKIN_GNDP1

PCH_CLK14P3M_REFCLK

PCIE_CLK100M_PCH_P

PCH_CLK100M_SATA_N

PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_N

PCH_CLK96M_DOT_P

ITPXDP_CLK100M_N

PCIE_CLK100M_ENET_P

TP_SATA_F_D2RN

TP_SATA_E_R2D_CN

RTC_RESET_L

LPC_AD_R<1>

SATARDRVR_EN

LPC_AD<3>

PCIE_CLK100M_FW_N

PCIECLKRQ0_L_GPIO73

PCIE_CLK100M_ENET_N

AP_CLKREQ_L

PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

FW_CLKREQ_L

JTAG_DPMUXUC_TRST_L


PCIE_CLK100M_TBT_P

LPC_FRAME_R_L

LPC_AD_R<3>

LPC_AD_R<2>

TP_SATA_E_D2RP

TP_SATA_E_R2D_CP

TP_SATA_F_R2D_CP

PCH_SATALED_L

PCH_SATA3RBIAS

LPC_SERIRQ

LPC_AD<1>



EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_P

TP_PCIE_CLK100M_PEBN

TP_PCIE_CLK100M_PEBP

USB_EXTD_SEL_XHCI


PCIE_CLK100M_TBT_N

PEG_CLKREQ_L

PEG_CLK100M_P

PEG_CLK100M_N

PEGCLKRQB_L_GPIO56

PEG_CLKREQ_L

DP_AUXCH_ISOL

JTAG_TBT_TMS

HDA_SDOUT_R

R18001

2

R18011

2

R18021

2

R18031

2

C18031

2

C1802 1

2

R18301

2

R18201

2

R18901

2

U1800 C38

A38

B37

C37

D36

N34

C36

N32

K34

E34

G34

C34

A34

A36

L34

K22

C17

J3

K5

H1

H7

E36

K36

D20

A20

C20

V14

AM3

AM1

AP7

AP5

P1

AM10

AM8

AP11

AP10

AD7

AD5

AH5

AH4

AB13

AH1

AB12

AB8

AB10

AF3

AF1

Y7

Y5

AD3

AD1

Y3

Y1

AB3

AB1

Y10

Y11

P3

V5

T3

Y14

T1

U3

V4

T10

G22

U1800

M7

T11

P10

BF18

BE18

G24

E24

BJ30

BG30

H45

AK7

AK5

AV22

AU22

AM12

AM13

AK14

AK13

Y40

Y39

AB49

AB47

AA48

AA47

Y37

Y36

Y43

Y45

V45

V46

V40

V42

V38

V37

AB37

AB38

AB42

AB40

K43

F47

H47

K49

J2

M1

V10

A8

L12

L14

T13

K12

M10

E6

BG34

BE34

BG36

BF36

BG37

BJ38

BG40

BE38

BJ34

BF34

BJ36

BE36

BH37

BG38

BJ40

BC38

AV32

BB32

AV34

AY34

AY36

AU36

AY40

AW38

AU32

AY32

AU34

BB34

BB36

AV36

BB40

AY38

K45

E12

H14

C9

A12

C8

G12

C13

E14

M16

Y47

V47

V49

R18401 2

R18411 2

R18721 2

R18731

2

R18321

2

R18311

2

R1876 1 2

R1877 1 2

R1878 1 2

R1834 1 2

R1842 1 2

R1869 1 2

R1844 1 2

R1845 1 2

R1847 1 2

R1814 2 1

R1815 1 2

R1843 1 2

R1833 1 2

R1879 1 2

R1846 1 2

R1853 1 2

R1848 1 2

R1854 1 2

R1855 1 2

R1812 1 2

R1813 1 2

R1810 1 2

R1811 1 2

R1861 1 2

R1862 1 2

R1863 1 2

R1864 1 2

R1860 1 2

R1891 1 2

R1892 1 2

R1893 1 2

R1894 1 2

R1895 1 2

R1896 1 2

R1897 1 2

R1870 1 2

R1871 1 2

R1880 1 2

051-9585

3.0.0

18 OF 132

16 OF 105

16

16 39

16

16

7 17 18 19

16

16 32

16

16 25

16 35

16 36

16

16

16

7 17 18 19 30

16

6

6

16 96

10 93

6

16 96

6

16 96

16

16 96

16 96

16

16 24 96

95

23 93

16

16

16

16

6

6

16

16 96

16 96

6

6

6

16

16

16

8

8

8

8

16

7 22

7 17 20

16

16

16

7 20 22

7 22

6

16

6

6

6

95

16

16

16

6

10 93

7 20 22

7 19

16

6

16

16

16

16 96

16 96

16 96

16 96

16 96

16 96

23 93

6

6

16

16

23 41

16

6

16

16

16

6

6

6

16

6

6

6

6

16

16 24

16

8 16

23 87

16 33

16 24 96

IN

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT DMI1TXP

SUSACK*

DMI_ZCOMP

DMI0TXN

FDI_RXN6

FDI_RXN7

FDI_RXP0

FDI_RXP3

FDI_RXP1

FDI_RXP2

FDI_RXP5

FDI_RXP4

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_LSYNC0

FDI_FSYNC1

FDI_LSYNC1

DMI2TXN

DMI1TXN

DMI3TXN

DMI3TXP

FDI_RXN0

FDI_RXN1

FDI_RXN3

FDI_RXN2

FDI_RXN4

FDI_RXN5

DMI0RXN

FDI_RXP6

DMI1RXN

DMI0TXP

DMI3RXP

DMI2RXP

DMI1RXP

DMI0RXP

DMI3RXN

DMI2RXN

DMI2TXP

DMI2RBIAS

DMI_IRCOMP

SUS_STAT*/GPIO61

SLP_S4*

SLP_S5*/GPIO63

SUSCLK/GPIO62

SLP_SUS*

SLP_A*

SLP_S3*

PMSYNCH

SLP_LAN*/GPIO29

SYS_RESET*

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST*

SUSWARN*/SUSPWRDNACK/GPIO30

PWRBTN*

ACPRESENT/GPIO31

BATLOW*/GPIO72

RI*

DSWVRMEN

DPWROK

WAKE*

CLKRUN*/GPIO32

SYSTEM POWER

MANAGEMENT

FDI

DMI

(3 OF 10)

LVD_VBG

DDPD_3P

DDPD_2P

DDPD_3N

DDPD_2N

DDPD_1P

DDPD_1N

DDPD_0P

DDPD_0N

DDPD_HPD

DDPD_AUXN

DDPD_AUXP

DDPD_CTRLDATA

DDPD_CTRLCLK

DDPC_3P

DDPC_3N

DDPC_2P

DDPC_2N

DDPC_0P

DDPC_1P

DDPC_1N

DDPC_0N

DDPC_HPD

DDPC_AUXN

DDPC_AUXP

DDPC_CTRLDATA

DDPC_CTRLCLK

DDPB_3P

DDPB_3N

DDPB_1P

DDPB_2P

DDPB_2N

DDPB_1N

DDPB_0P

DDPB_HPD

DDPB_0N

DDPB_AUXN

DDPB_AUXP

SDVO_CTRLCLK

SDVO_CTRLDATA

SDVO_INTP

SDVO_INTN

SDVO_STALLP

SDVO_STALLN

SDVO_TVCLKINP

SDVO_TVCLKINN

L_CTRL_CLK

DAC_IREF

CRT_IRTN

CRT_VSYNC

CRT_HSYNC

CRT_DDC_DATA

CRT_DDC_CLK

CRT_RED

CRT_GREEN

CRT_BLUE

L_VDD_EN

L_DDC_DATA

L_CTRL_DATA

LVD_IBG

LVD_VREFH

LVD_VREFL

LVDSA_CLK

LVDSA_CLK*

LVDSA_DATA0*

LVDSA_DATA1*

LVDSA_DATA2*

LVDSA_DATA3*

LVDSA_DATA0

LVDSA_DATA1

LVDSA_DATA2

LVDSA_DATA3

LVDSB_CLK*

LVDSB_CLK

LVDSB_DATA0*

LVDSB_DATA1*

LVDSB_DATA2*

LVDSB_DATA0

LVDSB_DATA3*

LVDSB_DATA3

LVDSB_DATA1

LVDSB_DATA2

L_DDC_CLK

L_BKLTCTL

L_BKLTEN

LVDS

(4 OF 10)

DIGITAL DISPLAY INTERFACE

CRT

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(IPD)

(IPD)

(IPD)

(IPD)

(IPD)

(IPD)

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPU)

(IPU)

(IPU)

(IPD-DeepS4/S5)

9 93

6 9 93

6 9 93

6 9 93

6 9 93

6 9 93


49.9

MF201

1%1/20W

9 93

6 9 93

6 9 93

6 9 93

6 9 93

6 9 93

6 9 93

6 9 93

6 9 93

9 93

9 93

6 9 93

6 9 93

6 9 93

6 9 93

PLACE_NEAR=U1800.T43:2.54mm

1K

MF201

5%1/20W

PLACE_NEAR=U1800.BH21:2.54mm

750

MF201

1%1/20W

OMIT_TABLE

PANTHERPOINTMOBILE

FCBGA

OMIT_TABLE

PANTHERPOINTMOBILE

FCBGA

390K

MF201

5%1/20W

10K

MF201

5%1/20W

0

MF201

5%1/20W

17 74

100K

MF201

5%1/20W

6 24 45

23 45 92

10 26 93

24 92

92

74

17 23 45

45 46 74

46

6 17 24 32

6 17 45 47

6 45 47

46

17 45 74

17 26 32 45 74

6 17 26 45 74

10 93

45

86

86

PLACE_NEAR=U1800.AF37:2.54mm

2.37K

MF201

1%1/20W

8 17

8 17

8

8

89 95

8

89 95

89 95

8

89 95

89 95

89 95

89 95

89 95

8 95

89 95

89 95

89 95

8 95

89 95

89 95

89 95

8

9 93

6 9 93

6 9 93

6 9 93

6 9 93

9 93

9 93

6 9 93

6 9 93

9 93

9 93

6 9 93

9 93

6 9 93

6 9 93

6 9 93

100KMF 2015% 1/20W

1KMF 2015% 1/20W

8.2KMF 2015% 1/20W

1KMF 2015% 1/20W

100KMF 2015% 1/20W

100KMF 2015% 1/20W

100KMF 2015% 1/20W

10K

MF201

5%1/20W

87

10KMF 2015% 1/20W

17

100KMF 2015% 1/20W

100KMF 2015% 1/20W

SYNC_DATE=05/26/2011SYNC_MASTER=J5_MLB

PCH DMI/FDI/PM/GraphicsPCIE_WAKE_L

MAKE_BASE=TRUE

=PP3V3_SUS_PCH_GPIO

=PP3V3_S0_PCH_GPIO

LVDS_IG_BKL_ON

LVDS_IG_PANEL_PWR

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L

PM_SLP_SUS_L

PM_SLP_S4_L

PM_SLP_S3_L

PM_CLKRUN_L

MEM_VDD_SEL_1V5_L

PM_PWRBTN_L

=TBT_WAKE_L

=PP3V3_S5_PCH

PM_DSW_PWRGD

FDI_LSYNC<0>

SMC_ADAPTER_EN

PM_BATLOW_L

PCH_RI_L

PM_SYSRST_L

=PP3V3_SUS_PCH_GPIO

PCH_SUSWARN_L

MEM_VDD_SEL_1V5_L

PM_SLP_SUS_L

PM_PCH_SYS_PWROK

PM_PCH_PWROK

PCH_DMI2RBIAS

PCH_DSWVRMEN

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_CLK_P

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_CLK_N

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_DATA_N<3>

LVDS_IG_A_DATA_N<2>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK_N

LVDS_IG_BKL_ON

LVDS_IG_BKL_PWM

LVDS_IG_DDC_CLK

TP_LVDS_IG_CTRL_DATA

LVDS_IG_DDC_DATA

LVDS_IG_PANEL_PWR

TP_CRT_IG_BLUE

TP_CRT_IG_GREEN

TP_CRT_IG_RED

TP_CRT_IG_DDC_CLK

TP_CRT_IG_DDC_DATA

TP_CRT_IG_HSYNC

TP_CRT_IG_VSYNC

PCH_DAC_IREF

TP_LVDS_IG_CTRL_CLK

TP_SDVO_TVCLKINN

TP_SDVO_TVCLKINP

TP_SDVO_STALLN

TP_SDVO_STALLP

TP_SDVO_INTN

TP_SDVO_INTP

DPA_IG_DDC_DATA

DPA_IG_DDC_CLK

DPA_IG_AUX_CH_P

DPA_IG_AUX_CH_N

TP_DP_IG_B_MLN<0>

DPA_IG_HPD

TP_DP_IG_B_MLP<0>

TP_DP_IG_B_MLN<1>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLP<1>

TP_DP_IG_B_MLN<3>

TP_DP_IG_B_MLP<3>

DPB_IG_DDC_CLK

DPB_IG_DDC_DATA

DPB_IG_AUX_CH_P

DPB_IG_AUX_CH_N

DPB_IG_HPD

TP_DP_IG_C_MLN<0>

TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLP<0>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLP<2>

TP_DP_IG_C_MLN<3>

TP_DP_IG_C_MLP<3>

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXP

TP_DP_IG_D_AUXN

TP_DP_IG_D_HPD

TP_DP_IG_D_MLN<0>

TP_DP_IG_D_MLP<0>

TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLN<2>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLP<3>

TP_PCH_LVDS_VBG

PCH_LVDS_IBG

DMI_S2N_P<1>

DMI_S2N_N<3>

DMI_S2N_P<0>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_N<0>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<3>

DMI_N2S_P<0>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_N<1>

DMI_N2S_N<0>

PCH_DMI_COMP

PM_SLP_S5_L

PCIE_WAKE_L

PM_SLP_S4_L

PM_SLP_S3_L

TP_PM_SLP_A_L

LPC_PWRDWN_L

PCH_SUSACK_L

FDI_FSYNC<1>

PM_CLKRUN_L

FDI_DATA_N<1>

FDI_DATA_N<2>

FDI_DATA_N<3>

FDI_DATA_N<4>

FDI_DATA_N<0>

FDI_DATA_N<5>

FDI_DATA_N<6>

FDI_DATA_N<7>

FDI_DATA_P<7>

FDI_INT

FDI_DATA_P<6>

FDI_DATA_P<5>

FDI_DATA_P<0>

FDI_DATA_P<4>

FDI_DATA_P<3>

FDI_DATA_P<2>

FDI_DATA_P<1>

PM_SYNC

FDI_LSYNC<1>

FDI_FSYNC<0>

PM_PWRBTN_L

PCH_SUSWARN_L

PM_RSMRST_L

PM_MEM_PWRGD

PM_PCH_APWROK

PCH_SUSACK_L

=PP3V3_SUS_PCH_GPIO

=PP1V05_S0_PCH_VCCIO_PCIE

=PPVRTC_G3_PCH

DMI_S2N_P<3>

DMI_S2N_P<2>

R19001

2

R19511

2

R19201

2

U1800

H20

L10

E10

N3

BC24

BE24

AW24

AY24

BE20

BC20

AW20

AY20

BH21

BG18

BJ18

BB18

AY18

BG20

BJ20

AV18

AU18

BG25

BJ24

E22

B13

A18

AV12

BC10

AW16

AV14

BB10

BJ14

AY14

BE14

BH13

BC12

BJ12

BG10

BG9

BG14

BB14

BF14

BG13

BE12

BG12

BJ10

BH9

AP14

E20

L22

A10

C21

G10

K14

F4

H4

D10

G16

G8

C12

N14

K16

P12

K3 B9

U1800

N48

T39

M40

P49

M47

T42

T49

M49

T43

AV42

AV40

AV45

AV46

AU48

AU47

AV47

AV49

AT49

AT47

AT40

AY47

AY49

AY43

AY45

BA47

BA48

BB47

BB49

AP47

AP49

P46

P42

AT38

BB43

BB45

BF44

BE44

BF42

BE42

BJ42

BG42

AT45

AT43

M43

M36

BH41

P45

J47

T45

P39

T40

K47

M45

AF37

AF36

AE48

AE47

AK40

AK39

AN47

AN48

AM49

AM47

AK49

AK47

AJ47

AJ48

AF39

AF40

AH43

AH45

AH49

AH47

AF47

AF49

AF43

AF45

P38

M39

AP39

AP40

AM42

AM40

AP43

AP45

R19151

2

R19051

2

R198612

R19091

2

R19501

2

R1923 2 1

R1925 1 2

R1991 1 2

R1985 1 2

R1922 2 1

R1921 2 1

R1924 2 1

R19831

2

R1982 1 2

R1984 2 1

R1981 2 1

051-9585

3.0.0

19 OF 132

17 OF 105

6 17 24 32

7 16 17 18 19

7 16 18 19 30

8 17

8 17

17 45 74

17 74

17 26 32 45 74

6 17 26 45 74

6 17 45 47

17

17 23 45

7

7 16 17 18 19

17

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

17

17

17

7 16 17 18 19

7

7 16 20

USB3RP4

USB3RP3

USB3RP2

USB3RP1

USB3RN1

RSVD8

RSVD9

RSVD10

RSVD12

USBP0N

USBP0P

USBP1N

USBP2N

USBP1P

USBP2P

USBP3N

USBP4N

USBP3P

USBP4P

USBP5N

USBP5P

USBP6P

USBP6N

USBP7N

USBP7P

USBP8P

USBP8N

USBP9N

USBP9P

USBP10P

USBP10N

USBP11N

USBP11P

USBP12P

USBP12N

USBP13N

USBP13P

OC0*/GPIO59

USBRBIAS*

USBRBIAS

OC1*/GPIO40

OC2*/GPIO41

OC3*/GPIO42

OC4*/GPIO43

OC5*/GPIO9

OC6*/GPIO10

OC7*/GPIO14

PIRQA*

PIRQB*

PIRQC*

REQ1*/GPIO50

PIRQD*

REQ3*/GPIO54

REQ2*/GPIO52

GNT1*/GPIO51

GNT2*/GPIO53

GNT3*/GPIO55

PIRQE*/GPIO2

PIRQF*/GPIO3

PIRQG*/GPIO4

PME*

PIRQH*/GPIO5

PLTRST*

CLKOUT_PCI0

CLKOUT_PCI2

CLKOUT_PCI1

CLKOUT_PCI4

CLKOUT_PCI3

RSVD1TP1

TP2 RSVD2

RSVD3TP3

TP4 RSVD4

RSVD5TP5

TP6RSVD6

RSVD7

TP7

TP8

TP9

TP10

RSVD11

TP11

RSVD13TP14

RSVD14

RSVD15

TP15

TP16

RSVD16

RSVD17

TP17

TP18

RSVD18

RSVD19

TP19

TP20

RSVD20

RSVD21

RSVD22

RSVD23

RSVD24

RSVD25

RSVD27

RSVD26

RSVD28

RSVD29

TP13

TP12

TP23

TP22

TP21

USB3RN4

USB3RN3

USB3RN2

USB3TN2

USB3TN1

USB3TN3

USB3TN4

USB3TP1

USB3TP2

USB3TP3

USB3TP4

TP24

PCI

USB

(5 OF 10)

NC

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

NCNC

NC

NC

NCNCNCNCNCNCNCNCNCNCNCNCNCNC

NCNC

NC

NCNCNC

NC

NCNC

NCNC

NCNC

NC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

BI

IN

BI

BI

BI

OUT

OUT

OUT

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Redundant to pull-up on audio page

Redundant to pull-up on audio page

Unused

USB Hub (All LS/FS Devices)

Ext C (XHCI/EHCI)

Camera

RSVD: SD

Ext D (EHCI)

RSVD: WiFi

Unused(IPD)

(IPD)

Ext B (XHCI)

Ext D (XHCI) (Mobiles: Trackpad?)

Ext B (EHCI)

Ext A (XHCI/EHCI)

(IPU-PCIERST#)

Unused

RSVD: BT (HS)

(IPU)

OMIT_TABLE

PANTHERPOINTMOBILE

FCBGA

25 95

25 95

8

8

25 95

25 95

8 95

8 95

25 95

25 95

25 95

25 95

6 42 95

6 42 95

6 42 95

6 42 95

6 43 95

6 43 95

6 43 95

6 43 95

8

8

8

8

8

8

8

8

1/20W

10KMF 2015%

1/20W5% 201MF

10K

2011/20W5% MF

10K

MF1/20W5% 201

10K

NO STUFF10K

MF 2015% 1/20W

1/20W MF

10K5% 201

10KMF5% 2011/20W

10KMF 2015% 1/20W

MF

10K2015% 1/20W

201

10KMF5% 1/20W

NO STUFF10K

MF 2015% 1/20W

5% 1/20W

10KMF 201

18 89

18

18

18

18 63

18 87

18 63

10KMF 2015% 1/20W10KMF 2015% 1/20W10KMF 2015% 1/20W10KMF 2015% 1/20W

1/20W5% 201MF

10KNO STUFF

1/20W5% 201MF

10K

18 23

18 23

18 23

18 23

18 23

23

23

42 95

23

42 95

32 95

32 95


22.6

MF201

1%1/20W

24 26

24

24 96

24

SYNC_DATE=06/02/2011SYNC_MASTER=J31_ANNE

PCH PCI/USB/TP/RSVD

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

PCH_USB_RBIAS

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_DB2_PCH_GPIO10_AP_PWR_EN

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

TBT_PWR_REQ_L

=PP3V3_S0_PCH_GPIO

LPC_CLK33M_LPCPLUS_R

TP_PCI_CLK33M_OUT3

TP_USB_13N

TP_USB_13P

USB_EXTB_EHCI_P

USB_CAMERA_N

USB_HUB_UP_P

USB_HUB_UP_N

USB_EXTB_XHCI_N

USB_EXTA_P

USB_EXTA_N

=PP3V3_S3_PCH_GPIO

=PP3V3_S0_PCH_GPIO

AUD_I2C_INT_L


XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L



=PP3V3_SUS_PCH_GPIO

AP_PWR_EN

USB3_EXTD_RX_P

TP_PCI_PME_L

TP_USB_BT_HSP

AUD_I2C_INT_L

AUD_IP_PERIPHERAL_DET

BLC_GPIO

PCH_STRP_TOPBLK_SWP_L

USB_EXTC_N

USB3_EXTA_TX_P

USB3_EXTD_TX_N

USB3_EXTB_RX_P

USB3_EXTC_RX_P

USB3_EXTA_RX_N

PCI_INTD_L

PCI_INTC_L

PCI_INTB_L

PCI_INTA_L

USE_HDD_OOB_L

BLC_I2C_MUX_SEL

JTAG_GMUX_TMS

USB3_EXTC_TX_P

USB3_EXTD_TX_P

USB3_EXTC_TX_N

USB3_EXTB_TX_N

USB3_EXTA_RX_P

USB3_EXTD_RX_N

USB3_EXTC_RX_N

USB3_EXTB_RX_N

TP_PCH_TP23

TP_PCH_STRP_BBS1 TP_USB_12N

TP_USB_12P

TP_USB_BT_HSN

USB_EXTD_EHCI_N

USB_EXTD_EHCI_P

USB_EXTB_EHCI_N

USB_CAMERA_P

TP_USB_WLANN

TP_USB_WLANP

TP_USB_SDP

TP_USB_SDN

TP_USB_4P

TP_USB_4N

USB_EXTB_XHCI_P

PLT_RESET_L

TP_PCH_STRP_ESI_L

BLC_I2C_MUX_SEL

JTAG_GMUX_TMS

USB_EXTD_XHCI_P

USB_EXTD_XHCI_N

USB_EXTC_P

USB3_EXTB_TX_P

USE_HDD_OOB_L

BLC_GPIO


TBT_PWR_REQ_L

LPC_CLK33M_SMC_R

TP_PCI_CLK33M_OUT2

PCH_CLK33M_PCIOUT

USB3_EXTA_TX_N



R20701

2

U1800

H49

H43

J48

K42

H40

D47

E42

F46

A14

K20

B17

C16

L16

A16

D14

C14

K40

K38

H38

G38

G42

G40

C42

D44

C6

K10

C46

C44

E40

AY7

AT1

AY3

AT5

AV3

AV1

BB1

BA3

BB5

BB3

BB7

AV7

BE8

BD4

BF6

AV5

AV10

AT8

AY5

BA2

AT12

BF3

AU3

BG4

AT10

BC8

AU2

AT4

AT3

BG26

C18

N30

H3

AH12

AM4

AM5

Y13

K24

L24

AB46

BJ26

AB45

B21

M20

AY16

BG46

BH25

BJ16

BG16

AH38

AH37

AK43

AK45

BE28

BC30

BE32

BJ32

BC28

BE30

BF32

BG32

AV26

BB26

AU28

AY30

AU26

AY26

AV28

AW30

C24

A24

C30

A30

L32

K32

G32

E32

C32

A32

C25

B25

C26

A26

K28

H28

E28

D28

C28

A28

C29

B29

N28

M28

L30

K30

G30

E30

B33

C33

R2067 2 1

R2068 1 2

R2061 1 2

R2062 1 2

R2033 1 2

R2060 1 2

R2030 1 2

R2018 1 2

R2016 1 2

R2017 1 2

R2014 1 2

R2031 1 2

R2010 1 2

R2011 1 2

R2012 1 2

R2013 1 2

R2054 2 1

R2069 1 2

051-9585

3.0.0

20 OF 132

18 OF 105

95

7 16 17 18 19 30

6 7 24

7 16 17 18 19 30

18 63

18 23

18 23

18 23

18 23

7 16 17 19

23 32 74

6

18

18 89

18

18

18 63

18 87

24

18 23

OUT

OUT

BI

IN

NC

IN

OUT

OUT

OUT

IN

BI

ININ

OUT

OUT

IN

OUT

SATA2GP/GPIO36

SATA3GP/GPIO37

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_29

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_24

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_19

VSS_NCTF_21

VSS_NCTF_20

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_14

NC_1

TS_VSS4

TS_VSS3

TS_VSS1

TS_VSS2

DF_TVS

INIT3_3V*

THRMTRIP*

PROCPWRGD

RCIN*

PECI

A20GATE

TACH7/GPIO71

TACH6/GPIO70

TACH5/GPIO69

TACH4/GPIO68

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_9

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_4

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_0

VSS_NCTF_1

SATA5GP/GPIO49/TEMP_ALERT*

SLOAD/GPIO38

GPIO27

GPIO24

GPIO57

SDATAOUT1/GPIO48

BMBUSY*/GPIO0

TACH1/GPIO1

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

SATA4GP/GPIO16

TACH2/GPIO6

SDATAOUT0/GPIO39

GPIO35

SCLOCK/GPIO22

TACH0/GPIO17

GPIO8

TACH3/GPIO7

GPIO28

STP_PCI*/GPIO34

GPIO

CPU/MISC

(6 OF 10)

NCTF

OUT

OUT

OUT

BI

IN

OUT

TABLE_BOMGROUP_ITEM


Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Systems with chip-down memory should add pull-downs on another page and set straps per software.

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

(IPU-RSMRST#)

DF_TVS:DMI & FDI Term Voltage

Set to Vss when Low

Set to Vcc when High

(IPD)

(IPU)

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

This has internal pull up and should not pulled low.

(IPD-PLTRST#?)

(IPU)

(IPD-PLTRST#)

(IPU-RSMRST#)

(IPU-DeepS4/S5)

(IPD-PLTRST#)

(PU necessary?)

Must stuff R2197 when R2180 NO STUFFed.

10 23 93

23

6 19 47

8 19

NO STUFF

1K

MF201

5%1/20W

8 19 39

23

19 41

23

8 19 89

6 19 47 56

10 46 93

RAMCFG3:H

10K

MF201

5%1/20W

RAMCFG2:H

10K

MF201

5%1/20W

10K

MF201

5%1/20W

RAMCFG1:H RAMCFG0:H

10K

MF201

5%1/20W

19 46

23

8 89

19 45

19 24

OMIT_TABLE

PANTHERPOINTMOBILE

FCBGA

1K

MF201

5%1/20W

2.2K

MF201

5%1/20W

20KMF 2015% 1/20W100KMF 2015% 1/20W

10KMF 2015% 1/20W

10KMF 2015% 1/20W100KMF 2015% 1/20W

10KMF 2015% 1/20W

10KMF5% 1/20W 201

10KMF 2015% 1/20W

NO STUFF

100KMF 2011/20W5%

10KMF 2015% 1/20W

10KMF 2015% 1/20W

10KMF 2015% 1/20W

10KMF 2011/20W5%

10KMF 2015% 1/20W

23

0

MF 2015% 1/20W

35

19 23

10KMF 2015% 1/20W10KMF 2015% 1/20W

10KMF 2015% 1/20W

1/20W5% 201MF

10K

10KMF 2015% 1/20W10KMF 2015% 1/20W

NO STUFF43

MF 2015% 1/20W

0

MF 2015% 1/20W

390

MF 2015% 1/20W

10 46 93

23 68

19 74

10KMF 2015% 1/20W

NO STUFF

PCH GPIO/MISC/NCTFSYNC_MASTER=J31_ANNE SYNC_DATE=06/02/2011

RAMCFG_SLOT RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

SPIROM_USE_MLB

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

FW_PWR_EN_PCH

JTAG_ISP_TDO

XDP_FC1_PCH_GPIO0

JTAG_ISP_TDO

ENET_LOW_PWR_PCH

=PP3V3_S5_PCH_GPIO

LPCPLUS_GPIO

TBT_SW_RESET_R_L

=PP3V3_T29_PCH_GPIO

FW_PME_L

JTAG_ISP_TCK

PCH_A20GATE

TBT_SW_RESET_L

SMC_SCI_L

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DC1_PCH_GPIO35_MXM_GOOD

SPIROM_USE_MLB

JTAG_ISP_TDI

TBT_SW_RESET_R_L

XDP_FC0_PCH_GPIO15PCH_A20GATE

PCH_RCIN_L

PM_THRMTRIP_L_R

PCH_DF_TVS

PCH_INIT3V3_L

CPU_PWRGD

PM_THRMTRIP_L

MLB_RAMCFG3

MLB_RAMCFG0

CPU_PROC_SEL_L


JTAG_TBT_TDI

SMC_RUNTIME_SCI_L

PCH_RCIN_L

WOL_EN

SPIROM_USE_MLB

DPMUX_UC_IRQ

ODD_PWR_EN_L

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

DPMUX_UC_IRQ

XDP_FC1_PCH_GPIO0

=PP3V3_SUS_PCH_GPIO


=PP3V3_S0_PCH_GPIO

MLB_RAMCFG2

MLB_RAMCFG1

CPU_PECI

PCH_PROCPWRGD

PCH_PECI

ODD_PWR_EN_L

LPCPLUS_GPIO

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

SMC_RUNTIME_SCI_L

SMC_SCI_L


PCH_GPIO24

WOL_EN

TP_PCH_GPIO8

FW_PME_L

PCH_GPIO24

FW_PWR_EN_PCH

=PP3V3_S0_PCH_GPIO

R21301

2

R21721

2

R21731

2

R21741

2

R21751

2

U1800

P4

T7

AY1

G2

E8

E16

P8

K4

D6

C10

T14

C4

P37

AU16

AY11

P5

V8

M5

U2

V3

T5

M3

V13

N2

K1

D40

A42

H36

E38

C40

B41

C41

A40

AY10

AH8

AK11

AH10

AK10

A4

BD49

BE1

BE49

BF1

BF49

BG2

BG48

BH3

BH47

BJ4

A44 BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

A45

E49

F1

F49

A46

A5

A6

B3

B47

BD1

R217812

R21791

2

R2111 2 1

R2195 2 1

R2191 1 2

R2192 1 2

R2193 1 2

R2194 1 2

R2184 1 2

R2197 1 2

R2190 1 2

R2196 1 2

R2185 1 2

R2160 1 2

R2186 1 2

R2112 2 1

R2180 1 2

R2198 2 1

R2113 2 1

R2199 1 2

R2116 2 1

R2150 1 2

R2155 1 2

R2170 1 2

R2140 1 2

R2156 1 2

R2181 2 1

051-9585

3.0.0

21 OF 132

19 OF 105

6 19 47 56 19 23

8 19 89

23 24

7

6 19 47

19

7 16

8 19 39

8 23

19

19 46

19

19

19

46

10 93

7 20 22

8 33

19 45

19

19 74

6 19 47 56

8 19

19 41

19 23

19 23

7 16 17 18

23 24

7 16 17 18 19 30

19

19

19 24

7 16 17 18 19 30

NC

NC

NC

NC

NCNC

NC

VCCTX_LVDS

VCCTX_LVDS

VCCTX_LVDS

VCCTX_LVDS

VSSALVDS

VCCALVDS

VCC3_3_7_HVCMOS

VCC3_3_6_HVCMOS

VCCCORE

VCCCORE

VSSADAC

VCCADAC

VCCDMI_2_FDI

VCCIO_27_PLLFDI

VCCAFDIPLL

VCCVRM_2_FDI

VCCIO_26_DP

VCC3_3_3_PCIE

VCCIO_24_PCIE

VCCIO_25_DP

VCCIO_21_PCIE

VCCIO_22_PCIE

VCCIO_23_PCIE

VCCIO_19_PCIE

VCCIO_20_PCIE

VCCIO_18_PCIE

VCCIO_17_PCIE

VCCIO_16_FDI

VCCIO_15_FDI

VCCAPLLEXP

VCCIO_28_PLLPCIE

VCCSPI

VCCDFTERM

VCCDFTERM

VCCDFTERM

VCCDFTERM

VCCCORE

VCCCORE

VCCCORE

VCCCORE

VCCCORE

VCCCORE

VCCCORE

VCCCORE

VCCCORE

VCCCORE

VCCCORE

VCCCORE

VCCCORE

VCCCORE

VCCCORE

VCCVRM_3_DMI

VCCDMI_1_DMI

VCCCLKDMI

DMI

CRT

VCCIO

FDI

DFT/SPI

VCC CORE

(7 OF 10)

HVCMOS

LVDS

NC

VCCIO_34_PLLUSB

VCCRTC

V_PROC_IO

DCPSUSBYP

VCCACLK

DCPRTC

VCCADPLLA

VCCADPLLB

DCPSST

DCPSUS_2_CLK

DCPSUS_1_CLK

VCCDIFFCLKN

VCCDIFFCLKN

VCCDIFFCLKN

VCCDSW3_3

VCCIO_7_CLK

VCC3_3_5_CLK

VCCASW_2_CLK

VCCASW_3_CLK

VCCASW_4_CLK

VCCASW_5_CLK

VCCASW_6_CLK

VCCAPLLDMI2

VCCASW_18_CLK

VCCASW_8_CLK

VCCASW_9_CLK

VCCASW_10_CLK

VCCASW_11_CLK

VCCASW_12_CLK

VCCASW_13_CLK

VCCASW_14_CLK

VCCASW_15_CLK

VCCASW_16_CLK

VCCASW_17_CLK

VCCASW_7_CLK

VCCVRM_4_CLK

VCCASW_20_CLK

VCCASW_19_CLK

VCCSSC

VCCASW_1_CLK

DCPSUS_3_CLK

VCCIO_14_PLLCLK

VCCIO_30_USB

VCCIO_29_USB

VCCIO_31_USB

VCCIO_32_USB

VCCIO_33_USB

VCCSUS3_3_7_USB

VCCSUS3_3_8_USB

VCCSUS3_3_6_USB

VCCSUS3_3_10_USB

VCCSUS3_3_9_USB

DCPSUS_4_USB

V5REF_SUS

VCCSUS3_3_1_USB

VCC3_3_2_SATA

VCCIO_5_PLLSATA

VCCIO_13_SATA3

VCCIO_12_SATA3

VCCAPLLSATA

VCCIO_6_PLLSATA3

VCCIO_2_SATA

VCCVRM_1_SATA

VCCIO_4_SATA

VCCIO_3_SATA

VCCASW_22_MISC

VCCASW_23_MISC

VCCASW_21_MISC

V5REF

VCCSUS3_3_2_GPIO

VCCSUS3_3_4_GPIO

VCCSUS3_3_3_GPIO

VCCSUS3_3_5_GPIO

VCC3_3_1_GPIO

VCC3_3_8_GPIO

VCC3_3_4_GPIO

VCCSUSHDA

USB

SATA

MISC

HDA

PCI/GPIO/

LPC

CPU

RTC

CLK/MISC

(8 OF 10)

Apple Inc.


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DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



PCH output, for decoupling only

10 mA Max, 1mA Idle

NC-ed per DG

AL24 left as NC per DG

55mA Max, 5mA Idle

NC-ed per DG

VCCACLK pin left as NC per DG

VCCAPLLDMI2 pin left as NC per DG

1.44 A Max, 474mA Idle

VCCAFDIPLL pin left as NC per DG

VCCAPLLSATA pin left as NC per DG


0.1UF

CERM402

20%10V


1UF

CERM402

10%6.3V

PLACE_NEAR=U1800.V16:2.54mm0.1UF

CERM402

20%10V

PLACE_NEAR=U1800.N16:2.54mm

0.1UF

CERM402

20%10V


0.1UF

CERM402

20%10V

OMIT_TABLE

PANTHERPOINTMOBILE

FCBGA

OMIT_TABLE

PANTHERPOINTMOBILE

FCBGA


PCH POWER





PP3V3_S0_PCH_VCC3_3_CLK_F




=PP5V_S0_PCH_V5REF






=PP5V_SUS_PCH_V5REFSUS










PPVOUT_S0_PCH_DCPSST

VOLTAGE=3.3V


PP1V05_S0_PCH_VCCADPLLB_F

PP1V05_S0_PCH_VCCADPLLA_F

PPVOUT_G3_PCH_DCPRTC

VOLTAGE=3.3V


TP_PPVOUT_PCH_DCPSUSBYP

=PPVRTC_G3_PCH

=PP1V05_S0_PCH_VCCIO_PLLUSB

PP1V05_S0_PCH_VCCCLKDMI_F




=PP1V05_S0_PCH_VCCIO_PLLPCIE

TP_1V05_S0_PCH_VCCAPLLEXP




=PP1V05_S0_PCH_VCCIO_PLLFDI

=PP1V05_S0_PCH_VCCDMI_FDI

PP3V3_S0_PCH_VCCA_DAC_F


=PP3V3_S0_PCH_VCCA_LVDS

PP1V8_S0_PCH_VCCTX_LVDS_F

C22321

2

C2231 1

2

C2222 1

2

C2210 1

2

C22331

2

U1800

BH29

V33

V34

U48

BG6

AK36

BJ22

AB36

AA23

AG26

AG27

AG29

AJ23

AJ26

AJ27

AJ29

AJ31

AC23

AD21

AD23

AF21

AF23

AG21

AG23

AG24

AG16

AG17

AJ16

AJ17

AT20

AU20

AN16

AN17

AN21

AN26

AN27

AP21

AP23

AP24

AP26

AT24

AN33

AN34

AP17

AN19

V1

AM37

AM38

AP36

AP37

AP16

AT16

U47

AK37

U1800

N16

V16

T17

V19

AL24

AN23

V12

P34

M26

BJ8

AA16

AJ2

T34

T38

W16

AD49

BD47

BF47

BH23

AK1

AA19

AC29

AC31

AD29

AD31

W21

W23

W24

W26

W29

W31

AA21

W33

T19

T21

V21

AA24

AA26

AA27

AA29

AA31

AC26

AC27

AF33

AF34

AG34

T16

AH13

AH14

AL29

AC16

N26

AC17

P26

P28

T27

T29

T26

AD17

AF13

AF14

AF17

A22

AG33

AN24

V24

N20

N22

P20

P22

P24

T23

T24

V23

P32

AF11

Y49

051-9585

3.0.0

22 OF 132

20 OF 105

7 16 20 22

7 22

7 22

7 22

22

7 22 24

7 22

7 22

22

7 20 22

7 20

7 16 20 22

7 22

7 22

22

7 22

7 22

7 20 22

7 22

7 20

7 20 22

7 20 22

7 22

7 16 22

22

22

7 16 17

7

22

7 22

7 20

7 19 22

7

6

7 22

7 22

7 20

7

7

22

7 22

7

22

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

(9 OF 10)

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

(10 OF 10)VSS

Apple Inc.


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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



FCBGA

MOBILE

PANTHERPOINT

OMIT_TABLE

FCBGA

MOBILE

PANTHERPOINT

OMIT_TABLE

PCH GROUNDSSYNC_DATE=03/21/2011SYNC_MASTER=J5_MLB

U1800H5

AA17

AB43

AM39

AM43

AM45

AM46

AM7

AN2

AN29

AN3

AN31

AP12

AB5

AP19

AP28

AP30

AP32

AP38

AP4

AP42

AP46

AP8

AR2

AB7

AR48

AT11

AT13

AT18

AT22

AT26

AT28

AT30

AT32

AT34

AC19

AT39

AT42

AT46

AT7

AU24

AU30

AV16

AV20

AV24

AV30

AC2

AV38

AV4

AV43

AV8

AW14

AW18

AW2

AW22

AW26

AW28

AC21

AW32

AW34

AW36

AW40

AW48

AV11

AY12

AY22

AY28

AC24

AC33

AC34

AC48

AA2

AD10

AD11

AD12

AD13

AD19

AD24

AD26

AD27

AD33

AD34

AA3

AD36

AD37

AD38

AD39

AD4

AD40

AD42

AD43

AD45

AD46

AA33

AD8

AE2

AE3

AF10

AF12

AD14

AD16

AF16

AF19

AF24

AA34

AF26

AF27

AF29

AF31

AF38

AF4

AF42

AF46

AF5

AF7

AB11

AF8

AG19

AG2

AG31

AG48

AH11

AH3

AH36

AH39

AH40

AB14

AH42

AH46

AH7

AJ19

AJ21

AJ24

AJ33

AJ34

AK12

AK3

AB39

AK38

AK4

AK42

AK46

AK8

AL16

AL17

AL19

AL2

AL21AB4

AL23

AL26

AL27

AL31

AL33

AL34

AL48

AM11

AM14

AM36

U1800AY4

AY42

AY46

AY8

B11

B15

B19

B23

B27

B31

B35

B39

B7

F45

BB12

BB16

BB20

BB22

BB24

BB28

BB30

BB38

BB4

BB46

BC14

BC18

BC2

BC22

BC26

BC32

BC34

BC36

BC40

BC42

BC48

BD46

BD5

BE22

BE26

BE40

BF10

BF12

BF16

BF20

BF22

BF24

BF26

BF28

BD3

BF30

BF38

BF40

BF8

BG17

BG21

BG33

BG44

BG8

BH11

BH15

BH17

BH19

H10

BH27

BH31

BH33

BH35

BH39

BH43

BH7

D3

D12

D16

D18

D22

D24

D26

D30

D32

D34

D38

D42

D8

E18

E26

G18

G20

G26

G28

G36

G48

H12

H18

H22

H24

H26

H30

H32

H34

F3

H46

K18

K26

K39

K46

K7

L18

L2

L20

L26

L28

L36

L48

M12

P16

M18

M22

M24

M30

M32

M34

M38

M4

M42

M46

M8

N18

P30

N47

P11

P18

T33

P40

P43

P47

P7

R2

R48

T12

T31

T37

T4

W34

T46

T47

T8

V11

V17

V26

V27

V29

V31

V36

V39

V43

V7

W17

W19

W2

W27

W48

Y12

Y38

Y4

Y42

Y46

Y8

BG29

N24

AJ3

AD47

B43

BE10

BG41

G14

H16

T36

BG22

BG24

C22

AP13

M14

AP3

AP1

BE16

BC16

BG28

BJ28

051-9585

3.0.0

23 OF 132

21 OF 105

NC

NC

NC NC

Apple Inc.


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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



PCH VCCSUSHDA BYPASS

(PCH DPLLB PWR)PCH VCCADPLLB Filter

(PCH Reference for 5V Tolerance on USB)

PCH VCCADPLLA Filter(PCH DPLLA PWR)

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

(PCH PCI 3.3V PWR)PCH VCC3_3 BYPASS

PCH VCCIO BYPASS

PCH VCCSUS3_3 BYPASS(PCH SUSPEND USB 3.3V PWR)

(PCH USB 1.05V PWR)PCH VCCIO BYPASS

(PCH 1.05V CORE PWR)PCH VCCCORE BYPASS

PCH V5REF Filter & Follower(PCH Reference for 5V Tolerance on PCI)1 mA

<1 mA<1 mA S0-S5

1 mA S0-S5PCH V5REF_SUS Filter & Follower

68 mA

69 mA



10V10%

402X5R

1UF

PLACE_NEAR=U1800.P34:2.54mm

1/16W5%

402MF-LF

100

PLACE_NEAR=U1800.M26:2.54mm

10V20%

402CERM

0.1UF

SOT-363BAT54DW-X-G

1/16W5%

402MF-LF

10

SOT-363BAT54DW-X-G

PLACE_NEAR=U1800.AJ2:2.54mm

16V10%

402X5R

0.1UF

10V20%

402CERM

0.1UF



10V20%

402CERM

0.1UF

6.3V10%

402CERM

1UF

PLACE_NEAR=U1800.AT20:2.54mm

16V10%

402X5R

0.1UF

PLACE_NEAR=U1800.BH29:2.54mm

16V10%

402X5R

0.1UF

PLACE_NEAR=U1800.V24:2.54mm

16V10%

402X5R

0.1UF


6.3V20%

402X5R

4.7UF


16V10%

402X5R

0.1UF


25V10%

402X5R

0.1UF

PLACE_NEAR=U1800.AA16:2.54mm

6.3V10%

402CERM

1UF

PLACE_NEAR=U1800.AN27:2.54mm

6.3V10%

402CERM

1UF

PLACE_NEAR=U1800.AG33:2.54mm

6.3V10%

402CERM

1UF


6.3V10%

402CERM

1UF


6.3V10%

402CERM

1UF


6.3V20%

603X5R

10UF


6.3V10%

402CERM

1UF

PLACE_NEAR=U1800.AC17:2.54mm

10V20%

402CERM

0.1UF


6.3V10%

402CERM

1UF


25V10%

402X5R

0.1UF


6.3V10%

402CERM

1UF

PLACE_NEAR=U1800.AH13:2.54mm

6.3V10%

402CERM

1UF


16V10%

402X5R

0.1UF


6.3V20%

603X5R

10UF


6.3V10%

402CERM

1UF


6.3V10%

402CERM

1UF

PLACE_NEAR=U1800.AD21:2.54mm

6.3V10%

402CERM

1UF


6.3V10%

402CERM

1UF


6.3V10%

402CERM

1UF


X5R-CERM-1


22UF

603

20%6.3V 6.3V

10%

402CERM

1UF


6.3V10%

402CERM

1UF


6.3V10%

402CERM

1UF


MF-LF402

5%1/16W

0

6.3V20%

603X5R

10UF


16V10%

402X5R

0.1UF


6.3V20%

603

22UF


X5R-CERM-1

CERM

PLACE_NEAR=U1800.AM37:2.54mm

16V10%

402

0.01UF

X5R-CERM-1


CRITICAL

22UF

603

20%6.3V

CERM


16V10%

402

0.01UF

0805

0.1UH

CRITICAL

1/20W5%

201MF

0

10%

402CERM

0.01UF

PLACE_NEAR=U1800.U48:2.54mm

16V16V10%

402X5R

0.1UF


6.3V20%

603X5R

10UF

CRITICAL


1/16W5%

402MF-LF

1

6.3V20%

603X5R

10UF

CRITICAL


10V10%

402X5R

1UF


0603

10UH-0.12A-0.36OHM

CRITICAL

6.3V10%

402CERM

1UF


2.5V20%

B16TANT

220UF

CRITICAL

PLACE_NEAR=U1800.BD47:2.54MM

402

10%

NO STUFF

6.3VCERM

1UF

PLACE_NEAR=U1800.BD47:2.54MM

CERM6.3V10%1UF

NO STUFF

402

PLACE_NEAR=U1800.BF47:2.54MM

2.5V20%

B16TANT

220UF

CRITICAL

PLACE_NEAR=U1800.BF47:2.54MM

0603

10UH-0.12A-0.36OHM

CRITICAL

0603

10UH-0.12A-0.36OHM

CRITICAL

MF-LF402

0

1/16W5%

1/16W5%

402MF-LF

0

1098AS-SM

10UH-0.58A-0.35OHM

CRITICALSYNC_DATE=05/26/2011

PCH DECOUPLINGSYNC_MASTER=J5_MLB

=PP1V05_S0_PCH_VCCADPLL


VOLTAGE=1.05VMIN_NECK_WIDTH=0.25 MM

PP1V05_S0_PCH_VCCCLKDMI_R


VOLTAGE=3.3V

PP3V3_S0_PCH_VCCA_DAC_F


=PP5V_SUS_PCH_V5REFSUS

=PP3V3_S0_PCH

=PP5V_S0_PCH

=PP1V8_S0_PCH_VCCTX_LVDS

=PP3V3_S0_PCH_VCCADAC

=PP3V3_S0_PCH_VCC3_3_CLK

=PP1V05_S0_PCH




















=PP5V_S0_PCH_V5REF

=PP5V_SUS_PCH



PP5V_SUS_PCH_V5REFSUS



PP5V_S0_PCH_V5REF


VOLTAGE=3.3V

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MMPP1V05_S0_PCH_VCCADPLLA_R



PP1V05_S0_PCH_VCCADPLLB_R

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP1V05_S0_PCH_VCCADPLLA_F

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP1V05_S0_PCH_VCCADPLLB_F


VOLTAGE=1.05V

PP1V05_S0_PCH_VCCCLKDMI_F


VOLTAGE=1.8V

PP1V8_S0_PCH_VCCTX_LVDS_F


PP3V3_S0_PCH_VCC3_3_CLK_FMIN_LINE_WIDTH=0.5 MM


C2439 1

2

R24052

1

C2438 1

2

D24001

6

R24042

1

D24004

3

C2423 1

2

C2440 1

2

C2441 1

2

C2419 1

2

C2421 1

2

C24131

2

C24171

2

C2416 1

2

C24841

2

C24851

2

C24631

2

C2475 1

2

C2434 1

2

C2469 1

2

C24141

2

C2401 1

2

C2452 1

2

C2499 1

2

C2442 1

2

C24861

2

C2444 1

2

C2446 1

2

C2424 1

2

C2460 1

2

C24821

2

C24811

2

C24831

2

C24071

2

C24291

2

C2420 1

2

C24961

2

C24561

2

C24261

2

R24151 2

C2411 1

2

C24301

2

C2428 1

2

C24061

2

C2400 1

2

C24081

2

L2407

1 2

R24501 2

C24551

2

C24511

2

C2450 1

2

R24511 2

C2453 1

2

C24541

2

L2451

1 2

C2476 1

2

C2491 1

2

C24921

2

C24941

2

C2493 1

2

L2490

1 2

L2491

1 2

R24901 2

R24911 2

L2406

1 2

051-9585

3.0.0

24 OF 132

22 OF 105

52

7

20

7 20

20

7 16

7 24

7

7

7

7 16

7 20

7 20

7 20

7 20

7 20

7 20

7 16 20

7 20

7 16 20

7 20

7 20 24

7 19 20

7 20

7 20

7 20

7 20

7 20

7 20

7 20

20

7

20

20

20

20

20

7 20

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

OUT

OUT

NC

IN

OUT

IN

BI

IN

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

NC

IN

IN

OUT

OUT

OUTOUT

BI

IN

IN

IN

IN

IN

BI

IN

OUT

IN

IN

IN

IN

IN

Apple Inc.


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REVISION

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6 3



support chipset debug.

NOTE: This is not the standard XDP pinout.

XDP_PRESENT#

doc id 404081.

- ’Output’ non-XDP signals require pulls.

Initially, stuffing both 33 and 0 ohms and validate whether

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3

R252x, R253x, R257x and R259x should be placed where signal path

and path to non-XDP signal destination.needs to split between route from PCH to J2550

PCH/XDP Signal Isolation Notes:

- ’Output’ PCH/XDP signals require pulls.

OBSFN_A1

OBSDATA_A0

OBSFN_A0

OBSDATA_C1it is functional in that state, else add BOM options.

998-2516

TCK0

OBSDATA_A1

(R2520-R2537)XDP SIGNALS

(R2564-R2567)

OBSDATA_B2

OBSDATA_D1

OBSDATA_D2

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

OBSDATA_D3

VCC_OBS_CD

DBR#/HOOK7

OBSDATA_D0

ITPCLK/HOOK4ITPCLK#/HOOK5

RESET#/HOOK6

PCH SIGNALS

RESET#/HOOK6

OBSFN_B0

OBSDATA_A2

VCC_OBS_ABHOOK2

PWRGD/HOOK0

OBSDATA_B2

OBSFN_B1

VCC_OBS_CD

OBSDATA_B3

OBSDATA_B1

OBSDATA_A3

OBSDATA_B0

- For isolated GPIOs:

PCH Micro2-XDP

VCC_OBS_ABHOOK2HOOK3

SDASCL

TCK1

(R2560-R2563)

OBSFN_C0

OBSDATA_C0

OBSDATA_B1

OBSFN_C1

OBSFN_B1

OBSDATA_B0

support chipset debug.

TRSTnTDI

TDO

OBSDATA_A3OBSDATA_A2

OBSDATA_A1

OBSFN_A1OBSFN_A0

OBSFN_D0OBSFN_D1

OBSDATA_C1

OBSDATA_C2OBSDATA_C3

OBSDATA_C2

OBSFN_D0

ITPCLK/HOOK4

HOOK3

SDA

HOOK1

TDITMS

TDOTRSTn

DBR#/HOOK7

ITPCLK#/HOOK5

OBSFN_D1

OBSFN_C1

OBSDATA_C3

OBSDATA_C0

OBSDATA_D2

OBSDATA_D0OBSDATA_D1

1K series R on PCH Support Page

XDP_PRESENT#

TMSTCK0

OBSDATA_A0

OBSDATA_D3

HOOK1

TCK1SCL

Non-XDP Signals

PWRGD/HOOK0

Use with 921-0133 Adapter Flex toNOTE: This is not the standard XDP pinout.

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

OBSFN_C0

PCH SIGNALS

CPU Micro2-XDP

OBSFN_B0

OBSDATA_B3

Use with 921-0133 Adapter Flex to

998-2516

9 93

10 24

10 93

10 93

10 93

10 93

10 93

9 23 93

9 93

9 93

24

16 23

16 23

16 23

9 93

16 23

9 93

23 48

23 48

10 23 24 93

16V10%

402X5R

0.1uF

XDP

16V10%

402X5R

XDP

0.1uF

17 23 45

17 45 92

10 23 93

10 23 24 93

9 93

10 23 93

16 93

16 93

10 23 93

10 23 93

1/16W5%

402MF-LF

1K

NO STUFF

1/20W5% 201MF

0XDP PLACE_NEAR=R1841.1:2.54mm

1/20W5% 201MF

0XDP PLACE_NEAR=R1840.1:2.54mm

1/20W5% 201MF

1KXDP PLACE_NEAR=U1000.G3:2.54mm

1/20W5% 201MF

51XDP PLACE_NEAR=J2550.52:2.54mm

1/20W5% 201MF

51XDP PLACE_NEAR=U1800.K5:2.54mm

1/20W5% 201MF

51XDP PLACE_NEAR=U1800.H7:2.54mm

1/20W5% 201MF

51XDP PLACE_NEAR=U1800.J3:2.54mm

1/20W5% 201MF

51XDP PLACE_NEAR=J2500.52:2.54mm

1/20W5% 201MF

51XDP PLACE_NEAR=U1000.K61:2.54mm

1/20W5% 201MF


1/20W5% 201MF

51XDP PLACE_NEAR=U1000.J58:2.54mm

1/20W5% 201MF


1/20W5% 201MF

330XDP

1/20W5% 201MF

1KXDP


1/20W5% 201MF

0XDP


1/20W5% 201MF

1KXDP

PLACE_NEAR=U1000.C60:2.54mm

1/20W5% 201MF

0XDP_CPU:BPM

10 93

1/20W5% 201MF

0

XDP_CPU:BPM

1/20W5% 201MF

0

XDP_CPU:BPM

1/20W5% 201MF

0

XDP_CPU:BPM

1/20W5% 201MF

0

XDP_CPU:CFG

1/20W5% 201MF

0

XDP_CPU:CFG

1/20W5% 201MF

0XDP_CPU:CFG

1/20W5% 201MF

0

XDP_CPU:CFG

9 93

9 93

9 93

9 93

MF 2011/20W5%

33

XDP

201MF1/20W5%

33

XDP

1/20W5% 201MF

33

XDP

1/20W5% 201MF

33

XDP

2015% MF

33

XDP

1/20W

1/20W5% MF

33

XDP

201

MF1/20W5% 201

33

XDP

MF1/20W5%

33

XDP

201

1/20W5% MF

33

XDP

201

1/20W5% 201MF

33

XDP

1/20W5% 201MF

33

XDP

19 23

19 23

19 23

19

9 23 93

16 23

16 23

19

19 23

18 23

18 23

18 23

18

18 23

18 23

PLACE_NEAR=J2550.39:2.54mm 1/20W5% 201MF

1KXDP

PLACE_NEAR=U4900.P17:2.54mm 1/20W5% 201MF

0XDP

45 74 89 92

17 23 45

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

M-ST-SM

M-ST-SMDF40RC-60DP-0.4V

CRITICAL

1/20W5% 201MF

33

XDP

24

26

16 87

19 24

1/20W5% 201MF

0 1/20W5% 201MF

0

1/20W5% 201MF

01/20W5% 201MF

0

1/20W5% 201MF

0

19 24 1/20W5% 201MF

0

18 23

19 23

16V10%

402

XDP

19 23

19 23

1/20W5% 201MF

33

XDP

5% 201MF

33

XDP

1/20W

1/20W5% 201MF

33

XDP

2011/20W5% MF

33

XDP

2011/20W5%

33

XDP

MF

MF1/20W5%

33

XDP

201

19 68

19

18 23

18 23

1/20W5% 201MF

0

1/20W5% 201MF

0

9 93

16 23

16 23

16 41

1/20W5% 201MF

0 1/20W5% 201MF

0

18 23

18 23

42

42

18 32 74

18 23

8 19 19 23

1/20W5% 201MF

1K

1KMF 2015% 1/20W

16V10%

402X5R

0.1uF

XDP

10 93

10 93

9 93

9 93

9 93

9 93

23 48

23 48

10 23 93

9 93

10 19 93

9 93

10 93

10 93

SYNC_MASTER=J31_ANNE SYNC_DATE=06/09/2011

CPU & PCH XDP

TP_XDPPCH_HOOK2

XDP_BPM_L<1>

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L




XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL





XDP_FC1_PCH_GPIO0


XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L


XDP_DD1_JTAG_ISP_TCK

XDP_DA1_USB_EXTB_OC_L

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

=SMBUS_XDP_SDA

=PP3V3_S5_XDP

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

TP_XDP_PCH_OBSFN_A<0>

XDP_DA0_USB_EXTA_OC_L XDP_DC0_ISOLATE_CPU_MEM_L

XDP_DC1_MXM_GOOD


ALL_SYS_PWRGD

XDP_DA2_USB_EXTC_OC_L

XDP_DB2_AP_PWR_EN

XDP_FC1

XDP_DD0_DP_GPU_TBT_SEL

XDP_DC3_SATARDRVR_EN

XDP_DC1_MXM_GOOD

XDP_DB1_USB_EXTD_OC_EHCI_L

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_DA0_USB_EXTA_OC_L

XDP_DA3_USB_EXTD_OC_L

XDP_FC0

XDP_DB3_SDCONN_STATE_CHANGE

XDP_DC1_PCH_GPIO35_MXM_GOOD


XDP_OBSDATA_B<1>

XDP_CPU_CFG<0>

XDP_DC2_DP_AUXCH_ISOL

CPU_CFG<12>


XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK JTAG_ISP_TCK

XDP_OBSDATA_B<2>

XDP_VR_READY

XDP_OBSDATA_B<0>

XDP_CPU_PWRGD

XDP_OBSDATA_B<3>


AP_PWR_EN

CPU_CFG<4>

XDP_CPU_CLK100M_P

CPU_CFG<15>

CPU_PWRGD

USB_EXTA_OC_L

USB_EXTB_OC_L


CPU_CFG<9>

XDP_CPURST_L

DP_AUXCH_ISOLXDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL



SATARDRVR_EN

SDCONN_STATE_CHANGE

ISOLATE_CPU_MEM_L

XDP_DBRESET_L


XDP_CPU_CLK100M_N

XDP_PCH_S5_PWRGD

XDP_DB3_SDCONN_STATE_CHANGE

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_PCH_PWRBTN_L

XDP_DA1_USB_EXTB_OC_L

XDP_DA3_USB_EXTD_OC_L

TP_XDP_PCH_OBSFN_B<1>

XDP_DA2_USB_EXTC_OC_L

XDP_DC3_SATARDRVR_EN

TP_XDP_PCH_OBSFN_B<0>

XDP_DC0_ISOLATE_CPU_MEM_L

ENET_LOW_PWR_PCHXDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH


XDP_CPU_TCK

XDP_DD3_ENET_LOW_PWR

XDP_DD2_AUD_IPHS_SWITCH_EN

TP_XDP_PCH_OBSFN_D<1>

XDP_DD0_DP_GPU_TBT_SEL

XDP_DD3_ENET_LOW_PWR

PM_PCH_SYS_PWROK

XDP_BPM_L<2>XDP_BPM_L<5>

CPU_CFG<13>

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<4>

XDP_CPU_TMS

=PP1V05_SUS_PCH_JTAG

CPU_CFG<1>

CPU_CFG<0>

CPU_CFG<2>

CPU_CFG<14>

CPU_CFG<11>

CPU_CFG<10>

XDP_BPM_L<3>

XDP_BPM_L<0>

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

CPU_RESET_L

ITPXDP_CLK100M_N

ITPXDP_CLK100M_P

CPU_CFG<17>

CPU_CFG<16>

TP_XDP_PCH_OBSFN_D<0>

XDP_DD2_AUD_IPHS_SWITCH_EN

TP_XDP_PCH_HOOK4

XDP_PCH_TDI

XDP_DB1_USB_EXTD_OC_EHCI_L

TP_XDPPCH_HOOK3

=SMBUS_XDP_SCL

XDP_PCH_TCK

XDP_DB2_AP_PWR_EN

=PPVCCIO_S0_XDP

PM_PWRBTN_L

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TMS

XDP_CPU_TRST_L

XDP_CPU_TCK

XDP_PCH_TDO

XDP_PCH_TMS

XDP_PCH_TDI

XDP_PCH_TCK

XDP_DC2_DP_AUXCH_ISOL

CPU_CFG<7>

CPU_CFG<6>

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TRST_L

PM_PWRBTN_L

XDP_FC1

XDP_FC0

TP_XDP_PCH_HOOK5

CPU_CFG<0>

=PP3V3_S0_XDP

=SMBUS_XDP_SCL

=SMBUS_XDP_SDA

XDP_CPU_PWRBTN_L

XDP_PCH_TMS

TP_XDP_PCH_TRST_L

XDP_PCH_TDO

XDP_DBRESET_L

XDPPCH_PLTRST_L

XDP_DD1_JTAG_ISP_TCK


TP_XDP_PCH_OBSFN_A<1>



XDP_FC0_PCH_GPIO15

CPU_CFG<5>

CPU_CFG<8>

CPU_CFG<3>

XDP_CONN_PCH

DF40RC-60DP-0.4V

CRITICAL

XDP_CONN_CPU

=PPVCCIO_S0_XDP

0.1uF

X5R

C25011

2

C2500 1

2

C2580 1

2

C25811

2

R25401

2

R2515 1 2

R2516 1 2

R2505 1 2

R2550 2 1

R2551 2 1

R2552 2 1

R2556 2 1

R2510 2 1

R2511 2 1

R2512 2 1

R2513 2 1

R2514 2 1

R2504 1 2

R2501 1 2

R2502 1 2

R2500 1 2

R2560 1 2

R2561 1 2

R2562 1 2

R2563 1 2

R2566 1 2

R2565 1 2

R2564 1 2

R2567 1 2

R2524 1 2

R2525 1 2

R2526 1 2

R2527 1 2

R2530 1 2

R2532 1 2

R2533 1 2

R2534 1 2

R2535 1 2

R2536 1 2

R2537 1 2

R2584 1 2

R2585 1 2

J2500

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

78

9

J2550

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

78

9

R2521 1 2

R2597 1 2

R2596 1 2

R2572 1 2

R2570 1 2

R2576 1 2

R2577 1 2

R2528 1 2

R2529 1 2

R2520 1 2

R2522 1 2

R2523 1 2

R2531 1 2

R2575 1 2

R2573 1 2

R2591 1 2

R2590 1 2

R2580 1 2

R2581 1 2

051-9585

3.0.0

25 OF 132

23 OF 105

6

18 23

18 23 18 23

18 23

7

23 23

23

93

7 23

93

93

23

23

23

23

23

23

23

23

7

23

23

6

23

7 23

10 23 93

10 23 93

10 23 93

10 23 93

10 23 93

16 23

16 23

16 23

16 23

23

23

23

7

23

IN

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

OUT

OUT

OUTIN

IN

OUT

OUT

OUT

BI

OUT

D

GS

OUT IN

OUT

OUT

OUT

OUT

NC

NC

OUT

OUT

OUT

OUT

D

SG

IN

D

SG

NCNC

OUT

D

SG

D SG

IN

OUT

OUT

08

Y1

Y2

GNDB2

VCC

A1B1A2

IN

IN

IN

OUT

OUT

08

Y1

Y2

GNDB2

VCC

A1B1A2

IN

IN

IN

PAD

+3.42V

VDD_25M

+V3.3A

VDDIO_25M_C

VDDIO_25M_B

VDDIO_25M_A

25MHZ_C

25MHZ_B

25MHZ_A

X1

X2

VDD_RTC_OUT

THRMGND

32KHZ_A

Y

B

A

Apple Inc.


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REVISION

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6 3



Ethernet WAKE# Isolation

Note: Based on K91/K92 layout, ENET,AP and BKLT are moved to Buffered reset.

SDCONN_STATE_CHANGE

SB XTAL Power

Ethernet XTAL Power

VDDIO_25M_B: Ethernet power rail for XTAL circuit.

VDDIO_25M_A: SB power rail for XTAL circuit.

GreenClk 25MHz Power

T29 XTAL Power

VDDIO_25M_C: T29 power rail for XTAL circuit.

NOTE: 30 PPM crystal required

Coin-Cell: VBAT (300-ohm & 10uF RC)

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.3V S5

No bypass necessary

VBAT and +V3.3A are

create VDD_RTC_OUT.

to reduce VBAT draw.

available ~3.3V power

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.If high, ME is disabled. This allows for full re-flashing of SPI ROM.

PCH ME Disable Strap

SMC controls strap enable to allow in-field control of strap setting.Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

IPD = 9-50k

Buffered CPU reset

VTT voltage divider on CPU page

Buffered

Series R on Pg38, R3803

Series R is R4283

Unbuffered

Platform Reset Connections

Coin-Cell & No G3Hot: 3.3V S5

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

PCH Reset Button

GPIO Glitch Prevention

ENET_MEDIA_SENSE ISOLATION CIRCUIT

internally ORed to

+V3.3A should be first

For SB RTC Power

No Coin-Cell: 3.42V G3Hot (no RC)

System RTC Power Source & 32kHz / 25MHz Clock Generator

10 23 93 0

5%1/16WMF-LF402

XDP

33

402MF-LF1/16W5%

1/16W

33

MF-LF402

5%

6 47

45

32

18 26

22

201MF

5%1/20W

5%

MF

22

201

1/20W

18 96

31

1/16W

402MF-LF

5%

0

6 47 96

45 96

18

89

22

MF

5%1/20W

201

23

MF-LF

1K

402

5%1/16W

XDP

10VCERM

20%

402

0.1UF

CRITICAL

MC74VHC1G08SC70-HF

100K

MF-LF

5%

402

1/16W

16 96

1/20W

22

5%

MF201

18

18

89

0

402

5%1/16WMF-LF

OMIT

SILK_PART=SYS RESET

MF-LF1/16W

402

5%0

89 96

90

MF-LF402

1/16W5%4.7K

6 17 45

39

CRITICAL

SSM3K15FVSOD-VESM-HF

6 17 32 36

1/16W

402

5%10K

MF-LF

16

16

33

6.3VCERM

1UF10%

402

402-1

10%1UF

10VX5R

402

0.1UF20%10VCERM

20%10VCERM402

0.1UF

1/16W

402

5%

MF-LF

NO STUFF

1M

20%10V

402CERM

0.1UF

1/16W5%

MF-LF

0

402CERM

12PF

5%

402

50V

402CERM

5%

12PF

50V

10 23

MF-LF402

1/16W5%100K

74LVC1G07SC70

CRITICAL

402CERM10V

0.1UF20%

0

1/16WMF-LF402

5%

MF-LF1/16W5%

402

0

30

35

0

201

1/20W5%

MF

36

16

MF-LF

12K 5%

1/16W402

SOT563

SSM6N37FEAPE

CRITICAL

100K5%

MF

1/20W

201

36

SSM6N37FEAPE

SOT563

0

1/16W5%

MF-LF402

25.000MHZ-12PF-20PPM

SM-3.2X2.5MM

CRITICAL

100K

MF201

5%1/20W

16 96

1K

MF201

5%1/20W

SOT563SSM6N37FEAPE

SSM6N37FEAPE

SOT563

45

39

30 36

CERM

20%

402

0.1UF

10V

CRITICAL

SOT833

74LVC2G08GT

19 23

17 24 92

19

63

35

0.1UF

CERM402

10V20%

CRITICAL

SOT83374LVC2G08GT

16

17 24 92

19 23

SLG3NB148ATQFN

CRITICAL

CRITICALTC7SZ08FEAPE

SOT665

201X5R

0.1UF10%6.3V


Chipset Support

LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

MAKE_BASE=TRUELPC_CLK33M_GMUX_R


LPC_CLK33M_SMC_R

PCIE_WAKE_L

PM_SYSRST_L

SYSCLK_CLK25M_ENET_R

=PPVRTC_G3_OUT

SDCONN_STATE_CHANGE

AUD_IPHS_SWITCH_EN

=PP3V3_S0_SB_PM

SDCONN_STATE_CHANGE_SMC

=PP3V3_S3_SDBUF

PM_PCH_PWROK

ENET_LOW_PWR_PCH

FW_PWR_EN_PCH

ENET_LOW_PWR

FW_PWR_EN

XDP_DBRESET_L

ENET_WAKE_LMAKE_BASE=TRUE

=ENET_WAKE_L

=PP3V3_ENET_PHY

=PP3V3_ENET_SYSCLK

=PPVDDIO_ENET_CLK

=PPVDDIO_S0_SBCLK

=PPVDDIO_T29_CLK

=PPVBAT_G3_SYSCLK

=PP3V3_S5_SYSCLK

SYSCLK_CLK25M_TBT

SYSCLK_CLK25M_SB

SYSCLK_CLK25M_X1

SYSCLK_CLK25M_X2_R

SYSCLK_CLK32K_RTC

ENET_MEDIA_SENSE_EN

LPC_RESET_L

PCA9557D_RESET_L

XDPPCH_PLTRST_L

SMC_LRESET_L

LPCPLUS_RESET_LMAKE_BASE=TRUE

=GMUX_PCIE_RESET_L

GMUX_RESET_LMAKE_BASE=TRUE

=FW_RESET_L

PLT_RST_BUF_LMAKE_BASE=TRUE

=ENET_RESET_L

=TBT_RESET_L

AP_RESET_L

BKLT_PLT_RST_L

PLT_RESET_LMAKE_BASE=TRUE

=PP3V3_S0_RSTBUF

CPU_RESET_LMAKE_BASE=TRUEPLT_RST_CPU_BUF_L

=PP5V_S0_PCH

SPI_DESCRIPTOR_OVERRIDE_LS5V

HDA_SDOUT_R

SPI_DESCRIPTOR_OVERRIDE

SPI_DESCRIPTOR_OVERRIDE_L


SYSCLK_CLK25M_X2

SYSCLK_CLK25M_ENET

=PP3V3_S3_PCH_GPIO


ENET_MEDIA_SENSELPC_CLK33M_LPCPLUS

LPC_CLK33M_SMC

LPC_CLK33M_GMUX

PCH_CLK33M_PCIIN

TP_PCI_CLK33M_OUT2

=PP3V3_S3_PCH_GPIO

TBT_PWR_EN

PM_PCH_PWROK

TBT_PWR_EN_PCH

=PP3V3_S3_PCH_GPIO


=PP3V3_S0_RSTBUF

ENET_MEDIA_SENSE_EN_L

R26961 2

R26831 2

R26811 2

R26561 2

R26551 2

R26711 2

R26571 2

R26891 2

C2680 1

2

U2680

3

2

1

4

5

R26801

2

R26591 2

R26871 2R26971

2

R26951

2

Q2630

3

1

2

R26301

2

C26101

2

C26021

2

C2620 1

2

C2622 1

2

R26061

2

C2624 1

2

R26051 2

C2605

12

C2606

1 2

R26901

2

U2690

2

3

5

4

C2690 1

2

R26881 2

R26931 2

R26001 2

R2610

1 2

Q26103

54

R26111

2

Q26106

21

R26121

2

Y2605

24

13

R26201

2

R26211

2

Q2620 6

21

Q2620

3

54

C21501

2U2150

1

5

2

6

4

8

7

3

C21521

2U2152

1

5

2

6

4

8

7

3

U2600

9

8

15

12

7 10

16

13

2

17

5

1

11

6

14

4

3

U2630

2

1

3

5

4

C26301

2

051-9585

3.0.0

26 OF 132

24 OF 105

1

7

23

7 92

30 46

7

7 36 72

7

7

7

7

7

7

7 24

7 22

7 20 22 24

7 18 24

7 20 22 24

7 18 24

7 18 24

7 24

BI

BI

BI

BI

VDD33

PLLFILT

CRFILT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

XTALIN/CLKIN

XTALOUT

TEST

RESET*

THRM_PAD

USBDP_UP

NC

OSC3*

OCS1*

OCS2*

USBDM_UP

RBIAS

VBUS_DET

NC

NC

NC

USBDP_DN3/PRT_DIS_P3

USBDM_DN3/PRT_DIS_M3





PRTPWR3/BC_EN3*

PRTPWR1/BC_EN1*

PRTPWR2/BC_EN2*

SYM VER 1

BI

BI

BI

BI

BI

BI

IN

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

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CRITICAL BOM OPTIONTABLE_5_HEAD

PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

USB XHCI/EHCI2 PORT MUX FOR EXT B

USB MUX FOR LS/FS INTERNAL DEVICES

BLUETOOTH FOR J5 & J3X

NOSTUFF R5701 & R5702, STUFF R2720 & R2721TO CONNECT TP/KB TO PCH XHCI

SMC DEBUG PORT FOR J5, TP/KB FOR J3X

NC FOR J5, SMC DEBUG PORT FOR J3X

TP/KB FOR J5, IR FOR J3X

J3X ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B J5 ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B

BOM TABLE

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

PCH PORT 9 (EHCI2)

PCH PORT 1 (XHCI)

J5 USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATIONJ3X USE 197S0284 FOR Y2700 TO SAVE COST

0 : 1 PORT 1 IS NON REMOVABLE

IPU

IPU

TO PCH XHCI TO TP/KB

IPU

TO CONNECTOR

1 : 0 PORT 1&2 ARE NON REMOVABLE 1 : 1 PORT 1&2&3 ARE NON REMOVABLE

IPU

PCH PORT 7 (EHCI1)

SEL=0 CHOOSE USB EHCI2 PORT

SEL=1 CHOOSE USB XHCI PORT

PCH GPIO60

NON_REM 1 : NON_REM 0 STRAP PIN CFG

0 : 0 ALL PORTS ARE REMOVABLE

CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H

5%1/16WMF-LF402

10K

MF-LF1/16W5%

1M

CRITICAL

402

402

1UF10%16VX5R

0.1UF

X7R-CERM402

10%16V

402

16V10%

X5R

1UF

X7R-CERM16V

0.1UF

402

10%

402

BYPASS=U2700.23::2MM

0.1UF

X7R-CERM16V10%

5%

402MF-LF

10K

1/16W

402

1/16WMF

1%12K

CRITICAL18 95

18 95


X7R-CERM402

16V

0.1UF10%


X7R-CERM

10%16V

402

0.1UF


X7R-CERM402

10%16V

0.1UF

1/16W5%

100

402MF-LF

5%50VCERM402

18PF

CRITICALCRITICAL

18PF

402CERM50V5%

402MF-LF1/16W5%10K

1/16WMF-LF

10K5%

402

MF-LF1/16W

402

5%

HUB_NONREM0_1

10K5%

402MF-LF1/16W

10K

HUB_NONREM1_1

402

1/16W

10K5%

HUB_NONREM0_0

MF-LF402

5%10K

MF-LF1/16W

HUB_NONREM1_0

8

8

USB2513B

OMIT

QFN

402

0.1UF

X7R-CERM

10%16V


402

10%16VX7R-CERM

0.1UF

BYPASS=U2700.5::2MM

603X5R

20%6.3V

4.7UF



603

20%

X5R6.3V

4.7UF

8 25

8 25

X7R-CERM

0.1UF

402

16V10%


8 25

8 25

402

5%

MF-LF

10K

1/16W

NOSTUFF NOSTUFF

402

1/16W

10K

MF-LF

5%

NOSTUFF

402

5%

MF-LF

10K

1/16W

NOSTUFF

402

5%

MF-LF

10K

1/16W

43 95

43 95

16

CERM402

10V20%

0.1UF

PI3USB102ZLE

CRITICALTQFN

18 95

18 95

18 95

18 95

53 95 101

53 95 101

NOSTUFF

402

5%1/16WMF-LF

27

1/16W

402MF-LF

5%

27

NOSTUFF

18 95

18 95

8

8

24.000M-60PPM-16PF

5X3.2X1.4-SM

CRITICAL

402MF-LF1/16W5%0

HUB_NONREM1_0,HUB_NONREM0_1HUB_1NONREM

HUB_2NONREM HUB_NONREM1_1,HUB_NONREM0_0

HUB_NONREM1_1,HUB_NONREM0_1HUB_3NONREM

HUB_NONREM1_0,HUB_NONREM0_0HUB_ALLREM

USB HUB 2513B338S0923 USBHUB2513B1 U2700CRITICAL

1 U2700CRITICAL

338S0824 USB HUB 2514B USBHUB2514B

USBHUB2512BUSB HUB 2512B338S0983CRITICAL

U27001

SYNC_MASTER=J31_LINDA SYNC_DATE=09/16/2011

USB HUB & MUX

USB_HUB_XTAL_C

=PP3V3_S3_USBMUX

USB_EXTB_MUX_P

USB_EXTB_MUX_N

=PP3V3_S3_USB_RESET

USB_EXTB_SEL_XHCI

USB_EXTB_XHCI_N

USB_EXTD_XHCI_P

=PP3V3_S3_USB_HUB

USB_HUB_RESET_L

USB_EXTB_XHCI_P

USB_EXTB_EHCI_N

USB_EXTB_EHCI_P

USB_EXTD_XHCI_N USB_TPAD_R_N

USB_TPAD_R_P

USBHUB_DN4_P

USBHUB_DN4_N

USBHUB_DN3_N

=PP3V3_S3_USB_HUB

USBHUB_DN3_P

NC_USB_HUB_PRTPWR2

TP_USB_HUB_PRTPWR1

NC_USB_HUB_PRTPWR3

USBHUB_DN1_N

USBHUB_DN1_P

USBHUB_DN2_N

USBHUB_DN2_P

USBHUB_DN3_N

USBHUB_DN3_P

USBHUB_DN4_P

USBHUB_DN4_N

NC_USB_HUB_OCS4

USB_HUB_VBUS_DET

USB_HUB_RBIAS

USB_HUB_UP_N

NC_USB_HUB_OCS2

TP_USB_HUB_OCS1

NC_USB_HUB_OCS3

NC_USB_HUB_PRTPWR4

USB_HUB_UP_P

USB_HUB_RESET_L

USB_HUB_TEST

USB_HUB_XTAL2

USB_HUB_XTAL1

USB_HUB_CFG_SEL1

USB_HUB_CFG_SEL0

USB_HUB_NONREM1

USB_HUB_NONREM0

PPUSB_HUB2_VDD1V8

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

VOLTAGE=1.8V

PPUSB_HUB2_VDD1V8PLL


VOLTAGE=1.8V

=PP3V3_S3_USB_HUB

R27121

2

R27001 2

C27141

2

C27131

2C27121

2

C27111

2

C2708 1

2

R27081

2

R27091

2

C2701 1

2

C2706 1

2

C2705 1

2

R27011 2

C27101

2

C2709 1

2

R27071

2

R27061

2

R27031

2

R2702 1

2

R27051

2

R2704 1

2

U2700

14

25

8

9

20

21

13

17

19

34

12

16

18

35

26

24

22

28

11

37

1

3

6

30

2

4

7

31

27

5 10

15

23

29

36

33

32

C27021

2

C27031

2

C2700 1

2

C2704 1

2

C2715 1

2

R27161

2

R27171

2

R27181

2

R27191

2

C2760 1

2

U2760

6

7

3

4

5

8 10

9

2

1

R27201 2

R27211 2

Y27001 2

R27101

2

051-9585

3.0.0

27 OF 132

25 OF 105

7

7

7 25

25

8 25

8 25

8 25

7 25

8 25

25

7 25

IN IN

IN

OUT

OUT

OUT

IN

IN

IN

G

D

S

OUT

D

SG

D

SG

D

S G

D

SG

D

S G

D

SG

D SG

D

SG

D

SG

DSG

OUT

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The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

1V5 S0 "PGOOD" for CPU

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

75mA max load @ 0.75V

5 0 1 1 1 0 (*) 1 1 1

4 0 0 1 1 X 1 0 1

3 0 0 0 1 X 1 0 0

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

S0

to

S3

to

S0

60mW max power

Ensures CKE signals are held low in S3

MEMVTT Clamp

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

6 0 1 1 1 1 1 1 1

2 0 0 1 1 1 1 0 1

1 0 1 1 1 1 1 1 1

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

23 6 17 45 74

18 24

CPUMEM_S0

100K

1/16W

402MF-LF

5%

8

MF-LF402

CPUMEM_S0

5%1/16W

10K

CPUMEM_S0

MF-LF1/16W

5%100K

402

27 29

1K

CPUMEM_S0

402

5%1/16WMF-LF

73

MF-LF402

5%1/16W

10K

CPUMEM_S0

17 32 45 74

402

CPUMEM_S0

MF-LF

100K5%

1/16W

8 68

MF-LF1/16W

5%100K

CPUMEM_S0

402

CERM

20%0.001UF

50V

402

NO STUFF

CPUMEM_S0

1/10W

603

5%10

MF-LF

CPUMEM_S3

0

402

5%1/16WMF-LF

10

1/16W

402

33.2K1%

MF-LF

MF-LF1/16W

1%27.4K

402

DMB53D0UV

CRITICAL

SOT-563

1/16WMF-LF402

10K5%

CRITICAL

DMB53D0UVSOT-563

10 17 93

0.001UF20%50V

402

NO STUFF

CERM

CPUMEM_S0

402

10%0.1UF

X5R16V

SSM6N37FEAPE

CRITICAL

SOT563

CPUMEM_S0

SSM6N37FEAPE

CPUMEM_S0

SOT563

CRITICAL

SOT563

SSM6N37FEAPE

CPUMEM_S0

CRITICAL

CPUMEM_S0

SOT563

SSM6N37FEAPECRITICAL

SOT563

CPUMEM_S0SSM6N37FEAPE

CRITICAL

SSM6N37FEAPE

SOT563

CPUMEM_S0

CRITICAL

SSM6N37FEAPE

SOT563

CPUMEM_S0

CRITICAL

SOT563

SSM6N37FEAPE

CPUMEM_S0CRITICAL

CPUMEM_S0

SOT563

SSM6N37FEAPE

CRITICAL

SSM6N37FEAPE

CRITICAL

CPUMEM_S0

SOT56331

0.047UF

201

6.3V

NOSTUFF

X5R

10%

CPU Memory S3 Support


=PP5V_S3_MEMRESET

=PP3V3_S3_MEMRESET

ISOLATE_CPU_MEM_L

MEM_RESET_L

=PP1V5_S3_MEMRESET

MAKE_BASE=TRUECPU_MEM_RESET_L

VTTCLAMP_L

VTTCLAMP_EN

=DDRVTT_EN

=PP5V_S3_MEMRESET

P1V5CPU_EN_L

PM_SLP_S3_L

MEMVTT_EN_L

PLT_RESET_L

MEMVTT_EN

P1V5CPU_EN

=MEM_RESET_L

=PPVTT_S0_VTTCLAMP

PM_SLP_S4_L



PM_MEM_PWRGD_L

PM_MEM_PWRGD

P1V5_S0_DIV

MEMRESET_ISOL_LS5V_L

R28021

2

R28101

2

R28151

2

R28161

2

R28051

2

R28011

2

R28511

2

C2851 1

2

R28501

2

R28171 2

R28211

2

R28201

2

Q28205

3

4

R28221

2 Q2820

6

2

1

C2820 1

2

C28161

2

Q28003

54

Q28006

21

Q28053

54

Q28056

21

Q28103

54

Q28106

21

Q2815

6

21

Q28503

54

Q28506

21

Q2815

3

54

C28171

2

051-9585

3.0.0

28 OF 132

26 OF 105

7 26

7

7

7 26

7

7 10 13 15

7

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4*

DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS

DQ58

DQ59

DM7

VSS

DQ57

DQ56

DQ50

DQ51

VSS

DQS6*

DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS

DQ42

SDA

SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60

DQ61

VSS

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS

DQ40

DQ34

VSS

DQ32

TEST

VDD

VDD

S1*

A13

CAS*

WE*

BA0

VDD

VDD

CK0

A1

A3

VDD

VDD

A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS

DQ44

DQ45

DQ39

DQ38

VSS

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD

ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

VDD

A0

CK1

A2

VDD

A4

VDD

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI

BIBI

BI

IN

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

DQ16

DM3

DQ26

DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24

DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8

DQ9

DM0

DQ0

DQ1

VREFDQ

DQ3

DQ2

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

KEY

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

(SYMBOL 1 OF 2)

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NC

NC

NC

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SPD ADDR=0xA0(WR)/0xA1(RD)

516-0229

"Factory" (top) slot

Signal aliases required by this page:

Page NotesPower aliases required by this page:

- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A

- =PP0V75_S0_MEM_VTT_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

BOM options provided by this page:

(NONE)

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

See CSA05 BOM table

F-RT-THB

DDR3-SODIMM-DUAL-K6

OMIT_TABLE

28

28

0.1UF

10V

20%

402

CERM

2.2UF20%

402-LF

CERM

6.3V

28

28

6 11 94

28

28

28

28

28

28

28

26 29

28

28

28

28

28

28

28

28

28

28

28

OMIT_TABLE

F-RT-THB

DDR3-SODIMM-DUAL-K6

CRITICAL

28

28

28

28

28

28

28

28

28

28

28

28

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

28

28

28

28

28

28

6 11 94

28

28

28

28

28

28

28

28

28

0.1UF

CERM

402

20%

10V

CERM

2.2UF

6.3V

20%

402-LF

28

28

28

28

28

28

28

28

28

28

28

29 45 46

48

48

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

5%

1/16W

MF-LF

402

10K

402

5%

1/16W

MF-LF

10K

6.3V

402-LF

CERM

20%

2.2UF

PLACE_NEAR=J2900.75:2.54mm

20%

603

6.3VX5R

10UF 10UF

X5R6.3V20%

603



0.1UF20%10V

402CERM CERM

10V20%

402

0.1UF


CERM


402

10V20%0.1UF 0.1UF

20%10VCERM


402

0.1UF20%

CERM402

10V


CERM402

10V20%0.1UF


CERM402

20%0.1UF

10V


CERM402

20%0.1UF

10V


CERM402

20%10V

0.1UF


CERM402

20%0.1UF

10V


0.1UF

CERM402

20%10V


CERM402

20%0.1UF

10V


CERM402

20%0.1UF

10V

PLACE_NEAR=J2900.75:2.54mmPLACE_NEAR=J2900.75:2.54mm

CERM402

20%0.1UF

10V

10%10V

1UF

X5R402

10%10V

1UF

X5R402

10%10V

1UF

X5R402

10%10V

1UF

X5R402

SYNC_MASTER=K92_SUMA SYNC_DATE=06/23/2010

DDR3 SO-DIMM Connector A

=PP1V5_S3_MEM_A

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<3>

=MEM_A_DQ<0>

MEM_A_A<15>

MEM_A_CKE<1>

=MEM_A_DQ<25>

=MEM_A_DQ<8>

MEM_RESET_L

=MEM_A_DQ<27>

=MEM_A_DQ<19>

=MEM_A_DQS_N<2>

=MEM_A_DQ<17>

=MEM_A_DQ<10>

=PPSPD_S0_MEM_A

=MEM_A_DQ<58>

=MEM_A_DQ<59>

=MEM_A_DQ<52>

=MEM_A_DQ<45>

=MEM_A_DQ<44>

=MEM_A_DQ<36>

=MEM_A_DQ<42>

=MEM_A_DQ<43>

MEM_A_A<5>

MEM_A_BA<0>

=MEM_A_DQ<34>

=MEM_A_DQ<51>

=MEM_A_DQ<56>

=MEM_A_DQ<32>

=MEM_A_DQ<50>

=MEM_A_DQ<49>

=MEM_A_DQ<48>

MEM_A_A<11>

=MEM_A_DQ<11>

=MEM_A_DQ<29>

MEM_A_ODT<1>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_RAS_L

MEM_A_A<2>

MEM_A_CS_L<0>

MEM_A_A<8>

MEM_A_A<1>

MEM_A_A<10>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_A<13>

MEM_A_CS_L<1>

MEM_A_CKE<0>

=MEM_A_DQS_P<4>

=MEM_A_DQ<33>

=MEM_A_DQS_N<4>

=MEM_A_DQ<35>

=MEM_A_DQ<57>

=MEM_A_DQS_N<6>

=MEM_A_DQS_P<6>

=I2C_SODIMMA_SDA

MEM_EVENT_L

=MEM_A_DQS_N<7>

=MEM_A_DQS_P<7>

=MEM_A_DQ<60>

=MEM_A_DQ<40>

MEM_A_BA<2>

=MEM_A_DQ<39>

=MEM_A_DQ<38>

MEM_A_ODT<0>

=MEM_A_DQ<16>

=MEM_A_DQ<26>

=MEM_A_DQ<4>

=MEM_A_DQ<31>

=MEM_A_DQ<30>

=MEM_A_DQS_P<3>

=MEM_A_DQS_N<3>

=MEM_A_DQ<28>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

=MEM_A_DQ<13>

=MEM_A_DQ<12>

=MEM_A_DQ<7>

=MEM_A_DQ<6>

=MEM_A_DQS_P<0>

=MEM_A_DQS_N<0>

=MEM_A_DQ<5>

=MEM_A_DQ<24>

=MEM_A_DQS_P<1>

=MEM_A_DQS_N<1>

=MEM_A_DQ<1>

=MEM_A_DQ<3>

=MEM_A_DQ<2>

=MEM_A_DQ<23>

=MEM_A_DQ<22>

=MEM_A_DQ<21>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<12>

MEM_A_A<9>

=MEM_A_DQ<9>

PP0V75_S3_MEM_VREFDQ_A

=MEM_A_DQ<53>

=MEM_A_DQ<41>

=MEM_A_DQ<20>

=MEM_A_DQ<46>

=MEM_A_DQ<55>

=MEM_A_DQS_P<2>

=MEM_A_DQ<18>

=MEM_A_DQ<47>

MEM_A_A<0>

MEM_A_A<7>

MEM_A_A<14>

=MEM_A_DQ<37>

=MEM_A_DQS_N<5>

=MEM_A_DQS_P<5>

=MEM_A_DQ<61>

=MEM_A_DQ<63>

MEM_A_SA<1>

=PP0V75_S0_MEM_VTT_A

MEM_A_SA<0>

=I2C_SODIMMA_SCL

=MEM_A_DQ<54>

=MEM_A_DQ<62>

J2900

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101

103

102

104

73 74

136

153

170

187

129

131

141

143

130

132

140

142

147

149

157

159

146

148

158

160

163

165

175

177

164

166

174

176

181

183

191

193

180

182

192

194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99 100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

C29311

2

C29301

2

J290011

28

46

63

5

7

33

35

22

24

34

36

39

41

51

53

15

40

42

50

52

57

59

67

69

56

58

17

68

70

4

6

16

18

21

23

12

10

29

27

47

45

64

62

30

1 2

3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

C29361

2

C29351

2

R29411

2

R29401

2

C29401

2

C29001

2

C29011

2

C29101

2

C29111

2

C29121

2

C29131

2

C29141

2

C29151

2

C29161

2

C29171

2

C29181

2

C29191

2

C29201

2

C29211

2

C29221

2

C29231

2

C29501

2

C29511

2

C29521

2

C29531

2

051-9585

3.0.0

29 OF 132

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Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



CPU CHANNEL B DQS 0 -> DIMM B DQS 0



CPU CHANNEL A DQS 4 -> DIMM A DQS 4













DDR3 Byte/Bit Swaps

SYNC_MASTER=K92_SUMA SYNC_DATE=05/10/2010

MEM_A_DQ<33>MAKE_BASE=TRUE


MEM_A_DQS_P<5>MAKE_BASE=TRUE



=MEM_A_DQ<51>

=MEM_A_DQ<58>

=MEM_A_DQ<56>

=MEM_A_DQ<60>MEM_A_DQ<56>MAKE_BASE=TRUE



=MEM_A_DQ<62>

=MEM_A_DQ<63>

=MEM_A_DQ<61>

=MEM_A_DQS_P<7>

=MEM_A_DQ<50>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

=MEM_A_DQS_N<6>

=MEM_A_DQ<49>

=MEM_A_DQ<48>

=MEM_A_DQ<59>




=MEM_A_DQ<52>

MAKE_BASE=TRUE

MEM_B_DQ<54>

MEM_B_DQ<53>MAKE_BASE=TRUE

=MEM_A_DQ<53>




=MEM_A_DQ<28>

MEM_A_DQS_N<6>MAKE_BASE=TRUE



=MEM_A_DQ<57>

=MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MEM_A_DQ<63>

MAKE_BASE=TRUE


MEM_A_DQS_N<7>


MAKE_BASE=TRUE


MEM_A_DQ<52>




MAKE_BASE=TRUE

MEM_A_DQS_P<6> =MEM_A_DQS_P<6>

MEM_B_DQS_N<6>MAKE_BASE=TRUE

=MEM_B_DQ<62>


MAKE_BASE=TRUE


MEM_A_DQ<42>


MAKE_BASE=TRUE

MEM_A_DQ<35>


=MEM_A_DQ<40>

=MEM_A_DQ<46>

=MEM_A_DQ<44>

=MEM_A_DQ<41>

=MEM_A_DQ<43>

=MEM_A_DQ<47>

MAKE_BASE=TRUE

MEM_A_DQ<46>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MAKE_BASE=TRUE


MEM_A_DQ<44>

=MEM_A_DQ<42>

=MEM_A_DQ<45>

=MEM_A_DQS_P<5>

=MEM_A_DQS_N<5>

=MEM_A_DQ<36>



=MEM_A_DQ<37>

=MEM_A_DQ<33>

=MEM_A_DQ<35>

=MEM_A_DQ<32>


=MEM_A_DQ<34>

=MEM_A_DQ<38>


MAKE_BASE=TRUE

MEM_A_DQ<21>


MAKE_BASE=TRUE

MEM_A_DQ<16>

=MEM_A_DQ<30>

=MEM_A_DQ<29>

MAKE_BASE=TRUE

MEM_A_DQ<36>

=MEM_A_DQS_P<4>

=MEM_A_DQ<24>

=MEM_A_DQ<25>

=MEM_A_DQ<27>

=MEM_A_DQ<26>


MAKE_BASE=TRUE

MEM_A_DQ<28>


MAKE_BASE=TRUE

MEM_A_DQ<26>

=MEM_A_DQ<31>

=MEM_A_DQ<18>

=MEM_A_DQ<19>

=MEM_A_DQ<20>

MAKE_BASE=TRUE

MEM_A_DQ<18>

=MEM_A_DQ<16>

=MEM_A_DQ<17>

=MEM_A_DQ<23>

=MEM_A_DQ<22>

=MEM_A_DQ<21>

MAKE_BASE=TRUE

MEM_A_DQ<23>

=MEM_A_DQS_P<2>


=MEM_A_DQ<8>

=MEM_A_DQ<9>

=MEM_A_DQ<10>

=MEM_A_DQ<13>

=MEM_A_DQ<12>

=MEM_A_DQ<15>

=MEM_A_DQS_N<1>

=MEM_A_DQ<1>



MAKE_BASE=TRUE

MEM_A_DQ<5>


=MEM_A_DQ<4>

=MEM_A_DQ<5>

MAKE_BASE=TRUE

MEM_A_DQ<0>


MAKE_BASE=TRUE

MEM_A_DQ<10>


MAKE_BASE=TRUE

MEM_A_DQ<13>



=MEM_A_DQS_P<1>


MAKE_BASE=TRUE

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQ<15>

MAKE_BASE=TRUE

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>


MAKE_BASE=TRUE

MEM_A_DQ<6>

=MEM_A_DQ<2>

=MEM_A_DQ<0>

=MEM_A_DQ<3>

=MEM_A_DQ<6>


MEM_A_DQS_N<0>


MAKE_BASE=TRUE

MEM_B_DQS_P<2>

=MEM_B_DQ<21>

=MEM_B_DQ<19>

=MEM_B_DQ<18>

=MEM_B_DQ<16>

MAKE_BASE=TRUE

MEM_B_DQ<18>

=MEM_B_DQ<29>

=MEM_B_DQ<28>


=MEM_B_DQ<26>

=MEM_B_DQS_N<4>

=MEM_B_DQS_P<4>

=MEM_A_DQ<14>

=MEM_A_DQ<11>

=MEM_A_DQS_N<3>MAKE_BASE=TRUE

MEM_A_DQS_N<3>

MAKE_BASE=TRUE

MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MEM_A_DQ<31>

=MEM_B_DQ<46>

=MEM_B_DQ<40>

=MEM_B_DQ<45>

=MEM_B_DQ<44>

=MEM_B_DQ<43>

=MEM_B_DQ<42>MEM_B_DQ<42>MAKE_BASE=TRUE


=MEM_B_DQ<58>

=MEM_B_DQ<53>

=MEM_B_DQ<48>



=MEM_B_DQ<1>

=MEM_B_DQS_N<1>

=MEM_B_DQS_P<1>

=MEM_B_DQ<14>

=MEM_B_DQ<13>


=MEM_B_DQ<10>

=MEM_B_DQ<8>

=MEM_B_DQS_N<2>

=MEM_B_DQ<23>


=MEM_B_DQS_N<3>

=MEM_B_DQ<30>

=MEM_B_DQ<24>


=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>MAKE_BASE=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<35>


MEM_B_DQ<36>

=MEM_B_DQ<32>

=MEM_B_DQS_N<5>

=MEM_B_DQS_P<5>

=MEM_B_DQ<47>


MEM_B_DQ<41>

=MEM_B_DQS_N<6>

=MEM_B_DQS_P<6>MAKE_BASE=TRUE

MEM_B_DQS_P<6>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

=MEM_B_DQ<52>

=MEM_B_DQ<51>

=MEM_B_DQ<50>



=MEM_B_DQS_P<7>MEM_B_DQS_P<7>MAKE_BASE=TRUE

=MEM_B_DQS_N<7>MEM_B_DQS_N<7>MAKE_BASE=TRUE






=MEM_B_DQ<57>



=MEM_B_DQ<9>

=MEM_B_DQ<27>

=MEM_B_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQS_P<1>

MAKE_BASE=TRUE

MEM_B_DQ<1>

=MEM_B_DQS_P<2>

=MEM_B_DQ<22>

MAKE_BASE=TRUE

MEM_B_DQ<15>


=MEM_B_DQ<15>

=MEM_B_DQ<12>

=MEM_B_DQ<20>

=MEM_B_DQS_P<3>

=MEM_B_DQ<31>



=MEM_B_DQ<35>

=MEM_B_DQ<34>

=MEM_B_DQ<33>

=MEM_B_DQ<25>



=MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MEM_B_DQ<51>





MAKE_BASE=TRUE

MEM_B_DQ<38>





MAKE_BASE=TRUE

MEM_B_DQ<0>

MAKE_BASE=TRUE

MEM_B_DQ<10>

MAKE_BASE=TRUE

MEM_B_DQ<8>

=MEM_A_DQS_P<0>




=MEM_A_DQS_N<4>

MAKE_BASE=TRUE


MEM_A_DQS_N<4>

MAKE_BASE=TRUE

MEM_A_DQ<24>




MAKE_BASE=TRUE

MEM_B_DQ<44>

MEM_B_DQS_P<5>MAKE_BASE=TRUE




MAKE_BASE=TRUE

MEM_B_DQ<34>






MAKE_BASE=TRUE

MEM_B_DQ<31>


MAKE_BASE=TRUE



MEM_B_DQ<21>


=MEM_A_DQS_N<0>

=MEM_A_DQS_N<2>

MAKE_BASE=TRUE

MEM_B_DQ<2>


MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_B_DQ<6>




=MEM_B_DQ<0>

=MEM_B_DQ<2>

=MEM_B_DQ<7>

=MEM_B_DQ<4>

=MEM_B_DQ<5>

=MEM_B_DQ<3>

=MEM_B_DQ<6>

=MEM_B_DQS_P<0>MEM_B_DQS_P<0>MAKE_BASE=TRUE

051-9585

3.0.0

30 OF 132

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29 6 11 94

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29 6 11 94

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29

29

29

29 6 11 94

29

29

29

6 11 94

29

29

29 6 11 94

6 11 94

29 6 11 94

29

29

29

29

29 6 11 94

29

29 6 11 94

29

29

29

29

29

29 6 11 94

6 11 94

29 6 11 94

29 6 11 94

6 11 94

29 6 11 94

29 6 11 94

29 6 11 94

29 6 11 94

29

6 11 94

29 6 11 94

29

29

29

6 11 94

6 11 94

29

29

6 11 94

6 11 94

29

29

29

29

29

6 11 94

6 11 94

29

29

29

29

6 11 94

6 11 94

27

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

27

6 11 94

6 11 94

6 11 94

27

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

27

27

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

29

29

29

29

29

29

29

29 6 11 94

IN

BI

BI

BI

OUT

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NC

NC

NC

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42

DQ43

DQ48

DQ49

VSS

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15

A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36

DQ37

VSS

DM4

VSS

VSS

DQ38

DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD

NC

BA2

CK0

VDD

BA0

WE*

A13

S1*

VDD

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54

DQ55

VSS

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS

DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PINMTG PIN

MTG PIN MTG PIN

MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PINMTG PINS

KEY

(2 OF 2)

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

DQ2

DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1*

DQS1

DQ10

DQ11

DQ17

DQS2*

DQS2

DQ18

DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6

DQ7

DQ12

DQ13

DM1

RESET*

DQ14

DQ15

DQ20

DQ21

DM2

DQ22

DQ23

DQ28

DQ29

DQS3*

DQS3

DQ30

DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

KEY

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

Apple Inc.


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DSIZEDRAWING NUMBER

REVISION

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6 3



- =I2C_SODIMMB_SDA


- =PP0V75_S0_MEM_VTT_B

Page Notes


DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR) Power aliases required by this page:

- =I2C_SODIMMB_SCL

(NONE)

"Expansion" (bottom) slot

- =PP1V5_S3_MEM_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

516S0806

516S0806

SPD ADDR=0xA4(WR)/0xA5(RD)

- =PP1V5_S0_MEM_B

6 11 94

28

28

28

27 45 46

48

48

CERM

10V

20%

402

0.1UF

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

CERM

402-LF

6.3V

20%

2.2UF

5%

MF-LF

402

10K

1/16W

MF-LF

1/16W

402

5%

10K2.2UF

6.3V

402-LF

CERM

20%

PLACE_NEAR=J3100.75:2.54mm603

6.3VX5R

20%10UF


20%

603X5R

10UF

6.3V

0.1UF20%10V

402CERM


20%10VCERM402

0.1UF

PLACE_NEAR=J3100.75:2.54mmPLACE_NEAR=J3100.75:2.54mm

402

10V20%0.1UF

CERM


20%10V

0.1UF

402CERM

28


20%

CERM402

10V

0.1UF


402

20%0.1UF

CERM10V


CERM402

20%0.1UF

10V


CERM402

20%0.1UF

10V


CERM402

20%0.1UF

10V


CERM402

20%0.1UF

10V


0.1UF

CERM402

20%10V


CERM402

20%0.1UF

10V


CERM402

20%0.1UF

10V


CERM402

20%0.1UF

10V

28

10%10VX5R402

1UF10%10VX5R402

1UF

6 11 94

10%10V

1UF

X5R402

10%10V

1UF

X5R402

F-RT-BGA6

DDR3-SODIMM

OMIT_TABLE

28

28

28

28

28

28

28

26 27

28

28

28

28

28

28

28

28

28

28

28

28

28

F-RT-BGA6

DDR3-SODIMM

CRITICAL

OMIT_TABLE

28

28

28

28

28

28

28

28

28

28

28

28

28

6 11 94

6 11 94

6 11 94

28

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

6 11 94

28

28

28

28

28

28

6 11 94

28

28

28

28

28

28

28

28

CERM

402

10V

0.1UF20%

2.2UF

6.3V

CERM

20%

402-LF

28

28

28

28

28

28

28

28

DDR3 SO-DIMM Connector B

SYNC_DATE=06/23/2010SYNC_MASTER=K92_SUMA

=MEM_B_DQ<54>

=MEM_B_DQ<33>

=MEM_B_DQ<42>

=MEM_B_DQ<48>

=MEM_B_DQ<49>

=MEM_B_DQS_N<6>

=MEM_B_DQS_P<6>

MEM_B_A<3>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_A<10>

MEM_B_BA<0>

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_ODT<1>

MEM_B_CLK_P<1>

MEM_B_RAS_L

MEM_B_ODT<0>

=MEM_B_DQ<59>

=MEM_B_DQ<13>

MEM_B_A<1>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<12>

=MEM_B_DQ<41>

=MEM_B_DQS_N<4>

MEM_B_CKE<1>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<11>

MEM_B_A<7>

MEM_B_A<2>

MEM_B_A<0>

MEM_B_CLK_N<1>

MEM_B_BA<1>

MEM_B_CS_L<0>

PP0V75_S3_MEM_VREFCA_B

=MEM_B_DQ<36>

=MEM_B_DQ<37>

=MEM_B_DQ<38>

=MEM_B_DQ<39>

=MEM_B_DQ<45>

=MEM_B_DQ<44>

=MEM_B_DQS_N<5>

MEM_B_CKE<0>

MEM_B_BA<2>

MEM_B_A<13>

=MEM_B_DQ<32>

=MEM_B_DQ<40>

=MEM_B_DQ<46>

=MEM_B_DQS_P<5>

=MEM_B_DQ<47>

=MEM_B_DQ<52>

=MEM_B_DQ<53>

=MEM_B_DQ<55>

=MEM_B_DQ<63>

MEM_EVENT_L

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=MEM_B_DQ<51>

=MEM_B_DQ<35>

=MEM_B_DQ<56>

=MEM_B_DQ<57>

MEM_B_SA<1>

=MEM_B_DQ<58>

=MEM_B_DQ<2>

=MEM_B_DQ<3>

PP0V75_S3_MEM_VREFDQ_B

=MEM_B_DQ<1>

=MEM_B_DQ<0>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQS_N<1>

=MEM_B_DQS_P<1>

=MEM_B_DQ<10>

=MEM_B_DQ<11>

=MEM_B_DQ<17>

=MEM_B_DQS_N<2>

=MEM_B_DQS_P<2>

=MEM_B_DQ<18>

=MEM_B_DQ<19>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQ<5>

=MEM_B_DQS_N<0>

=MEM_B_DQ<6>

=MEM_B_DQ<7>

=MEM_B_DQ<12>

MEM_RESET_L

=MEM_B_DQ<14>

=MEM_B_DQ<15>

=MEM_B_DQ<20>

=MEM_B_DQ<21>

=MEM_B_DQ<22>

=MEM_B_DQ<23>

=MEM_B_DQ<28>

=MEM_B_DQ<29>

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<3>

=MEM_B_DQ<30>

=MEM_B_DQ<31>

=MEM_B_DQ<4>

=MEM_B_DQ<27>

=MEM_B_DQ<26>

=MEM_B_DQ<16>

=MEM_B_DQ<50>

=MEM_B_DQ<62>

=MEM_B_DQ<34>

=MEM_B_DQS_P<4>

=PPSPD_S0_MEM_B

MEM_B_A<4>

=PP1V5_S3_MEM_B

MEM_B_A<6>

=MEM_B_DQ<43>

MEM_B_SA<0>

=MEM_B_DQS_P<7>

=MEM_B_DQS_N<7>

=MEM_B_DQ<61>

=MEM_B_DQ<60>

=MEM_B_DQS_P<0>

=PP0V75_S0_MEM_VTT_B

MEM_B_WE_L

J3100

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101

103

102

104

73 74

136

153

170

187

129

131

141

143

130

132

140

142

147

149

157

159

146

148

158

160

163

165

175

177

164

166

174

176

181

183

191

193

180

182

192

194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99 100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

205 206

207 208

209 210

211 212

203 204

113

C31311

2

C31301

2

J310011

28

46

63

5

7

33

35

22

24

34

36

39

41

51

53

15

40

42

50

52

57

59

67

69

56

58

17

68

70

4

6

16

18

21

23

12

10

29

27

47

45

64

62

30

1 2

3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

C31361

2

C31351

2

R31411

2

R31401

2

C31401

2

C31001

2

C31011

2

C31101

2

C31111

2

C31121

2

C31131

2

C31141

2

C31151

2

C31161

2

C31171

2

C31181

2

C31191

2

C31201

2

C31211

2

C31221

2

C31231

2

C31531

2

C31521

2

C31511

2

C31501

2

051-9585

3.0.0

31 OF 132

29 OF 105

31 93

6

31 93

7

7

6

7

OUT

BI

BI

OUT

BI

BI

BI

IN

BI

BI

BI

OC*

OUT2

OUT1

OUT0

THRMGND

EN

IN1

IN0

PAD

IN

VDD

WRITE_PROTECT_SW

CARD_DETECT_SW

CARD_DETECT_GND

DAT6

DAT7

DAT1

CD/DAT3

DAT2

DAT4

DAT5

VSS

VSS

CLK

CMD

DAT0

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

OUT

OUT

INOUT

IN

OUT

LOW_PWR

GNDTHRM

VDD

RST_OUT*

DET_OUT

DET_CHNGD*

DET_LVL

DET_IN

RST_IN*

DET_CH_EN*

DLY

RST

LOGIC

XOR

(IPU)

XOR (OD)

(OD)

PAD

Apple Inc.


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6 3



SD Not Inserted, CARD_DETECT is OPEN.

Place near attr for series resistors:

SDCONN_DETECT Debounce, Inversion, Detect-Changed PCH GPIO Latch Circuit

Must STUFF R3312 and NOSTUFF R3314

R3314 and R3312 mutually exclusive

to bypass reset logic

R3311 and R3310 mutually exclusive

on DET_CHANGED# logic.

TPS2065-1 (1.0A limit) has active load discharge so R4810 is NOSTUFF.

to control effect of =ENET_RESET_L

Otherwise RST_OUT# follows RST_IN#

-> From PCH GPI0

-> From SD Conn

(Low active)

353S3004

SD Card 3.3V Overcurrent Protection

DLY block is 20ms nominal

When ENET_LOW_PWR deasserts, RST_OUT#

10ms regardless ofmove RST_IN# state.

deasserts for >80ms, then asserts for

(Low active pulse signal)

-> To ENET Chip

516-0225

CAESAR-IV Card Detect is programmable,

but a Silicon bug makes the active

high case unusable.

SD Card Connector

when R3311 is NOT STUFFED.

SD Detect & Reset Logic

Converts SDCONN from active-low level signal to active-high pulses.

-> To SMC & to Isolation Circuit (then to PCH GPIO)

36 97

36 97

36 97

36

36 97

36 97

36 97

36 97

36 97

36 97

36 97

DGN

TPS2065-1

CRITICAL

6.3V20%

603X5R

10UF

CRITICAL

16V10%

402X7R-CERM

0.1UF1/16W5%

402MF-LF

47K

NOSTUFF

CRITICAL

10UF

X5R603

20%6.3V

0.1UF

X7R-CERM402

10%16V

1/16W5%

402MF-LF

0

1/16W5%

402MF-LF

10K

24

F-RT-THSD-CARD-K19-K24

CRITICAL

24 46

36

10V10%

402-1X5R

1UF

1/16W5%

402MF-LF

0

24 36

1/16W5%

402MF-LF

036 97

MF-LF

PLACE_NEAR=U3900.21:5MM

1/16W5% 402330402

47NH-1.3OHM

CRITICAL

50V5%

402CERM

15PF

NOSTUFF

50V5%

402CERM

22PF

NOSTUFF

30

10PF25VCER

NOSTUFF

0201

5%

30

1/16W33 5% 402MF-LF


1/16W33 5% 402MF-LF


1/16W5% 402MF-LF33


1/16W5% 402MF-LF33


1/16W5% 402MF-LF33


1/16W5% 402MF-LF33


1/16W5% 402MF-LF33


MF-LF


1/16W5% 402331/16W5% 402MF-LF33


TDFNSLG4AP026V

CRITICAL

MF-LF402

5%1/16W

10K

NOSTUFF

MF-LF402

5%1/16W

10K

5%1/16W

10K

402MF-LF

0

MF-LF402

5%1/16W

NOSTUFF

MF-LF402

10K

1/16W5%

NOSTUFF

25VCER

10PF

0201

5%25VCER

NOSTUFF

10PF

0201

5% 5%

0201

10PF

NOSTUFF

CER25V

5%

0201

10PF

NOSTUFF

CER25V

5%

0201

10PF

NOSTUFF

CER25V

5%

0201

10PF

NOSTUFF

CER25V

5%

0201

10PF

NOSTUFF

CER25V

5%

0201

10PF

NOSTUFF

CER25V

5%

0201

10PF

NOSTUFF

CER25V

SD Card Connector

SYNC_DATE=10/25/2011SYNC_MASTER=J31_YONAS

SDCONN_STATE_CHANGE_SMC

SDCONN_DETECT_L

SDCONN_CMDSDCONN_CLK_R_L

=PP3V3_S0_SW_SD_PWR

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmMAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S0_SW_SD_PWR

SDCONN_OC_L

=PP3V3_S0_PCH_GPIO

SDCONN_OC_L_R

SDCONN_DATA<7>SDCONN_DATA<6>SDCONN_DATA<5>SDCONN_DATA<4>SDCONN_DATA<3>SDCONN_DATA<2>SDCONN_DATA<1>SDCONN_DATA<0>

SDCONN_CLK

ENET_CR_PWREN

SLG_ENET_RESET_OUT_L

=PP3V3_S0_SDCARD

SD_DET_LVL_LSDCONN_CARDDETECT_L

SLG_ENET_RESET_IN_LSD_DET_CH_EN_L

ENET_RESET_LENET_LOW_PWR

=ENET_RESET_L

=PP3V3_S0_SW_SD_PWR

SDCONN_R_DATA<3>

SDCONN_CMD_R

=PP3V3_S4_SD_HPD

SDCONN_R_DATA<5>

SDCONN_WP

SDCONN_R_DATA<2>

SDCONN_CLK_R

SDCONN_R_DATA<4>

SDCONN_R_DATA<6>

SDCONN_R_DATA<0>SDCONN_R_DATA<1>

SDCONN_R_DATA<7>SDCONN_CARDDETECT_L

U3300

4

1

2

3

5

6

7

8

9

C33021

2

C33031

2

R33001

2

C33001

2

C33011

2

R33021 2

R33011

2

J3300

15

14

1

5

2

7

8

9

10

11

12

13

17

18

19

20

4

3

6

16

C3310 1

2

R33111 2

R33141 2

R3379 1 2

L3300

1 2

C33701

2

C33711

2

C33731

2

R3361 1 2

R3371 1 2

R3372 1 2

R3373 1 2

R3374 1 2

R3375 1 2

R3376 1 2

R3377 1 2

R3378 1 2

U3311

6

97

18

5

2

3

4

11

10

R33101

2

R33161

2

R33171

2

R33121

2

R33151

2

C33751

2

C33771

2

C33791

2

C33811

2

C33721

2

C33741

2

C33761

2

C33781

2

C33801

2

051-9585

3.0.0

33 OF 132

30 OF 105

97

30

7 16 17 18 19

36

7

30

97

7

97

97

97

97

97

97

97

97

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

IN

DSG

DSG

NC

NC

NC

NC

NC

NC

RESET*

A0

A1

A2

SCL

SDA

P0

P1

P2

P5

P6

P7

P3

P4

THRM

VCC

GNDPAD

NC

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTASCL

SDA

A0

A1

GND

IN

BI



Apple Inc.


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6 3



+61uA - -61uA (- = sourced)



VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.

RST* on ’platform reset’ so that system

NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.

NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step

1.5V (DAC: 0x3A) 0.75V (DAC: 0x3A)

+3.4mA - -3.4mA (- = sourced)

7.69mV / step @ outputDAC step size:

VRef current:

Margined target:

MEM B VREF DQMEM A VREF DQ

Addr=0x98(WR)/0x99(RD)

both at the same time!

DDR3L (1.35V) 6.99mV per step

1

DAC range:

VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.

Required zero ohm resistors when no VREF margining circuit stuffed

- =PP3V3_S3_VREFMRGN

- =PPDDR_S3_MEMVREF

- =I2C_VREFDACS_SCL

- =PPVTT_S3_DDR_BUF

- =I2C_VREFDACS_SDA- =I2C_PCA9557D_SCL- =I2C_PCA9557D_SDA


VREFCA:LDO - LDO outputs sent to CA inputs.

VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.

VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.

VREFDQ:LDO - LDO outputs sent to DQ inputs.

DDRVREF_DAC - Stuffs Apple margining circuit.

Addr=0x30(WR)/0x31(RD)

10mA max load

NOTE: MEMVREG and FRAMEBUF share

a DAC output, cannot enable

D

6

0.000V - 3.000V (0x00 - 0x74)

1.000V - 2.000V (+/- 500mV)

MEM VREG

D

5

0.000V - 1.501V (0x00 - 0x74)

C

0.300V - 1.200V (+/- 450mV)

B

2

ADAC Channel:

Nominal value

PCA9557D Pin:

(OD)

4

MEM A VREF CA

1.51mV / step @ output

+6.0mA - -5.0mA (- = sourced)

1.056V - 1.442V (+/- 180mV)

GPU Frame Buffer (1.8V, 70% VRef)

0.000V - 3.300V (0x00 - 0xFF)

1.267V (DAC: 0x8B)

NOTE: Must not enable more than two SO-DIMM margining

buffers at once or VRef source may be overloaded.

C

3

watchdog will disable margining.

MEM B VREF CA

8.59mV / step @ output

6 68

CERM10V

402

20%

DDRVREF_DAC

0.1UF

MF-LF

DDRVREF_DAC

402

1/16W1%

33.2K

100K

MF-LF402

5%1/16W

DDRVREF_DAC

100K

MF-LF

5%1/16W

402

DDRVREF_DAC

DDRVREF_DAC

CRITICAL

UCSPMAX4253

DDRVREF_DAC

UCSPMAX4253

CRITICAL

UCSPMAX4253

CRITICAL

DDRVREF_DAC

DDRVREF_DAC

UCSPMAX4253

CRITICAL

DDRVREF_DAC

CRITICAL

MAX4253UCSP

MAX4253

CRITICAL

UCSP

DDRVREF_DAC

1%1/16WMF-LF


402

VREFCA:LDO_DAC

200

1/16W

200

1%

402MF-LF


VREFCA:LDO_DAC

OMIT

NONE

NONENONE

402

SHORT

OMIT

NONE402

NONENONE

SHORT

24

402


1%

200

1/16WMF-LF

VREFDQ:LDO_DAC

PLACE_NEAR=R3403.2:1mmMF-LF

1%1/16W

133

402

VREFDQ:LDO_DAC

402

200 PLACE_NEAR=J3100.1:2.54mm

MF-LF

1%1/16W

VREFDQ:LDO_DAC

1%

133

1/16WMF-LF402


VREFDQ:LDO_DAC

402

DDRVREF_DAC

1/16W5%

MF-LF

0

DDRVREF_DAC

0

MF-LF402

5%1/16W

VREFDQ:M1_M3

10%

X5R

0.1UF

402

16V

PLACE_NEAR=Q3420.3:2mmVREFDQ:M1_M3

SSM6N15FEAPE

SOT563

CRITICAL

VREFDQ:M1_M3

PLACE_NEAR=Q3420.6:2mm

0.1UF10%

402

16VX5R

VREFDQ:M1_M3

CRITICAL

SOT563

SSM6N15FEAPE


402MF-LF1/16W1%1K

VREFDQ:M1_M3

PLACE_NEAR=R3441.2:1mm1%1/16W

1K

402

VREFDQ:M1_M3

MF-LF

1K

1/16WMF-LF

VREFDQ:M1_M3

402

1%


1/16W1%1K

VREFDQ:M1_M3


MF-LF402

100K

1/16WMF-LF

5%

402

DDRVREF_DAC

100K

402

5%1/16WMF-LF

DDRVREF_DAC

402MF-LF

1% PLACE_NEAR=R3409.2:1mm

133

1/16W

VREFCA:LDO_DAC

MF-LF402

5%100K

1/16W

DDRVREF_DAC

QFN

CRITICAL

PCA9557

DDRVREF_DAC

DDRVREF_DAC

0.1UF20%10V

402CERM

1/16WMF-LF402

1%

133


VREFCA:LDO_DAC

100K

1/16WMF-LF

5%

402

DDRVREF_DAC

48

48

MSOP

DAC5574

DDRVREF_DAC

CRITICAL

48

48

CERM

20%10V

0.1UF

402

DDRVREF_DAC

6.3V20%

2.2UF

CERM402-LF

DDRVREF_DAC

0.1UF

402

10VCERM

20%

DDRVREF_DAC

CERM10V

402

20%0.1UF

DDRVREF_DAC


DDR3/FRAMEBUF VREF MARGINING

SYNC_MASTER=J31_ANNE

VREFDQ:M1_DACR3404,R34062 RES,MTL FILM,332,1%,0402,SM,LF114S0171

RES,MTL FILM,1K,1%,0402,SM,LF114S0218 VREFDQ:M1_DACR3421,R3422,R3441,R34424

RES,MTL FILM,0,5%,0402,SM,LF116S0004 VREFCA:LDOR3409,R34112

RES,MTL FILM,0,5%,0402,SM,LF116S0004 VREFDQ:LDO2 R3403,R3405

VREFMRGN_SODIMMS_CA

VREFMRGN_MEMVREG_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_DQ_SODIMMB_EN

=PP3V3_S3_VREFMRGN

VREFMRGN_SODIMMB_DQ

VREFMRGN_DQ_SODIMMA_EN


VOLTAGE=3.3V

PP3V3_S3_VREFMRGN_CTRL

DDRREG_FB

PP0V75_S3_MEM_VREFDQ_A


=I2C_VREFDACS_SCL

=I2C_PCA9557D_SCL

PPCPU_MEM_VREFDQ_B


VREFMRGN_FRAMEBUF_BUF_RVREFMRGN_MEMVREG_FBVREF_R

MIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.75V


=I2C_PCA9557D_SDA

=I2C_VREFDACS_SDA

=PPDDR_S3_MEMVREF

VREFMRGN_SODIMMA_DQ

PPCPU_MEM_VREFDQ_A

VREFMRGN_FRAMEBUF_BUF

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPP3V3_S3_VREFMRGN_DAC

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mmPP0V75_S3_MEM_VREFDQ_A


VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_BUF

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mmPP0V75_S3_MEM_VREFCA_B


=PPVTT_S3_DDR_BUF

MIN_LINE_WIDTH=0.3 mmPP0V75_S3_MEM_VREFCA_A

MIN_NECK_WIDTH=0.2 mmVOLTAGE=0.75V

VREFMRGN_MEMVREG_FBVREF

=PPDDR_S3_MEMVREF


VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_MEMVREG_EN

VREFMRGN_FRAMEBUF_EN

PCA9557D_RESET_L

VREFMRGN_DQ_SODIMMB_BUF

U3401

3

4

5

8

6

7

9

10

11

12

13

14

15

1

2

17

16

C3403 1

2

C3402 1

2

R34021

2

R34011

2

R34101 2

R34071

2

C3404 1

2

R34121 2

R34081

2

U3400

9

10

3

6

7

8

1

2

4

5

C34011

2

C3400 1

2

C3405 1

2 R34141 2

R34131

2

R34151

2

U3402

C3

C2

C1

C4

B1

B4

U3403

A3

A2

A1

A4

B1

B4

U3402

A3

A2

A1

A4

B1

B4

U3403

C3

C2

C1

C4

B1

B4

U3404

A3

A2

A1

A4

B1

B4

U3404

C3

C2

C1

C4

B1

B4

R34091 2

R34111 2

R34181 2

R34191 2

R34031 2

R34041 2

R34051 2

R34061 2

R34171

2

R34161

2

C34401

2

Q3420

3

54

C34201

2

Q3420

6

21

R34221

2

R34421

2

R34211

2

R34411

2

051-9585

3.0.0

34 OF 132

31 OF 105

7

27 31 93

26 31

9 93

26 31

29 31 93

7 31

9 93

27 31 93

29 93

7 68

27 93

7 31

29 31 93

BI

BI

IN

BI

SYM_VER-1

IN

IN

OUT

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE +-

PAD

(OD)

0.7V

DLY

IN

IN

IN

IN

SYM_VER-1

OUT

OUT

OUT

OUT

IN

VCC

GND

SEL OE*

D+

D-

Y+

Y-

M+

M-

BI

BI

OUT

D

G S

IN

G

SD

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



155S0367

BLUETOOTH

516S0582

CHANNEL

3V S3 WLAN FET

1 A (EDP)

206 mA nominal max

518S0815

Delay = 60 ms +/- 20%

275 mA peak

Supervisor & CLKFREG # ISolation

CAMERA

ALS

H USB_BT

P-TYPE

TPCP8102

LOADING

MOSFET

20-30 MOHM @2.5VRDS(ON)

L USB_BT_WAKE

SEL OUTPUT

AIRPORT

PLACE_NEAR=J3502.6:2.54MM

FERR-120-OHM-1.5A

0402-LF

0.1uF

CERM402

20%10V

18 95

18 95

48

48

DLP0NS


CRITICAL

90-OHM

CRITICAL

819Q-3506-K281F-RT-SM1

24

18 23 74

16

10VCERM

0.1uF20%

402

CRITICAL

TDFN

SLG4AP016V1/16W

402MF-LF

1%232K100K

MF-LF

1%1/16W

402

1/16W

100K

MF-LF

1%

402

16 96

16 96


0.1UF10% 16V

X5R-CERM 020110%

PLACE_NEAR=J3501.17:2.54mm0.1UF

0201X5R-CERM

16V

16 96

16 96


CRITICAL

DLP11S330-OHM-80MA

FERR-120-OHM-1.5A0402-LF

BTPWR:S4


10%16VCERM

0.01UF

402

6 45 46

6 17 24

500913-0302

F-ST-SM

CRITICAL

16 96

16 96

0

MF 2015% 1/20W

0

MF 2015% 1/20W

NOSTUFF

15K

1/20W

201

1%

MF1/20WMF201

15K1%

NOSTUFF

BTPWR:S4

201

1/20W

0

MF

5%

17 26 45 74

05%

MF201

1/20W

BTPWR:S3

1/20WMF201

15K1%

NOSTUFF

TQFNPI3USB102ZLE

CRITICAL

NOSTUFF

0.01UF10%10VX5R201

BTPWR:S4

15K

MF201

1%1/20W

NOSTUFF

15K

MF201

1%1/20W

201

15K

MF

1%1/20W

BTPWR:S4

8 95

8 95

201

10%0.1UF

X5R6.3V

46

BTPWR:S4

CRITICAL

SSM3K15AMFVAPE

VESM

74

MF-LF

5%1/16W

10K

402

10%0.033UF

X5R16V

402

MF-LF1/16W5%

402

33K0.1UF

X5R

10%

402-1

16V


402

CERM10V20%

0.1uF

FERR-120-OHM-3A

0603


CERM

0.1uF20%10V

402

CRITICAL

DFN2563-6

DMP2018LFK

402

5%511/16WMF-LF

402MF-LF1/16W

515%

SM


X19/ALS/CAMERA CONNECTOR

WIFI_EVENT_L

PCIE_AP_D2R_R_N

AP_TEMP_SMB_SCL_PD

AP_CLKREQ_Q_L

AP_RESET_CONN_L

PCIE_WAKE_L

PCIE_AP_R2D_P

PCIE_AP_D2R_R_P

AP_TEMP_SMB_SDA_PD

PCIE_CLK100M_AP_CONN_N

PCIE_CLK100M_AP_CONN_P

USB_BT_CONN_P

PP3V3_S3RS4_BT_F


USB_CAMERA_CONN_P

PP3V3_WLAN_FBTMUX_SEL

USB_BT_CONN_N

USB_BT_WAKEN

USB_BT_WAKEP

=PP3V3_S4_BT

MIN_LINE_WIDTH=1 mm

PP3V3_WLANMIN_NECK_WIDTH=0.4 mm

=PP3V3_S4_BT

P3V3WLAN_SS

PM_SLP_S4_L

PCIE_CLK100M_AP_N

P3V3WLAN_VMON

=PP3V3_S3_WLAN

=BT_WAKE_L

USB_BT_N

USB_BT_P

AP_RESET_L

PM_WLAN_EN_L

AP_PWR_EN

AP_CLKREQ_L

=PP3V3_S3_WLAN

=PP5V_S3_ALSCAMERA

=I2C_ALS_SCL

USB_CAMERA_CONN_N

=I2C_ALS_SDA

USB_CAMERA_N

USB_CAMERA_P

PCIE_AP_R2D_C_N

PCIE_AP_R2D_C_P

PCIE_AP_R2D_N

PCIE_CLK100M_AP_P

PP5V_S3_ALSCAMERA_FMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mm

PP3V3_WLAN_F

MIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.4 mm

PCIE_AP_D2R_N

MIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.5 mm

PP3V3_WLAN_R

PCIE_AP_D2R_P

L3508

12

C35521

2

L3507

1 2

34

J3502

7

8

1

2

3

4

5

6

C35401

2

U3540

6

5

7

3

8

4

2

9

1

R35541

2

R35531

2

R35551

2

C35311 2

C3530

1 2

L3501

1 2

34

L3505

12C35321

2

J3501

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

4

56

78

9

R35101 2

R35111 2

R35161

2

R35151

2

R35191 2

R35181

2

R35171

2

U3510

6

7

3

4

5

810

9

2

1

C3511 1

2

R35141

2

R35131

2

R35121

2

C35101

2

Q35103

12

R35511

2

C3551 1

2

R35501 2

C3550

1 2

C3521 1

2

L3504

1 2

C3522 1

2

Q3550

4

3

12

R35201

2

R35211

2

XW3552

12

051-9585

3.0.0

35 OF 132

32 OF 105

96

6

6

6 96

96

6 101

6 101

6 95

6

6 95

32

6 95

7 32

6 46

7 32

7 32

7 32

7

6 95

6 96

6

32

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT

OUT

IN

IN

IN

OUT

IN

IN

OUT

OUT

BI

DPSNK0_ML_LANE_3P

DPSNK0_ML_LANE_3N

DPSNK0_ML_LANE_2P

DPSRC0_HOT_PLUG_DET

TEST_POINT_2

TEST_POINT_3

DPSNK0_HOT_PLUG_DET

DPSNK0_AUX_CHN

DPSNK0_AUX_CHP

DPSNK0_ML_LANE_0N

DPSNK0_ML_LANE_0P

DPSNK0_ML_LANE_1N

DPSNK0_ML_LANE_1P

DPSNK0_ML_LANE_2N

TEST_POINT_0

TEST_EN

THERM_DP

EE_CLK

EE_CS*

EE_DO

EE_DI

PCIE_CLKREQ_3*

PCIE_CLKREQ_2*

PCIE_CLKREQ_1*

PCIE_CLKREQ_0*

DPSNK1_ML_LANE_1P

DPSNK1_ML_LANE_2N

DPSNK1_ML_LANE_2P

DPSNK1_ML_LANE_3N

DPSNK1_ML_LANE_3P

DP_RES_1

DP_RES_0

DP_ATEST

DPSRC0_AUX_CHN

DPSRC0_AUX_CHP

DPSRC0_ML_LANE_0N

DPSRC0_ML_LANE_0P

DPSRC0_ML_LANE_1N

DPSRC0_ML_LANE_1P

DPSRC0_ML_LANE_2N

DPSRC0_ML_LANE_2P

DPSRC0_ML_LANE_3N

DPSRC0_ML_LANE_3P

TMU_CLK_OUT

TMU_CLK_IN

XTAL_25_IN

XTAL_25_OUT

REFCLK_100_IN_P

REFCLK_100_IN_N

TDO

TCK

TMS

TDI

PCIE_RST_3*

PCIE_RST_1*

PCIE_RST_2*

PCIE_RST_0*

RBIAS

RSENSE

PERST*

WAKE*

PER_1_P

PER_2_P

PER_3_P

MONDC0

MONOBSN

MONOBSP

MONDC1

PER_3_N

PER_2_N

PER_0_N

PER_0_P

PET_3_P

PET_3_N

PET_2_N

PET_2_P

PET_1_P

PET_1_N

PET_0_N

PET_0_P

TEST_POINT_1

DPSNK1_ML_LANE_0N

PER_1_N

DPSNK1_ML_LANE_0P

DPSNK1_ML_LANE_1N

DPSNK1_AUX_CHP

DPSNK1_HOT_PLUG_DET

DPSNK1_AUX_CHN

PRT0_T29T_N

PRT0_T29R_P

PRT0_T29R_N

T29_0_LSEO

T29_0_LSOE

PRT1_T29T_P

PRT1_T29T_N

PRT1_T29R_P

PRT1_T29R_N

T29_1_LSEO

T29_1_LSOE

T29_SDA

T29_SCL

PRT2_T29T_P

PRT2_T29T_N

PRT2_T29R_P

PRT2_T29R_N

T29_2_LSEO

T29_2_LSOE

PRT3_T29T_P

PRT3_T29T_N

PRT3_T29R_P

PRT3_T29R_N

T29_3_LSEO

T29_3_LSOE

PRT0_T29T_P

PORT2

PCIE GEN2

RECEIVE

TRANSMIT

PORTS

(SYM 1 OF 2)

JTAG

POWER ON RESET

MISC

CLOCKS

SOURCE PORT 0

DISPLAY

PORT3

PORT0

PORT1

CLK REQUEST

EEPROM

TEST PORT

SINK PORT 0

SINK PORT 1

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

IN

IN

IN

OUT

IN

C

VCC

THMVSS PAD

D Q

S_L

W_L

HOLD_L

OUT

IN

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Apple Inc.


124578

B

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C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(TBT_SPI_MISO)

together. Other signals okay to float (TP/NC).

NOTE: All unused LSOE/EO pairs should be aliased

SNK1 AC Coupling

SNK0 AC Coupling

(TBT_SPI_MOSI)

(TBT_SPI_CLK)

(TBT_SPI_CS_L)

100pF SRF > 40MHz

Use B1 GND ball for THERM_DN

DEBUG: For monitoring clock

DEBUG: For monitoring current/voltage

Not used in host mode.3.3K

MF-LF402

5%1/16W

402

1/16W1%

MF-LF

14.0K 402

BYPASS=U3600.Y19::2mm

5%50VCERM

100PF 0.01UF

402CERM16V10%

BYPASS=U3600.Y19::5.08mm

82 86

82 86

402MF-LF1/16W5%0

MF-LF402

100K

1/16W5%

87

87 98

87 98

87

6 87 98

6 87 98

6 87 98

87 98

6 87 98

87 98

8

8 98

8 98

8

8 98

8 98

8 98

8 98

8 98

8 98

402MF-LF

100K

1/16W5%

1/16W

402

100K

MF-LF

5%

5%10K

402

NO STUFF

MF-LF1/16W

48 98

48 98

T29FCBGA

CRITICAL

OMIT_TABLE

MF-LF

5%0

402

1/16W

1/16WMF-LF402

5%3.3K

1/16W5%10K

402MF-LF

402

5%1/16WMF-LF

10K

MF-LF

10K

1/16W

402

5%1/16W5%10K

MF-LF402

X5R16V

0.1uF10%

402

6 81 98

6 81 98

6 81 98

6 81 98

6 81 98

6 81 98

6 81 98

6 81 98

6 81 98

6 81 98

0.1uF X5R10% 16V

402

X5R0.1uF16V402

10%

4020.1uF X5R10% 16V

40216V

X5R0.1uF10%

0.1uF10%

402X5R16V

402X5R16V10%

0.1uF

X5R0.1uF10% 16V

402

1/16WMF-LF402

1K1%

0.1uF16V402X5R

10%

16V4020.1uF

10%X5R

16V402X5R

10%0.1uF

16V402X5R

10%0.1uF

40216V10%

X5R0.1uF

16V402

10%0.1uF X5R

16V402

10%X5R0.1uF

16V402X5R

10%0.1uF

16V402

10%X5R0.1uF

16V402X5R

10%0.1uF

16V402X5R

10%0.1uF

16V10%0.1uF X5R 402

6 81 98

6 81 98

6 81 98

6 81 98

6 81 98

6 81 98

6 81 98

6 81 98

402CERM

10%1UF

6.3V

6 81 98

6 81 98

10K 402MF-LF1/16W5%

8 19

16

8

8

1K

402

5%1/16WMF-LF

1%

806

402

1/16WMF-LF

24

MLPM95320-RMB6TG

CRITICAL

OMIT_TABLE

87

87

8

8

X5R10% 6.3V 2010.1UF

X5R10%0.1UF

6.3V 201

X5R10%0.1UF

6.3V 201

X5R0.1UF

6.3V 20110%

X5R10%0.1UF

6.3V 201

X5R10%0.1UF

6.3V 201

X5R10%0.1UF

2016.3V

X5R10%0.1UF

6.3V 201

X5R10%0.1UF

6.3V 201

X5R10%0.1UF

6.3V 201

X5R10%0.1UF

6.3V 201

X5R10%0.1UF

6.3V 201

X5R10%0.1UF

6.3V 201

X5R10%0.1UF

6.3V 201

X5R10%0.1UF

6.3V 201

35

16 96

16 96

X5R10%0.1UF

2016.3V

3.3K5%

402

1/16WMF-LF1/16W

5%

MF-LF402

3.3K

35

8 96

8 96

8 96

8 96

8 96

8 96

8 96

8 96

8 96

8 96

8 96

8 96

8 96

8 96

8 96

8 96

Thunderbolt Host (1 of 2)

SYNC_MASTER=T29_REF SYNC_DATE=06/14/2011

TP_DP_TBTSRC_ML_CN<3>


DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK0_ML_N<0>

TBT_D2R_P<0>

TBT_R2D_C_N<0>

TBT_DP_RES

TBT_GPIO<2>


TBT_RBIAS

TBT_RSVD

TBT_TEST_POINT_3

TP_TBT_TEST_POINT_0

TP_TBT_THERM_DP

TBT_LSOE<0>


TBT_LSEO<0>

TBT_D2R_P<1>

TBT_R2D_C_N<1>

TBT_R2D_C_P<1>

DP_TBTSNK1_AUXCH_P

TP_DP_TBTSRC_ML_CP<3>

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_P<3>

TP_TBT_MONDC0

TP_TBT_MONDC1

TP_TBT_MONOBSP

TBT_GPIO<1>

TBT_SPI_CLK

TBT_TEST_EN

=TBT_CLKREQ_L

TBT_SPI_MISO

TBT_SPI_CS_L

TP_TBT_TEST_POINT_2





TP_TBT_MONOBSN

PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_P<1>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_N<3>PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_C_P<3>PCIE_TBT_D2R_P<3>



PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>



PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_N<3>

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<2>PCIE_TBT_R2D_P<2>

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_C_N<0>PCIE_TBT_R2D_N<0>

PCIE_TBT_R2D_P<0>

TBT_RSENSE

TBT_R2D_C_P<2>

TBT_R2D_C_N<2>

TBT_D2R_P<2>

TBT_LSEO<2>

TBT_D2R_N<2>

TBT_LSOE<2>

TBT_R2D_C_P<3>

TBT_R2D_C_N<3>

TBT_D2R_P<3>

TBT_D2R_N<3>

TBT_LSEO<3>

TBT_LSOE<3>

DP_TBTSRC_HPD

TBT_DP_ATEST

TP_DP_TBTSRC_AUXCH_CP

TP_DP_TBTSRC_AUXCH_CN

SYSCLK_CLK25M_TBT

PCIE_CLK100M_TBT_N

PCIE_CLK100M_TBT_P

JTAG_TBT_TDO

JTAG_TBT_TCK

JTAG_TBT_TMS

JTAG_TBT_TDI

SYSCLK_CLK25M_TBT_R




TP_TBT_XTAL25OUT

TBT_TMU_CLK_IN

TBT_TMU_CLK_OUT

=PP3V3_TBT_RTR

TBT_RESET_L

TBT_PCIE_WAKE_L

=PP3V3_TBT_RTR

I2C_TBT_SCL

I2C_TBT_SDA

TBT_LSOE<1>

TBT_LSEO<1>

TBT_D2R_N<1>

TBT_D2R_N<0>

TBT_R2D_C_P<0>

DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<3>

=PP3V3_TBT_RTR

TBT_SPI_MOSI

TBTROM_HOLD_L

TBTROM_WP_L

PCIE_TBT_R2D_C_P<0>

TP_TBT_TEST_POINT_1

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<3>

















DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_AUXCH_N

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_HPD

DP_TBTSNK1_HPD

R36901

2

C3690 1

2

R36921

2

R36911

2

R36991

2

R36551

2

C3600 1 2

R36851

2

C3685 1

2

C36861

2

R36251

2

R36321

2

R36301

2

R36311

2

U3600

Y19

Y21

AA20

W2

V1

V5

Y9

AA10

Y7

AA8

Y5

AA6

Y3

AA4

U6

V7

U4

U14

V15

U12

V13

U10

V11

U8

V9

U16

W16

V3

Y11

AA12

Y13

AA14

Y15

AA16

Y17

AA18

L2

N2

P1

M1

B21

A20

M17

K17

P3

N4

M3

L4

K1

J2

K3

J4

T19

V19

M19

P19

H19

K19

D19

F19

E6

T21

V21

M21

P21

H21

K21

D21

F21

C2

C4

A4

A6

C6

C8

A8

A10

C10

C12

A12

A14

C14

C16

A16

A18

E16

G16

H17

E14

J6

K5

G6

H5

G4

H3

G2

H1

F5

F3

R2

T3

T1

E4

P5

N6

M5

L6

A2

R4

E2

U2

F1

P17

R16

R36291

2

R36931

2

R36981

2

R36231

2

R36221

2

R36211

2

C3629 1 2

C3628 1 2

C3627 1 2

C3626 1 2

C3625 1 2

C3624 1 2

C3623 1 2

C3622 1 2

C3621 1 2

C3620 1 2

C3630 1 2

C3631 1 2

C3632 1 2

C3633 1 2

C3634 1 2

C3635 1 2

C3636 1 2

C3637 1 2

C3638 1 2

C3639 1 2

R3651 2 1

R36961

2

R36951 2

U36906

5

7

2

1

9

8

4

3

C3601 1 2

C3602 1 2

C3603 1 2

C3604 1 2

C3605 1 2

C3606 1 2

C3607 1 2

C3640 1 2

C3641 1 2

C3642 1 2

C3643 1 2

C3645 1 2

C3644 1 2

C3646 1 2

C3647 1 2

051-9585

3.0.0

36 OF 132

33 OF 105

6

6

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6

6

6 33 98

6

96

96

6

6

6

98

98

98

6

6

6

6

6

96

96

96

96

96

96

96

96

96

96

96

96

96

96

6

6

6

6

6

7 33 34 35

7 33 34 35

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

7 33 34 35

98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

VCC3P3_DP_RX1

VCC3P3_DP_RX1

VCC3P3_DP_TXRX

VCC3P3_DP_TXRX

VDD3P3DP_PLL

VCC3P3_DP_TXRXBIAS

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP_PLL

VSSDP

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VDD1P0_DP_TXRX

VDD1P0_DP_RX1

VDD1P0_DP_TXRX

VDD1P0_DP_PLL

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VCC1P0_PE

VCC1P0_PE

VCC3P3

VCC3P3

VCC3P3

VCC3P3_T29

VCC3P3_T29

GND

VCC

(SYM 2 OF 2)

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EDP: 200 mA

135 mA (Single-Port)

152 mA (Dual-Port)

Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.

2100 mA (Single Port)

2250 mA (Dual Port)

EDP: 3000 mA

FERR-120-OHM-1.5A

0402

10%

402CERM

1UF

6.3VCERM402

10%6.3V

1UF 1UF

CERM402

10%6.3V

402-LF

2.2UF20%6.3VCERM

1UF

CERM402

10%6.3V

1UF

CERM402

10%6.3V

1UF

CERM402

10%6.3V

6.3V10%

402CERM

1UF

6.3V20%

603X5R

10UF

X5R603

10UF20%

6.3V1UF

CERM402

10%6.3V

1UF

CERM402

10%6.3V

1UF

CERM402

10%6.3V

1UF

CERM402

10%6.3V

6.3V10%

402CERM

1UF

402-LF

2.2UF20%

CERM6.3V

402

10%1UF

6.3VCERM

FERR-120-OHM-1.5A

0402

1UF

402

10%6.3VCERM

6.3V10%

402

1UF

CERM

6.3V10%

402CERM

1UF

X5R

10UF20%6.3V

603

10UF

X5R603

20%6.3V

CERM

1UF

402

10%6.3V 6.3V

10%

402CERM

1UF

T29

CRITICAL

OMIT_TABLE

FCBGA

CERM402

10%6.3V

1UF 1UF

6.3V10%

402CERM

1UF

6.3V10%

402CERM

Thunderbolt Host (2 of 2)

SYNC_DATE=06/14/2011SYNC_MASTER=T29_REF

=PP3V3_TBT_RTR

=PP1V05_TBT_RTR

PP1V05_TBT_VDD_DPPLL

VOLTAGE=1.05V


PP3V3_TBT_DPBIAS

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm

C37091

2

C37101

2

C37111

2

C37051

2

C37061

2

C37071

2

L3730

1 2

C37121

2

C37131

2

C37141

2

C37301

2

C37201

2

C37211

2

C37221

2

C37081

2

C3700 1

2

C3701 1

2

C3753 1

2

C3752 1

2

C3744 1

2

C3743 1

2

C3770 1

2

C3760 1

2

L3770

1 2

C3751 1

2

C3750 1

2

C3745 1

2

C37461

2

C37471

2

U3600H9

H11

H13

K9

K11

K13

M9

M11

M13

H15

K15

M15

E8

E10

E12

G14

H7

M7

K7

P7

R6

P9

P11

P15

G10

G12

R14

R8

R10

R12

P13

G8

J8

N10

N12

N14

J10

J12

J14

L8

L10

L12

L14

N8

T5

T7

W10

W12

W14

Y1

AA2

T9

T11

T15

T17

V17

W4

W6

W8

T13B1

B3

C18

C20

D1

D3

D5

D7

D9

D11

D13

D15

B5

D17

E18

E20

F7

F9

F11

F13

F15

F17

G18

B7

G20

J16

J18

J20

L16

L18

L20

N16

N18

N20

B9

R18

R20

U18

U20

W18

W20

B11

B13

B15

B17

B19

051-9585

3.0.0

37 OF 132

34 OF 105

7 33 35

7 104

GND

VOUT

ON

VIN

OUT

OUT

IN

IN

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE+-

PAD

(OD)

0.7V

DLY

IN

IN

IN

D

G S

D

S G

D

S G

IN

S

G

D

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND GND

NC

SNS1

SNS2

VOUT

GNDON

VIN

Apple Inc.


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SGND shorted to

GND inside package,

no XW necessary.

Thunderbolt 15V Boost Regulator

Vout = 15.47V<Ra>

<Rb>

UVLO(rising) = UVLO(falling) + (2uA * R1)

UVLO(falling) = 1.22 * (R1 + R2) / R2

UVLO = 4.55V (falling), 4.95 (rising)

- =PP3V3_S0_P3V3TBTFET (3.3V FET Input)

- =PP3V3_TBT_FET (3.3V FET Output)

- =PP3V3_S0_TBTPWRCTL

- =PP1V05_S0_P1V05TBTFET (1.05V FET Input)

- =PP1V05_TBT_FET (1.05V FET Output)

- =PPVIN_SW_TBTBST (8-13V Boost Input)

- =PP15V_TBT_REG (15V Boost Output)



Platform (PCIe) Reset

Power aliases required by this page:

Page Notes

- =TBT_CLKREQ_L

- =TBT_RESET_L

TBTBST:Y - Stuffs 15V boost circuitry.

for 2S.

8-13V Input

Changes required

<R2>

Max Vgs: 10V

Max Current = 2A (85C)

Max Current = 4A (85C)

@ 1.05V

@ 2.5V

R(on)

11.5 mOhm Max

8 mOhm Typ

24 mOhm Max

18.3 mOhm Typ

1.05V Thunderbolt Switch

3.3V Thunderbolt Switch

DLY = 60 ms +/- 20%

U3810

Load Switch

TPS22924C

TPS22920

U3815

Load Switch

R(on)

Part

Type

Part

Type

Pull-ups provided by SB page.

Supervisor & CLKREQ# Isolation

Open-Drain GPIO

Rds(on): 46mOhm @ 4.5V Vgs

Voltage not specified here,add property on another page.

SI8409DB:

Vds(max): -30V

Vgs(max): +/-12V

Vgs(th): -1.4V

Id(max): 3.7A @ 70C

<R1>

Max Current = 1A

Freq = 300KHz

Vout = 1.6V * (1 + Ra / Rb)

CRITICAL

CSPTPS22924

33

1/16W

10K5%

MF-LF402

16

402

25VX5R

10%0.1UF

24

33

6.3V10%1UF

CERM402

402CERM6.3V10%1UF

TDFN

CRITICAL

SLG4AP016V

100K5%1/16WMF-LF402

19

24

87 88

TBTBST:Y

330K

1/16WMF-LF

5%

402

TBTBST:Y

470K

1/16W5%

402MF-LF

TBTBST:Y

X5R

10%25V

0.1UF

402

TBTBST:Y

SOD-VESM-HF

SSM3K15FV

402

1%

MF-LF

TBTBST:Y

73.2K

1/16W

1/16W5%

402MF-LF

330K

TBTBST:Y

SSM6N37FEAPESOT563

TBTBST:Y

SOT563

TBTBST:Y

SSM6N37FEAPE

TBTBST:Y

1/16WMF-LF

1%41.2K

402CERM-X5R6.3V10%

TBTBST:Y

402

0.33UF

TBTBST:Y

330K5%

402

1/16WMF-LF

45 46 92

NO STUFF

100PF

50VCERM

5%

402 402

1/16W

15.8K

MF-LF

1%

TBTBST:Y

TBTBST:Y

4.7UF10%50VX7R-CERM1206

TBTBST:Y

50V

4.7UF

X7R-CERM1206

10%

TBTBST:Y

4.7UF10%

1206X7R-CERM50V

402

50V5%

TBTBST:Y

CERM

47PF

805

10%10VX5R

TBTBST:Y

4.7UF

TBTBST:Y

BGASI8409DB

CRITICAL

1%

MF-LF1/16W

402

TBTBST:Y

10K

TBTBST:Y

402

1%200K

1/16WMF-LF

10UF

25V

805X5R

10%

TBTBST:Y TBTBST:Y

10UF10%25VX5R805

10UH-4A-68-MOHM

PCMB063T-100MS

CRITICAL

TBTBST:Y

22PF

402

5%

CERM50V

TBTBST:Y

CRITICAL

TBTBST:Y

LT3957QFN

TBTBST:Y

137K1%

1/16WMF-LF

402

SM


TBTBST:Y

402

05%

MF-LF1/16W

CRITICAL

POWERDI-123

DFLS230L

TBTBST:Y

TBTBST:Y

50VX7R-CERM

4.7UF10%

1206

50VX7R402

0.001UF10%

TBTBST:Y

TBTBST:Y

10%

402

50VCERM

0.0033UF

TPS22920CSP

CRITICAL

1UF10%6.3VCERM402

NO STUFF

MF-LF1/16W

402

5%0

49.9K

MF-LF1/16W1%

TBTBST:Y

402


Thunderbolt Power Support


PPVIN_SW_TBTBST

TBTBST_RT

TBTBST_VC

TBTBST_EN_UVLO

TBTBST_INTVCC

=PPVIN_SW_TBTBST

TBT_A_HV_EN

=PP3V3_TBT_FET

=PP1V05_TBT_FET

TBT_PWR_EN_RC



TBT_RESET_L

=TBT_CLKREQ_L

MAKE_BASE=TRUETBT_CLKREQ_ISOL_L

PP1V05_TBT

=PP3V3_TBT_RTR

=PP3V3_S0_TBTPWRCTL

TBT_SW_RESET_L

TBT_CLKREQ_L

=TBT_RESET_L

TBT_PWR_EN

TBTBST_PWREN_L

TBTBST_SHDN_DIV

SMC_DELAYED_PWRGD

TBTBST_SS

TBTBST_PWREN_DIV_L

TBTBST_VC_RC

TBTBST_BOOST

DIDT=TRUE

MIN_NECK_WIDTH=0.25 mmSWITCH_NODE=TRUE


TBTBST_SNS1

TBTBST_SNS2

TBTBST_FBX

TBTBST_VSNS_RC TBTBST_VSNS

=PP15V_TBT_REG

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmGND_TBTBST_SGND

VOLTAGE=0V

U3810

C1

C2

A2

B2

A1

B1

R38032

1

C3800 1

2

C3810 1

2

C3815 1

2

U3800

6

5

7

3

8

4

2

9

1 R38071

2

R38811

2

R38801

2

C38801

2

Q38053

12

R38921

2

R38871

2

Q38883

54

Q38886

21

R38941

2

C38941

2

R38881

2

C38891

2

R38961

2

C38951

2

C3896 1

2

C38971

2

C38871

2

C3892 1

2

Q3880

23

1

4

R38931

2

R38911

2

C3890 1

2

C3891 1

2

L3895

1 2

C38881

2

U389025

31

12

13

14

15

16

17

28

1

2

10

35

36

33

6

3

4 23

24

37

32

8 9

20

21

38

34

30

27

R38951

2

XW3895

12

R38891

2

D3895A

K

C3898 1

2

C38991

2

C38931

2

U3815

D1

D2

A2

B2

C2

A1

B1

C1

C3816 1

2

R38161

2

R389012

051-9585

3.0.0

38 OF 132

35 OF 105

7

7 8

7

7

7

7

7

7 33 34

7

7 8

IN

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

NC

BI

BI

BI

OUT

IN

IN

IN

OUT

OUT

BI

BI

BI

BI

BI

NC

WAKE*

CR_DATA4

CR_DATA5

CR_LED*/CR_BUS_PWR

MS_INS*

CR_DATA7

CR_DATA6

CR_DATA0

CR_WP*

CR_CLK

TRD3_N

TRD3_P

GPIO_0/CR_ACT_LED*

GPIO_1/LR_OUT

GPIO_2/MEDIA_SENSE

SD_DETECT

CR_CMD

PCIE_TXD_P

PCIE_RXD_P

CR_DATA3

CR_DATA2

CR_DATA1

SR_DISABLE

SCLK_SPD1000LED*

SO_LINKLED*

CS*/EECLK

LOW_PWR

SI/EEDATA

BIASVDDH

XTALVDDH

VDDO

SMB_DATA

PERST*

SMB_CLK

PCIE_TXD_N

PCIE_REFCLK_N

AVDDH VDDC

SR_LX

SR_VFB

SR_VDDP

SR_VDD

SPD100LED*/SERIAL_DO

TRAFFICLED*/SERIAL_DI

TRD0_P

TRD1_P

TRD0_N

TRD1_N

TRD2_N

VMAIN_PRSNT

PCIE_RXD_N

PCIE_REFCLK_P

CLKREQ*

THRM_PAD

XTALI

XTALO

RDAC

AVDDL

PCIE_PLLVDDL

GPHY_PLLVDDL

TRD2_P

RESET*

CS*

SCK

SOWP*

SI

GND

VCC

Apple Inc.


124578

B

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8 7 6 5 4 3

C

B

A


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D

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



281mA (1000base-T max power, Caesar IV)

LimitingResistor

(IPD)

(See note)

(IPD)

VDD for Card Reader I/O

Special Star routing needed on these pins. Decoupling on Pg 37.

If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.

BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.

NOTE: Pull-down on SO plus internal pull-ups on

BCM57765 supports both active-levels for WP.

Connect only to U3900 pin 20.

the card reader on-chip I/O.

Must isolate from PCIe WAKE# if PHY

internal SR. IPD has a race condition.

SR_DISABLE must be pulled down to use

No MS (Memory Stick) Insert feature needed.

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for

N-channel FET isolation suggested.

WAKE#

info as well as code for Bonjour proxy.

Required for proper PHY operation.

Internal 1.2V Switching Regulator pins.

If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.

???mA (1000base-T, Caesar V)

ROM contains MAC address, PCIe config

is powered-down in S3/S5. Standard

If PHY is always powered then alias

=ENET_WAKE_L to PCIE_WAKE_L.

(Required ROM size TBD)

PHY Non-Volatile Memory

NOTE: ENETM requires SI pull-down instead of SO.

(OD)

o

(OD)

Current

(IPD)

(OD)

(OD)

(IPD)

(IPU)

(IPU)

Control signal to light LED or control SD bus power.

(IPU)

other 3 SPI pins configures ENET for the

Atmel AT45DB011D (1Mbit) ROM. If a different

ROM is used then the straps must change.

(IPx)

(IPD)

(IPU)

SD_DETECT can only be used active low due to errata.

NOTE: "IPx" == Programmable pull-up/down

402

16V10%

X7R-CERM

0.1UF

X5R

10UF10%

805

6.3V

CRITICAL

X5R-CERM603

10%4.7UF

6.3V

SM

CRITICAL

FERR-600-OHM-0.5A

10%6.3V

603X5R-CERM

4.7UF

SM

CRITICAL

FERR-600-OHM-0.5ASM

FERR-600-OHM-0.5A

CRITICAL

CRITICAL

SM

FERR-600-OHM-0.5A

MF-LF

1K

402

5%1/16W

16 96

16 96

30 97

16

24

24 30

24

0.1uF

402

10%16VX5R

0.1uF

402X5R16V10%

0.1uF

402X5R

10%16V

0.1uF

10%16VX5R402

1%1.24K

MF-LF402

1/16W

16 96

16 96

16 96

16 96

37 97

37 97

37 97

37 97

37 97

37 97

37 97

37 97

MF-LF402

5%4.7K

1/16W5%

402MF-LF1/16W

4.7K

30 97

30 97

30 97

30 97

30 5%

0

402MF-LF1/16W

402

5%

MF-LF1/16W

4.7K

NOSTUFF

30 97

30

X5R-CERM

4.7UF

603

6.3V10%

X7R-CERM

10%0.1UF

402

16V

0.1UF

X7R-CERM402

16V10%

24

MF-LF402

5%1/16W

4.7K

MF-LF5% 402

1K1/16W

30

CRITICAL

SM

FERR-600-OHM-0.5A

30 97

30 97

30 97

16V10%

402X7R-CERM

0.1UF

30 97

30 97

402X7R-CERM

16V10%

0.1UF

QFN-8X8

BCM57765B0

X7R-CERM16V10%

402

0.1UF

10%

402

16VX7R-CERM

0.1UF

X7R-CERM16V

0.1UF10%

402

603X5R-CERM6.3V10%4.7UF

10%16V

0.1UF

X7R-CERM402

SM

FERR-600-OHM-0.5A

CRITICAL

10%6.3V

X5R-CERM603

4.7UF

402

0.1UF

16VX7R-CERM

10%

AT45DB011D

OMIT

SOIC-8S1

1/16W5%

402

4.7K

MF-LF

0.1UF10%16V

402X7R-CERM

0.1UF

X7R-CERM

10%16V

402

SYNC_DATE=10/11/2010SYNC_MASTER=K91_ERIC

ETHERNET PHY (CAESAR IV)

PCIE_ENET_R2D_P

PCIE_CLK100M_ENET_N

TP_BCM57765_SPD100LED_L

ENET_WAKE_R_L

SDCONN_DATA<4>

SDCONN_DATA<5>

ENET_CR_PWREN

TP_CE_L_MS_INS_L

SDCONN_DATA<7>

SDCONN_DATA<6>

SDCONN_DATA<0>

SDCONN_WP

SDCONN_CLK

ENET_MDI_N<3>

ENET_MDI_P<3>

MAKE_BASE=TRUE


VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mm

PP3V3R1V8_ENET_LR_OUT_REG

ENET_MEDIA_SENSE

SDCONN_DETECT_L

SDCONN_CMD

PCIE_ENET_D2R_C_P

SDCONN_DATA<3>

SDCONN_DATA<2>

SDCONN_DATA<1>

BDM57765_SR_DISABLE

BCM57765_SCLK

BCM57765_MOSI

BCM57765_CS_L

ENET_LOW_PWR

BCM57765_MISO

=PP3V3R1V8_ENET_LR_OUT

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mmPP3V3_S3_ENET_PHY_BIASVDDH



MIN_LINE_WIDTH=0.4 mmPP3V3_S3_ENET_PHY_XTALVDDH

=PP3V3_ENET_PHY

BCM57765_SMB_DATA

ENET_RESET_L

BCM57765_SMB_CLK

PCIE_ENET_D2R_C_N


PP3V3_S3_ENET_PHY_AVDDH

=PP1V2_ENET_PHY

ENET_SR_LX

ENET_SR_VFB

TP_BCM57765_TRAFFICLED_L

ENET_MDI_P<0>

ENET_MDI_P<1>

ENET_MDI_N<0>

ENET_MDI_N<1>

ENET_MDI_N<2>

ENET_VMAIN_PRSNT

PCIE_ENET_R2D_N

PCIE_CLK100M_ENET_P

ENET_CLKREQ_L

SYSCLK_CLK25M_ENET

BCM57765_RDAC

VOLTAGE=1.2VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmPP1V2_ENET_PHY_AVDDL

VOLTAGE=1.2VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmPP1V2_ENET_PHY_PCIEPLL


PP1V2_ENET_PHY_GPHYPLL

ENET_MDI_P<2>

=PP3V3_ENET_PHY

=ENET_WAKE_L

BCM57765_SCLK

BCM57765_CS_L

BCM57765_MISO

=PP3V3R1V8_ENET_LR_OUT

BCM57765_MOSI

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

=PP3V3_S0_ENETPHY

L3910

1 2

C39101

2

C39111

2

C39901

2

C39051

2

C39301

2

C3931 1

2

L3930

1 2

C3915 1

2

C39161

2

U3990

4

7

3

2 1

8

6

5

R39971

2

C3936 1

2

C3926 1

2

C3921 1

2

C39351

2

C39251

2

L3925

1 2

C39201

2

L3920

1 2

L3900

1 2

L3905

1 2

R39421

2

C3951

1 2

C3950

1 2

C3956

1 2

C3955

1 2

R39651

2

R39411

2

R39401

2

R39431 2

R39901

2

C39701

2

C39711

2

C39721

2

R39101

2

R3980 1 2

C3900 1

2

U3900

42

48

39

45

51

37

12

21

26

25

24

23

22

52

53

54

55

60

57

63

36

5

8

9

4

59

29

32

30

31

34

33

27

28

11

38

66

1

64

6

10

65

2

68

16

14

15

13

69

67

41

40

43

44

47

46

49

50

20

35

61

7 56

62

58

3

18

19

17

051-9585

3.0.0

39 OF 132

36 OF 105

96

96

36

36

36

36

36

7 24 36 72

96

7

72

72

96

7 24 36 72

36

36

36

36

36

7

BI

RX

TX

BIRX

TX

BI

IO

NC

NC

IO

NC

IO

IO

NC

GND

IO

NC

NC

IO

NC

IO

IO

NC

GND

BI

BI

BI

BI

BI

Apple Inc.


124578

B

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Transformers should be



mirrored on opposite

Place one of 0.1uf cap close to each centertap pin of transformer

514-0636

(NONE)

(NONE)

(NONE)


sides of the board

36 97

CRITICAL

SM

TLA-6T213HF

75

MF-LF

5%1/16W

402

75

MF-LF

5%1/16W

402

75

MF-LF

5%1/16W

402

75

MF-LF

5%1/16W

402

10%2KV

1206CERM

CRITICAL

1000PF

36 97

16VX5R402-1

0.1UF10%

0.1UF16VX5R402-1

10%0.1UF16VX5R402-1

10%

TLA-6T213HF

SM

CRITICAL

0.1UF16VX5R402-1

10%

36 97

CRITICAL

RJ45-M97-3F-RT-TH

NOSTUFF

PLACE_NEAR=T4001.1:5mm

RCLAMP0524P

CRITICAL

SLP2510P8

NOSTUFF

PLACE_NEAR=T4000.5:5mm

RCLAMP0524P

CRITICAL

SLP2510P8

36 97

36 97

36 97

36 97

36 97

SYNC_DATE=05/26/2010SYNC_MASTER=K91_TRINHNI

Ethernet Connector

ENET_MDI_N<0> ENETCONN_N<0>

ENETCONN_N<2>

ENETCONN_N<1>

ENETCONN_P<2>

ENET_CTAP3

ENET_BOB_SMITH_CAPMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm

ENET_CTAP0

ENET_CTAP1

ENETCONN_P<1>

ENET_CTAP2

ENET_MDI_N<1>

ENETCONN_CTAP

ENETCONN_P<0>

ENETCONN_P<3>

ENETCONN_N<3>ENET_MDI_N<3>

ENET_MDI_P<3>

ENET_MDI_P<0>

ENET_MDI_P<2>

ENET_MDI_P<1>

ENET_MDI_N<2>T4001

1

10

11

12

2

3

4

5

6 7

8

9

T40001

10

11

12

2

3

4

5

6 7

8

9

R40001

2

R40011

2

R40021

2

R40031

2C40081 2

C40061

2

C40041

2

C40021

2

C40001

2

J4000

1

10

11

12

2

3

4

5

6

7

8

9

D4001

3

5 4 2 1

D4000

3

5 4 2 1

051-9585

3.0.0

40 OF 132

37 OF 105

10976 10976

101

101

101

101

101

101

101

101

DS2

ATBUSH

ATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMS

TCK

REFCLKN

PCIE_TXD0P

TRST*

ATBUSB

TDI

DS1

TPA0N

TPA0P

AVREG

CE

CLKREQN

FW_RESET*

FW620*

JASI_EN

MODE_A

NAND_TREE

OCR_CTL_V12

PCIE_RXD0N

PCIE_RXD0P

PCIE_TXD0N

PERST*

R0

REFCLKP

REGCLT

REXT

SCIFCLK

SCIFDAIN

SCIFDOUT

SCIFMC

SCL

SDA

SE

SM

TDO

TPA1N

TPA2N

TPA2P

TPB0N

TPB0P

TPB1N

TPB1P

TPB2N

TPB2P

TPBIAS0

TPBIAS1

TPBIAS2

TPCPS

VAUX_DISABLE

VBUF

VDDH VP VREG_PWR

WAKE*

XI

XO

DS0

TPA1P

VDD33VDD10

VREG_VSSVSS

SERIAL EEPROM

MISCELLANEOUS

CONTROLLER

POWER MANAGEMENT

TEST CONTROLLER

PCI EXPRESS PHY

CHIP RESET

SCIF

1394 PHY

NCNCNC

NC

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

NCNC

Apple Inc.


124578

B

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8 7 6 5 4 3

C

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



135 mA

NT-10 (IPD)

(IPD) NT-21

(IPD) NT-18NT-6

NT-2 (IPU)

NT-1 (IPU)

NT-13

FIXME!!! - TYPO IN SYMBOL REGCTL

NT-3 (IPU)

NAND tree order.

NOTE: NT-xx notes show

(IPU)

NT-15 (IPD)

(IPD) NT-11

(IPU) NT-8

138 mA7 mA I/O

114 mA FireWire PHY

0 mA VReg PWR

17 mA PCIe SerDes

NT-4 (IPU)

(OD)

NT-16 (IPD)

NT-17

NT-5

NT-14 (IPD)NT-OUT

(Reserved)

(IPD) NT-19

(IPD) NT-20

(IPU)

NT-12 (IPD)

NT-7

(IPD)

(IPD)

(IPD)

NT-9

25 mA PCIe SerDes

110 mA Digital Core

191

MF-LF

1%1/16W

402

0.33UF

CERM-X5R6.3V

402

10%

470K5%

1/16WMF-LF

402

OMIT

CRITICAL

FW643

BGA

22PF

CERM

5%50V

402

50V

22PF

CERM

5%

402

200K

MF-LF

1%1/16W


402

412

MF-LF

1%1/16W

402

10K

MF-LF

5%1/16W

402

10K

MF-LF

5%1/16W

402

FW643_LDO

10K

MF-LF

5%1/16W

402


0.1UF16V

X5R 402-1

10%

PLACE_NEAR=U1800.BG36:2.54mm

0.1UF16V

X5R 402-1

10%

10K

MF-LF

5%1/16W

402

PLACE_NEAR=U1800.AU34:2.54mm16V

402-10.1UF X5R

10%

0.1UF

PLACE_NEAR=U1800.AV34:2.54mm10% 16V

X5R 402-1

1UF

CERM6.3V

402

10%1UF

CERM6.3V

402

10%

1UF

CERM6.3V

402

10%1UF

CERM6.3V

402

10%

1UF

CERM6.3V

402

10%

1UF

CERM6.3V

402

10%1UF10%6.3VCERM402

1UF

CERM6.3V

402

10%1UF

CERM6.3V

402

10%

6.3V

1UF

CERM402

10%

1UF

CERM6.3V

402

10%

1UF

CERM6.3V

402

10%1UF

CERM6.3V

402

10%

1UF

CERM6.3V

402

10%1UF

CERM6.3V

402

10%1UF

CERM6.3V

402

10%1UF

CERM6.3V

402

10%1UF

CERM6.3V

402

10%

0.1UF

CERM

20%10V

402

1UF

CERM6.3V

402

10%

1UF

CERM6.3V

402

10%

16 96

16 96

16 96

16 96

16 96

16 96

8 39

39

2.94K

MF-LF

1%1/16W

402

40

40

40

40 97

40 97

40 97

40 97

40

40

40 97

40 97

40 97

40 97

40

40

40

39 40

40

120-OHM-0.3A-EMI

0402-LF

120-OHM-0.3A-EMI

0402-LF

39

120-OHM-0.3A-EMI

0402-LF

CRITICAL

SM-3.2X2.5MM24.576MHZ

0

1/16WMF-LF402

5%


FireWire LLC/PHY (FW643)

MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V

PP3V3_FW_FWPHY_VP25

PP3V3_FW_FWPHY_VDDA

VOLTAGE=3.3V


PP1V0_FW_FWPHY_AVDD

VOLTAGE=1.0VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM

TP_FW643_SCIFDAIN

FW643_SCL

TP_FW643_MODE_A

TP_FW643_CE

TP_FW643_JASI_EN

PCIE_CLK100M_FW_N

PCIE_FW_D2R_C_N

TP_FW643_TDO

TP_FW643_NAND_TREE

FW_P0_TPA_N

FW_P0_TPA_P

FW_P0_TPB_P

FW_P1_TPBIAS

=FW_PHY_DS1

=FW_PHY_DS0

=FW_PHY_DS2

FW643_REXT

FW_P2_TPBIAS

FW_P0_TPBIAS

FW_P2_TPB_P

FW_P1_TPB_P

FW_P1_TPB_N

FW_P0_TPB_N

FW_P2_TPA_P

FW_P2_TPA_N

FW_P1_TPA_N

FW_P1_TPA_P

TP_FW643_VBUF

TP_FW643_SM

TP_FW643_FW620_L

TP_FW643_AVREG

TP_FW643_OCR10_CTL

=PPVP_FW_PHY_CPS

FW_CLK24P576M_XOTP_FW643_SCIFMC

TP_FW643_SCIFDOUT

FW_RESET_L

TP_FW643_SDA

FW643_PU_RST_L

FW_P2_TPB_N

FW643_R0

=PP1V0_FW_FWPHY

FW643_TPCPSTP_FW643_SCIFCLK

PCIE_FW_R2D_N

PCIE_FW_R2D_P

TP_FW643_TCK

TP_FW643_TDI

TP_FW643_TMS

=FW_CLKREQ_L

=PP3V3_FW_FWPHY

PCIE_FW_D2R_C_P

PCIE_CLK100M_FW_P

FW643_VAUX_DETECT

FW643_REGCTL

=FW_PME_L

FW643_TRST_L

TP_FW643_VAUX_ENABLE

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_FW_D2R_N

PCIE_FW_D2R_P

TP_FW643_SE

FW_CLK24P576M_XI

FW_CLK24P576M_XO_R

=PP3V3_FW_FWPHY

VOLTAGE=1.0VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP1V0_FW_R

R41701

2

C41621

2

R41621

2

U4100

B13

A13

A11

A10

L13

L2

F12

E12

E13

D12

K13

D1

J2

K1

J12

J13

N8

N7

N5

N6

N4

B11

N9

N10

D13

L8

G2

G1

H1

F2

N12

M11

M13

N13

M4

N2

M1

M3

B8

A8

B5

A5

B3

A3

B9

A9

B6

A6

B4

A4

B7

C3

A2

B10

N1

E1

D2

H13

A1

B1

M12

N3

N11

B12

C13

E2

E10

H2

H12

K2

L1

C1

C12

F1

G12

J1

L3

L11

M2

A12

D5

D6

D8

L5

L10

L6

L9

K12

L12

B2

D4

F7

F8

F10

G4

G6

G7

G8

G10

H4

H6

D7

H7

H8

H10

J4

J5

J9

J10

K4

K5

K7

D9

K8

K9

L7

K6

K10

D10

E4

E5

E9

F4

F6

C2

G13

F13

C4151

1 2

C4150

1 2

R41601

2

R41501 2

R41631

2

R41641

2

R41651

2

C41761 2

C41751 2

R41661

2

C41711 2

C41701 2

C4130 1

2

C4131 1

2

C41001

2

C41011

2

C4132 1

2

C41021

2

C41031

2

C4135 1

2

C4136 1

2

C41041

2

C41101

2

C41051

2

C41061

2

C4120 1

2

C4121 1

2

C4122 1

2

C4123 1

2

C4124 1

2

C4141 1

2

C41111

2

C41401

2

R41611

2

L4130

1 2

L4135

1 2

L4110

1 2

Y4150

24

13

R41001 2

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38 OF 105

6

6

6

96

6

6

6

6

6

40

6

6

6

7 39

6

96

96

6

6

6

7 38 39 40

96

6

6

7 38 39 40

G

D

S

IN

IN

G

D

S

OUT

IN

S

G

D

(SYM-VER2)

G

S (SYM-VER1)

D

GND

VOUT

ON

VIN

GND

VOUT

ON

VIN

IN

OUT

IN

OUT

IN

IN

D

G S

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE+-

PAD

(OD)

0.7V

DLY

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6 3



Supervisor & CLKREQ# Isolation

FireWire Port Power Switch

FireWire PHY WAKE# Support


- =PPBUS_S5_FWPWRSW (FW VP FET Input)

- =PPBUS_FW_FET (FW VP FET Output)

- =PP3V3_FW_P3V3FWFET (3.3V FET Input)

Dual-purpose output:

DLY = 60 ms +/- 20%

Type

to reduce voltage.

TPS22924C

18 mOhm TypR(on)

Max Output: 2A

- =PP3V3_S0_FWPWRCTL

- =PP1V0_FW_FWPHY (PHY 1.0V)


- =PP1V05_FW_P1V0FWFET (1.0V FET Input)

- =PP3V3_FW_FET (3.3V FET Output)

- =PP3V3_FW_FWPHY (PHY 3.3V Power)

- =PP1V05_S0_FWPWRCTL (5KPD Bias Rail)

(NONE)

- =PP1V0_FW_FET_R (1.0V FET Output)

- =PP3V3_S0_FWLATEVG


Current source only active when FW_PWR_EN is low.

Host can detect as load on TPBIAS signal.

1) 5K Pull-down Detect when FW_PWR_EN is low.

Pull-up provided on another page.

- =FW_PME_L

- =FW_CLKREQ_L

2) FW643 WAKE# (PME#) when PHY is powered.

50 mOhm Max

Load Switch

Max Current = 1.7A (85C)

1.05V is used with a series R

To avoid an extra power supply,

LSI FireWire PHY requires 1.0V.

When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.

U4201 & U4202Part

1.0V FW Switch

3.3V FW Switch

Pull-up provided by another page.

Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)

All FireWire devices require 5K pull-down on TPB pair.

FireWire Port 5K Pull-Down Detect

402

25VX5R

10%0.1UF

1/16W5%

402MF-LF

300K

1/16W5%

402MF-LF

470K

1.1A-24V

MINISMDC110H24

CRITICAL

SOT563

BC847CDXV6TXG

CRITICAL

SOT563

BC847CDXV6TXG

CRITICAL

MF-LF

5%

402

1/16W

330K 56K

MF-LF402

5%1/16W

5%1/16WMF-LF

402

12K


MF-LF402

5%1K

1/16W

CRITICAL

DMB53D0UVSOT-563 CRITICAL

SOT-563

DMB53D0UV

10%0.1UF

402X5R16V

38 40

1/16WMF-LF

5%1K

402

24 39

DMB53D0UVSOT-563

CRITICAL

CRITICAL

DMB53D0UVSOT-563

5%1/16WMF-LF402

100K

NO STUFF

0.1UF10%16VX5R402

MF-LF

5%1/16W

402

10K 8 19

8 38

CRITICAL

SOT-363

BSS8402DW

402

1/16W5%

MF-LF

10K

CRITICAL

BSS8402DWSOT-363

402

25VX5R

10%0.1UF

NO STUFF

105%

1/16WMF-LF402

CRITICAL

CSPTPS22924

TPS22924CSP

CRITICAL

40

402MF1/16W1%0.549

38

1/16W

402

5%10K

MF-LF

24 39

16

402

25VX5R

10%0.1UF

24

38

CRITICAL

FDC638P_GSM

CRITICAL


402CERM6.3V10%1UF

CERM6.3V10%1UF

402

TDFN

CRITICAL

SLG4AP016V 402

5%

MF-LF1/16W

100K

CRITICAL

PWRDI123

SBR3U30P1


FireWire Port & PHY Power

=PPBUS_S5_FWPWRSW

FWPORT_PWREN_L_DIV

=PP3V3_FW_FWPHY

=PP3V3_S0_FWPWRCTL

FW_CLKREQ_L

=PP1V05_FW_P1V0FWFETMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

PP1V05_FW_FET

FW_RESET_R_L

FWPORT_PWR_EN

FW_PWR_EN_L

FW_5KPD_DET_RC

MAKE_BASE=TRUEFW_5KPD_DET_L

=PP3V3_FW_P3V3FWFET

=PP1V0_FW_FET_R

MAKE_BASE=TRUEFW643_WAKE_L

FWDET_MIRROR

FWDET_EMITFW_P1_TPBIAS_R

=PP1V05_S0_FWPWRCTL

=PP3V3_FW_FWPHY

FW_WAKE

FW_P1_TPBIAS

FW_PWR_EN

FW_PME_L

=FW_PME_L


PPBUS_FW_FWPWRSW_FMIN_LINE_WIDTH=0.5 mm

VOLTAGE=12.6V

FWPORT_FASTOFF_L

=PP3V3_S0_FWLATEVG

FWPORT_PWREN_L

=PP3V3_FW_FET

=FW_CLKREQ_L

FW_RESET_L

=PP1V0_FW_FWPHY

MAKE_BASE=TRUEFW_CLKREQ_PHY_L

FW_PWR_EN

=FW_RESET_L

FWPORT_FASTOFF_L_DIV

=PPBUS_FW_FET

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPPBUS_FW_FWPWRSW_D

VOLTAGE=12.6V

C4260 1

2

R42601

2

R42611

2

F4260

1 2

Q42702

6

1

Q42705

3

4

R42701

2

R42711

2

R42731

2

R42721

2

Q4275

6

2

1

Q42755

3

4C4270 1

2

R42751

2

Q42765

3

4

Q4276

6

2

1

R42761

2

C4276 1

2

R42771

2

Q4262

3

5

4

R42621

2

Q4262

6

2

1

C4261 1

2

R42631

2

U4201

C1

C2

A2

B2

A1

B1

U4202

C1

C2

A2

B2

A1

B1

R42021

2

R42832

1

C4290 1

2

Q4260

1

2

5

6

3

4

Q42613

12

C4201 1

2

C4202 1

2

U4290

6

5

7

3

8

4

2

9

1 R42901

2

D4260

A K

051-9585

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39 OF 105

7

7 38 39 40

7

7

7

7

8

7

7 38 39 40

7 40

7

7 38

7

SC/NC

TPA+ TPA(R)

VG

VPTPB+

TPB(R)TPB-

TPA-

CHASSISGND

S

G

D

(SYM-VER2)

G

S (SYM-VER1)

D

NC

VCC

VCLMP

D1-

GNDD2-

D2+

D1+

FWPWR_ENOUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

BI

BI

BI

BI

IN

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"Snapback" & "Late VG" Protection

FireWire Design Guide (FWDG 0.6, 5/14/03)

1394b implementation based on Apple


properly terminate unused signals.

appropriate connectors and/or to

the necessary aliases to map the

- =FW_PHY_DS1


- =PP3V3_S0_FWLATEVG

- =PPVP_FW_PHY_CPS (To PHY)

- =PPVP_FW_PHY_CPS_FET (From Port)

BILINGUAL

Cable Power

AREF needs to be isolated from all

beta-only device, there is no DC path

BREF should be hard-connected to logic

Note: Trace PPVP_FW_PORT1 must handle up to 5A

(NONE)

- =FW_PHY_DS2

- =FW_PHY_DS0

- =PP3V3_FW_FWPHY

From Port

To FW643

- =PPVP_FW_PORT1FET blocks current to TPCPS until VDD33 is powered.

FW643 TPCPS Leakage Protection

Termination

(FW_PORT1_TPA_P)

(FW_PORT1_TPA_N)

(FW_PORT1_TPA_N)

(FW_PORT1_TPB_P)

(FW_PORT1_TPB_P)

(FW_PORT1_TPB_N)

(FW_PORT1_TPB_N)

514S0605

PORT 1

(GND)

local grounds per 1394b spec

(FW_PORT1_BREF)

ground for speed signaling and connection

between them (to avoid ground offset issue)

When a bilingual device is connected to a

TPA<R>

TPA+

TPA-

VG

TPB+

VP

NC

INPUT

OUTPUTTPB<R>

TPB-

(All unused port signals TP/NC)

Disabled per LSI instructions

Unused FireWire Ports

- Port "1" Bilingual (1394B)

Configures PHY for:

FireWire PHY Config Straps

(FW_PORT1_TPA_P)

Place close to FireWire PHY

NOTE: This page is expected to contain

Page Notes

FireWire TPA/TPB pairs to their

FW643 has internal leakage path from TPCPS pin to VDD33.

1/16W1%

402MF-LF

56.2

SIGNAL_MODEL=EMPTY

1/16W1%

402MF-LF

4.99K

SIGNAL_MODEL=EMPTY

56.2

MF-LF402

1%1/16W

220pF

CERM402

5%25V

56.2

MF-LF402

1%1/16W

SIGNAL_MODEL=EMPTY

0.33UF

CERM-X5R402

10%6.3V

1/16W1%

402MF-LF

56.2

SIGNAL_MODEL=EMPTY

PLACE_NEAR=J4310.5:2 mm

50V10%

0.1uF

X7R603-1

PLACE_NOTE=J4310.5:2 mm

1/16W5%

402MF-LF

1M

50V10%

X7R

0.01UF

402

SM

FERR-250-OHM

CRITICAL

F-RT-TH

CRITICAL

1394B-M97

1/16W1%

402MF-LF

10K

10K

MF-LF402

1%1/16W 1/16W

1%

402MF-LF

10K

BSS8402DW

SOT-363

CRITICAL

BSS8402DWSOT-363

CRITICAL

330K

MF-LF402

5%1/16W

470K

MF-LF402

5%1/16W

LLPTPD4S1394

CRITICAL

402

10%

X5R16V

0.1UF

PLACE_NEAR=U4350.1:2 mm

MF-LF402

1/16W5%

100K

39

38

38

38

38 97

38 97

38 97

38 97

38

38

38

38

38

38

38 97

38 97

38 97

38 97

38 39


FireWire Connector

=PPVP_FW_PHY_CPS_FET

FW_P1_TPBIAS

FWPORT_PWR_EN

FW_PORT1_TPA_PMAKE_BASE=TRUE

=PP3V3_S0_FWLATEVG

=PP3V3_FW_FWPHY

MAKE_BASE=TRUEFWPHY_DS0

MAKE_BASE=TRUEFWPHY_DS2

=FW_PHY_DS0

=FW_PHY_DS2

=FW_PHY_DS1MAKE_BASE=TRUEFWPHY_DS1

NO_TEST=TRUEMAKE_BASE=TRUENC_FW0_TPBIAS

NO_TEST=TRUEMAKE_BASE=TRUENC_FW0_TPAP

NO_TEST=TRUEMAKE_BASE=TRUENC_FW0_TPAN

NO_TEST=TRUENC_FW0_TPBP

MAKE_BASE=TRUE

NO_TEST=TRUENC_FW0_TPBN

MAKE_BASE=TRUE

NO_TEST=TRUENC_FW2_TPBIAS

MAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_FW2_TPAP

NO_TEST=TRUEMAKE_BASE=TRUENC_FW2_TPAN

NO_TEST=TRUENC_FW2_TPBP

MAKE_BASE=TRUE

NO_TEST=TRUENC_FW2_TPBN

MAKE_BASE=TRUE

FW_P0_TPBIAS

FW_P0_TPB_P

FW_P0_TPA_N

FW_P0_TPA_P

FW_P2_TPBIAS

FW_P2_TPA_P

FW_P0_TPB_N

FW_P2_TPB_N

FW_P2_TPB_P

FW_P2_TPA_N

FW_PORT1_AREF

=PPVP_FW_PORT1

FW_PORT1_TPB_C

FW_P1_TPA_N

FW_P1_TPB_P

FW_P1_TPB_N

FW_P1_TPA_P

TP_FWLATEVG_VCLMP

CPS_EN_L

=PP3V3_FW_FWPHY

=PPVP_FW_PHY_CPS

MAKE_BASE=TRUEFW_PORT1_TPA_N


VOLTAGE=33V

PPVP_FW_PORT1_F


MAKE_BASE=TRUEFW_PORT1_TPB_NMAKE_BASE=TRUE

FW_PORT1_TPB_P

CPS_EN_L_DIV

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=12.6VMAKE_BASE=TRUE

PPVP_FW_CPS

R43631

2

R43641

2

R43621

2

C43641

2

R43611

2

C43601

2

R43601

2

C4319 1

2

R43191

2

C43141

2

L4310

1 2

J4310

1

10

11

12

13

2

3

4

5

6

7

8

9

R43811

2

R43821

2

R43801

2

Q4300

3

5

4

Q4300

6

2

1

R43121

2

R43111

2

U4350

7

8

5

6

4

21

3

C4350 1

2

R43501

2

051-9585

3.0.0

43 OF 132

40 OF 105

7

7 39

7 38 39 40

6

6

6

6

6

6

6

6

7

7 38 39 40

38

D

SG

OUT

OUT

OUT

IN

IN

IN

BI

IN

EN

A_INN

A_INP

TEST

B_PRE0/I2C_ADDR0

APRE0/I2C_ADDR1

I2C_EN*

A_OUTP

B_INN

A_OUTN

B_INP

REXT

B_PRE1/SDA_CTL

A_PRE1/SCL_CTL

VDD

THRMGND

B_OUTP

B_OUTN

PAD

OUT

OUT

IN

IN

IN

IN

OUT

IN

OUT

OUT

IN

OUT

IN

OUT

VCC+

GND

G

S D

IN

D

SG

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ODD Power Control

0x96/0x97

Note: Indicates disc presence.

SATA OOB Comparator

SATA ODD Connector

OOBR2D was TEMP_CTL, from SMC, to SSD

OOBD2R was OOB_TEMP, from SSD, to SMC

Note: 3.3V must be S0 if 5V is S3 or S5 to

ensure the drive is unpowered in S3/S5.

VALUE: 3.0 DB

R2D Passive DeEmphasis

0x98/0x99

H

516S0616

338S0907

Write:0xB6 Read:0xB7

0xB6/0xB7

0xB8/0xB9

Address (R/W)

L

L

ADD0

H

H

L

H

L

Notes:

C4518 & C4517 Placement Note:

It is critical that these two should be near

to U1800 pin AM1 and AM3.

VALUE: 4.5 DB

D2R Passive DeEmphasis

ADDR1

Internally PD ~150K

516S0687

SATA Redriver

SATA HDD Connector (Gen3)

20%16V

402CERM

0.01UF


0.01UF 10% 402

NOSTUFF

5%

5.0PF C0G 25V

402

20%0.1UF

SATA_HDD_D2R_RDROUT_P

SATA_HDD_D2R_RDROUT_N


=PP1V5_S0_RDRVR

GND_VOID=TRUE

46

100K

10V20%

MF-10612

0.001

0.01UF

10%

10%

0.01UF

ODD_PWR_SS

=PP3V3_S0_ODD

10%

=PP1V5_S0_RDRVR

SYS_LED_ANODE

PP5V_S0_HDD_RMIN_LINE_WIDTH=0.6MM

VOLTAGE=5VMIN_NECK_WIDTH=0.4MM

ISNS_HDD_N

SMC_SSD_OOBR2D_L

ODD_PWR_EN_L

=PP3V3_S0_ODD

=PP5V_S0_HDD

ISNS_HDD_P

=PP3V3_S0_HDD

SSD_OOBD2R_FTL_L

=PP1V5_S0_RDRVR

SSD_OOBD2R_FTL_L

SSD_OOB1V0REF

SSD_OOBD2R_R_L

SATARDRVR_TEST

SATA_HDD_D2R_RC_N

SATA_HDD_D2R_RC_PSATA_HDD_D2R_C_P

SATA_HDD_R2D_N

SATA_HDD_R2D_P

MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.2MMVOLTAGE=5V

PP5V_S3_IR_R

SYS_LED_ANODE_R

SATA_HDD_R2D_RC_N

SATA_HDD_R2D_RC_P

ODD_PWR_EN

SMC_ODD_DETECT

SATARDRVR_I2C_EN_L

SATA_HDD_D2R_RDRIN_N

SATA_HDD_D2R_RDRIN_P

SATA_HDD_D2R_C_N

SATA_HDD_R2D_RDRIN_PSATA_HDD_R2D_RDROUT_P

SATA_HDD_R2D_RDROUT_N

SATARDRVR_REXTSATARDRVR_EN

SATA_HDD_D2R_P

SATARDRVR_I2C_ADDR0

SATARDRVR_I2C_ADDR1

SATA_HDD_R2D_RDRIN_N

=SATARDRVR_I2C_SDA

=SATARDRVR_I2C_SCL

SATA_ODD_D2R_P

SATA_ODD_R2D_C_PSATA_ODD_R2D_P

SATA_ODD_D2R_N

SATA_HDD_D2R_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATARDRVR_I2C_ADDR0

=PP1V5_S0_RDRVR

SATA_ODD_R2D_N SATA_ODD_R2D_C_N

ODD_PWR_EN_LS5V_L

SMC_SSD_OOBD2R_L

SATARDRVR_I2C_ADDR1

=PP5V_S3_IR

SSD_OOBR2D_L

PP5V_S0_HDD_FLTMIN_LINE_WIDTH=0.6MM


SSD_OOBD2R_L

IR_RX_OUT

=PP5V_S3_ODD

MIN_NECK_WIDTH=0.4MMVOLTAGE=5V

MIN_LINE_WIDTH=0.6MMPP5V_SW_ODD

SATA_ODD_D2R_C_N

SATA_ODD_D2R_C_P

SMC_SSD_OOBD2R_R_L

=PP3V3_S0_SMC


SATA Redriver/Conn, IR, SIL

SOT563SSM6N37FEAPE

FERR-70-OHM-4A

0603

PLACE_NEAR=J4501.9:3MMCRITICAL

2011% 1/20W68.1

GND_VOID=TRUE

MF

GND_VOID=TRUE

0201 C0G 25V5.0PF +/-0.1PF

PLACE_NEAR=L4500.2:2MM

0.1UF

402CERM


CERM402

20%0.1UF10V

19

CRITICALDMP2018LFKDFN2563-6

MF-LF

5%

402

1/16W

1206

10V20%

PLACE_NEAR=J4501.10:10MM

X5R-CERM

NOSTUFF

100UF

X5R-CERM10V


20%

NOSTUFF

100UF

1206

LMV331SC70-5

46

41

0402FERR-220-OHM

1K5%1/16WMF-LF402

5%1/16WMF-LF402

0

20%0.1UF

10VCERM402

1%1/16WMF-LF402

49.9K

0.1UF20%

CERM402

10V1/16W

100K5%

MF-LF402

402MF-LF

5%1/16W

100K

3.3K

5%

402

1/16WMF-LF

41

1% MF-LF 4021/16W453

402MF-LF1/16W4.7

1/16W5%

402MF-LF

4.7K

1/16W5%

402MF-LF

4.7K

NO STUFF

1%1W

CRITICAL

103 101

103 101

MF-LF402

5%1/16W

0

X7R-CERM402

16V

0.1UF10%

46 6

44 6

0.001UF

402CERM50V10%

54722-0224

CRITICAL

GND_VOID

GND_VOID

GND_VOID

F-ST-SM

GND_VOID

0.01UF

PLACE_NEAR=U4510.11:5MMGND_VOID=TRUE

402CERM16V10%

0.01UF

PLACE_NEAR=U4510.12:5MMGND_VOID=TRUE

402CERM16V10%

0.01UF

GND_VOID=TRUE

402CERM16V10%

PLACE_NEAR=U1800.AM3:5MM

PLACE_NEAR=U1800.AM1:5MM

0.01UF

GND_VOID=TRUE

402CERM16V10%

05%

402MF-LF1/16W

402MF-LF1/16W1%3.74K

5%15PF 25V NPO 201

GND_VOID=TRUE

MF41.2

GND_VOID=TRUE

1% 1/20W 201

15PF 5% NPO

GND_VOID=TRUE

25V 201

41.2 MF1% 1/20W 201

GND_VOID=TRUE

0201

GND_VOID=TRUE

+/-0.1PF

1/20W1% MF 201

GND_VOID=TRUE

68.1

GND_VOID=TRUE

402CERM16V10%0.01UF

0.01UF

GND_VOID=TRUE

402CERM16V10%

16V CERM 40210%0.01UF

41

41

95 16

95 16

95 16

95 16

CRITICAL

GND_VOID

GND_VOID

GND_VOID

GND_VOID

TQFN

PS8521A

GND_VOID

GND_VOID

GND_VOID

GND_VOID

48

48

4.7K

MF-LF402

5%1/16W

10V

402CERM

23 16

0.01UF

GND_VOID=TRUE

10% CERM 40216V

GND_VOID=TRUE

16V CERM 4020.01UF

GND_VOID=TRUE

10% 16V CERM 40295 16

95 16 GND_VOID=TRUE

16V CERM 4020.01UF

CERM402

16V

95 16

95 16

54722-0164

CRITICAL

F-ST-SM

1/16W

402

5%33K

MF-LF

45 6

CERM16V

GND_VOID=TRUE

0.068UF

402

10VCERM

10%

100K

5%1/16WMF-LF402

MF-LF402

5%1/16W

100K

SSM6N37FEAPESOT563

100K

1/16W5%

MF-LF

C45012

1

C45022

1

C4536 1 2

R4536 1 2

L4500

1 2

Q4596 3

5 4

R45971

2

Q4596 6

21

R45961

2

R45951 2

C4595 1

2

C4516 1 2

R45901

2

J4500

1

10

11 12

13 14

15 16

2

3 4

5 6

7 8

9

C4596

1 2

C4520 1 2

C4521 1 2

C4526 1 2

C4525 1 2

C45191

2

C45141

2R45101

2

U4510

2

1

14

15

19

9

12

11

4

5

8

17

7

3

13

10

20

18

21

6 16

C4515 1 2

C4511 1 2

C4510 1 2

R4535 1 2

C4535 1 2

R4534 1 2

C4534 1 2

R4533 1 2

C4533 1 2

R45121

2R45111

2

C4518 1 2

C4517 1 2

C4513 1 2

C4512 1 2

J4501

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

3 4

5 6

7 8

9

C4531 1

2

C45321

2

R45321

2

R4599

1 2

3 4

R45151

2

R45131

2R4531 1 2

R4537 1 2

R45821 2

R45811

2

R45841

2

C45841

2

R45831

2

C45801

2

R45861 2

R45851

2

L4539 1 2

U4580

2

3

1

4

5

C4537

12

C4538

12

R45381

2

Q4590

4

3

12

051-9585

3.0.0

45 OF 132

41 OF 105

41

95

41 7

41 7

7

7

41 7

95

95 95 6

95 6

95 6

6

6

95

95

95

95 95 6

95 95

95 95

95

95 6

41

41 7

95 6

41

41 7

44 7

6

6

6

7

7

6

95 6

95 6

7

SYM_VER-1

OUT

OUT

IN

IN

L2

L1

L2

L1

D+

D-

VBUS

GND

GND_DRAIN

STDA_SSRX-

STDA_SSRX+

STDA_SSTX-

STDA_SSTX+

SHIELD

NC

NC

GND

VBUS

IO

IO

NC

GND

OUT

BI

BI

IN

OUT

IN

OUT

GNDTHRM

OUT2

OUT1

ILIM

IN_0

IN_1

EN2

FAULT1*

FAULT2*

EN1

PAD

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

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6 3



USB Port A (Front Port)

SEL=1 Choose USB

SEL=0 Choose SMC

USB Port Power Switch

Mojo SMC Debug Mux

Current limit per port (R4600): 2.18A min / 2.63A max

DLP11S

CRITICAL

90-OHM-100MA

95

6 18 95

6 18 95

6 18 95

2016.3V10%

X5R

GND_VOID=TRUE

0.1UF

GND_VOID=TRUE2016.3V10%

X5R

0.1UF

0504

CRITICAL

80OHM-25%-100MA

GND_VOID=TRUE

0504

GND_VOID=TRUE

CRITICAL

80OHM-25%-100MA

CRITICAL

F-RT-THUSB-3.0-J30

RCLAMP0582N

PGTSLP91-XSON-COMBOESD3V3U4ULC-IP4292CZ10

CRITICAL

10UF

6.3VX5R603

20%0.1UF20%10VCERM402

23

18 95

18 95

MOJO:YES

CERM402

10V20%

0.1UFMF-LF

MOJO:YES

5%10K

402

1/16W

45 46

45 46

45

MOJO:NO

1/16WMF-LF

5%

402

0

5%1/16W

MOJO:NO

0

402MF-LF

X5R

10UF20%

603

6.3V

23

603

10UF

X5R6.3V20%

SON

CRITICAL

TPS2561DR

PI3USB102ZLE

CRITICAL

SIGNAL_MODEL=MOJO_MUX

MOJO:YES

TQFN

402

23.2K

1/16W1%

MF-LF

CRITICAL

CASE-B2-SM1

FERR-120-OHM-3A

0603

CRITICAL

SYNC_MASTER=J31_LINDA

External A USB3 Connector


USB3_EXTA_TX_F_P

USB3_EXTA_TX_F_N

USB3_EXTA_RX_F_P

USB3_EXTA_RX_F_N

=PP5V_S3_USB

VOLTAGE=5VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mmPP5V_S3_USB_A_F

USB_EXTA_MUXED_F_N

USB_EXTA_MUXED_F_P

USB3_EXTA_TX_C_N


VOLTAGE=5V

PP5V_S3_USB_B_ILIM

USB_EXTA_MUXED_N

USB_EXTA_MUXED_P

USB_EXTA_P

USB_EXTB_OC_L

SMC_DEBUGPRT_TX_L

=PP3V42_G3H_SMCUSBMUX

SMC_DEBUGPRT_EN_L

SMC_DEBUGPRT_RX_L

USB_EXTA_N

USB3_EXTA_RX_P

USB3_EXTA_TX_P

=USB_PWR_EN

USB_ILIM

USB_EXTA_OC_L

USB3_EXTA_TX_N

USB3_EXTA_TX_C_P

220UF-35MOHM20%6.3VPOLY-TANT

18 6 USB3_EXTA_RX_N

CRITICALSLP1210N6

PP5V_S3_USB_A_ILIM


VOLTAGE=5V

402CERM

0.01UF

16V20%

C4695 1

2

C46911

2

C4650 1

2

R46501

2

R46511 2

R46521 2

C4617 1

2

C4690 1

2

U4600

4

5

10

6

1

7

2

3

9

8

11

U4650

6

7

3

4

5

8 10

9

2

1

R46001

2

C46961

2

L4605

1 2

C4605 1

2 L4600

1 2

34

C4620

1 2

C4621

1 2

L4610

1 2

34

L4620

1 2

34

J4600

2

3

4

10

11

12

13

14

15

16

17

18

7

5

6

8

9

1

D4600

1

452 3

6

D4610

3

1 2 4 5

6 7 8 9

051-9585

3.0.0

46 OF 132

42 OF 105

6 95

6 95

6 95

6 95

7

95

95

6 95

43

95

95

7

74

6 95

OUT

OUT

BI

BI

IN

IN

L2

L1

L2

L1

D+

D-

VBUS

GND

GND_DRAIN

STDA_SSRX-

STDA_SSRX+

STDA_SSTX-

STDA_SSTX+

SHIELD

NC

NC

GND

VBUS

IO

IO

NC

GND

SYM_VER-1

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NOTE: Swapped pin4 and 5, pin6 and 7 for layout.

USB Port B (Back Port)

6 18 95

6 18 95

25 95

25 95

6 18 95

6 18 95

201

GND_VOID=TRUE

6.3V

0.1UF

X5R10%

FERR-120-OHM-3A

CRITICAL

0603

GND_VOID=TRUE2016.3V

0.1UF

X5R10%

80OHM-25%-100MA

GND_VOID=TRUE

CRITICAL

0504

80OHM-25%-100MA0504

CRITICAL

GND_VOID=TRUE

CRITICAL

F-RT-THUSB-3.0-J30

CRITICAL

ESD3V3U4ULC-IP4292CZ10PGTSLP91-XSON-COMBO

DLP11S

External B USB3 Connector



PP5V_S3_USB_B_FMIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

USB_EXTB_F_N

USB_EXTB_F_P

USB3_EXTB_TX_C_P

USB3_EXTB_TX_C_NUSB3_EXTB_TX_N

USB3_EXTB_TX_P

USB3_EXTB_RX_P

PP5V_S3_USB_B_ILIM

USB_EXTB_MUX_N

USB3_EXTB_RX_N

USB3_EXTB_RX_F_N

USB3_EXTB_RX_F_P

USB3_EXTB_TX_F_N

USB3_EXTB_TX_F_P

USB_EXTB_MUX_P

CRITICAL

CRITICALSLP1210N6

90-OHM-100MA

RCLAMP0582N

0.01UF

402

16VCERM

20%

L4705

1 2

C4705 1

2 L4700

1 2

34

C4720

1 2

C4721

1 2

L4710

1 2

34

L4720

1 2

34

J4700

2

3

4

10

11

12

13

14

15

16

17

18

7

5

6

8

9

1

D4700

1

452 3

6

D4710

3

1 2 4 5

6 7 8 9

051-9585

3.0.0

47 OF 132

43 OF 105

95

95

6 95

6 95

42

6 95

6 95

6 95

6 95

BI

BI

VCC

P1.0/D+

P1.1/D-

P1.2/VREG

P1.3/SSEL

P1.4/SCLK

P1.5/SMOSI

P1.6/SMISO

P0.0

P0.1

INT0/P0.2

INT1/P0.3

TIO1/P0.6

NC

TIO0/P0.5

INT2/P0.4

VSSPADTHRML

IN

NCNCNCNCNC

NC

NCNCNCNC

NCNCNCNCNCNCNCNC

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IR SUPPORT

8 95

8 95

1UF10%10V

402-1X5R

CRITICALOMIT

QFNCY7C63803-LQXC

16V

402

0.1UF10%

X7R-CERM

50V10%

402CERM

0.001UF

1/16W5%

402MF-LF

1006 41

Front Flex Support


IR_VREF_FILTER

=PP5V_S3_IR

IR_RX_OUTIR_RX_OUT_RC

DIFFERENTIAL_PAIR=USB2_TPADUSB_IR_P

DIFFERENTIAL_PAIR=USB2_TPADUSB_IR_N

C48031

2

U4800

5

4

3

8

9

10

20

21

22

23

24

7

6

12

13

15

16

17

18

19

25

2

1

14

11

C48011

2

C48041

2

R48001 2

051-9585

3.0.0

48 OF 132

P/N 338S0633

44 OF 105

7 41

45

LPC0AD3

LPC0CLK

LPC0FRAME*

LPC0AD1

LPC0AD2

AIN08

AIN07

LPC0CLKRUN*

LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX

PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119

PP4/IRQ120

C0-

WT2CCP0/PH0

WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2

SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127

PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4

PF5

T1CCP0/PJ0

T2CCP0/PJ2

T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK

SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

IN

BI

BI

BI

BI

IN

IN

IN

BI

OUT

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

IN

NC

OUT

NC

BI

OUT

IN

OUT

OUT

IN

OUT

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

BI

IN

IN

OUT

IN

NC

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

OUT

BI

IN

OUT

BI

IN

BI

NCNC

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NC FOR STACK BRD

NC FOR STACK BRD

(OD)

NC FOR ENG PKG

1.2V FOR ENG PKG

(OD)

NC FOR ENG PKG

NC FOR ENG PKG

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

NOTE:

NOTE:

(OD)

(OD)

NC FOR ENG PKG

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR ENG PKG

(OD)

those designated as inputs require pull-ups.pins designed as outputs can be left floating,Unused pins have "SMC_Pxx" names. Unused

If SMS interrupt is not used, pull up to SMC rail.SMS Interrupt can be active high or low, rename net accordingly.

NC FOR ENG PKG

BGA

LM4FSXAH5BB

OMIT_TABLE

OMIT_TABLE

BGA

LM4FSXAH5BB

PLACE_NEAR=U4900.A1:4MM

SM

6 46 47 65

46

1/20W5%

201MF

1M

10V10%

0201X5R-CERM

0.1UF

10V10%

0201X5R-CERM

0.1UF

10V10%

0201X5R-CERM

0.1UF

10V10%

0201X5R-CERM

0.1UF

10V10%

0201X5R-CERM

0.1UF10%10V

0201X5R-CERM

0.1UF

10V10%

0201X5R-CERM

0.1UF

6 16 47 89 96

6 16 47 89 96

6 16 47 89 96

6 16 47 89 96

24 96

6 16 47 89 96

24

6 16 47

6 17 47

6 17 47

19

48 99

48 99

48 99

48 99

6 48 99

6 48 99

48 99

48 99

46

46

6 48 99

6 48 99

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46 74

17

35 46 92

46

42 46

42 46

46

46

46

46

46

42

46 82

23 74 89 92

46

17 23

6 17 24

17 46 74

46

46

46

6 46 47

6 46 47

52

52

46

54

52

52

46

46

46 53 64

55

46 64

46

6 17 26 74

17 26 32 74

17 74

6 46 53

46

46 74

46 74

6 32 46

46

6 46 64

46

74

24

0402

30-OHM-1.7A

10 46 69 93

46

46

46

64

17 23 92

10 93

46

46

10V10%

0201X5R-CERM

0.1UF

10V10%

0201X5R-CERM

0.1UF

10V10%

0201X5R-CERM

0.1UF

10V10%

0201X5R-CERM

0.1UF

10V10%

0201X5R-CERM

0.1UF

10V10%

0201X5R-CERM

0.1UF

6.3V20%

0201X5R

1UF

27 29 46

44

46

46

6 41

10V20%

0201-1X5R-CERM

1.0UF

NOSTUFF

10V20%

0201-1X5R-CERM

1.0UF

10V20%

0201-1X5R-CERM

1.0UF

0.01UF

10V10%

201X5R

PLACE_NEAR=U4900.D1:1MMPLACE_NEAR=U4900.D2:1MM

82

6.3V20%

0201X5R

1UF

PLACE_NEAR=U4900.D1:1MMPLACE_NEAR=U4900.D2:1MM


SMC

PM_SLP_S5_L

SMC_ONOFF_L

SMC_RX_L

SMC_TX_L

SMBUS_SMC_5_G3_SDA

SMC_S4_WAKESRC_EN

SPI_SMC_MISO

SMC_PROCHOT

SMC_VCCIO_CPU_DIV2

SMC_ADC22

SMC_ADC13

CPU_THRMTRIP_3V3

=PP3V3_S5_SMC

SMC_ADC0

SMC_ADC5

IR_RX_OUT_RC

MIN_NECK_WIDTH=0.1MM

PP1V2_S5_SMC_VDDCMIN_LINE_WIDTH=0.25MM

VOLTAGE=1.2V

SMC_PME_S4_WAKE_L

SMC_PME_S4_DARK_L

ENET_ASF_GPIO

SMS_INT_L

SMC_BC_ACOK

G3_POWERON_L

PM_SLP_S3_L

PM_SLP_S4_L

SMC_ADC23

CPU_PROCHOT_L

PM_PWRBTN_L

BDV_BKL_PWM

ALL_SYS_PWRGD

SMC_GFX_THROTTLE_L

SMC_PM_G2_EN

SMC_LID

PM_DSW_PWRGD

MEM_EVENT_L

SMC_SYS_LED

SMC_DEBUGPRT_TX_L

SMC_DEBUGPRT_RX_L

SMBUS_SMC_3_SDA

SMC_DEBUGPRT_EN_L

SMC_GFX_OVERTEMP

SMC_ADAPTER_EN

SMC_OOB1_RX_L

SMC_OOB1_TX_L

SPI_SMC_MOSI

SMC_ADC14

SMC_WAKE_SCI_L

SMBUS_SMC_3_SCL

SMC_LRESET_L

SMC_ADC17

SMC_ADC20 SMC_TDI

SMC_EXTAL

NC_SMC_HIB_L

NC_SMC_XOSC1

SMC_XTAL

SMBUS_SMC_0_S0_SDA

LPC_FRAME_L

PM_CLKRUN_L

LPC_PWRDWN_L

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_2_S3_SDA

LPC_AD<3>

SMC_RUNTIME_SCI_L

SPI_SMC_CS_L

SMC_DELAYED_PWRGD

SMC_WAKE_L

SMC_CLK32K

SMC_TMS

SMC_TCK

WIFI_EVENT_L SMC_TDO

PM_PCH_SYS_PWROK

S5_PWRGD

CPU_CATERR_L

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_4_ASF_SCL

SPI_SMC_CLK

SPI_DESCRIPTOR_OVERRIDE_L

SMC_THRMTRIP

SMC_BATLOW_L

SMC_ADC19

SMC_ADC18

SMC_ADC16

SMC_ADC2

SMC_ADC3

SMC_ADC1

SMC_ADC12

SMC_ADC10

SMC_ADC6

SMC_ADC21

SMC_ADC11

SMC_ADC9

SMC_S5_PWRGD_VIN

SMC_ADC4

SMC_ADC7

SMC_ADC8

LPC_AD<2>

LPC_CLK33M_SMC

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_1_S0_SCL

PM_SYSRST_L

SMC_DP_HPD_L

SMC_BIL_BUTTON_L

SMC_PECI_L

CPU_PECI_R

SMC_ODD_DETECT

HISIDE_ISENSE_OC

SYS_ONEWIRE

SYS_TDM_ONEWIRE

SMC_T25_EN_L

SMC_SYS_KBDLED

SMC_MPM5_LED_CHG

SMC_MPM5_LED_PWR

SMC_FAN_1_TACH

SMC_FAN_1_CTL

SMC_FAN_0_TACH

SMC_FAN_0_CTL

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_4_ASF_SDA

SMC_ADC15

SMC_RESET_L


VOLTAGE=3.3V

PP3V3_S5_SMC_VDDA

GND_SMC_AVSS

PP3V3_S5_AVREF_SMC

LPC_AD<0>

LPC_SERIRQ

LPC_AD<1>

U4900

E2

E1

F2

F1

B3

A3

B4

A4

B5

A5

B6

A6

C1

C2

B1

B2

G2

G1

H1

H2

B7

A7

B8

A8

K2

K1

L2

E10

D13

M4

N2

N8

M8

L8

K8

N7

M7

N4

N3

B13

A13

C12

D11

H12

G11

D12

F13

C13

F12

H13

L1

C4

C6

L9

K9

J4

J2

B12

C11

A12

H11

L13

G3

D10

L11

N12

N11

M11

M13

L12

M5

J12

J13

L5

D8

K6

D4

E4

F5

N5

N6

K5

M6

L6

M2

M3

L4

N1

L10

K10

M9

N9

F4

F3

C9

B9

A9

C8

D5

C5

L3

M1

F11

E11

E13

E12

K7

L7

K3

K4

J3

H4

H3

G4

H10

U4900

A1

C7

K11

D9

E5

F9

H5

H9

J5

J8

J11

C3

E3

M12

G12

G13

B11

G10 C10

A10

A11

B10

K12

D7

E6

E8

E9

F10

J7

J9

J10

D3

J1

J6

K13

D6

D1

D2

N13

M10

N10

XW4900

12

R49021

2

C49061

2

C49051

2

C49091

2

C49081

2

C49041

2

C49031

2

C49071

2

L4901

1 2

C49171

2

C49161

2

C49151

2

C49141

2

C49131

2

C49011

2

C49021

2

C49101

2

C49111

2

C49121

2

C49201

2

C49211

2

051-9585

3.0.0

49 OF 132

45 OF 105

A2

46

7 46 82

46

6 46 47

46

46

6 46 47

6 46 47

6 46 47

46

46 49 50 103

6 46

IN

OUT

BI

IN

IN

IN

REFOUT

MR1*

THRMGND

RESET*

DELAY

MR2*

VINV+

SN0903048

PAD

OUT

IN OUT

IN OUT

IN OUT

OUTIN

OUTIN

OUTIN

OUTIN

IN

E

Q2

C

BD

Q1

GS

OUT

IN

OUT

D

S G

D

S G

OUT

D

GS

D

G S

IN

OUT

OUT

IN

BI

D

G S

IN

D

S G

NC NC

IN

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6 3



Eng Package requires 1.2V ON SMC_ADC23 pin.

SCM12 Eng Pkg Support

SMC USB Clock require 12 MHz.

SMC Crystal Circuit

System (Sleep) LED Circuit

NOTE: Internal pull-ups are to VIN, not V+.

Used on mobiles to support SMC reset via keyboard.

Notes:

OOBD2R was OOB_TEMP, from SSD, to SMC

OOBR2D was TEMP_CTL, from SMC, to SSD

SMC12 SPI SupportSeries resistors are no stuffed until the

From SMC.

topology of 2 SPI Masters are verified.

SMC12 PECI Support

From/To CPU/PCH.To SMC.

Note:

Desktops: 5V

(IPU)

(IPU)

MR1* and MR2* must both be low to cause manual reset.

PM_BATLOW_L in PCH.

Internal 20K pull-up on

Mobiles: 3.42V

S4 HPD SMC Wake Source

share with comparators

on Stack Board.

ADC10 and ADC11 are

SMC Reset "Button", Supervisor & AVREF Supply

BATLOW# Isolation

Debug Power "Buttons"

10K5% 1/20W MF 201

100KMF 2015% 1/20W

1/20W

10KMF 2015%

1/20W

100KMF 2015%

10KMF 2015% 1/20W10KMF 2015% 1/20W10KMF 2015% 1/20W10KMF 2015% 1/20W

1/20W5% 201MF

10K

45 46

19

PLACE_SIDE=TOPSILK_PART=PWR_BTN

1/10W5%

603MF-LF

0

OMIT

10 45 69 93

45

1/20W5% 201MF

10K

10KMF 2015% 1/20W

1/20W

201MF

1%

2.49K

50V5%

402CERM

12PF

470KMF 2015% 1/20W

10KMF 2015% 1/20W

603

PLACE_SIDE=BOTTOMSILK_PART=PWR_BTN

MF-LF1/10W

5%0

OMIT

PLACEMENT_NOTE=Place R5001 on BOTTOM side

SILK_PART=SMC_RST

1/10W5%

603MF-LF

0

OMIT

6 45 46 53

53

16V10%

402CERM

0.01UF

6.3V10%

402CERM-X5R

0.47UF

VREF-3.3V-VDET-3.0V

CRITICAL

DFN

6.3V20%

603X5R

10uF

16V10%

402CERM

0.01UF

6 45 47 65

17 PLACE_NEAR=U1800.N14:5MM

1/20W5%

201MF

2245

100KMF 2011/20W5%

53 45

1/20W5%

201MF

100K

45 74 17

1/20W5%

201MF

100K

1/16W5%

402MF-LF

0

NOSTUFF

0

MF-LF402

5%1/16W

SMC_PACKAGE:ENG

201

10KMF5% 1/20W100KMF 2015% 1/20W

5%

10K201MF1/20W

1/20W5%

201MF

1K

50V5%

402CERM

12PF

47 56

5%

402MF-LF

0NO STUFF


1/16W

45

47 56

1/16W5%

MF-LF

0

402


NO STUFF

45

47 56

1/16W5%

402

0NO STUFF


MF-LF

45

47 56

1/16W5%

402MF-LF

0

NO STUFF

PLACE_NEAR=U6100.1:1MM45

45

1/16W1%

402MF-LF

1.47K

1/16W1%

402MF-LF

523

1/16W1%

402MF-LF

20

CRITICAL

SOT-563

DMB54D0UV

6 41

86 87

1/20W5%

201MF

100K

45

SSM6N15AFESOT563

CRITICAL

SSM6N15AFE

CRITICALSOT563

100K

MF-LF402

1%1/16W

100K

1/16W1%

402MF-LF

1/20W5% 201MF

100K

SMC_PACKAGE:PROD

1/20W

0

MF201

5%

100K5%1/16WMF-LF402

6 45 46 53

SSM3K15AMFVAPE

CRITICALVESM

SSM3K15AMFVAPE

CRITICAL

VESM

10KMF 2015% 1/20W

MF 2015% 1/20W

100K

10 19 93

45 46

45

402

43

5%

MF-LF1/16W

45

402MF-LF1/16W5%

0

402

NOSTUFF

1.6K5%1/16WMF-LF

10 19 93

402MF-LF1/16W5%330

VESM

CRITICAL

SSM3K15AMFVAPE

MMBT3904LP-7

CRITICALDFN1006-3

45 82

SSM6N15AFE

CRITICALSOT563

3.3K

201

5%1/20WMF

12.000MHZ-30PPM-10PF3.2X2.5MM-SM

CRITICAL

32

5% 1/20W 201MF

100K

100KMF 2011/20W5%

SYNC_MASTER=J31_YONAS

SMC Support


CPU_THRMTRIP_3V3

SMC_S5_PWRGD_VIN

SMC_BC_ACOK

SMC_BIL_BUTTON_L

MAKE_BASE=TRUESMC_CPUMEM_ISENSE_R

=PPVCCIO_S0_SMC

SMC_SSD_OOBR2D_LMAKE_BASE=TRUE

=PP3V3_S5_SMC

SPI_SMC_CLK

HISIDE_ISENSE_OC

PM_CLK32K_SUSCLK_R

DP_A_EXT_HPD

=PSOC_WAKE_LMAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

=BT_WAKE_L

SYS_LED_L

SMC_BATLOW_L PM_BATLOW_L

SMC_TCK

NC_ENET_ASF_GPIOMAKE_BASE=TRUE

SMC_EXTAL

SMC_XTAL_R

SPI_SMC_MOSI

PM_THRMTRIP_B_L PM_THRMTRIP_L

SMC_ADC11

SMC_GPU_FB_VSENSEMAKE_BASE=TRUE

SMC_CPUVCCSA_ISENSEMAKE_BASE=TRUE

SMC_XTAL

=CHGR_ACOK

NC_SMBUS_SMC_4_ASF_SDAMAKE_BASE=TRUE

SDCONN_STATE_CHANGE_SMCMAKE_BASE=TRUE

SMC_DEBUGPRT_TX_L

SMC_DEBUGPRT_RX_L

SMC_TDI

SMC_ADC23

SMBUS_SMC_4_ASF_SCL

SMC_OOB1_TX_L

SMC_OOB1_RX_LMAKE_BASE=TRUESMC_SSD_OOBD2R_L

SMC_TMS

MAKE_BASE=TRUESMC_BC_ACOK

MAKE_BASE=TRUESMC_CPUVCCSA_VSENSE

MAKE_BASE=TRUESMC_AXG_ISENSE

=PP3V3_S5_SMC

SMC_AXG_VSENSEMAKE_BASE=TRUE

SMC_RESET_L

SYS_TDM_ONEWIRE

NC_SMC_MPM5_LED_CHGMAKE_BASE=TRUE

SMC_SCI_L

SMC_MPM5_LED_CHG

SMC_TDO

G3_POWERON_L

ENET_ASF_GPIO

SMC_MPM5_LED_PWR NC_SMC_MPM5_LED_PWRMAKE_BASE=TRUE

SMC_ADC14

SMC_ADC18

SMC_PROCHOT

CPU_PROCHOT_L

MEM_EVENT_L

SMC_RX_L

SMC_TX_L

SMC_LID

PP1V2_S5_SMC_VDDC

SMC_VCCIO_CPU_DIV2

SMC_DP_HPD_L

=PP3V3_SUS_SMC

WIFI_EVENT_L

SMC_ADC15

SMC_ADC20

SMC_ADC0

SMC_CPUVCCIO_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_AIRPORT_ISENSE

SMC_MEM_ISENSEMAKE_BASE=TRUE

SMC_OTHER_HI_ISENSEMAKE_BASE=TRUE

SPI_SMC_MISO

SPI_MLB_CS_L

SPI_MLB_MOSI

SPI_MLB_CLK

SPI_MLB_MISO

BDV_BKL_PWM NC_BDV_BKL_PWMMAKE_BASE=TRUE

SMBUS_SMC_4_ASF_SDA

NC_SMBUS_SMC_4_ASF_SCLMAKE_BASE=TRUE

=PP3V3_S5_SMCBATLOW

=PP5V_S3_SYSLED

SMC_SYS_LED SYS_LED_ANODE

SYS_LED_L_VDIV

=PP3V3_S4_SMC

=PP3V3_S4_SMC

SMC_ADC1

MAKE_BASE=TRUESMC_GPU_FB_ISENSE

SMC_CPU_HI_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_HDD_ISENSE

SMC_PBUS_VSENSEMAKE_BASE=TRUE

SMC_DCIN_ISENSEMAKE_BASE=TRUE

SMC_DCIN_VSENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_GPU_HI_ISENSE

SMC_TPAD_RST_L

PP3V3_WLAN

SMC_ADC5

SMC_ADC13

SMC_ADC21

SMC_MANUAL_RST_L

SMC_ONOFF_L

SMC_ADC4

SMC_THRMTRIP

SMC_ROMBOOT

SMC_GPU_ISENSEMAKE_BASE=TRUE

SMC_ADC12

SPI_SMC_CS_L

PP3V3_S5_AVREF_SMCMIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.1MMVOLTAGE=3.3V

MAKE_BASE=TRUESMC_BMON_ISENSE

SMC_ADC8

SMC_ADC2

SMC_ADC6

SMC_ADC7

SMC_GPU_VSENSEMAKE_BASE=TRUE

SMC_ADC22

SMC_PCH_ISENSEMAKE_BASE=TRUE

SMC_ADC19

SMC_ADC17

MAKE_BASE=TRUESMC_GPU_1V05_ISENSE

SMC_ADC23

=PPVIN_S5_SMCVREF

SMC_ONOFF_L

=PPVCCIO_S0_SMC

SMC_PECI_L_RSMC_PECI_L

MAKE_BASE=TRUESMC_CPU_VSENSE

MAKE_BASE=TRUENC_SYS_TDM_ONEWIRE

SMC_ADC3

SMC_THRMTRIP

CPU_PECI_R CPU_PECI

MAKE_BASE=TRUESMC_CPU_ISENSE

CPU_THRMTRIP_3V3

SMC_CPUMEM_ISENSE

SMC_GFX_OVERTEMP

PM_THRMTRIP_L_R

NC_HISIDE_ISENSE_OCMAKE_BASE=TRUE

SMC_ADC16

SMC_PME_S4_DARK_L

SMC_CLK32K


VOLTAGE=0V

GND_SMC_AVSS

SMC_ADC10

SMC_ADC9

SMC_ONOFF_L

SYS_LED_ILIM

SMC_T25_EN_L

SMC_WAKE_SCI_LMAKE_BASE=TRUE

NC_SMC_T25_EN_LMAKE_BASE=TRUE

SMC_ADAPTER_EN

SMC_S4_WAKESRC_EN

SMC_PM_G2_EN

SMC_DELAYED_PWRGD

R5070 1 2

R5071 1 2

R5073 1 2

R5074 1 2

R5077 1 2

R5078 1 2

R5079 1 2

R5080 1 2

R5085 1 2

R50151

2

R5089 1 2

R5081 1 2

R50101 2

C50111

2 R5087 1 2

R5072 1 2

R50161

2

R50011

2

C5001 1

2

C5020 1

2U5010

4

2

6

7

8

5

9

1 3

C5025 1

2

C50261

2

R50121 2

R5090 1 2

R50821

2

R50401

2

R50411 2

R50991

2

R5075 1 2

R5076 1 2

R5086 1 2

R50881

2

C50101

2

R50211 2

R50221 2

R50231 2

R50241 2

R50321

2

R50311

2

R50301

2

Q5030

5

3

6 4

21

R50201

2

Q5059

6

21

Q50593

54

R50961

2

R50971

2

R5092 1 2

R50131 2

R50001

2

Q5040

3

12

Q50203

12

R5014 1 2

R5017 1 2

R5054

1 2

R5052

1 2

R50531

2

R50511

2

Q50503

1 2

Q50581

3

2

Q50573

54

R50581 2

Y5010

2 4

1 3

R5091 1 2

R5093 1 2

051-9585

3.0.0

50 OF 132

46 OF 105

45 46

45

45 46 64

6 45 64

7 46

41

7 45 46 82

45

6 45 47

45

45

103

49

45

49 65

24 30

42 45

42 45

6 45 47

45 46

45

45

45 41

6 45 47

45 46 64

49

50

7 45 46 82

49

45

19

45

6 45 47

45

45

45

45

45

27 29 45

6 45 47

6 45 47

45 53 64

45

45

7

6 32 45

45

45

45

49

103

49

50

45

45

7

7

7 46

7 46

45

103

50

103

49

50

49

50

6 32

45

45

45

45

45 46

6 47

49

45

6 45

50

45

45

45

45

49

45

103

45

45

103

45 46

7

6 45 46 53

7 46

49

45

50

103

45

45

45 49 50 103

45

45

45

45

17 45 74

45 74

45 74

35 45 92

OUTIN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

BI

BI

OUT

IN

BI

IN

IN

OUT

BI

BI

IN

OUTIN

OUTIN

INOUT

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SPI Bus Series Termination

LPC+SPI Connector

516S0573

LPCPLUS_R:YES

402

PLACE_NEAR=J5100.12:5mm47

MF-LF1/16W5%

46 56


47

MF-LF

5%1/16W

402

1/16W5%

MF-LF402

15

PLACE_NEAR=U1800.AY1:5mm

16 96

LPCPLUS_R:YES

PLACE_NEAR=J5100.9:5mm475%1/16WMF-LF402

LPCPLUS_R:YES

1/16WMF-LF

0

402

5%PLACE_NEAR=J5100.11:5mm

6 45 46

6 45 46

55909-0374

LPCPLUS_CONN:YES

M-ST-SM

CRITICAL

6 19

6 45 46

6 46

6 45 46 65

6 45 46

6 45 46

6 24

6 47

6 16 45 89 96

6 17 45

6 47

6 16 45 89 96

6 16 45 89 96

6 45 46

6 17 45

6 16 45

6 47

6 47

6 19 56

6 16 45 89 96

6 16 45 89 96

6 24 96

46 56

PLACE_NEAR=U1800.AV3:5mm

402

15

MF-LF1/16W5%

16 96

46 56

PLACE_NEAR=U1800.BA2:5mm

1/16W5%

MF-LF402

1516 96

46 56

PLACE_NEAR=U6100.2:5mm

15

402MF-LF

5%1/16W

16 96


47

402

1/16W5%

MF-LF

LPCPLUS_R:YES

PLACE_NEAR=J5100.14:5mm47

402MF-LF1/16W5%

PLACE_NEAR=R5126.2:5mm1/16W

47

MF-LF

5%

402

LPC+SPI Debug Connector


=PP5V_S0_LPCPLUS

SMC_TX_L

LPC_SERIRQ

LPC_PWRDWN_L

SMC_TDI

SMC_TCK

LPC_AD<1>

SPI_ALT_MOSI

SPI_ALT_MISO

SPI_ALT_MOSI

SPI_ALT_CLK

SPIROM_USE_MLB

LPCPLUS_RESET_L

SMC_TMS

LPC_FRAME_L

SPI_ALT_MISO

LPC_AD<0>

LPC_AD<3>

LPC_AD<2>

LPC_CLK33M_LPCPLUS

SPI_MOSI

SPI_MISO

SPI_CLKSPI_CLK_R

SPI_CS0_R_L SPI_CS0_L

SPI_ALT_CS_L

SPI_MLB_MOSI

SPI_MLB_CLK

SPI_MLB_CS_L

SPI_MLB_MISO

SPI_MOSI_R

SPI_ALT_CLK

SPI_ALT_CS_L

PM_CLKRUN_L

SMC_TDO

TP_SMC_TRST_L

TP_SMC_MD1

LPCPLUS_GPIO

SMC_RESET_L

=PP3V3_S5_LPCPLUS

SMC_ROMBOOT

SMC_RX_L

R51101 2

R51111 2

R51231 2

R51201 2

R51251

2

R51211 2

R51261

2

R51221 2

R51121 2

R51271

2

R51281

2

J5100

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

4

5 6

7 8

9

051-9585

3.0.0

51 OF 132

47 OF 105

7

6 47

6 47

6 47

96

96

96

6 47

7

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T29 SMBus Connections

T29 Port A MCU

(Write: 0x26 Read: 0x27)

J9330

Panther Point

Panther Point

Panther Point

J2500 & J2550


U3301

Margin Control


U3300

VRef DACs

LED BACKLIGHT

(WRITE: 0x58 READ: 0x59)

Battery Manager - (Write: 0x16 Read: 0x17)

(MASTER)

U4900

SMC

SMC "5" SMBus Connections


SMC



Trackpad


J5800


Digital SMSPCH "SMLink 0" Connections

(MASTER)

U9310

(MASTER)

U1800

(MASTER)(Write: 0xA0 Read: 0xA1)

Sensor ADC A

J3100

SO-DIMM "A"

(See Table)

J2900

J6955

ISL6258 - U7000

Battery

Battery Charger

U1800

access PCH & CPU via PECI.

U5930

Mikey

U4510

CPU Temp

(MASTER)

U4900

U6880

U9701

DP SDRV "A"

U1800

SMLink 1 is slave port to


LIS331DLH: U5920


U4900

(MASTER)



PCH "SMLink 1" Connections


EMC1412-A: U5520

T29 Temp


EMC1414-A: U5570


Battery LED Driver - (Write: 0x36 Read: 0x37)

J3401

ALS

Lid Angle Detect


T29 IC

U3600

(MASTER)

SMC

U4900

(MASTER)

U9310


DP SDRV "A"


NOTE: SMC RMT bus remains powered and may be active in S3 state


PCH SMBus "0" Connections

GPU Temp (Ext)

EMC1414-A: U5550


U4900

SMC

Battery Temp - (Write: 0x92 Read: 0x93)

(MASTER)

XDP Connectors

(Write: 0xB6 Read: 0xB7)

SATA Redriver

Battery(Write: 0xA4 Read: 0xA5)

SO-DIMM "B"

KEPLER: U8000

GPU Temp (Int)


SMC

1/16WMF-LF402

4.7K5%

4.7K5%

MF-LF402

1/16W

MF-LF1/16W5%4.7K

402402MF-LF

4.7K

1/16W5%

5%

402MF-LF1/16W

2.0K

402MF-LF1/16W5%2.0K

1/16WMF-LF

402

5%1K

1/16W5%

MF-LF

1K

402

MF-LF

5%1/16W

4.7K

402

4.7K5%

402MF-LF1/16W

8.2K

1/16W5%

402MF-LF

5%

MF-LF1/16W

8.2K

402

8.2K5%

NO STUFF

1/16W

402MF-LF

NO STUFF

MF-LF

8.2K

1/16W5%

402

0

1/16W

402

5%

MF-LF

5%1/16W

402MF-LF

0

402

1K5%1/16WMF-LFMF-LF

402

1/16W

1K5%

1/16WMF-LF

5%

402

4.7K 4.7K5%1/16WMF-LF402

SDRVI2C:MCU

5%0

MF1/20W

201

SDRVI2C:MCU

05%

MF1/20W

201

5%0

SDRVI2C:SB

MF1/20W

201

05%

SDRVI2C:SB

MF1/20W

201

SMBus Connections


SMBUS_SMC_5_G3_SDAMAKE_BASE=TRUE

SMB_0_S0_DATAMAKE_BASE=TRUESMBUS_PCH_CLK

MAKE_BASE=TRUESMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUESMBUS_SMC_0_S0_SCL

SMBUS_PCH_DATAMAKE_BASE=TRUE

=I2C_SODIMMB_SCL

GPU_SMB_DAT_R

=I2C_GPUTHMSNS_SDA

GPU_SMB_CLK_R


=I2C_PCA9557D_SCL

MAKE_BASE=TRUEI2C_DPSDRVA_SCL

SMB_2_S3_DATA

SMB_2_S3_CLK

MAKE_BASE=TRUEI2C_TBT_SDA

I2C_TBT_SCLMAKE_BASE=TRUE

SMBUS_SMC_2_S3_SCLMAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCLMAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDAMAKE_BASE=TRUE

=I2C_ALS_SDA

SMBUS_SMC_1_S0_SDAMAKE_BASE=TRUE

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

SMB_3_DATA

I2C_DPSDRVA_SDAMAKE_BASE=TRUE

MAKE_BASE=TRUEI2C_DPSDRVA_SCL

=I2C_SMC_SMS_SDA

SMBUS_SMC_3_SCLMAKE_BASE=TRUE

SMBUS_SMC_3_SDAMAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_3

SMB_1_S0_CLK

SMB_1_S0_DATA


=PP3V3_S0_SMBUS_PCH

=I2C_TPAD_SCL

=I2C_TPAD_SDA

=I2C_SODIMMB_SDA

=I2C_T29THMSNS_SDA

=I2C_DPSDRVA_SCL

=I2C_DPSDRVA_SDA

SML_PCH_0_CLKMAKE_BASE=TRUE

=I2C_VREFDACS_SDA

SMB_0_S0_CLK

=SMBUS_XDP_SCL

=SMBUS_XDP_SDA

=PP3V3_S0_SMBUS_PCH

=I2C_VREFDACS_SCL

=I2C_MIKEY_SDA

=I2C_SMC_ADCS_SCL

MAKE_BASE=TRUESML_PCH_1_CLK

MAKE_BASE=TRUESML_PCH_1_DATA

=SMBUS_BATT_SDA

=SMBUS_BATT_SCL

=SMBUS_CHGR_SDA=I2C_SODIMMA_SDA

=I2C_SODIMMA_SCL

=I2C_T29THMSNS_SCL

SML_PCH_0_DATAMAKE_BASE=TRUE

=I2C_MIKEY_SCL

=SATARDRVR_I2C_SDA

=SATARDRVR_I2C_SCL

=I2C_PCA9557D_SDA

=I2C_BKL_1_SCL=I2C_SMC_ADCS_SDA

=I2C_DPSDRVA_SCL

I2C_DPSDRVA_SDAMAKE_BASE=TRUE

=I2C_ALS_SCL

=I2C_SMC_SMS_SCL

=I2C_DPSDRVA_SDA

=PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0

=I2C_BKL_1_SDA

=I2C_GPUTHMSNS_SCL =SMBUS_CHGR_SCLSMBUS_SMC_5_G3_SCLMAKE_BASE=TRUE

SMB_5_CLK

SMB_5_DATA

=PP3V42_G3H_SMBUS_SMC_5

=I2C_TBTAMCU_SCL

=I2C_TBTAMCU_SDA

SMB_3_CLK

=PP3V3_S0_T29I2C

R52911

2

R52901

2

R52611

2

R52601

2

R52801

2

R52811

2

R52701

2

R52711

2

R52511

2

R52501

2

R52101

2

R52111

2

R52211

2

R52201

2

R5223

1 2

R5222

1 2

R52011

2

R52001

2

R52301

2

R52311

2

R52351

2

R52341

2

R52371

2

R52361

2

051-9585

3.0.0

52 OF 132

48 OF 105

16 96

45 99

45 99

16 96

29

82

51

82

7

31

48

33 98

33 98

45 99

32

45 99

51

51

48

48

55

45 99

45 99

7

7

7 48

54

54

29

48 87

48 87

16 96

31

23

23

7 48

31

63

104

16 96

16 96

64

64

65 27

27

16 96

63

41

41

31

90 104

48 87

48

32

55

48 87

7 48 7

90

51 65

7

87

87

7

OUT

IN

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

OUT

V+

REFIN+

IN- OUT

GND

OUT

IN

V-

V++

-

V-

V++

-

V-

V++

-

OUT

IN

IN

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

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D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




DC-In Voltage Sense & Enable (VD0R)CPU VCCIO 1.05V Load Side Current Sense (IC1C)

GPU Core Load Side Current Sense (IG0C)

Gain Number needs Updating!

CPU Core Voltage Sense (VC0C)

AXG Core Voltage Sense (VN0C)

GPU Core Voltage Sense (VG0C)

CPU VCCSA Voltage Sense (VC2C)

CPU VCCSA Load Side Current Sense (IC2C)

divider when AC present.

Enables DC-In VSense

DDR 1.5V S3 (Memory) Current Sense (IM0C)Gain: 200x, EDP: 9A

Rsense: 0.001 (R5370)

V across Rsense: 25 mV

Gain needed: 132.0x

Gain: 161.5x, EDP: 20 A

Gain: 130.2x, EDP: 25 A

Rthevenin = 4573 Ohms

PBUS Voltage Sense & Enable (VP0R)

Rsense: 0.001 (R7640)

Gain needed: 550x

Rthevenin = 4573 Ohms

Enables PBUS VSensedivider when in S0.

Gain: 549x, EDP: 6A

Rsense: 0.001 (R7140)

V across Rsense: 6mV

Rsense: 0.001 (R8940)

Gain needed: 336.7x


Gain needed: 165x


CRITICAL

SC70-5

ISNS_GPU_IOUT

OPA333DCKG4

3 RES,100K,201 C5358,C5327,C5367117S0008

CRITICAL

SIGNAL_MODEL=EMPTY

OPA333DCKG4

=PP3V3_S3_ISNS

ISNS_CPUVCCSA_IOUT

SMC_CPUVCCIO_ISENSE

SMC_GPU_VSENSE

AXGVSENSE_IN

CPUVCCSAVSENSE_IN

GFXIMVP6_IMON

=PPVCORE_S0_CPU

=PP3V3_S0_ISNS

PM_SUS_EN

ISNS_1V5_S3_DDR_N

ISNS_1V5_S3_DDR_P

ISNS_1V5_S3_DDR_IOUT

GND_SMC_AVSS

GND_SMC_AVSS

=PPVCCSA_S0_REG

GND_SMC_AVSS

SMC_CPU_VSENSECPUVSENSE_IN

GPUVSENSE_IN=PPVCORE_GPU_REG

=PPVCORE_S0_AXG_REG SMC_AXG_VSENSE

GND_SMC_AVSS

GND_SMC_AVSS

ISNS_CPUVCCIO_R_P

ISNS_CPUVCCIO_R_N

GND_SMC_AVSS

GND_SMC_AVSS

GND_SMC_AVSS

GND_SMC_AVSS

SMC_DCIN_VSENSE

GND_SMC_AVSS

SMC_PBUS_VSENSE

PBUSVSENS_EN_L_DIV

ISNS_CPUVCCIO_IOUT

=PP1V5_S3_DDR_ISNS_R

DCIN_S5_VSENSE

PBUSVSENS_EN_L

PBUS_S0_VSENSE

=PP1V5_S3_DDR_ISNS

=PPBUS_S0_VSENSE

=PBUSVSENS_EN

CPUVCCIOS0_CS_P

CPUVCCIOS0_CS_N

VCCSAS0_CS_P

VCCSAS0_CS_N ISNS_CPUVCCSA_R_N

ISNS_CPUVCCSA_R_P

SMC_MEM_ISENSE

=PP3V3_S0_ISNS

SMC_CPUVCCSA_VSENSE

DCIN_VSENSE_EN=CHGR_ACOK

DCINVSENS_EN_L

=PPDCIN_S5_VSENSE

SMC_GPU_ISENSE

=PP3V3_S0_ISNS

Power Sensors: Load Side

SYNC_MASTER=J31_YONAS SYNC_DATE=01/19/2012

LOADISNS:NO

SM

PLACE_NEAR=R7510.2:5 MM

MF201

1%1/20W

4.53K

PLACE_NEAR=U4900.E2:5MM

46

SM


0

5%1/20WMF201

MF

0

NOSTUFF

201

1/20W5%

74

65 46

4.53K

1/20W1%

201MF

PLACE_NEAR=U4900.G1:5MM 0.22UF

X5R6.3V20%

0201

PLACE_NEAR=U4900.G1:5MM

46

SM


0.22UF

6.3V

PLACE_NEAR=U4900.B2:5MM

X5R0201

20%

6.3VX5R0201

20%


20%

X5R0201

6.3V

0.22UF


X5R6.3V20%0.22UF

0201

X5R6.3V20%

0201

0.22UF


0201X5R

0.22UF

PLACE_NEAR=U4900.C1:5MM

6.3V20%

0201

20%6.3VX5R

0.22UF

0201

0.22UF20%6.3VX5R

PLACE_NEAR=U4900.F1:5MM

X5R6.3V20%0.22UF

0201


SC70-5

LOADISNS:YES

LOADISNS:YESCRITICAL

SC70-5

OPA333DCKG4

84

4.53K

1/20W1%

201

NOSTUFFPLACE_NEAR=U4900.B2:5MM

MF

1/20WMF

1%

201

SIGNAL_MODEL=EMPTY

499K

1%1/20W

1M

MF


4.53K

201

1%

MF1/20W

46

0.1UF

CERM402

20%10V

CRITICAL

INA210SC70

PLACE_NEAR=R5370.4:10MM

PLACE_NEAR=R5370.3:10MM0612

0.0011%1W

MF-1

7

7

101 66

101 66

MF-LF402

1/16W1%

1.82K

SIGNAL_MODEL=EMPTY

LOADISNS:YES

SIGNAL_MODEL=EMPTY

LOADISNS:YES

1.82K

1%

MF-LF402

1/16W

402

LOADISNS:YES

MF-LF

1M

1/16W1%

SIGNAL_MODEL=EMPTY

LOADISNS:YES

1M

1%1/16WMF-LF402

10V20%

402

0.1UF

CERM

LOADISNS:YES

201

1/20WMF

4.53K


1%

46

101 71

LOADISNS:YES

201

1/20W

6.19K

MF

1%

101 71

1/20W1%

201MF

6.19K

SIGNAL_MODEL=EMPTY

LOADISNS:YES

SIGNAL_MODEL=EMPTY

1/20W

201MF

1%

LOADISNS:YES

1M

1/20W

201MF

1%

1M

LOADISNS:YES

SIGNAL_MODEL=EMPTY

LOADISNS:YESPLACE_NEAR=U4900.A6:5MM

1/20W1%

MF

4.53K

201

46

46

4.53K

201MF

1%1/20W


20%10VCERM402

0.1UF

SM

PLACE_NEAR=R8940.1:5 MM1/20W1%

4.53K

201MF


46

100K

MF-LF

1%1/16W

402


5.49K

MF201

1%1/20W

SOT-963

CRITICAL

100K

MF-LF402

1%1/16W

MF

27.4K

201

1%1/20W


46

NTUD3169CZSOT-963

CRITICAL

1/20WMF

5.49K


201

1%

1/20W


27.4K

MF201

1%

46

1/16W

402

1%

MF-LF

100K

402

100K

MF-LF

1%1/16W

74

1/20W1%

201MF


4.53K46

201

LOADISNS:YES

LOADISNS:YESLOADISNS:YES

LOADISNS:YESLOADISNS:YES

LOADISNS:YES

ISNS_GPU_INV

SIGNAL_MODEL=EMPTY

0.22UFLOADISNS:YES

LOADISNS:YES

LOADISNS:YES


SMC_CPUVCCSA_ISENSE


PDCINVSENS_EN_L_DIV

NTUD3169CZ

SIGNAL_MODEL=EMPTY

R53301 2

XW5330

1 2

R53201 2

XW5320

1 2

R53021

2

R53011

2

R53031

2

R53041

2

Q5300

6

3

2

5

1

4

R53131

2

R53121

2

Q5310

6

3

2

5

1

4

R53141

2

R53111

2

R53351 2

XW5335

1 2

C53501

2

R53581 2

R53271 2

R53261 2

R53251

2

R53231 2

R53241 2

R53671 2

C53601

2

R53661 2

R53651

2

R53631 2

R53641 2

R5370 2

1

4

3

U5370

2

5

4

6

1

3

C53701

2

R53791 2

R53571 2

R53501

2

R53591 2

U53601

3

4

2

5

U5320

1

3

4

2

5

U53501

3

4

2

5

C53041

2

C53141

2

C53201

2

C53301

2

C53351

2

C53791

2

C53671

2

C53271

2

C53581

2

XW5380

1 2

C53801

2

R53801 2

R53931 2

R53941 2

051-9585

3.0.0

53 OF 132

49 OF 105

104 103 7

105 14 12 7

104 103 50 49 7

101

101

103 46 45

103 50 49 46 45

66 7

103 50 49 46 45

7

70 7

103 50 49 46 45

103 50 49 46 45

101

103 50 49 46 45

103 50 49 46 45

103 50 49 46 45

103 50 49 46 45

103 50 49 46 45

7

101

104 103 50 49 7

7

104 103 50 49 7

50 49

V+

REFIN+

IN- OUT

GND

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

OUTIN OUTIN

OUT

IN

IN

IN

IN

IN

IN

V-

V++

-

OUT

V-

V++

-

IN

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

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D

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




Gain needed: 48.25x

V across Rsense: 68.4 mV

Rsense: 0.003 (R5400)

OTHER High Side Current Sense (IO0R)

Gain needed: 211.54x (Kepler)

GPU High Side Current Sense (IG0R)

CPU Core Load Side Current Sense (IC0C)

AXG Core Load Side Current Sense (IN0C)

Rsense: 2x of 0.00075 (R7550, R7560), Rsum: 0.000375.

Rsense: 0.003 (R5410)

Gain: 200x, EDP: 5.2 A (Kepler)

Gain: 185.5x, EDP: 46 A

Charger Gain: 20x

DC-In (AMON) Current Sense (ID0R)


Gain needed: 191.3x

Rsense: 3x of 0.00075 (R7510, R7520. R7530), Rsum: 0.00025.


Gain needed: 136.1x

Gain: 136.1x, EDP: 97 A

Gain needed: 64.1x

Charger Gain: 36x

Rsense: 0.010 (R7050)

Max Measured I: 9.2 A

Rsense: 0.020 (R7020)

Max Measured I: 8.3 A

Gain: 50x, EDP: 10.3 A

Rsense: 0.005 (R5440)


CPU High Side Current Sense (IC0R)

Charger (BMON Prod) Current Sense (IPBR)


Gain: 50x, EDP: 22.8 A

CRITICAL

INA213SC70

7

7

2%0.5W

CRITICAL

0.003

MF0612

7

7

10V20%

402CERM

0.1UF

1/20W1%

201MF

4.53K


46

0.1UF

CERM402

20%10V

4.53K

MF

1%1/20W


201

46

46

1/20W1%

201MF

4.53K


10V20%

402

0.1UF

CERM

2%0.5W

0.005

CRITICAL

MF0612

7

7

SC70

CRITICAL

INA210

SC70INA213

CRITICAL


MF201

1%1/20W

45.3K46 65 46

4.53K

1%


1/20WMF201

65

LOADISNS:YES

732K

MF-LF402

1%1/16W

SIGNAL_MODEL=EMPTY

3.57K

MF-LF402

1%

LOADISNS:YES

1/16W

LOADISNS:YES

3.57K

MF-LF402

1%1/16W

LOADISNS:YES

732K

MF-LF402

1%1/16W SIGNAL_MODEL=EMPTY

LOADISNS:YES

4.53K

MF201

1%1/20W


46

CERM402

20%10V


LOADISNS:YES

0.1UF

201

1%1/20W


LOADISNS:YESSIGNAL_MODEL=EMPTY

MF

5.23K69 70 101

201

1%1/20WSIGNAL_MODEL=EMPTY


LOADISNS:YES MF

5.23K69 70 101

201

1%1/20W

LOADISNS:YESSIGNAL_MODEL=EMPTYPLACE_NEAR=R7530.3:5MM

MF

5.23K69 70 101

70 101

70 101

201

1%1/20W



MF

5.23K

201

1%1/20W



MF

5.23K

69 70 101

201

1%1/20W

LOADISNS:YESSIGNAL_MODEL=EMPTYPLACE_NEAR=R7510.4:5MM

MF

5.23K

LOADISNS:YES

OPA333DCKG4

CRITICAL

SC70-5

46

0.1UF

CERM402

20%10V

LOADISNS:YESPLACE_NEAR=U5460.5:3MM

LOADISNS:YES

4.53K

MF201

1%

OPA333DCKG4SC70-5

CRITICAL

1.33K

MF-LF402

1%1/16W

LOADISNS:YES

1.33K

MF-LF402

1%1/16W

LOADISNS:YES

5.23K

MF402

0.5%1/16W

LOADISNS:YES

MF402

0.5%1/16W

PLACE_NEAR=R7550.4:5MMSIGNAL_MODEL=EMPTYLOADISNS:YES

70

70 101

732K

MF-LF402

1%1/16W SIGNAL_MODEL=EMPTY

LOADISNS:YES

732K

MF-LF402

1%


2%0.003

0.5WMF

0612CRITICAL

5.23K

MF402

1/16WLOADISNS:YES

0.5%PLACE_NEAR=R7550.3:5MMSIGNAL_MODEL=EMPTY

70 101

5.23K

MF402

0.5%1/16W

PLACE_NEAR=R7560.3:5MMSIGNAL_MODEL=EMPTYLOADISNS:YES

70 101

0201

0.22UF20%6.3VX5R


0201

0.22UF20%6.3VX5R PLACE_NEAR=U4900.F2:5MM

0.22UF20%6.3VX5R


0201

PLACE_NEAR=U4900.A4:5MM0201

6.3VX5R-CERM

0.022UF10%

0.22UF20%6.3VX5R0201


0.22UF20%6.3VX5R0201

PLACE_NEAR=U4900.H1:5MMLOADISNS:YES

0.22UF20%6.3VX5R0201

LOADISNS:YESPLACE_NEAR=U4900.E1:5MM

2 C5451,C5461


Power Sensors: High Side, CPU, AXG

CPUIMVP_ISUM_R_N

=PPVIN_S5_HS_GPU_ISNS

CHGR_BMON

HS_COMPUTING_IOUT

CPUIMVP_ISNS1G_R_N

CPUIMVP_ISNS2G_P

CPUIMVP_ISNS_N

CPUIMVP_ISNS_P

CPUIMVP_ISNS1_P

=PP3V3_S0_IMVPISNS

CPUIMVP_ISUM_IOUT

CPUIMVP_ISUM_R_P

CPUIMVP_ISNS2_P

CPUIMVP_ISNS3_P

CPUIMVP_ISNS3_N

CPUIMVP_ISNS2G_N

CPUIMVP_ISUMG_R_N

=PP3V3_S0_ISNS

ISNS_HS_COMPUTING_P

=PPVIN_S5_HS_COMPUTING_ISNS_R

ISNS_HS_COMPUTING_N

CPUIMVP_ISNS1_N

=PP3V3_S0_ISNS

ISNS_HS_GPU_P

HS_GPU_IOUT

=PPVIN_S5_HS_GPU_ISNS_R

ISNS_HS_GPU_N

HS_OTHER_IOUT

=PPVIN_S5_HS_OTHER_ISNS_R

=PPVIN_S5_HS_OTHER_ISNS

ISNS_HS_OTHER_N

CHGR_AMON

CPUIMVP_ISNS1G_R_P CPUIMVP_ISUMG_R_P=PP3V3_S0_ISNS

=PPVIN_S5_HS_COMPUTING_ISNS

ISNS_HS_OTHER_P

CPUIMVP_ISNS2_N

SMC_CPU_HI_ISENSE

GND_SMC_AVSS

SMC_GPU_HI_ISENSE

GND_SMC_AVSS

SMC_OTHER_HI_ISENSE

SMC_BMON_ISENSE

GND_SMC_AVSS

SMC_DCIN_ISENSE

GND_SMC_AVSS

SMC_AXG_ISENSE

GND_SMC_AVSS

SMC_CPU_ISENSE

GND_SMC_AVSS

CPUIMVP_ISNS1G_P

CPUIMVP_ISNS1G_N

GND_SMC_AVSS

101

PLACE_NEAR=R7560.3:5MMSIGNAL_MODEL=EMPTY

5.23K

1/16W

LOADISNS:YES

CPUIMVP_ISUMG_IOUT

PLACE_NEAR=U4900.H1:5MM

LOADISNS:NORES,100K,201117S0008

1/20W

=PP3V3_S0_IMVPISNS

U5400

2

5

4

6

1

3

R5410 2

1

4

3

C54111

2

R54131 2

C54011

2

R54031 2

R54331 2

C54311

2

R5430 2

1

4

3

U54102

5

4

6

1

3

U5430

2

5

4

6

1

3

R54221 2

R54411 2

R54541

2

R54531 2

R54521 2

R54551 2

R54511 2

C54501

2

R54561 2

R54571 2

R54581 2

R54721 2

R54711 2

R54701 2

U5450

1

3

4

2

5

C54601

2

R54611 2

U5460

1

3

4

2

5R5462

1 2

R54631 2

R54681 2

R54671 2

R54651 2

R54641

2

R5400 2

1

4

3

R54661 2

R54691 2

C54031

2

C54131

2

C54331

2

C54221

2

C54411

2

C54611

2

C54511

2

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101

7 50

101

7 50

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101

101

7 49 50 103 104

101

101

101

101 101

7 49 50 103 104

101

45 46 49 50 103

45 46 49 50 103

45 46 49 50 103

45 46 49 50 103 45 46 49 50 103

45 46 49 50 103

45 46 49 50 103

BI

BI

BI

BI

BI

BI

ALERT*

GNDSMCLK

SMDATA

VDD

THRM_PADDN2

DP2

DN1

THERM*/ADDRDP1

ALERT*

GNDSMCLK

SMDATA

VDD

THRM_PADDN2

DP2

DN1

THERM*/ADDRDP1

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GPU Proximity, GPU Die, Left Heat Pipe, Right Fin StackI2C Write: 0x98, I2C Read: 0x99

Thermal Sensor B:

I2C Write: 0x98, I2C Read: 0x99

CPU Proximity, Memory Proximity, T29/PCH Proximity, LVDS Proximity (Airflow)

Placement Note:

Place U5550 on bottom side under GPU

Placement Note:

Place Q5503 under the Left Heat Pipe,

Thermal Diode: GPU Die

Placement Note:

near GPU.

Thermal Diode: Right Fin Stack

Placement Note:

close to the Right Fin Stack.

Place Q5501 on the bottom side,

Placement Note:

Placement Note:

Place Q5502 on the bottom side,

close to the LVDS connector.

Place U5570 on bottom side under CPU

Placement Note:

Thermal Sensor: CPU Proximity

Placement Note:

Thermal Diode: T29/PCH Proximity

Place between the T29 and PCH.

connector.

Thermal Sensor: GPU Proximity

Place side is either side.

Thermal Diode: Left Heat Pipe

Thermal Sensor A:

None.

Thermal Diode: LVDS Prox (Airflow)

Thermal Diode: Memory Proximity

Place Q5505 on the right side of the DIMM

Thermal Sensor: T29 Die

Note: Use GND pin B1 on U3600 for N leg.

SM PLACE_NEAR=U3600.B1:2mm

5%

402

10K

1/16W

MF-LF

NOSTUFF

PLACE_SIDE=BOTTOM

5%22PF

CERM50V

402

NOSTUFF

PLACE_NEAR=Q5501.2:5MM


BC846BMXXHSOT732-3 CRITICAL

PLACE_SIDE=BOTTOM


CERM

5%22PF

50V

402

NOSTUFF


SOT732-3CRITICAL

BC846BMXXH

48

48

81 101

81 101

10K

MF-LF402

5%1/16W

10K

MF-LF402

5%1/16W

48

48

0.1uF

CERM402

20%10V

402CERM

SIGNAL_MODEL=EMPTY0.0022uF

10%50V



1/16W5%

402MF-LF

47

10%SIGNAL_MODEL=EMPTY0.0022uF

CERM402

50V



SOT732-3BC846BMXXH

CRITICAL


50V


NOSTUFF402CERM

22PF5%

BC846BMXXHSOT732-3 CRITICAL

PLACE_SIDE=BOTTOM22PF

CERM50V

402

NOSTUFF



5%

CRITICAL

BC846BMXXHSOT732-3



5%22PF

CERM402

NOSTUFF 50V

EMC1414

PLACE_SIDE=BOTTOM

DFN

EMC1414

PLACE_SIDE=BOTTOM

DFN

X5R-CERM0201

10V

0.1UF10%

2200PF


10%

X7R-CERM10V

0201

SIGNAL_MODEL=EMPTY


10%2200PF

X7R-CERM10V

0201

SIGNAL_MODEL=EMPTY

10K

MF1/20W

201

5%10K

MF1/20W

201

5%

201MF

1/20W

47

5%


Thermal Sensors

TBT_THERMDN

GPUTHMSNS_D_P

GPUTHMSNS_D_N

GPU_TDIODE_N GPUTHMSNS_ALERT_L

GPUTHMSNS_THM_L

=PP3V3_S0_GPUTHMSNS

TBT_THERMDPTP_TBT_THERMDPMAKE_BASE=TRUE

CPUTHMSNS_ALERT_L

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.38 mmPP3V3_S0_CPUTHMSNS_R

CPUTHMSNS_D2_N

CPUTHMSNS_D2_P

CPUTHMSNS_D1_N

CPUTHMSNS_THM_L

CPUTHMSNS_D1_P

=I2C_GPUTHMSNS_SCL

=I2C_GPUTHMSNS_SDA

=PP3V3_S0_CPUTHMSNS

GPU_TDIODE_P

PP3V3_S0_GPUTHMSNS_RMIN_LINE_WIDTH=0.38 mm


XW5520

1 2

R55201

2

C55011

2

Q5501

1

3

2 C55031

2

Q5503 1

3

2

R55721

2

R55711

2

C55701

2

C5571 1

2

R55701 2

C5590 1

2

Q5504 1

3

2

C55041

2

Q5502

1

3

2C55021

2

Q5505 1

3

2

C55051

2

U5550

83

5

2

4

6

10

9

7

11

1

U5570

83

5

2

4

6

10

9

7

11

1

C55501

2

C5510 1

2

C5552 1

2

R55511

2

R55521

2

R55501 2

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101

101

7

101

101

101

101

7

G

S D

G

S DIN

OUT OUT

IN

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518S0369

Left Fan Right Fan

518S0369

47K

MF-LF402

5%1/16W

47K

MF-LF402

5%1/16W

47K

MF-LF402

5%1/16W

47K

MF-LF402

5%1/16W

100K

MF-LF402

5%1/16W

2N7002DW-X-GSOT-363

100K

MF-LF402

5%1/16W

2N7002DW-X-GSOT-363

CRITICAL

78171-0004M-RT-SM

CRITICAL

78171-0004M-RT-SM

45

45 45

45

Fan Connectors


SMC_FAN_0_TACH

=PP3V3_S0_FAN_LT

=PP5V_S0_FAN_LT

FAN_LT_TACH

=PP3V3_S0_FAN_RT

FAN_RT_TACH

=PP5V_S0_FAN_RT

FAN_RT_PWMSMC_FAN_0_CTL

SMC_FAN_1_TACH

SMC_FAN_1_CTLFAN_LT_PWM

R56501

2R56551 2

R56601

2R56651 2

R56511

2

Q5660

3

5

4

R56611

2

Q5660

6

2

1

J5650

5

6

1

2

3

4

J5660

5

6

1

2

3

4

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7

7

6

7

6

7

6 6

P2_4

P2_6

VDD

P0_4

P0_2

P2_0P2_2P

0_0

P2_3P2_1P4_7P4_5P4_3P4_1P3_7P3_5P3_3P3_1P5_7P5_5P5_3P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSS

D+D-VDD

P7_0

P1_0

P1_2

P1_4

P1_6 P5_0

P5_2P5_4P5_6P3_0P3_2P3_4

P4_0P4_2P4_4P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PADTHRML

(SYM-VER2)

P0_1

IN

NC

NC

OUT

OUT

IN

NC

OUT

IN_2

IN_3

IN_1

OUT_2

OUT_3

OUT_ALL#

OE

THRMGND

OUT_1

VDD

PAD

(IPD)

(IPD)

(IPD)

(IPD)

D

G S

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PSOC USB CONTROLLER- SPI HOST TO Z2

(PP3V3_S3_PSOC)

TPAD Buttons Disable

LID OPEN => SMC_LID_LC ~ 3.42V

THE TPAD BUTTONS WILL BE DISABLE

LID CLOSE => SMC_LID_LC < 0.50V

0.6 V3V3 LDO

PSOC

18V BOOSTER

337S2983

VDD

VIN 0.0188 V

0.021 V0.012 V

0.012 V

0.204 V0.0255 V

POWERV_SNSR_SNSCURRENTIC

10UA- USB INTERFACES TO MLB

TMP102 V+80UA

VOUTVDD 60MA (MAX)

60MA (MAX)

8MA (TYP)

4MA (MAX)

14MA (MAX)

2.55 KOHM

10 OHM0.2 OHM

4.7 OHM

0.255E-6 W16.32E-6 W

0.72E-3 W

294E-6 W

75.2E-6 W

96E-6 W

- KEYBOARD SCANNER

518S0637

36E-3 W

PIN NAME

Keyboard Connector

1.5 OHM

- TRACKPAD PICK BUTTONS

Pull-up in U5010.

Left shift, option & control keys combined with power button cause SMC RESET# assertion.

SMC Manual Reset & Isolation

Keys ANDed with MSP power to isolate when MSP is not powered. No IPD on OE input pin PP3V3_S4 (symbol error).

ISSP SCLK/I2C SCL ISSP SDATA/I2C SDA

PLACE THESE COMPONENTS CLOSE TO J5800THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

WHEN THE LID IS CLOSED

BYPASS=U5701.49:50:11 mm

4.7UF

X5R603

20%6.3V

BYPASS=U5701.49:50:8 mm

0.1UF

X7R-CERM402

10%16V

BYPASS=U5701.49:50:5 mm

CERM

5%50V

402

100PF

BYPASS=U5701.22:19:8 mm

0.1UF

X7R-CERM402

10%16V

BYPASS=U5701.22:19:5 mm

100PF

CERM402

5%50V

BYPASS=U5701.22:19:11 mm

4.7UF

X5R603

20%6.3V

402

24

MF-LF

5%1/16W

OMIT

CY8C24794MLF

CRITICAL

MF-LF402

24

5%1/16W

45 46 64

PLACEMENT_NOTE=NEAR J5713

0.1UF

CERM402

20%10V

1K

MF-LF402

5%1/16W

470

MF-LF402

1%1/16W

10K

MF-LF402

1%1/16W

CRITICAL

FF14-30A-R11B-B-3H

F-RT-SM

6 45 46

1/16W

1.5

5%

402MF-LF

PLACE_SIDE=BOTTOM

46

74

402

5%

MF-LF1/16W

220K

0.1UF

X7R-CERM402

10%16V

46

SLG4AP021TQFN

CRITICAL

CRITICAL

SOD-VESM-HF

SSM3K15FV

WELLSPRING 1SYNC_MASTER=J30_MLB SYNC_DATE=06/10/2011

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MMPP3V3_S3_PSOC

WS_KBD10

WS_KBD3

WS_KBD1

WS_KBD8

WS_LEFT_SHIFT_KBD

TP_PSOC_SDA

TP_ISSP_SCLK_P1_1

TP_PSOC_P1_3

Z2_CLKIN

TP_ISSP_SDATA_P1_0

PSOC_MISO

PSOC_F_CS_L

Z2_SCLK

Z2_RESET

Z2_MISO

Z2_KEY_ACT_L

WS_CONTROL_KEY

WS_LEFT_OPTION_KEY

TP_PSOC_SCL

WS_KBD19WS_LEFT_SHIFT_KEY

WS_LEFT_OPTION_KBD

WS_CONTROL_KBD

=PP3V3_S4_TPAD

=PP3V42_G3H_TPAD

WS_LEFT_OPTION_KEY

WS_CONTROL_KEY

SMC_TPAD_RST_L

WS_LEFT_SHIFT_KEY

WS_KBD5

USB_TPAD_R_N

=PP3V3_S4_TPAD

WS_KBD21

=PP3V3_S4_TPAD

=PP3V42_G3H_TPAD

WS_KBD15_C

WS_LEFT_OPTION_KBD

WS_KBD16_NUM

WS_KBD15_C

WS_KBD16N

WS_KBD15_CAP

WS_KBD8

WS_KBD7

WS_KBD23

WS_KBD22

WS_KBD19

WS_KBD20

WS_KBD21

WS_KBD9

WS_KBD10

WS_KBD12

WS_KBD11

WS_KBD13

WS_KBD14

WS_KBD17

WS_KBD18

WS_KBD5

WS_KBD4

WS_KBD3

WS_KBD2

WS_KBD1

WS_KBD18

WS_KBD4

WS_KBD6

WS_KBD17

WS_KBD16N

WS_KBD14

WS_KBD12

WS_KBD13

WS_KBD11

WS_KBD2

USB_TPAD_P

USB_TPAD_N

WS_KBD_ONOFF_L

WS_LEFT_SHIFT_KBD

WS_CONTROL_KBD

USB_TPAD_R_P

SMC_ONOFF_L

WS_KBD6

Z2_DEBUG3

TP_P7_7

PSOC_SCLK

WS_KBD20

TPAD_VBUS_EN

Z2_MOSI

Z2_CS_L

PSOC_MOSI

BUTTON_DISABLE

BUTTON_DISABLE

SMC_LID

WS_KBD22

WS_KBD23

WS_KBD9

WS_KBD7

=PSOC_WAKE_L

PICKB_L

Z2_HOST_INTN

C57061

2

C57051

2

C57041

2

C57031

2

C57021

2

C57011

2

R57021 2

U5701

20

21

45

54

46

53

47

52

48

51

25

18

26

17

27

16

28

15

412

421

43

56

44

55

3310

349

358

367

376

385

394

403

2914

3013

3112

3211

24

23

57

22

49

19

50

R57011 2

C5710 1

2

R57101 2

R57141 2

R57151 2

J5713

31

32

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

R57042 1

R57031

2

C57501

2

U5750

5

1

2

3

4

9

8

7

6

11

10

Q57013

12

57 OF 132

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6 53

6 53

6 53

6 53

6

8

6

6 54

8

6 54

6 54

6 54

6 54

6 54

6 54

53

53

6

6 53 53

6 53

6 53

7 53 54

7 53

53

53

53

6 53

25 95 101

7 53 54

6 53

7 53 54

7 53

53

6 53

6

53

53

6

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

6 53

53

6 53

6 53

6 53

6 53

6 53

8 95

8 95

6

6 53

6 53

25 95 101

6 53

6 54

6

6 54

6 53

6 54

6 54

6 54

53

53

6 53

6 53

6 53

6 53

6 54

6 54

BI

THRML

CAP

SW

LED

VIN

CTRL

PADGND

NC CTRL

PGND

THRML

L

VIN

DO

FB

SW

PAD GND


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Keyboard Backlight Driver & Detection

518S0691

on keyboard backlight flex

Keyboard Backlight Connector

J5815 pin 1 is grounded

BOOSTER +18.5VDC FOR SENSORS

PIN 18 IS NC ON Z2 FLEX

IPD Flex Connector

If HIGH, keyboard backlight not present

If LOW, keyboard backlight present

- POWER CONSUMPTION

PIN 21 IS NC ON CUMULUS FLEX

516S0689

- RIPPLE TO MEET ERS

- DROOP LINE REGULATION

To detect Keyboard backlight, SMC will

grounded when KB BL flex connected.

R5853 always stuffed, R5854 only

tristate and read SMC_SYS_KBDLED:

(SMC_KBDLED_PRESENT_L)

BOOSTER DESIGN CONSIDERATION:

- 100-300 KHZ CLEAN SPECTRUM

- STARTUP TIME LESS THAN 2MS

- R5812,R5813,C5818 MODIFIED

M-ST-SM

55560-0228

CRITICAL

CRITICAL

B0520WSXG

TPAD:Z2

SOD-323

TPAD:Z2

10%1UF

25VX5R

603-1

TPAD:Z2

MF-LF

5%

402

0

1/16W

0.1UF

16V10%

402X7R-CERM

TPAD:Z2

402

1/16W

0

5%

MF-LF

2.2UF

TPAD:Z2

X5R603

16V10%

TPAD:Z2

CRITICAL

3.3UH-870MA

VLF3010AT-SM-HF

TPAD:Z2

100K1%

MF-LF402

1/16W

45

4.7K5%1/16WMF-LF402

402

5%1/16WMF-LF

470K

OMIT_TABLE

LT3491

CRITICAL

DFN

402MF-LF

5%1/16W

10K

NO STUFF

10V

1UF

402-1X5R

10%

10

1/16WMF-LF

1%

402

10UH-0.58A-0.35OHM

CRITICAL

1098AS-SM

CRITICAL

FF18-4A-R11AD-B-3HF-RT-SM

50V

39PF

TPAD:Z2

5%

402CERM

TPAD:Z2

MF-LF

1M1%1/16W

402

1/16WMF-LF402

71.5K1%

TPAD:Z2

TPAD:Z2

NP0-C0G402

1000PF5%25V

NOSTUFF

0402-LF


FERR-120-OHM-1.5A

NOSTUFF

CERM402

20%0.1UF

10VPLACE_NEAR=J5800.18:3MM

50V10%0.47UF

0603CERM-X5R CERM-X5R

50V10%0.47UF

0603

TPAD:Z2

CRITICAL

QFN-1TPS61045

SYNC_MASTER=J31_LINDA SYNC_DATE=07/01/2011

WELLSPRING 2

IC,STLA02,1-STRING LED DRIVER,2X2DFN-6353S3085 U5850 CRITICAL1

VOLTAGE=5VMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MMPP5V_S5_P18V5S5_VIN=PP5V_S5_TPAD

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MMPP5V_S4_P18V5S5

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 MMSWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.3 MMKBDLED_SW

KBDLED_CAP


PP5V_S5_CUMULUS


VOLTAGE=5V

=PP5V_S0_KBDLED

SMC_KDBLED_PRESENT_L

Z2_RESET

PSOC_F_CS_L

PSOC_MOSI

PSOC_SCLK

=I2C_TPAD_SCL

Z2_DEBUG3

Z2_CLKIN

Z2_MISO

Z2_SCLK

Z2_KEY_ACT_L

Z2_MOSI

PICKB_L

=PP3V3_S0_TPAD

VOLTAGE=18.5V

PP18V5_Z2


PP18V5_S4_R


VOLTAGE=18.5V

PP18V5_Z2

PSOC_MISO

Z2_HOST_INTN

Z2_BOOST_EN

=I2C_TPAD_SDA

Z2_CS_L

=PP3V3_S4_TPAD


KBDLED_ANODESMC_SYS_KBDLED


P18V5S4_SW

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.50MM

P18V5S4_FB

Z2_BOOST_EN

J5800

1

10

1112

1314

1516

1718

19

2

20

2122

34

56

78

9

D5802

A K

C5819 1

2

R58061 2

C5816 1

2

R58052 1

C58171

2

L5801

1 2

R58111

2

R58541

2

R58531

2

U5850

4

6

2

5

3

7

1

R58521

2

C5850 1

2

R58551

2

L5850

1 2

J5815

1

2

3

4

C5818 1

2

R58121

2

R58131

2

C58151

2

L5800

1 2

C58001

2

C58551

2

C58561

2

U5805

53

4

6

1

7

8

9

2

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6

7

6

6 53

6 53

6 53

6 53

48

6 53

6 53

6 53

6 53

6 53

6 53

6 53

7

6 54

6 54

6 53

6 53

6 54

48

6 53

7 53

6

6 54

INT2

VDD VDD_IO

SDO

GND

NC

RESERVED

INT1

CS

SDA/SDI/SDO

SCL/SPC

NCNC

OUT

BI

IN

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placed on board bottom-side (view thru top):

Front of system

Circle indicates pin 1 location when placed

338S0687

+X

+Y

in correct orientation

+Z (dn)

Desired orientation when

NOTE: SDA and SCL have internal pull-ups to VDD_IO.

SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)

SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)

CRITICAL

LGA

LIS331DLH

PLACEMENT_NOTE=See schematic for orientation.

BYPASS=U5920.14:13:8 mm

6.3V

0.1UF

201X5R

10%

BYPASS=U5920.14:13:8 mm603X5R6.3V

10UF20%

10K

1/20W5%

MF201

10K5%

1/20WMF

201 201

1/20W5%

0

MF

201

1/20W

0

MF

5%

10K5%

1/20W

201MF

45

48

48

MF

5%1/20W

NOSTUFF

201

10K


Digital Accelerometer

SMS_I2C_SEL

=PP3V3_S3_SMS

=I2C_SMC_SMS_SCL

SMS_ADDR_SELECT

I2C_SMC_SMS_SDA_R

TP_SMS_INT2

SMS_INT_L

I2C_SMC_SMS_SCL_R

=I2C_SMC_SMS_SDA

U5920

8

5

12

13

16

11

9

2

3

10

15

4

6

7

14

1C59221

2

C5926 1

2

R59201

2

R59211

2

R59221 2

R59231 2

R59241

2

R59251

2

051-9585

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59 OF 132

55 OF 105

7

OUTIN

IN IN

IN

WP*

SI

HOLD*VSS

SCK

CE*

VDD

SO

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NOTE: If HOLD* is asserted

ROM will ignore SPI cycles.

10V

0.1UF

CERM

20%

402402MF-LF1/16W5%3.3K

46 47 46 47

46 47 46 47

6 19 47

CRITICAL

OMIT

64MBIT

SST25VF064C

SOIC

SYNC_DATE=06/08/2010SYNC_MASTER=K91_BEN

SPI ROM

SPI_MLB_MISOSPI_WP_L

SPI_MLB_MOSI

SPIROM_USE_MLB

SPI_MLB_CS_L

SPI_MLB_CLK

=PP3V3_SUS_ROM

C6100 1

2

R61011

2 U6100

1

7

6 5

2

84

3

051-9585

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61 OF 132

56 OF 105

7

IN

IN

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

BI

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

OUT

IN

OUT

OUT

OUT

BP

NC

SHDN*

IN OUT

GND

/SPDIF_OUT2

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REFVD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC

FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+

MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI

SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+

LINEOUT_L2-

LINEOUT_R2+

IN

NC

OUT

IN

OUT

OUT

IN

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AUDIO CODECAPPLE P/N 353S3199

APPLE P/N 353S2234

4.5V POWER SUPPLY FOR CODEC

DAC1 FSOUTPUT= 1.34VRMS

DAC2/3 FSOUTPUTSE= 1.34VRMS

Control for spk amps.

NOTES ON CODEC usage

DAC2/3 FSOUTPUTDIFF= 2.67VRMS

Hpamp of Codec enabled

Feeding into Woofer amp LO1_R only

VCOM - filter connection for internal quiescent voltage

Low ESL cap

Replacing 2 0402s with one 0306

VL_IF - supply for GPIO, S/PDIF and DMIC

VL_HD - supply for HDA interface

Feeding into Tweeter amps

SM

CRITICAL

CASE-P3-HF

20V10%

TANT

1UF

16 96

16 96

16 96

16 96

16 96

63

61

61 101

61 101

61 101

63

58

58

63

63

63

63

58

FERR-220-OHM

0402

CRITICAL

0.1UF

402-1X5R16V10%

MF-LF402

1/16W1%2.67K

5%100K

1/16WMF-LF402

39

402MF-LF1/16W5%

402-1X5R

0.1UF10%16V

2012-LLP

10UF

16VTANT-POLY

20%

CRITICAL

CRITICAL

2012-LLP

20%16V

10UF

TANT-POLY

8 57

62

57 63

7

57 63

57 63

62

402-1X5R10V10%1UF

CRITICAL

402X7R-CERM

16V10%

0.1UF

61 101

61 101

61 101

SM

FERR-220-OHM

CRITICAL

0402

1/16W5%

MF-LF

39

402

CRITICAL

UDFNMAX8840-4.5V

1UF

402-1

CRITICAL

10%10VX5R

10%

X5R

1UF

10V

CRITICAL

402-1

CASE-B2-SM

20%16V

10UF

POLY-TANT

CRITICAL

CS4206B

CRITICAL

QFN

201

MF

1/20W

5%

100K

0306X5R

CRITICAL

4.7UF

6.3V20%

7 57 62 63

402MF-LF1/16W1%

2.21K

CRITICAL

1UF

402-1

10%

X5R10V

62

62

0402-1X5R-CERM

20%10UF

10V

10UF

10VX5R-CERM

20%

0402-1

402-LF

CERM

2.2UF

6.3V

20%

CERM

6.3V

402-LF

20%

2.2UF

60 62

60 62

59

402

16V

10%

X5R

0.1UF 10UFCRITICAL

X5R-CERM

20%

0402-1

10V

SYNC_MASTER=J31_AUDIO SYNC_DATE=10/26/2011

AUDIO: CODEC/REGULATOR

=PP3V3_S0_AUDIO

PP4V5_AUDIO_ANALOG

NC_AUD_LO1_LN

AUD_LO2_L_N

AUD_LO2_R_P

AUD_LO2_R_N

GND_AUDIO_CODEC

GND_AUDIO_CODECVOLTAGE=0V


GND_AUDIO_CODECMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.2MM

GND_AUDIO_HPAMPVOLTAGE=0V


GND_AUDIO_HPAMP

GND_AUDIO_HPAMP

GND_AUDIO_HPAMPMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM

PP1V5_S0_AUDIO_DIG

MIN_LINE_WIDTH=0.30MMVOLTAGE=1.5V



VBIAS_DAC

=PP1V5_S0_AUDIO

AUD_GPIO_3

AUD_SENSE_A

HDA_SDOUT

NC_AUD_GPIO_2

NC_AUD_GPIO_1

AUD_DMIC_SDA1

VHP_FILTM

HDA_SDIN0

HDA_SYNC

HDA_BIT_CLK

AUD_SPDIF_OUT_CHIP

AUD_HP_PORT_LMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

MIN_LINE_WIDTH=0.30MM AUD_HP_PORT_RMIN_NECK_WIDTH=0.20MM

AUD_LI_REF

AUD_CODEC_MICBIAS

AUD_MIC_INP_L

AUD_LO1_R_N

NC_AUD_LO1_LP

AUD_LO1_R_P

AUD_LO2_L_P

VHP_FILTP

AUD_SDI_R

PP4V5_AUDIO_ANALOG

=PP5V_S0_AUDIO

MIN_LINE_WIDTH=0.30MM HPAMP_REFMIN_NECK_WIDTH=0.20MM

=PP5V_S0_AUDIO

CS4206_FLYP

=PP3V3_S0_AUDIO 4V5_REG_EN

CS4206_FLYC

CS4206_FLYN

AUD_MIC_INN_L

4V5_REG_INVOLTAGE=5V



4V5_NR

AUD_SPDIF_OUT


PP4V5_AUDIO_ANALOG

VOLTAGE=4.5V

AUD_MIC_INP_R

AUD_SPDIF_INCS4206_VREF_ADCMIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.15MM

AUD_DMIC_CLK

AUD_MIC_INN_R

MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.20MMCS4206_VCOM

AUD_LI_P_R

AUD_LI_P_L

HDA_RST_L

XW6201

1 2

C6224 1

2

L6200

1 2

C6215 1

2

R62101

2

R62131

2

R62111 2

C6218 1

2

C62171

2

C6219 1

2

C6216 1

2

C6202

1 2

XW6200

1 2

L6201

1 2

R62121 2

U6200

4

2

1 6

3

C62011

2

C62031

2

C62251

2

U6201

26

6

7

4

43

42

45

2

12

14

15

38

40

39

22

21

23

34

35

30

31

37

36

33

32

16

17

18

20

1911

8

5

13

47

48

10

49

25

46

24

29

28

9

41

44

3

1

27

R6203

12

C62101

2

R62021 2

C62001

2

C62211

2

C62201

2

C62231

2

C6222 1

2

C6214 1

2

C62131

2

051-9585

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62 OF 132

57 OF 105

5

7 57 62 63

57 58 63

57 58 63

57 58 63

57 59 60

57 59 60

57 59 60

57 59 60

96

8 57

IN

IN

IN

OUT

OUT

OUT

IN

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VIN = 2VRMS, CODEC VIN = 1.14 VRMSFC = 0.36 HZ

CODEC RIN = 20K OHMSNET RIN = 18K OHMS

LINE INPUT VOLTAGE DIVIDER

62

62

62

57

57

57

57 63

7.87K

1/16WMF-LF402

1%

MF-LF

1%1/16W

402

7.87K

21.5K

402MF-LF1/16W

1%

20%10VTANT

SM-HF-PL

22UF

CRITICAL

20%10VTANT

SM-HF-PL

22UF

CRITICAL

20%10VTANT

SM-HF-PL

22UF

CRITICAL

402

1%1/16WMF-LF

21.5K

402

1/16WMF-LF

1%10

AUDIO: LINE INPUT FILTER

SYNC_DATE=10/26/2011SYNC_MASTER=J31_AUDIO

MIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

AUD_LI_L

AUD_LI_R

MIN_NECK_WIDTH=.1MMMIN_LINE_WIDTH=.1MM

GND_AUDIO_CODEC

MIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

AUD_LI_L_DIVMIN_LINE_WIDTH=.1MM

AUD_LI_P_L

MIN_NECK_WIDTH=.1MM

AUD_LI_GND

MIN_NECK_WIDTH=.1MMMIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

AUD_LI_REF

MIN_NECK_WIDTH=.1MMMIN_LINE_WIDTH=.1MMAUD_LI_R_DIV

MIN_NECK_WIDTH=.1MMMIN_LINE_WIDTH=.1MM

AUD_LI_P_R

R63011

2

R63031

2

R63001 2

R63061 2

R63051

2

C6300

12

C6302

12

C6303

12

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OUT

OUT

IN

IN

IN

OUT

ADDR

SDA

SCL

REF

MIC

CLAMPO

CLAMPI

RAMPO

RAMPI

GND2

MIC2

GND

MIC1

VDD

GND1

IN

IN

IN

BI

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U6400 should get VDD from battery. Should be powered all the time.

FROM HEADSET

I2C ADDRESSES: CHS uses SMBus 0 connections

EXTERNAL (HEADSET) MIC INPUT CIRCUITRY

APN: 353S3066 as of JUly 2011

TO MIKEY & FILTER

CHS U6400 WRITE 0111 0110 0x76

CHS U6400 READ 0111 0111 0x77

63

63

62

62

63

10UF6.3V20%

CERM-X5R0402-1

57

SM

TS3A8235YFPWCSP

10UF

0402-1

NOSTUFF

CERM-X5R6.3V20%

62

62

63

63

0402

FERR-220-OHM

CRITICAL

0402-1

6.3V20%10UF

CERM-X5R

10UF

CERM-X5R6.3V20%

0402-1

10%16VX5R402

0.1UF

1.02K

1%

MF-LF1/16W

402402

1%

MF-LF

2.21K

1/16W1%

402MF-LF1/16W

2.21K

NOSTUFF

1/16W

0

5%

402MF-LF

402

5%33PF

50VCERM

MF-LF402

5%

0

1/16W

MF-LF402

5%

0

1/16W

MF-LF402

5%

0

1/16W


AUDIO: DETECT/MIC BIASSYNC_MASTER=J31_AUDIO

CHS_CLAMPO

CHS_CLAMPI

=PP3V42_G3H_AUDIO

AUD_HS_MIC1_RET MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM


AUD_HS_MIC2_RET MIN_NECK_WIDTH=0.2MM



AUD_HS_MIC1_HI


AUD_HS_MIC2_HIMIN_LINE_WIDTH=0.1MM

EXT_MIC_BIAS

EXT_MIC_P

GND_AUDIO_HPAMP

HS_SCL

HPAMP_REF

HS_SDA

CHS_SDA

CHS_SCL

EXT_MIC_REF

CHS_CAP_REF

PP3V42_G3H_CHS MIN_NECK_WIDTH=0.175 MM

VOLTAGE=3.42VMIN_LINE_WIDTH=0.3 MM

C64011

2

XW6400

1 2

U6400

A2

C4

B4

C2

B2

B3

C3

D2B1

C1

D4

D3

D1

A3

A4

A1

C64021

2

L6400

1 2

C64101

2

C64051

2

C64001

2

R6401

1 2

R6402

1 2

R6403

1 2

R6404

1 2

C6416 1

2

R6405

1 2

R6406

1 2

R6407

1 2

051-9585

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64 OF 132

59 OF 105

7

57 60

IN

IN

IN

3

12

D

A

C

A

B

C

345678

D

B

8 7 6 5 4 2 1

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

57 62

57 59

CRITICAL

402

X7R-CERM

16V

10%

0.1UF

5%

1/16W

MF-LF

402

39

57 62

16V

X7R-CERM

402

10%

0.1UF

CRITICAL

1/16W

MF-LF

402

39

5%


AUD_HP_PORT_R

GND_AUDIO_HPAMP

AUD_HP_ZOBEL_L

AUD_HP_PORT_L

AUD_HP_ZOBEL_R

C6510 1

2

R65001

2

C6500 1

2

R65101

2

IN

IN

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT

IN

IN

IN

VDD

EDGE

GND

GAINSD*

OUT+

OUT-IN-

IN+

VDD

EDGE

GND

GAINSD*

OUT+

OUT-IN-

IN+

VDD

EDGE

GND

GAINSD*

OUT+

OUT-IN-

IN+

NC

NC

NC

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TWEETER with HPF FC=737Hz

TWEETER with HPF FC=737Hz

WOOFER with HPF FC=90Hz

PLACE C6631 CLOSE TO VDD PIN

3X MONO SPEAKER AMPLIFIERS (SSM2375)

1ST ORDER FC (L&R) = ~737 HZ

APN: 353S2958 as of July 2011

Gain Pin

Not connected

Connect to GND

3

Gain dB

Connect to VDD

Connect to VDD through 47k

Connect to GND through 47k

12

6

9

0

Rin=80k irrespective of gain



1ST ORDER FC (SUB) = ~90 HZ

GAIN = +3 DB

402

100K

1/16WMF-LF

5%

CRITICAL

0402

FERR-1000-OHM

57 101

57

FERR-1000-OHM

CRITICAL

0402

6 62 101

6 62 101

6 62 101

10%0.1UF

402-1

16VX5R

CRITICAL

20%

CRITICAL

6.3V

47UF

TANT-POLYCASE-A4 402-1

0.1UF

X5R16V10%

CRITICAL

FERR-1000-OHM

CRITICAL

0402

57 101

6 62 101

TANT-POLY

CRITICAL

47UF

6.3V

CASE-A4

20%

CRITICAL

6.3VTANT

20%100UF

CASE-AL1

0402

FERR-1000-OHM

CRITICAL

57 101

6 62 101

6 62 101

FERR-1000-OHM

CRITICAL

0402

57 101

0402

FERR-1000-OHM

CRITICAL

57 101

CRITICAL

FERR-1000-OHM

0402

57 101

10%

X5R

0.1UF

CRITICAL

16V

402-1

WLCSPSSM2375

CRITICAL

SSM2375WLCSP

CRITICAL

CRITICAL

WLCSPSSM2375

402

50V10%

0.0027UF

CERM

CRITICAL

0402

CRITICAL

10%25VX7R

0.022UF

10%25VX7R0402

CRITICAL

0.022UF

10%

0.0027UF

50VCERM402

CRITICAL

10%50V

CRITICAL

0.0027UF

402CERM

0.0027UF

CERM402

CRITICAL

10%50V

402MF-LF

5%100K

1/16W


AUDIO: SPEAKER AMP

PP5V_S0_AUDIO_AMP_R

NO_TEST=TRUE

AUD_SPKRAMP_SUBIN_N

AUD_SPKRAMP_SHUTDOWN_L

SSM2375S_N

SSM2375S_P

SPKRCONN_S_OUT_PMIN_NECK_WIDTH=0.20 MM


SPKRCONN_L_OUT_N



PP5V_S0_AUDIO_AMP_L

SSM2375L_P

SPKRCONN_S_OUT_NMIN_NECK_WIDTH=0.20 MM


AUD_LO2_L_P

AUD_LO2_R_P

NO_TEST=TRUE

AUD_SPKRAMP_RIN_P

AUD_SPKRAMP_LIN_P

NO_TEST=TRUE

AUD_LO2_L_N

AUD_LO2_R_N

AUD_LO1_R_P

AUD_LO1_R_N



SPKRCONN_L_OUT_P

NO_TEST=TRUE

AUD_SPKRAMP_LIN_N

SSM2375L_N

SSM2375R_P

AUD_SPKRAMP_SUBIN_P

NO_TEST=TRUE

NO_TEST=TRUE

AUD_SPKRAMP_RIN_N




SPKRCONN_R_OUT_N

SPKRCONN_R_OUT_P



SSM2375R_N


AUD_GPIO_3

PP5V_S0_AUDIO_AMP_R

R66001

2

L6601

1 2

L6611

1 2

C66111

2

C6622 1

2

C66211

2

L6621

1 2

C6612 1

2

C6632 1

2

L6631

1 2

L6610

1 2

L6620

1 2

L6630

1 2

C66311

2

U6610

B2

A3

C1

A1

B1

B3

C3

A2

C2

U6620

B2

A3

C1

A1

B1

B3

C3

A2

C2

U6630

B2

A3

C1

A1

B1

B3

C3

A2

C2

C6623

1 2

C6633

1 2

C6634

1 2

C6624

1 2

C6614

1 2

C6613

1 2

R66011

2

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8 61

61

101

101

8

101

101

101

61

101

61

8 61

IN

IN

IN

IN

IN

IN

PINS

SHELL

SHIELD

POF

A - VDD

B - GND

C - VOUT

OPERATING VOLTAGE 3.3

AUDIO

SWITCH

LEFT

RIGHT

GROUND

DETECT FOR PLUG TYPE

OUT

OUT

RIGHT

MIC

AUDIO

GND

LEFT

SWITCH

DETECT

B - VCC

POF

SHIELD

SHELL

PINS

C - GND

A - VIN

OPERATING VOLTAGE 3.3

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

OUT

IN

BI

BI

OUT

OUT

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AUDIO JACK 2 LINE IN JACK, SPDIF RX

Place XW on/near Jack pin

AUDIO JACK 1 LO/HP JACK, SPDIF TX

Place XW on/near Jack pin

APN: 514-0671

GND PATCH

APN: 514-0635

APN: 518S0519

APN: 518S0521

MIC CONNECTOR

SPEAKER CONNECTOR

SPEAKER CONNECTOR

6 61 101

6 61 101

6 61 101

6 61 101

MF-LF

5%

402

1/16W

4.7

1UF

10V

402-1X5R

10%

CRITICAL

4026.8V-100PF6.8V-100PF

CRITICAL

402

CRITICAL

4026.8V-100PF

6.8V-100PF

CRITICAL

402

FERR-1000-OHM

0402

CRITICAL

0402

CRITICALFERR-1000-OHM

CRITICAL

6.8V-100PF402

CRITICAL

0402

FERR-1000-OHM

CRITICAL

FERR-1000-OHM

0402

0.1UF

16VX5R402-1

10%

M-RT-SM78171-0004

CRITICAL

78171-0002M-RT-SM

CRITICAL

6 61 101

6 61 101

2.2UF20%

402-LFCERM6.3V

1/16W

0

MF-LF

5%

402

FERR-1000-OHM

CRITICAL

0402

CRITICAL

F-RT-TH5

AUDIO-RCVR-M97

59

CRITICAL

0402

FERR-1000-OHM

59

CRITICAL

F-RT-TH

SPDIF-TXRX-K24

CRITICAL

402

6.8V-100PF

SM

SM

CRITICAL

78171-0003M-RT-SM

6 63 101

6 63

6 63 101

DIGI_MIC

CRITICAL

M-RT-SM78171-0004

CRITICALDIGI_MIC

600-OHM-300MA

0402

600-OHM-300MA

0402

CRITICAL

DIGI_MIC

DIGI_MICCRITICAL

600-OHM-300MA

0402

57

57

ESDALC5-1BM2SOD882

CRITICAL

CRITICAL

SOD882ESDALC5-1BM2

59

59

FERR-120-OHM-2.0A

0402

CRITICAL

FERR-120-OHM-2.0A

0402

CRITICAL

50V5%

CERM

100PF

402

FERR-120-OHM-2.0A

CRITICAL

0402

FERR-120-OHM-2.0A

0402

CRITICAL

SM

SM

CRITICAL

0402-1

600-OHM-300MA

CRITICAL

SOD882

ESDALC5-1BM2

57

58

58

63

57

57 60

57 60

63

63

MF-LF

5%

10K

1/16W

402

100PF5%

402

50VCERM

AUDIO: JACKS



AUD_CONNJ1_RIGHT


AUD_CONNJ1_USGND_DET


AUD_CONNJ1_LEFT

AUD_CONNJ1_USGND


AUD_J1_TIPDET_R

=PP3V3_S0_AUDIOCON_DMIC_PWR

AUD_J1_SLEEVEDET_R

AUD_HP_PORT_L

CON_DMIC_CLK

SPKRCONN_R_OUT_N

SPKRCONN_R_OUT_P

SPKRCONN_S_OUT_N

SPKRCONN_S_OUT_P

SPKRCONN_L_OUT_P

AUD_CONNJ2_RING


AUD_CONNJ2_TIPDETMIN_LINE_WIDTH=0.40MMMIN_NECK_WIDTH=0.20MM

AUD_CONNJ2_SLEEVEMIN_LINE_WIDTH=0.40MMMIN_NECK_WIDTH=0.20MM

AUD_HS_MIC2_UNFILT

AUD_HS_MIC1_RET

AUD_HS_MIC2_HI

BI_MIC_P

=PP3V3_S0_AUDIO

AUD_DMIC_SDA1 CON_DMIC_SDA

AUD_LI_R

AUD_LI_L

BI_MIC_SHIELD

BI_MIC_N

=PP3V3_S0_AUDIO

AUD_J2_OPT_OUT

AUD_DMIC_CLK


AUD_CONNJ2_TIPMIN_LINE_WIDTH=0.40MM


AUD_HS_MIC1_HIAUD_HS_MIC1_UNFILT

AUD_CONNJ1_USMIC


AUD_SPDIF_OUT

AUD_SPDIF_IN

AUD_J2_TIPDET_R

AUD_LI_GND

AUD_HP_PORT_R

GND_CHASSIS_AUDIO_JACKVOLTAGE=0VMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.50 MM

SPKRCONN_L_OUT_N

AUD_CONNJ1_TIPDET



AUD_HS_MIC2_RET

L6754

1 2

L6756

1 2

C67561

2

R67001 2

C67051

2

R67491 2

C67501

2

DZ6701

1

2

DZ6706

1

2

DZ6704

1

2

DZ6754

1

2

L6702

1 2

L6703

1 2

DZ6703

1

2L6705

1 2

L6752

1 2

C67001

2

J6782

5

6

1

2

3

4

J6781

3

4

1

2

C67011

2

R67011 2

J6750

5

7

4

10

11

12

9

1

3

2

6

8

J6700

5

4

10

11

12

13

7

8

9

1

6

3

2

DZ6756

1

2

XW6702

1 2

XW6701

1 2

J6780

4

5

1

2

3

J6783

5

6

1

2

3

4

L6783

1 2

L6784

1 2

L6785

1 2

DZ6757

1

2

DZ6758

1

2

L6704

1 2

L6706

1 2

L6707

1 2

L6708

1 2

XW6700

12

XW6704

12

L6758

1 2

DZ67001

2

051-9585

3.0.0

67 OF 132

62 OF 105

7 57 62 63

7 57 62 63

7 57 62 63

8 62

58

8 62

8 62

IN

OUT

IN

D

G S

OUT

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

CS

HDET

AGND

DGND

ENABLE

AVDD

SDA

BYPASS

DETECT

MICBIAS

INT*

SCL

IN

BI

OUT

IN

IN

IN

IN

D

SG

D

SG

OUT

BI

OUT

D

S

G

D

S

G

IN

D

G S

D

S

G

G

S

DP-CH

N-CH

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



CODEC INPUT SIGNAL PATHS

PORT B LEFT(HEADSET MIC)CODEC OUTPUT SIGNAL PATHS

N/A

PIN COMPLEX

0X0C (12,C)

PORT B DETECT(SPDIF DELEGATE)

0X05 (5)

0X03 (03)

0X0D (13)

PIRQ F

PORT A DETECT (HEADPHONES)

0X09 (Jack Detect A)

0X0C (Jack detect B)

N/A

NA

0X04 (4)

VOLUME

0X08 (8)

CONVERTER

0X06 (6)

SATELLITES

FUNCTION

0X0F (15)

SPDIF OUT

Voltage level shifting from 5V to 3.3V

EXTRACTION NOTIFICATION

APN:376S1017

MIKEY

PORT B RIGHT(BUILT-IN MIC)

N/A

GPIO 3

GPIO 5

GPIO

PULLUPS ON MCP PAGE

SATA4GP/GPIO 16

HP/LINE OUT

PORT C DETECT (LINE-IN)

0X06 (6)HEADSET MIC

APN:376S0975

N/A

Place this next to the connector

HP=80HZ

APN:376S0612

NC

MIKEY ENABLE

FUNCTION

SUB

LINE IN

MIKEY INTERRUPT

FUNCTION

N/A

SPDIF IN

I2C addresses: Mikey uses SMBus 0

PIRQ H

BUILT-IN MIC

0X07 (7)

MIKEY

VREF

INT

0X03 (3)

DET ASSIGNMENT

0X0C (Jack detect C)

N/A

APN:353S2640

MIKEY U6880 READ 0111 0011 0x73

MIKEY U6880 WRITE 0111 0010 0x72

HP=80HZ, LP=8.82KHZ

Place this next to Charleston

CSP MIKEY

PERIPHERAL DETECT

SYSTEM INT AND GPIO LINES

0X02 (2)

0X0D (13,V22,B,LEFT)

N/A

N/A

CONVERTER

0X02 (2)

0X04 (4)

DET ASSIGNMENT

N/A

GPIO_3

PIN COMPLEX

0X09 (9,A)

0X0B (11)

0X10 (16)

0X0A (10)

GPIO_3

MUTE CONTROL

CERM

0.1UF20% 10V

402

MF-LF

5%

402

1/16W

220K

62

39.2K

1/16W1%

402MF-LF

57 63

10K

1/16WMF-LF

1%

402

10V20%402CERM

0.1UF

270K

MF-LF402

1/16W5%

1/16W5%

402MF-LF

47K62

1/16W

402

20.0K1%

MF-LF


57 63

1%

MF402-1

2.4K

1/16W

CRITICAL

402

25V

0.1UF

X5R

10%

0.001UF

CRITICAL

10%CERM402

50V1/16W

402

100K5%

MF-LF

57

57

57

TANT

CRITICAL

20%6.3V

402

2.2UF

FERR-1000-OHM

0402

FERR-1000-OHM

0402

59

59

CRITICAL

50V5%402CERM

27PF

40225V

CRITICALX7R10%0.0082UF

402MF-LF1/16W

100K5%

X5R

CRITICAL

0.1UF

10%25V

402

57

MF-LF

1K

1/16W1%

402

0.01UF

40216V

CERM10%

FERR-1000-OHM

CRITICAL

0402

CRITICAL

603X5R

10UF20%6.3V

TANT

2.2UF

6.3V20%

402

CRITICAL

2.2K

5%1/16WMF-LF402

402

CRITICAL

25V10%

X5R

0.1UF

57

CRITICAL

0.1UF

X5R402

10%25V

100

1%1/16WMF-LF402

MF

1%1/16W

402-1

2.4K

18

20%0.1UF

10V402 CERM

CRITICAL

FERR-1000-OHM

0402

57

WCSP

CRITICAL

CD3282A1

48

48

18

24

MF-LF402

1/16W5%

0

1/16W

0

MF-LF

5%

402

MF-LF

5%1/16W

0

402

5%1/16W

0

MF-LF402

402

1/16W5%100K

MF-LF

10K5%

1/16WMF-LF402

CRITICAL

0.1UF10%25V

402X5R

402MF-LF1/16W5%

100K

NOSTUFF

402

1/16W5%

0

MF-LF

6 62 101

6 62 101

6 62

SM

SOT563

SSM6N37FEAPE

CRITICALCRITICAL

SSM6N37FEAPE

SOT563

59

59

59

5%

402MF-LF1/16W

220K

MF

5%

201

100K

1/20W

20%402

0.1UF10V

CERM

201

5%1/20WMF

100K

MF-LF1/16W

220K

402

5%

NTZD3152PSOT-563-HF NTZD3152P

SOT-563-HF

0.01UF

CERM

10%16V

402

62

150K

1/16W

402MF-LF

5%

220K5%

1/16WMF-LF402

402

MF-LF

1/16W

5%

220K

VESM

SSM3K15AMFVAPE

402

MF-LF

1/16W

5%

200K

SOT563DMC2400UV

AUDIO: JACK TRANSLATORS

SYNC_DATE=10/26/2011SYNC_MASTER=J31_AUDIO

HS_SW_DET

BI_MIC_LO_F


EXT_MIC_BIAS


GND_AUDIO_CODEC

=I2C_MIKEY_SDA

EXT_MIC_PMIN_NECK_WIDTH=0.05MMMIN_LINE_WIDTH=0.1MM

AUD_J1_TIPDET_R

GND_AUDIO_CODEC

AUD_MIC_INN_R

MIC_BIAS_FILTAUD_CODEC_MICBIAS

AUD_IPHS_SWITCH_EN

BI_MIC_SHIELD

=I2C_MIKEY_SCL

=PP3V3_S0_AUDIO

AUD_MIC_INP_R BI_MIC_P

TIPDET_UNFILT


PP3V3_S0_HS_RX

MIN_NECK_WIDTH=0.1MMVOLTAGE=3.3V

HS_RX_BP

AUD_J2_DET_RC

GND_AUDIO_CODEC

AUD_J2_TIPDET_R

AUD_SENSE_A

GND_AUDIO_CODEC

HS_ENABLE

=PP3V3_S0_AUDIO

BI_MIC_N

AUD_J1_DET_RC2

TIPDET_UNFILT

AUD_INJACK_INSERT_L

HS_SCL

HS_SDA

GND_AUDIO_CODEC

AUD_J1_DET_NMOS_GATE

AUD_J1_DET_R_GATE

GND_AUDIO_CODEC

AUD_MIC_INP_L HS_MIC_HI_RC

AUD_MIC_INN_L

GND_AUDIO_CODEC


AUD_J1_DET_NMOS_DRN

AUD_PORTB_DET_L

GND_AUDIO_CODEC

AUD_J1_DET_RC

EXT_MIC_REFMIN_LINE_WIDTH=0.1MMMIN_NECK_WIDTH=0.05MM

BI_MIC_HI_F

HS_INT_L

GND_AUDIO_CODEC

PP4V5_AUDIO_ANALOG

AUD_I2C_INT_L

AUD_J1_SLEEVEDET_R_BUF

VOLTAGE=5V



PP4V5_AUDIO_ANALOG_FLT

AUD_SENSE_A

AUD_PORTA_DET_L

AUD_J1_SLEEVEDET_R_INV

AUD_J1_SLEEVEDET_R_INV

GND_AUDIO_CODEC

AUD_J1_SLEEVEDET_R_BUF

PP4V5_AUDIO_ANALOG_FLT

AUD_J1_SLEEVEDET_R

C68011

2

R68011

2

R68061

2

R681312

C68111

2

R68111

2

R68121 2

R68051

2

Q68023

12

R68511 2

C6850

1 2

C68531

2

R68521

2

C68521

2

L6851

1 2

L6850

1 2

C68851

2

C68841

2

R68881

2

C6883

1 2

R68801

2

C68811

2

L6880

1 2

C6880 1

2

C68821

2

R68901 2

C6886

1 2

C6851

1 2

R68501 2

R68531 2

C68041

2

L6801

1 2

U6880

D2

A2

D1

B2

B1

C2

A3

A1

D3

C1C3

B3

R68821 2

R68831 2

R68841 2

R68851 2

R68871

2

R68861

2

C68871

2

R6840

1 2

R68301 2

XW6851

1 2

Q68016

21

Q68013

54

R68081

2

R68071 2

C68031

2

R68021 2

R68091

2

Q6804

3

5

4

Q6804

6

2

1

C68021

2

R68041

2

R68141

2

R6803

12

Q6800 3

12

R6841

12

Q6803

6

3

2

5

1

4

63 OF 105

051-9585

3.0.0

68 OF 132

57 58 63

57 58 63

7 57 62 63

63

57 58 63

57 58 63

7 57 62 63

63

57 58 63

57 58 63

57 58 63

57 58 63

57 58 63

63

63

57 58 63

63

63

BI

VCC

EXTINT

NCGND

IN

OUT

OUT

NCNC

BI

BI

P3

P4

P5

P6

P7

P8

P1

P2

P9

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

NC

OUT

Y

B

A

NC

SW

FB

BDPG

EN/UVL0

THRMGND

RT

VIN

PAD

BOOST

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6 3



350mA max output

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

<Rb>

<Ra>

GND

1-Wire OverVoltage Protection

SIG

516S0523

TO SMC

GND

518-0375

BIL CONNECTOR

PWR

PWR

PP18V5_DCIN_FUSE

ADAPTOR_SENSE

MagSafe DC Power Jack

connected.

Vout = 1.21V * (1 + Ra / Rb)

353S2730

(Switcher limit)

Vout = 3.414

BATTERY CONNECTOR

send transients onto ADAPTER_SENSE when AC is

The chassis ground will otherwise float and can

1206-2

6AMP-24V

CRITICAL

20%

603CERM

0.01UF

45

78048-0573

SC70-5MAX9940

CRITICAL

10V20%

402CERM

0.1UFPLACEMENT_NOTE=PLACE NEAR U6900 and U6901

45 46

50V10%

402CERM

0.001UF47PF

50V

402CERM

5%47PF

50V5%

402CERM

F-ST-SM

CPB6312-0101F

CRITICAL

25V10%

402X5R

0.1UF

50V10%

402CERM

0.001UF

1/16W5%

402

MF-LF

10045 46 53

6 45 46 48 64

48 64

1/16W5%

402MF-LF

2.0K

SOT-323BAT30CWFILM

CRITICAL

25V10%

402X5R

0.1UF

25V10%

603-1X5R

1UFSC-75

RCLAMP2402B

CRITICAL

1/16W5%

402MF-LF

10K

M-RT-THBAT-K90-K91-K92

CRITICAL

35V10%

0805X5R-CERM

4.7UF

6

SOT665TC7SZ08FEAPE

CRITICAL

1/16W1%

402MF-LF

150K

CRITICAL

DFN

LT3970

5%

1/16WMF-LF

0

402

5%50V

402CERM

47PF

1/16W1%

402MF-LF

549K

X5R-CERM-1

22UF

603

20%6.3V

16V10%

X5R402

0.1UF

D52LC-SM

CRITICAL

33UH-20%-0.44A-0.455OHM

402MF-LF1/16W1%1M

5%

47

1/3WMF0805

DC-In & Battery Connectors

SYNC_MASTER=J31_JACK SYNC_DATE=09/02/2011

=PP3V42_G3H_REG

=SMBUS_BATT_SCL

ADAPTER_SENSE

DIDT=TRUE

P3V42G3H_BOOST

DIDT=TRUE

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmP3V42G3H_SW

SWITCH_NODE=TRUE

VOLTAGE=18.5V

PPVIN_G3H_P3V42G3H


P3V42_BD_R

P3V42_RT

SMC_LID SMC_LID_R

=PP3V42_G3H_BIL

SMC_BIL_BUTTON_L

SYS_ONEWIRE

=SMBUS_BATT_SDA

SYS_DETECT_L

=SMBUS_BATT_SDA

PPVBAT_G3H_CONN

PP18V5_DCIN_FUSE

MIN_NECK_WIDTH=0.20mmMIN_LINE_WIDTH=1mm

VOLTAGE=18.5V

=PP18V5_DCIN_CONN

SMC_BC_ACOK_VCC

SMC_BC_ACOK

=PP3V42_G3H_ONEWIREPROT

P3V42G3H_FB

=SMBUS_BATT_SCL

P18V5_DCIN_CONN_R


=PP18V5_DCIN_CONN

50V

M-RT-SM

CRITICAL

VOLTAGE=18.5V

MF1/3W5%

5.1

0805-1

CRITICAL

PBUS_G3H_R


VOLTAGE=18.5V

=PPBUS_G3H

F6905

1 2

C69051

2

J6900

1

2

3

4

5

U6900

5

2

4

1

C69081

2

C6954 1

2

C6953 1

2

C6952 1

2

J6955

1

10

1112

1314

1516

2

34

56

78

9

C6951 1

2

C6955 1

2

R696112

R69291

2

D6990

1

2

3

C6950 1

2

C6960 1

2

D6950

3

1 2 R69501

2

J6950

10

11

12

13

1

2

3

4

5

6

7

8

9

C6990 1

2

U6901

2

1

3

5

4

R69911

2

U6990

8

7

2

1

4 5

9

10

6

11

3

R6992

1 2

C6995 1

2

R69961

2

C69991

2

C6994 1

2 L6995

1 2

R69951

2

R69901 2

R69051 2

051-9585

3.0.0

69 OF 132

64 OF 105

3

7

6

6

7

6

48 64

6 65

6

7 64

7

48 64

7 64

7 65

OUT

OUT

IN

BI

OUT

AMON

BMON

ACOK

LGATE

PHASE

BOOT

SGATE

AGATE

CSIP

CSIN

DCIN

VNEG

CSOP

CSON

THRM_PAD

PGND

VDDPVDD

BGATE

UGATE

ICOMP

VCOMP

ACIN

SDA

VFRQ

CELL

VHST

SCL

SMB_RST_N

IN

G

D

S

IN

NCNC

GG

S D S D

NC NC

G

D

SYM-VER-2

S

NC

NC

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

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6 3



Reverse-Current Protection

(PPVBAT_G3H_CHGR_R)

(L7030 limit)

200MA MAX OUTPUT

TO SYSTEM

(Switcher limit)

Vout = 5.506V

<Rb>

(CHGR_BGATE)

TO/FROM BATTERY

f = 400 kHz

36V/V

(CHGR_CSO_N)

sparkitecture requirements

(OD)

(AGND)

20V/V

30mA max loadInput impedance of ~40K meets

<Ra>

Vout = 1.25V * (1 + Ra / Rb)

Max Current = 8A

(GND)

(CHGR_CSO_P)

5.5V "G3Hot" Supply

353S2392

(PPVBAT_G3H_CHGR_R)

Inrush Limiter

(CHGR_SGATE)(CHGR_AGATE)

(CHGR_DCIN)

ACIN pin threshold is 3.2V, +/- 50mV

Divider sets ACIN threshold at 13.55V

FROM ADAPTER

1/16W1%

402MF-LF

9.31K

10V10%

402CERM

0.068UF

50V10%

402CERM

470PF

1/16W1%

402MF-LF

3.01K

50V10%

402X7R-CERM

220PF

1/16W5%

402MF-LF

330K

10V

402X5R

1UF10%

10V10%

X5R

1UF

402-1

402

1/16W5%

4.7

1/16W1%

402MF-LF

30.1K

16V10%

402CERM

0.01uF

16V10%

402-1X5R

0.1UFPLACE_NEAR=U7000.22:1mm

SM


1UF

10V10%

402X5R

0.1UF10%25VX5R402

25V10%

402X5R

0.1UF

CERM402

10V10%0.047UF

10V10%

402CERM

0.22UF


LFPAK-HF

CRITICAL

RJK0305DPB

OMIT_TABLE

1/16W5%

402MF-LF

10

5%

402

10

MF-LF1/16W

CRITICAL

25V20%

CASE-D2-SMPOLY-TANT

22UF

25V

CASE-D2-SMPOLY-TANT

22UF

CRITICAL

20%

1/16W5% 402MF-LF2.2

1/16W5% 402MF-LF0

0.22UF

25V20%

603X5R

50

50

48

48

16V10%

402CERM

0.01UF

16V10%

402X5R

1UF

50V10%

402CERM

0.001UF

46 49

50V10%

402X7R

0.001UF

PLACE_NEAR=C7036.1:3mm

NO STUFF

50V10%

402CERM

470PF

180

1/10W5%

603MF-LF

NO STUFF

50V10%

402X7R

0.001UF

TQFN

CRITICAL

1/16W5%

402MF-LF

74

CRITICAL

BAT30CWFILMSOT-323

1/16W1%

402MF-LF

1K

FDA1254F-SM

4.7UH-10.2A

CRITICAL

LFPAK-SM

RJK0332DPB-01

CRITICAL

OMIT_TABLE

25V20%

CASE-D2-SMPOLY-TANT

22UF

CRITICAL

1/16W5%

402MF-LF

20

603-1

25V10%

X5R

1UF

25V10%1UF

X5R603-1


25V10%

603-1X5R

1UF

MF-LF1/16W

402

0

0.1UF

X5R402

10%25V

1%470K

1/16WMF-LF402

1/16W1%

402

332K

MF-LF

62K

1/16W5%

402MF-LF

1/16W5%

402MF-LF

100K

DIRECTFET-MC

CRITICAL

IRF9395TRPBF

1206

8AMP-24V

CRITICAL

1206

8AMP-24V

CRITICAL

1W1%

0612MF

0.005

CRITICAL

1/16W5%

402MF-LF

0

SO-8SI7137DP

CRITICAL

CRITICAL

SIGNAL_MODEL=EMPTY

0.0200.5%

0612MF-LF

1W

LT3470A

CRITICAL

DFN

22PF5%50VCERM201

402CERM10V10%

0.22UF CRITICAL

DP418C-SM

33UH-20%-0.39A-0.435OHM

MF201

1%1/20W

200K

MF-LF1/16W

402

0

5%

NO STUFF402

5%

0

1/16WMF-LF

201MF

1/20W

681K1%

0805

10%35V

X5R-CERM

4.7UF

0603

CRITICAL

10VX5R

10UF20%

0603

CRITICAL

10VX5R

10UF20%

MF-LF

5%

0

1/16W

402

X5R

10%25V

1UF

603-1

PBus Supply & Battery Charger


PPCHGR_DCIN_D

CHGR_PHASE

SWITCH_NODE=TRUEDIDT=TRUE


MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmCHGR_LGATE DIDT=TRUEGATE_NODE=TRUE

PP5V1_CHGR_VDD

VOLTAGE=5.1V


PPCHGR_DCIN

CHGR_CSO_P

=CHGR_ACOK

CHGR_CSI_R_P



PPDCIN_G3H_CHGR

MIN_NECK_WIDTH=0.3 mmMIN_LINE_WIDTH=0.3 mmCHGR_SGATE_DIV

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmCHGR_UGATE GATE_NODE=TRUE DIDT=TRUE

GND_CHGR_AGND

CHGR_VFRQ

CHGR_CELL


VOLTAGE=0V

GND_CHGR_AGND


VOLTAGE=12.6V

PPVBAT_G3H_CONN

CHGR_ICOMP_RC

CHGR_ICOMP

CHGR_VCOMP_R

CHGR_VNEG_R

=PPBUS_G3H

CHGR_CSO_R_P


PPCHGR_DCIN_DMIN_LINE_WIDTH=0.2 mm

VOLTAGE=18.5V

CHGR_BMON

=SMBUS_CHGR_SDA

CHGR_AMON

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmCHGR_PHASE_RC

DIDT=TRUE

CHGR_CSI_R_N

CHGR_VNEG

P5V5G3H_BOOSTDIDT=TRUE

PP5V1_CHGR_VDDP

VOLTAGE=5.5VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPPCHGR_DCIN

=PP3V42_G3H_CHGR

CHGR_RST_L

CHGR_CSI_N

CHGR_BOOT DIDT=TRUE



PPDCIN_G3H_INRUSH


PP5V5_CHGR_VDDP

P5V5G3H_FB


VOLTAGE=12.6V

PPVBAT_G3H_CHGR_REG

CHGR_VCOMP


VOLTAGE=12.6V

PPVBAT_G3H_CHGR_R

CHGR_CSO_R_N


PPCHGR_DCIN_D_R


DIDT=TRUESWITCH_NODE=TRUE


P5V5G3H_SW

CHGR_AGATE=SMBUS_CHGR_SCL

CHGR_ACIN

CHGR_BGATE

CHGR_CSO_N


CHGR_AGATE_DIV

CHGR_CSI_P

CHGR_SGATE


PP5V1_CHGR_VDDPMIN_LINE_WIDTH=0.2 mm

VOLTAGE=5.1V

=PPDCIN_S5_CHGR

SMC_RESET_L

5%

ISL6259

MF-LF

100K

NO STUFF

NO STUFF

R70111

2

C70421

2

C70161

2

R70161

2

C7015 1

2

R70151

2

C7002 1

2

C70001

2

R70011 2

R70101

2

C7057 1

2

C7056 1

2

XW7000

1 2

C7001 1

2

C70211

2

C7022 1

2

C70201

2

C70251

2

Q7035

5

4

1 2 3

R70221 2

R70211 2

C70301

2

C70311

2

R7051 1 2

R7052 1 2

C7005 1

2

C7011 1

2

C70501

2

C7026 1

2

C70371

2

C70391

2

R70391

2

C70451

2

U7000

3

14

1

9

16

15

25

627

28

17

18

2

5

21

22

23

11

10

2613

29

24

7

19

20

4

12

8

R70021

2

D7005

1

2

3

R70121

2

L7030

1

2

3

Q7030

5

4

1 2 3

C70401

2

R70051 2

C70351

2

C70361

2

C7055 1

2

R70001 2

C70851

2

R70851

2

R70861

2

R70811

2

R70801

2

Q7080

8 79 10

6 3

4 15 2

F7041

1 2

F7040

1 2

R7050

2 1

4 3

R70421

2

Q7055

5

4

1

2

3

R7020

1

2

3

4

U7090

2

3

1

5

8 4

9

6

C70951

2

C7094 1

2 L7095

1 2

R70961

2

R70911 2

R70921 2

R70951

2

C7090 1

2

C70981

2

C70991

2

R70931 2

C70861

2

051-9585

3.0.0

70 OF 132

65 OF 105

7

65

6

6

65

99

101

6

65

65

6 64

6

7 64

101

65

101

6

65

65

7 74

99

6

6

101

6

99

99

65

7

FB

EN

PVCCVCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGNDGND

SET0

SET1

VID0

VID1

IN

IN

IN

OUT

IN

Apple Inc.


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DSIZEDRAWING NUMBER

REVISION

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6 3



152S0913

(ENDIAN SWAP)

OCP = 8.5A

376S0944

6A Max Output

INTEL TABLE:

VID1 VID0 Voltage

0 1 0.725V

1 0 0.8V

0 0 0.9V

1 1 0.675V

(VCCSAS0_OCSET)

(VCCSAS0_VO)

OCP = R7141 x 8.5uA / R7140

f = 300 kHz

ISL95870AHUTQFN

CRITICAL

0612

CRITICAL

MF-11W

0.0011%

CRITICAL

1.0UH-7.7A

FDV0630H-SM

4.64K

MF-LF402

1%1/16W

4.64K

MF-LF402

1%1/16W


SM

12 93

1.62K

MF-LF402

1%1/16W

1.62K

MF-LF402

1%1/16W

0.022UF

402

10%16V

CERM-X5R

499K

MF-LF402

1%1/16W

MF-LF402

1%1/16W

82.5K

12 93

12 93

SM


52.3K

MF-LF402

1%1/16W

MF-LF

41.2K

402

1%1/16W

2.2UF10%

603X5R16V

0

MF-LF

5%1/16W

402

74

74

402MF-LF

5%1/16W

2.2 10UF

X5R603

20%10V

CRITICAL

1K

MF-LF402

1%1/16W

SIGNAL_MODEL=EMPTY

1000PF

NP0-C0G402

25V5%SIGNAL_MODEL=EMPTY

MF-LF

0

603

1/10W5%

0.22UF10%10V

402CERM

MF-LF402

1/16W

1K1%

SIGNAL_MODEL=EMPTY

RJK0222DNS

CRITICAL

HWSON

16V

0805

10%

X5R-CERM

CRITICAL

10UF

CRITICAL

10UF10%16V

0805X5R-CERM

1000PF

402

5%25VNP0-C0G


10PF

CERM402

5%50V

10PF

CERM402

5%50V

1UF

X5R25V10%

603-1


System Agent Supply


VCCSAS0_SET_R

CPU_VCCSASENSE

=PPVIN_S0_VCCSAS0

VCCSAS0_RTN

CPU_VCCSA_VID<0>

VCCSAS0_SET1

VCCSAS0_SET0

VCCSAS0_AGNDMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0V

DIDT=TRUE


VCCSAS0_VBST

DIDT=TRUEGATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmVCCSAS0_DRVH

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mmVCCSAS0_DRVL

MIN_NECK_WIDTH=0.2 mmGATE_NODE=TRUE



VCCSAS0_LL

PVCCSA_PGOOD

VCCSAS0_OCSET

=PP5V_S0_VCCSAS0

=PVCCSA_EN

VCCSAS0_RTN_DIV

CPU_VCCSA_VID<1>

VCCSAS0_FSEL

VCCSAS0_VO

VCCSAS0_SREF

CPU_VCCSASENSE_DIV

DIDT=TRUE


VCCSAS0_BOOT_RCMIN_LINE_WIDTH=0.3 mm


VOLTAGE=5V

PP5V_S0_VCCSAS0_VCC


VOLTAGE=1.05V

PPVCCSA_S0_REG_R


=PPVCCSA_S0_REG

VCCSAS0_CS_P

VCCSAS0_CS_N

L7100

1 2

R71541

2

R71521

2

XW7101

1

2

R71531 2

R71511 2

C7103 1

2

R71491

2

R71501 2

XW7100

1 2

R71481

2

R71471

2

C71021

2

R71031

2

R71011

2

C71011

2

R71421

2

C7140

12

R71301

2

C71301

2

R71411

2

Q71002

1

6

7

3 4 5

C7119 1

2

C7120 1

2

C71221

2

C71051

2

C71061

2

C7121 1

2

U7100

1815

10

13

3

1

11

2

14

16

20

4

8

9

7

17

19

6

5

12

R7140

1 2

3 4

051-9585

3.0.0

71 OF 132

66 OF 105

7

6

6

6

7

6 7 49

49 101

49 101

OUT

IN

EN

EN2EN1

DRVL2

SKIPSEL1

SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2

CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

IN

IN

OUT

VSW

PGND

TGR

TG

BG

VIN

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Vout = 3.3V

(P5VP3V3_VREF2) (P5VP3V3_VREF2)

100mA MAX OUTPUTVout = 5V

8.07A MAX OUTPUT

f = 400 Khz f = 400 Khz

11.834A MAX OUTPUT

Vout = 5.0V

25V

603-1X5R

10%1UF

2.2UH-14A

CRITICAL

IHLP2525CZ-SM1603-1X7R50V10%

0.1UF

CRITICAL

10UF20%6.3V

603X5R

50VX7R

0.1UF

603-1

10%

CRITICAL

POLY-TANTCASE-D3L-SM1

6.3V20%

330UF 10UF

X5R805

10V20%

CRITICAL


10%25VX5R603-1

1UF

2.2UF

10V

402X5R-CERM

20%

CRITICAL

10UF

X5R6.3V

603

20%

402MF-LF1/16W

1%249K

74

PLACE_NEAR=L7260.2:3mm

SM

10%

402CERM10V

0.22UF

402MF-LF

23.2K1%

1/16W

10K1%

1/16WMF-LF402

CASE-D2E-SM

CRITICAL

POLY-TANT16V20%

68UF

CASE-D2E-SM

68UF

16V

CRITICAL

POLY-TANT

20%


SM

0.1UF

402-1

16VX5R

10%


SIGNAL_MODEL=EMPTY

SM


SIGNAL_MODEL=EMPTYSM

4700PF10%100VCERM402


SM


SM

SIGNAL_MODEL=EMPTY

CRITICAL

CASE-D3L-SM1

6.3V20%330UF

POLY-TANT

74 NO STUFF

50V10%

402CERM

0.0033UF

NO STUFF

603MF-LF1/10W5%1

603MF-LF

5%10

NO STUFF

1/10W

402X7R50V10%

0.001UF

PLACE_NEAR=C7281.1:3MM

10%50VX7R402

0.001UF

PLACE_NEAR=C7241.1:3MM402

50V10%

X7R

0.001UF

0.001UF10%50VX7R402

TPS51980

QFN

CRITICAL

16V20%

CASE-D2E-SM

68UF

CRITICAL

POLY-TANT

CRITICAL

CASE-D2E-SMPOLY-TANT

16V20%

68UF

74

RJK0214DPAWPAK2

CRITICAL

1/16WMF-LF402

0

5%

1UF10%25VX5R


603-1

74

74

50VX7R402

NO STUFF

10%0.001UF

PIMB104E2R2MS-SM

CRITICAL

2.2UH-14A-7.0M-OHM


SM

SON5X6

CRITICAL

CSD58872Q5D

MF-LF

1

402

5%1/16W

402

12.1K1%

1/16WMF-LF

10.5K

402MF-LF1/16W1%

1/16W1%

MF-LF402

6.04K

1/16W1%

8.25K

MF-LF402

12.1K

1/16WMF-LF402

1%

MF-LF1/16W

10.5K1%

402

1.21K

1%1/16WMF-LF402

MF-LF402

1%5.62K

1/16W

0402

10VCERM

2200PF5%

402

50VCERM

47PF5%

402-1

16V

0.1UF

X5R

10%

402

50VCERM

150PF5%

MF-LF1/16W

05%

402

SKIP_5V3V3:AUDIBLE

402

5%0

1/16WMF-LF

SKIP_5V3V3:INAUDIBLE

MF-LF1/16W

1%

402

41.2K

1/16W1%10.2K

402MF-LF

5V / 3.3V Power Supply


=PP5V_S3_REG

DIDT=TRUEMIN_NECK_WIDTH=0.2 mm

P5VS3_VSWMIN_LINE_WIDTH=0.6 mm

=PPVIN_S5_P5VP3V3

P5VS3_CSP1

P5VS3_CSP1_R

P5VS3_CSN1

GND_5V3V3_AGND


MIN_NECK_WIDTH=0.2 MMVOLTAGE=0V

P5VS3_VFB1

P5VP3V3_VREF2

=P5VS3_EN

=PP5V_S3_REG

P3V3S5_DRVHMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm

DIDT=TRUE GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mmGATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mmDIDT=TRUE

P3V3S5_DRVL

P3V3S5_RF

P3V3S5_CSN2

SWITCH_NODE=TRUEP3V3S5_LL

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmDIDT=TRUE


P3V3S5_VBSTDIDT=TRUE

=P5VS5_EN

P5VS3_COMP1_R

P5VP3V3_VREG3

=PP5V_S5_LDO

P5VP3V3_SKIPSEL


DIDT=TRUEP5VS3_VBST

GATE_NODE=TRUE

P5VS3_TGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

P5VS3_PGOOD

MIN_LINE_WIDTH=0.6 mmP5VS3_LL


SWITCH_NODE=TRUE

DIDT=TRUEP5VS3_DRVH


GATE_NODE=TRUE



P5VS3_SNUBR

P3V3S5_COMP2

P3V3S5_COMP2_R

P3V3S5_CSP2

P3V3S5_CSP2_R

P3V3S5_VFB2

P3V3S5_PGOOD


P3V3S5_SNUBRMIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P3V3S5_VFB2_R

=P3V3S5_EN


P3V3S5_TG


=PP3V3_S5_REG

MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE DIDT=TRUEMIN_NECK_WIDTH=0.2 mm

P5VS3_DRVL

P5VS3_COMP1

P5VS3_VFB1_R

C7200 1

2

L7260

2

1

C7264 1

2

C72901

2

C72241

2

C7252 1

2

C7250 1

2

C72811

2

C72031

2

C72051

2

R72061

2

XW7261

1

2

C7201 1

2

R72601

2

R72611

2

C7280 1

2

C7240 1

2

XW7260

1

2

C7218

1 2

XW7220

1

2

XW7221

1

2

C72361

2

XW7262

1

2

XW7222

1

2

C72921

2

C7299 1

2

R72991

2

R72981

2

C7272 1

2

C72831

2

C72701

2

C72711

2

U7201

10 15

8 17

7 18

1 24

30 27

12

4 21

28

11

14

5 20

3

6

19

32 25

33

2

31 26

9 16

23

13

22

29

C7242 1

2

C7282 1

2

Q7260

2

1

6

7

3 4 5

R72631 2

C72411

2

C72981

2

L7220

1

2

XW7200

1

2

Q7220

5

9

3

4

1

6

7

8

R72441

2

R72361

2

R72371

2

R72471 2

R72561

2

R72381

2

R72391

2

R72461 2

R72161

2

C7238 1

2

C72391

2

C7288

1 2

C7237 1

2

R72001

2

R72011

2

R72201

2

R72211

2

72 OF 132

3.0.0

051-9585

67 OF 105

7 67

7

6

6

7 67

6

6

6

6

7

6

6

6

6

6

6

6 6

6

7

6

IN

V5IN

REFIN

S5

VREF

S3

MODE

TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRMVTTGNDPGND PADGND

OUT

IN

D

GS

IN

G

D

S

G

D

S

IN

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(VTT Enable)

(VDDQ/VTTREF Enable)

(DDRREG_DRVL)

(DDRREG_LL)

10mA max load

(Q7335 limit)

f = 400 kHz

Vout = 1.5V

(DDRREG_VDDQSNS)

15A max output

(DDRREG_DRVH)

C7360, C7361 close to memory

10UF

X5R

20%

CRITICAL

10V

603


CRITICAL

20%16V

68UF

CRITICAL

16VPOLY-TANT

20%68UF

CASE-D2E-SM

1UF

X5R25V10%


603-1

603-1

50VX7R

0.1UF

10%

50V10%

402X7R


0.001UF

FDU1040D-SM

1.0UH-21A

CRITICAL

6.3V

603

10UF

CRITICAL

X5R

20%

X7R402

10%50V

0.001UF

SM


74 QFN

TPS51916

CRITICAL 92

SM



SMCERM

0.22UF10%

402

10V

X5R6.3V20%

CRITICAL

603

10UF

PLACE_NEAR=J3100.202:3mm

8 26

10%0.1UF

16VX5R402

603X5R

20%

CRITICAL

10UF

6.3V

PLACE_NEAR=J3100.202:1mm

1/16WMF-LF402

1%200K

20.0K1%1/16WMF-LF402

MF-LF1/16W

402

1%100K 0.01UF

CERM402

16V10%

10VX5R

20%

603

CRITICAL

10UF

10%25VX5R

1UF

603-1

MF-LF1/16W

402

1%150K

NOSTUFF

SSM3K15FV

SOD-VESM-HF

NOSTUFF

6 31

CRITICAL

HVSON-3333

RJK0225DNS

OMIT_TABLE

CRITICAL

HVSON-333

RJK0226DNS

OMIT_TABLE

19 23

MF

0

MEM_VDD_SEL:GPIO15

201

1/20W5%

66.5K

402

1%1/16WMF-LF

CRITICAL

CASE-B2-SM1

330UF20%2.0VPOLY-TANT

CRITICAL

CASE-B2-SM1

330UF20%

2.0VPOLY-TANT

SYNC_DATE=07/07/2011SYNC_MASTER=J31_JACK

1.5V DDR3 Supply

XDP_FC0_PCH_GPIO15GPIO15_MEM_VDD_SEL_1V5_L


GND_DDRREG_SGND

VOLTAGE=0V

DDRREG_FB

DDRREG_LL

DIDT=TRUE


SWITCH_NODE=TRUE


=PPVTT_S3_DDR_BUF

GATE_NODE=TRUE

DDRREG_DRVL

DIDT=TRUE



DDRREG_MODEDDRREG_VTTSNS

=PPVTT_S0_DDR_LDO

DIDT=TRUE


MIN_LINE_WIDTH=0.6 mmDDRREG_VBST

DDRREG_PGOODDDRREG_1V8_VREF

=PP5V_S3_DDRREG

=DDRREG_EN

=DDRVTT_EN

DDRREG_P1V35_L

=PPVIN_S0_DDRREG_LDO

DDRREG_TRIP

=PPVIN_S3_DDRREG



DIDT=TRUE

DDRREG_DRVH

GATE_NODE=TRUE



DDRREG_VDDQSNS

=PPDDR_S3_REG

C7300 1

2

C7330 1

2

C7331 1

2

C73321

2

C7325

1 2

C73331

2

L7330

1 2

C73451

2

C73461

2

XW7301

1

2

U730014

11

7

19

10

20

8

17

16

13

21

18

12 15

9

2

6

3

4

5

1

XW7360

1 2

XW7300

1

2 C7350 1

2

C7360 1

2

C7315 1

2

C73611

2

R73171

2

R73151

2

R73161

2

C73161

2

C7301 1

2

C73341

2

R73191

2

Q7319

3

12

Q7330

5

4

1 2 3

Q7335

5

4

1 2 3

R73511 2

R73181

2

C73401

2

C7341 1

2

051-9585

3.0.0

73 OF 132

68 OF 105

6

6

7

7

7

6

7

6

7

IN

IN

IN

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

CSPA3

DRVPWMA

POKB

POKA

CLK

VRHOT*

THRM

GNDSB

SR

THERMB

THERMA

DRVPWMB

VDIO

EN

ALERT*

AGND

GNDSA

CSPBAVE

IMAXB

IMAXA

TONB

TONA

LXA1

DHA1

BSTA1

CSPA1

DLA1

CSPAAVE

CSNA

FBA

CSPA2

LXA2

BSTA2

DHA2

DLA2

BSTB

DHB

LXB

DLB

PGNDA

PGNDB

FBB

CSPB1

CSPB2

CSNB

VDDB

VCC

VDDA

PAD

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



PLACE HOLDER

Note: value needs scrubbing

PLACE HOLDER

0402

100KOHM

CRITICAL


12 93

MF1/20W

300

5%

201

300

1/20WMF201

5%

5%

1

1/20WMF201

5%

10

1/20WMF201

5%

10

MF201

1/20W

201MF

1/20W5%

10

MF201

1/20W

180K

1%

1%

180K

1/20WMF201

201MF

1/20W

10

5%

5%

10

201MF

1/20W

74

1%137K

1/20WMF201

1%137K

1/20WMF201

1%5.76K

1/20WMF201

1%5.76K

1/20WMF201

1%

MF201

1/20W

200K

1%130

1/20WMF201

MF

54.91%

201

1/20W

NONE

0201

OMIT

NOSTUFF

NONENONE

10%

150PF

X7R-CERM25V

0201

NO STUFF

470PF

X5R-X7R16V

201

10%

201

16VX7R

1000PF10%

1000PF10%16VX7R201

10%1000PF

X7R16V

201

10%1000PF

16V

201X7R

201

16VX7R

1000PF

NO STUFF

10%10%1000PF

X7R16V

201

NO STUFF

201MF1/20W1%301K

201

NO STUFF

25VCERM

100PF5%

201

NO STUFF

25VCERM

5%100PF

201

NO STUFF

25VCERM

5%100PF

201

NO STUFF

25VCERM

5%100PF

201

NO STUFF

25VCERM

100PF5%

5%100PF

CERM25V

NO STUFF

201

5%

CERM25V

201

NO STUFF

100PF

5%50V

43PF

C0G-CERM0402

5%25VCERM

100PF

201

201CERM25V

100PF

5%

NO STUFF

5%

300

1/20WMF201

NO STUFF

50 70 101

201

301K1%1/20WMF

92

92

10 45 46 93

69 70

70

70

70

12 93

12 93

SM

6 70

6 70

6 70

0402

CRITICAL

100KOHM


6 70

6 70

6 70

6 70

6 70

QFN

CRITICAL

MAX15119GTM

6 70

6 70

6 70

6 70

12.7K

1%

1/16W

MF-LF

402

70

70

402

10V

20%

2.2UF

X5R-CERM

X5R-CERM

402

2.2UF

10V

20%


10V

X5R-CERM

2.2UF20%


402

12 93

12 93

70

12 93

70

70

50 70 101

50 70 101

50 70 101

12 93

17.4K

402

MF-LF

1/16W

1%

69 70

70

201MF

1/20W

300

5%


CPU IMVP7 & AXG VCore Regulator

SYNC_MASTER=J31_JACK

CPUIMVP_FBB

CPUIMVP_ISUM1_P

CPUIMVP_ISUM2_P

CPUIMVP_UGATE1CPU_PROCHOT_L

CPUIMVP_VR_ON

CPU_VIDSOUT

CPUIMVP_FBA

CPUIMVP_ISUM3_P

CPUIMVP_TONA

CPUIMVP_PGOOD

CPUIMVP_AXG_PGOOD

CPUIMVP_FBA

CPUIMVP_BOOT1CPUIMVP_ISUM3_P

CPUIMVP_AXG_PWM2

CPUIMVP_PHASE1

CPUIMVP_LGATE1

CPUIMVP_TONB

CPUIMVP_ISNS2_P

CPUIMVP_ISNS3_P

CPU_VCCSENSE_P

CPU_AXG_SENSE_P

CPU_AXG_SENSE_N

=PPVCCIO_S0_CPUIMVP

CPUIMVP_ISUM_R

CPUIMVP_BOOT1G

CPUIMVP_PHASE1G

CPUIMVP_UGATE1G

CPUIMVP_LGATE2

CPUIMVP_PHASE2

CPUIMVP_UGATE2

CPUIMVP_BOOT2

CPUIMVP_ISUMG_AVE_P

CPUIMVP_ISUMG2_P

CPUIMVP_PWM3

CPUIMVP_LGATE1G

CPUIMVP_FBB

CPU_VCCSENSE_N

=PP5V_S0_CPUIMVP

=PPVIN_S0_CPUIMVP

CPUIMVP_ISNS1_P

CPUIMVP_ISNS1_N

CPU_VCCSENSE_R

CPU_AXG_SENSE_R

CPUIMVP_ISUM_N

CPUIMVP_ISUM

CPUIMVP_ISUMG1_P

CPUIMVP_ISUMG_N

CPUIMVP_FBB_R

CPUIMVP_FBA_R

CPUIMVP_IMAXB

CPU_VIDALERT_L

CPU_VIDSCLK



GND_CPUIMVP_SGNDMIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

CPUIMVP_IMAXA


PP5V_S0_CPUIMVP_VCC


VOLTAGE=5V

CPUIMVP_SLEW

CPUIMVP_NTCG

CPUIMVP_NTC

R7469

1

2

R7467

1

2

XW7400

12

U7400

5

20

22

25

34

14

23

43

10

42

44

45

41

9

11

8

27

32

16

28

31

18

37

13

47

3

6

2 7

35

36

26

33

15

30

17

24

12

38

39

40

49

48

1

46

29

19

21

4

R7412

1 2

C7401 1

2

C74021

2

C74031

2

R7422

1 2

R74061 2

R74071 2

R74081 2

R74101 2

R74131 2

R74231 2

R74011 2

R74021 2

R74031 2

R74401 2

R74411 2

R74611

2

R74631

2

R74681

2

R74661

2

R74651

2

R74801

2

R74791

2

R74641

2

C7408

1 2

C7409

1 2

C7441 1

2

C74401

2

C7422 1

2

C74121

2

C74431

2

C74421

2

R74601

2

C74181

2

C74191

2

C74141

2

C74151

2

C74161

2 C74231

2

C74171

2

C74501

2

C7452

1 2

C7462

1 2

R74091 2

R74621

2

051-9585

3.0.0

74 OF 132

69 OF 105

69

69

69

7

69

7 70

7 70

IN

IN

IN

IN

IN

SKIP*

PWN

THRMDL

LX

VDD

BST

DH

PADGND

OUT

OUT

OUT

OUTOUT OUTOUT

OUTOUT

OUT

OUTOUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUTOUT

OUT

OUT

S

D

G

S

D

G

S

D

G

S

D

G

D

S

G

D

S

G

D

SG

D

S

G D

S

G

S

G

D

SKIP*

PWN

THRMDL

LX

VDD

BST

DH

PADGND

IN

IN

IN

IN

IN

IN

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



376S1011

PHASE 3

376S1010

376S1011

AXG PHASE 2

152S1019

THESE TWO CAPS ARE FOR EMC

152S1019







376S1011

PHASE 2376S1010

376S1010

376S1011

376S1014

AXG PHASE 1

PHASE 1

152S1019

376S1010

152S1019

152S1019

376S1011


Additonal Input Bulk Caps

69

1/16W

MF-LF

402

10K5%

10%10UF

0805

CRITICALNOSTUFF

X5R-CERM

16V

10UF

0805X5R-CERM

10%16V

CRITICALNOSTUFF

CRITICAL

POLY-TANT

20%

16V

68UF

CASE-D2E-SM

68UF

POLY-TANT

20%

16V

CASE-D2E-SM

CRITICAL

CASE-D2E-SM

68UF20%

16V

POLY-TANT

CRITICAL

6 69

6 69

6 69

6 69

402X7R50V10%

0.001UF


0.001UF

402

50V10%

X7R

1/16W

402

05%

MF-LF

0.22UF

402

10V10%

CERM

10%

CERM

NOSTUFF

50V

0.001UF

402

5%

MF-LF603

1/10W

2.2

NOSTUFF

CASE-D2E-SM

POLY-TANT

16V

20%

68UF

CRITICAL

MAX17491TQFN

CRITICAL

0.000751%

1W

MF

CRITICAL

0612

CRITICAL

68UF

POLY-TANT

16V

20%

CASE-D2E-SM

16V

0805

10%

X5R-CERM

10UF

CRITICALNOSTUFF

0805

10%

CRITICAL

10UF

16VX5R-CERM X5R

16V10%

1UF

402


1UF

X5R402

10%16V


0.001UF10%50V

X7R402


50V

0.001UF

X7R402

10%

16V

CRITICAL

68UF20%

POLY-TANT

CASE-D2E-SM

16V

20%

68UF

CASE-D2E-SM

POLY-TANT

CRITICAL

POLY-TANT

CASE-D2E-SM

20%

CRITICAL

16V

68UF

X7R50V10%

402

0.001UF


10%50VX7R

0.001UF

402

10%1UF

16VX5R

402

0.36UH-20%-40A-0.00075OHM

CRITICAL

PIMA104E-SM PIMA104E-SM

CRITICAL

0.36UH-20%-40A-0.00075OHM

PIMA104E-SM

CRITICAL

0.36UH-20%-40A-0.00075OHM

PIMA104E-SM

CRITICAL

0.36UH-20%-40A-0.00075OHM

PIMA104E-SM

0.36UH-20%-40A-0.00075OHM

CRITICAL

69

69

69

50 69 101 50 69 101 50 101 50 69 101

50 101 50 69 101

50 101

50 101 50 70 101

69

69

50 70 101

69

69 70

1%1/16WMF-LF

200

402

1%1/16WMF-LF402

200

0402

NP0-C0G

25V5%

1000PF

402

NOSTUFF

330PF

CERM50V10%

69 70

69 70

603

2.25%1/10W

NOSTUFF

MF-LF

0.001UF

402

10%

CERM50V

NOSTUFF

69 70 69 70

0.22UF10%

CERM10V

402

69 70

50 101


SIGNAL_MODEL=EMPTY

1/20WMF

201

46.41%

10.21%

MF201

1/20WSIGNAL_MODEL=EMPTY

PLACE_NEAR=C7581.1:1mm PLACE_NEAR=C7582.1:1mm

1%10.2

1/20WMF201

SIGNAL_MODEL=EMPTY

1%

MF

10.2 SIGNAL_MODEL=EMPTY


1/20W

201

50V

402

NOSTUFF

10%0.001UF

CERM


1%1/20WMF201

10.2SIGNAL_MODEL=EMPTY

1%1/20WMF201


SIGNAL_MODEL=EMPTY

10.2

46.4

MF201

1%SIGNAL_MODEL=EMPTY


1/20W


MF

46.41%

201

1/20WSIGNAL_MODEL=EMPTY


1%

201MF

1/20W

46.4SIGNAL_MODEL=EMPTY

1/20W1%

201MF

46.4


SIGNAL_MODEL=EMPTY


X7R-CERM

10%10V

0201

2200PF10%2200PF

X7R-CERM10V


0201


10%2200PF

X7R-CERM10V

0201


10%10V

0201X7R-CERM

2200PF

5%

10K

402

MF-LF

1/16W

603

1/10W

2.2

NOSTUFF

MF-LF

5%


10%2200PF

X7R-CERM10V

0201

MF

1%

0612

CRITICAL

1W

0.00075

CRITICAL

IRF6802SDTRPBFDIRECTFET-SA


CRITICAL

CRITICAL

DIRECTFET-SA

IRF6802SDTRPBF CRITICAL

DIRECTFET-SA

IRF6802SDTRPBF

1%200

1/20WMF

NOSTUFF

SIGNAL_MODEL=EMPTY

201

1%300

1/20WMF

201

SIGNAL_MODEL=EMPTY

201

1/20WMF

1%300

SIGNAL_MODEL=EMPTY

CRITICAL

DIRECTFET_S3C649135PBF

CRITICAL


DIRECTFET_S3C

CRITICAL

649135PBF

CRITICAL

DIRECTFET_S3C649135PBF CRITICAL


CRITICAL

S1649136PBF

402MF-LF1/16W

3.35%

402MF-LF1/16W

3.35%

CERM402

10V10%

0.22UF

CRITICAL

TQFN

MAX17491

68UF

CASE-D2E-SM

CRITICAL

POLY-TANT

20%

16V

6 69

68UF

16V

POLY-TANT

20%

CASE-D2E-SM

CRITICAL

10UF

CRITICAL

10%16V

0805X5R-CERM

10%

X5R

402

16V

1UF

6 69

6 69

6 69

6 69

402MF-LF

5%

1/16W

00.22UF

10V

402CERM

10%

6 69

0.001UF

CERM402

50V10%

NOSTUFF

NOSTUFF

1/10W

MF-LF603

5%

2.2

CASE-D2E-SM

CRITICAL

68UF

POLY-TANT

16V

20%

1W

0.000751%

CRITICAL

0612

MF

6 69

POLY-TANT

20%

16V

68UF

CASE-D2E-SM

CRITICAL CRITICAL

10%

10UF

0805

16VX5R-CERM

0805

CRITICAL

10UF

16VX5R-CERM

10%

NOSTUFF

10%16VX5R402

1UF


10%16V

10UF

X5R-CERM

CRITICAL

0805

0612

1%

1W

MF

0.00075

CRITICAL

X5R

10%

402

1UF


16V

402

0.001UF10%

X7R50V


X7R

0.001UF

402

50V10%

0.22UF

402

10V

CERM

10%

402

10%50VCERM

NOSTUFF

0.001UF

MF-LF

5%

603

1/10W

2.2

NOSTUFF

6 69

68UF20%

16V

POLY-TANT

CASE-D2E-SM

CRITICAL

POLY-TANT

68UF20%

16V

CASE-D2E-SM

CRITICAL

MF-LF402

0

1/16W

5%

0

402

MF-LF

5%

1/16W

0.000751%

1W

MF

0612

CRITICAL

10%

10UF

CRITICAL

0805X5R-CERM

16V

69

10UF

X5R-CERM

16V

CRITICAL

0805

10%16V10%

X5R402


1UF

50V

X7R

10%

402

0.001UF


0.001UF10%

X7R

50V

402

68UF

POLY-TANT

16V

20%

CRITICAL

CASE-D2E-SM CASE-D2E-SM

16V

20%

POLY-TANT

68UF

CRITICAL


CPU IMVP7 & AXG VCore Output

CPUIMVP_ISUM3_P


DIDT=TRUE

CPUIMVP_PH3_SNUBCPUIMVP_ISUM_N

VOLTAGE=1.05V

PPVCORE_S0_AXG1_L



PPVCORE_S0_AXG2_L

VOLTAGE=1.05V

CPUIMVP_ISNS2G_P

=PPVCORE_S0_CPU_REG

CPUIMVP_ISUM2_P

CPUIMVP_ISNS2_P

=PPVCORE_S0_CPU_REG

CPUIMVP_UGATE2DIDT=TRUEGATE_NODE=TRUEMIN_NECK_WIDTH=0.2 MM


CPUIMVP_AXG1_SNUB

DIDT=TRUE


CPUIMVP_UGATE2GMIN_LINE_WIDTH=0.5 MM


DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUEGATE_NODE=TRUEMIN_NECK_WIDTH=0.2 MM


MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.25 MMDIDT=TRUE

CPUIMVP_PH2_SNUB


DIDT=TRUE


CPUIMVP_BOOT2_RC

CPUIMVP_ISNS1G_N

CPUIMVP_ISUMG_N

CPUIMVP_ISNS1G_P

CPUIMVP_ISUM_N


DIDT=TRUE

CPUIMVP_BOOT2

PPVCORE_S0_CPU_PH1


VOLTAGE=1.25V

CPUIMVP_ISUMG1_P

CPUIMVP_ISNS3_P

CPUIMVP_AXG2_SNUB

DIDT=TRUEMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.5 MM

GATE_NODE=TRUE



DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE

CPUIMVP_UGATE1GMIN_LINE_WIDTH=0.5 MM DIDT=TRUE

GATE_NODE=TRUEDIDT=TRUE

CPUIMVP_UGATE1



CPUIMVP_BOOT1

CPUIMVP_ISUMG_N

PPVCORE_S0_CPU_PH2


VOLTAGE=1.25V

=PPVCORE_S0_AXG_REG

CPUIMVP_SKIP2G

CPUIMVP_AXG_PWM2

CPUIMVP_ISUMG_AVE_P

CPUIMVP_ISUMG_AVE_R_P

CPUIMVP_ISNS1G_P

CPUIMVP_BOOT1G


=PPVCORE_S0_CPU_REG

=PPVCORE_S0_AXG_REG

CPUIMVP_ISNS2G_N

CPUIMVP_ISUMG_N

CPUIMVP_ISUMG2_P

PPVCORE_S0_CPU_PH3


VOLTAGE=1.25V


CPUIMVP_ISNS1_P

CPUIMVP_ISNS3_N

CPUIMVP_ISNS1_N

CPUIMVP_PWM3

CPUIMVP_ISNS2_N

=PP5V_S0_CPUIMVP

=PP5V_S0_CPUIMVP

DIDT=TRUE



CPUIMVP_BOOT1G_R

CPUIMVP_SKIP3

CPUIMVP_PH1_SNUB


DIDT=TRUE


CPUIMVP_BOOT1_RC


VOLTAGE=1.25V


SWITCH_NODE=TRUE


PPVCORE_S0_CPU_PH1_L

SWITCH_NODE=TRUE

CPUIMVP_PHASE1DIDT=TRUE


MIN_LINE_WIDTH=0.5 MM DIDT=TRUE

GATE_NODE=TRUEMIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE2

SWITCH_NODE=TRUE


VOLTAGE=1.25V



DIDT=TRUE

CPUIMVP_PHASE2

MIN_LINE_WIDTH=1.5 MMSWITCH_NODE=TRUE

VOLTAGE=1.25V

SWITCH_NODE=TRUE




CPUIMVP_LGATE1G





SWITCH_NODE=TRUE

CPUIMVP_VSWG1

SWITCH_NODE=TRUEDIDT=TRUEMIN_LINE_WIDTH=1.5 MM


CPUIMVP_PHASE1G

CPUIMVP_LGATE2GDIDT=TRUE


GATE_NODE=TRUE


SWITCH_NODE=TRUE

CPUIMVP_VSWG2


SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE2GDIDT=TRUEMIN_LINE_WIDTH=1.5 MM

=PPVIN_S0_CPUIMVP


CPUIMVP_UGATE3





CPUIMVP_LGATE3


CPUIMVP_PHASE3DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

CPUIMVP_ISUM1_P

CPUIMVP_ISUM_N

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM DIDT=TRUE

CPUIMVP_LGATE1

GATE_NODE=TRUE

=PPVIN_S0_CPUAXG

CPUIMVP_BOOT2G


DIDT=TRUE

CPUIMVP_BOOT2G_RC

DIDT=TRUE


DIDT=TRUEMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT3


CPUIMVP_BOOT3_RC

DIDT=TRUE


R75401

2

R7556

1 2

R75471

2

U7542

1

8

4

3

7

2

6

9

5

C75401

2

C75301

2

C75521

2

R75521

2

C7551 1

2

U7541

1

8

4

3

7

2

6

9

5

C75531

2

C75541

2

C75551

2

C75411

2

R75111

2

C75111

2

C75121

2

R75121

2

C75131

2

R7510

1 2

3 4

C75141

2

C75151

2

C75161

2

C75171

2

C75561

2

R7550

1 2

3 4

C75571

2

C75581

2

C75591

2

C75311

2

C75321

2

R75321

2

C75331

2

C75341

2

R75661

2

R7560

1 2

3 4

C75351

2

C75361

2

C75371

2

C75381

2

C75391

2

C75601

2

C75611

2

C75621

2

C75631

2

C75701

2

C75711

2

C75721

2

C75181

2

C75191

2

R75211

2

C75211

2

C75221

2

R75221

2

C75231

2

R7520

1 2

3 4

C75241

2

C75251

2

C75261

2

C75271

2

C75641

2

C75651

2

C75661

2

C75731

2

C75741

2

C75751

2

C75281

2

C75291

2

L7510

1 2

L7520

1 2

L7530

1 2

L7550

1 2

L7560

1 2

R75631

2

R75641

2

C7568 1

2

C75691

2

R75681

2

C75851

2

R75131

2

R75141

2

R75241

2

R75341

2

R75621

2R75541

2

R75231

2

R75331

2

R75611

2R75531

2

C75811

2

C75821

2

C75671

2

C75831

2

C75841

2

R7530

12

34

Q7510

5 6

1

4

Q7510

7 8

2

3

Q7550

5 6

1

4

Q7550

7 8

2

3

R75151

2

R75251

2

R75361

2

Q7515

1 2 8 7

4

3 5 6

Q7525

1 2 8 7

4

3 5 6

Q7535

1 2 8 7

4

3 5 6

Q7551

1 2 8 7

4

3 5 6

Q7561

1 2 8 7

4

3 5 6

Q75301

2

5

64

3

R75311

2

R75351

2

051-9585

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75 OF 132

70 OF 105

6

7 70

7 70

6

6

6

6

6

7 49 70

7 70

7 49 70

7 69 70

7 69 70

6

6

6

6 6

6

6

6

6

6

7 69

6

6

6

7

6

6

6

6

OUT

IN BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC PVCC

GND PGND

EN

FB

G

D

S

OUT

OUT

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REVISION

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6 3



<Ra>

<Rb>

f = 300 kHz

OCP = R7641 x 8.5uA / R7640

Vout = 0.5V * (1 + Ra / Rb)

(CPUVCCIOS0_OCSET)

(CPUVCCIOS0_VO)

CPU VCCIO REGULATOR

20.076A Max Output

Vout = 1.05V

OCP = 27.54A

47PF

CERM402

5%50V

74

74


SM

UTQFN

ISL95870

CRITICAL

10V

603

20%

CRITICAL

X5R

10UF

47PF

CERM402

5%50V

CRITICAL

RJK0208DPAWPAK

CRITICAL

RJK0365DPA-01WPAK

1UF

16VX5R

10%

402

1000PF

NP0-C0G402

5%25V

270UF20%

TANTCASE-B4-SM

CRITICAL

2V

CRITICAL

0.68UH-22A-2.7MOHM

PIMB104T-SM

POLY-TANTCASE-D2E-SM

20%

CRITICAL

68UF

16V

0.047UF

X7R402

10%16V

CASE-D2E-SM

CRITICAL

68UF

POLY-TANT

20%16V

NP0-C0G402

1000PF5%25V


1000PF5%

25V

402NP0-C0G

PLACE_NEAR=R7640.1:1.5mm

CASE-B4-SM

NO STUFFCRITICAL

270UF

TANT

20%2V


1UF10%

X5R25V

603-1

49 101

49 101

5%1/16W

0

MF-LF402

402MF-LF1/16W

5%2.2

5%0

1/10WMF-LF603

2.2UF10%

X5R603

16V

0612

1%0.001

1WMF-1

CRITICAL

402MF-LF1/16W

2.74K1%

402MF-LF1/16W

2.74K1%

402MF-LF1/16W

3.24K1%

402MF-LF1/16W

3.24K1%

3.01K

MF-LF402

1%1/16W

MF-LF402

3.01K1%1/16W

CPU VCCIO (1V0R1V05 S0) POWER SUPPLY


CPUVCCIOS0_CS_N

CPUVCCIOS0_VO

CPUVCCIOS0_CS_P

CPUVCCIOS0_OCSET

CPUVCCIOS0_RTN

CPUVCCIOS0_AGND

VOLTAGE=0V


CPUVCCIOS0_FB

=PP5V_S0_CPUVCCIOS0

CPUVCCIOS0_PGOOD

=PPVIN_S0_CPUVCCIOS0

=PPCPUVCCIO_S0_REG

PPCPUVCCIO_S0_REG_RMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

PP5V_S0_CPUVCCIOS0_VCC



=CPUVCCIOS0_EN

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmCPUVCCIOS0_DRVL


CPUVCCIOS0_LL



CPUVCCIOS0_DRVH

MIN_NECK_WIDTH=0.2 mmGATE_NODE=TRUEDIDT=TRUE


CPUVCCIOS0_VBST

DIDT=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mm

CPUVCCIOS0_BOOT_RCMIN_LINE_WIDTH=0.3 mm


CPUVCCIOS0_FSEL

CPUVCCIOS0_SREF

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

C7604 1

2

C76051

2

C76031

2

R76031

2

C7602 1

2

R76041

2

R76441

2

XW7600

1 2

U7600

123

6

5

1

15

7

16

9

10

14

2

4

11

13

8

C76011

2

Q7635

5

4

1 2 3

Q7630

5

4

1 2 3

C76301

2

C7640

12

C76481

2

L7630

1 2

C7620 1

2

C7621 1

2

C76221

2

C7623 1

2

C7649 1

2

C76241

2

R76011

2R76301

2

R7640

1 2

3 4

R76051

2

R76451

2

R76411

2

R76421

2

051-9585

3.0.0

76 OF 132

71 OF 105

6

6

6

7

7

7

6

6

6

6

6

12 93

12 93

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

OUT

IN

NCNCNC

LX

VDD

VIN

THRM_PAD

PGND

SGND

EN

PG

SYNCH

LX

VFB

NC

IN

VI

SWENFB

GND

IN

VI

SWENFB

GNDApple Inc.


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Vout = 0.8V * (1 + Ra / Rb)

1.8V S0 Regulator

1.5V S0 Regulator

Vout = 1.2V

MAX CURRENT = 0.3A

F = 1MHZ

Vout = 1.5V

F = 1MHZ

Cougar Point-M requires JTAG pull-ups to be powered at 1.05V in Sus.

Pull-ups (3) must be 51 ohms to support XDP (not required in production).

dividers (200/100) to 3.3V Sus, which burns 100mW in all S-states.

1.05V SUS LDO<Ra>

Vout = 1.05V

Max Current = 0.35A

Freq = 1 MHz

Max Current = 4A

Vout = 1.794V

152S1302

<Rb>

70mA is required to support pull-ups. Alternative is strong voltage

MAX CURRENT = 0.3A

1.2V S0 (GMUX) Regulator

CAESAR IV 1.2V INT.VR CMPTS

CRITICAL

1.0UH-7APIMB053T-SM

XDP_PCH

X5R402

6.3V10%2.2UF

XDP_PCH

CRITICAL

TPS720105SON

XDP_PCH

1UF

CERM402

10%6.3V

90.9K

MF-LF

1%1/16W

402

74

74

113K

MF-LF402

1%1/16W

47PF

50V5%

402CERM


1000PF

NP0-C0G402

5%25V

CRITICAL

QFNISL8014A

X5R402

20%6.3V

4.7UF

CRITICAL

10UF

X5R402

20%4V

X5R402

10%16V

0.1UF

0.1UF

X5R402

10%16V

CRITICAL

4.7UH-0.8A

PCAA031B-SM

74

10uF

X5R603

20%6.3V

CRITICAL

TPS62201SOT23-5

10uF

X5R603

20%6.3V

CRITICAL

10UH-0.55A-330MOHMPCAA031B-SM

74

10uF

X5R603

20%6.3V

10uF

X5R603

20%6.3V

CRITICAL

10UH-0.55A-330MOHMPCAA031B-SM

SOT23-5

CRITICAL

TPS62207


1UF

X5R25V

603-1

10%

603

CRITICAL

6.3VX5R-CERM-1

22UF20%

20%22UF

X5R-CERM-16.3V

CRITICAL

603

CRITICAL

6.3VX5R-CERM-1

22UF20%

603


Misc Power Supplies

SYNC_MASTER=J31_JACK

=PP1V2_S3_ENET_PHY

ENET_SR_VFB

=PP3V3_SUS_P1V05SUSLDO =PP1V05_SUS_LDO

=PP3V3_S5_P1V2P1V8

=PP1V2_S0_REG

=P1V2S0_EN


P1V2S0_SWMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm

=P1V8S0_EN

P1V8S0_PGOOD


P1V8S0_SW

DIDT=TRUE

VOLTAGE=1.2V

ENET_SR_LX


SWITCH_NODE=TRUE

=PP3V3_ENET_PHY

=P1V5S0_EN


P1V5S0_SWMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm

=PP3V3_S5_P1V5S0

=PP1V5_S0_REG

=PP3V3_S5_P1V2P1V8

P1V8S0_FB

=PP1V8_S0_REG

L7720

1 2

C77411

2

U7740

4

3

5

6 1

7

C7740 1

2

R77211

2

R77201

2

C77231

2

C7724 1

2

U7720

5 14

15

6

16

13

7

11

129

10

4

17

3

8

1 2

C77371

2

C77351

2

C77381

2

C77361

2

L7730

1 2

C7750 1

2 U7710

3

4

2

5

1

C77711

2

L7770

1

2

C7760 1

2 C77611

2

L7760

1

2

U7760

3

4

2

5

1

C77251

2

C7720 1

2

C77211

2

C7722 1

2

051-9585

3.0.0

77 OF 132

72 OF 105

2

7

36

7 7

7 72

7

6

36 7 24 36

7

7

7 72

6

7

ININ

IN

S

D

G

D

G S

DS

G

DS

G

THRMGND

G

PG

SHDN*

D

VCC

S

ON

PAD

OUT

IN

DS

G

IN

DS

G

IN

DS

G

IN

EN

C_SR

DRAIN

VCC

GNDTHRM

C_DELAY NC

R_BLEED

SOURCE

EN_POL_CTRL

PAD

D

SG

D

SG

D

G S

D

SG

NCNC

D

G SIN

G

D

SYM-VER-2

S

G

D

SYM-VER-2

S

IN

D

SG

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6 3



5V_SUS FET

3.3V S3 FET

MOSFET

CHANNEL

1.8V GPU FET

RDS(ON)

LOADING

CHANNEL

376S0945

3.3V S4 FET

P-TYPE 8V/5V

CHANNEL

N-TYPE

RDS(ON)

SI7108DNMOSFET

6 mOhm @4.5V

SiA427

P-TYPE 8V/5V

5.5 MOHM @4.5V

P-TYPE 20V/12V

SI7615DN

5.0V S0 FET

5.5 mOhm @4.5V

P-TYPE 20V/12V

SI7615DN

26 mOhm @1.8V

CHANNEL

RDS(ON)

P-TYPE 8V/5V

0.11A (EDP)

5.6 A (EDP)

CHANNEL

MOSFET

LOADING

RDS(ON)

SWITCH

26 mOhm @1.8V

LOADING

MOSFET

8 A (EDP)

RDS(ON)

LOADING

3.3V S0 GPU FET

SiA427

2 mA (EDP)

MOSFET

29 mOhm @4.5V

3 A (EDP)

LOADING

U7880 default Turn on delay EN--> on is 200~650us.

1.5V S3/S0 FET

RDS(ON)

load side

26 mOhm @1.8V

input side

353S3256

LOADING 0.7? A (EDP)

CHANNEL

3.3V S4 FET

MOSFET

RDS(ON)

3.3V SUS FET

CHANNEL

LOADING

N-TYPE

5 A (EDP)

LOADING

MOSFET

CHANNEL

SiA427

RDS(ON)

LOADING

RDS(ON)

100? mA (EDP)

P-TYPE 8V/5V

3.3V_SUS FET

26 mOhm @1.8VSiA427

CHANNEL P-TYPE 12V

SiA413

5V SUS FET

1.5V S3/S0 FET

NCP4543

3.3V S3 FET

APN 376S0651

5V_SUS FET inuot filter

1.8V GPU FET

MOSFET

18 mOhm @4.5V

2.4A (EDP)

3.3V S0 FET

3.3V S0 GPU FET

0.01UF

1/16W

=P3V3S0_EN

P3V30S0_SS

=PP5V_S3_P5VS0FET

0.033UF10%

=PP3V3_GPU_P3V3GPUFET

=P5VSUS_EN

=PP1V8_GPU_FET

P1V5CPU_EN

P3V3S3_SS

=PP5V_SUS_FET

=PP3V3_S5_P3V3SUSFET

=P1V8GPU_EN

=PP3V3_SUS_FET

P3V3SUS_SS

=PP5V_S5_P1V5S3RS0FET

P5VSUS_SS

GPUFET_C_DELAY

P3V3S3_S4

GPUFET_C_SR

=PP1V8_GPU_FET

=PP3V3_S4_FET

=P3V3S3_EN

P3V3S3_EN_L

=P3V3S4_EN

P3V3SUS_EN_L

P1V5S3RS0FET_GATE_R

=PP5V_S5_P5VSUSFET PP5V_S5_P5VSUSFET_R

=PP3V3_S0_P1V8GPUFET

P1V5S3RS0FET_GATE

=PP3V3_S0_P1V8GPUFET

=PP3V3_S3_P3V3S3FET

=PP1V8_S0_GPUFET

P5VSUS_EN_L

=P3V3GPU_EN

P3V3GPU_EN_L

=PP3V3_S0GPU_FET

=P5VS0_EN

P5V0S0_EN_L P5V0S0_SS

=PP5V_S0_FET

=PP3V3_S3_FET

=PPVIN_S3_P1V5S3RS0_FET

P3V3S0_EN_L

=PP1V5_S3RS0_FET

=PP3V3_S0_FET

=PP3V3_S0_P3V3S0FET

=P3V3SUS_EN

=PP3V3_S4_P3V3S4FET

P3V3S4_EN_L

P1V5S3RS0_RAMP_DONE

VOLTAGE=5V


PP5V_S5_P5VSUSFET_R


SYNC_MASTER=J31_MARY

Power FETs


SOT563

SSM6N37FEAPE

74

47K5%

MF-LF

402

1/16W

1/16W

402

5%

MF-LF

33K

X5R

402

16V

CRITICAL

PWRPK-1212-8SI7615DN

CERM

16V

10%

402

0.01UF

CRITICAL

PWRPK-1212-8SI7615DN

74


220K5%

MF-LF

402

1/16W

MF-LF

10K

5%

402

1/16W

16V

0.033UF

402

X5R

10%

0.01UF

402

10%

16V

CERM

SOT563

SSM6N37FEAPE


SOT563

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

402

1/16WMF-LF

0

NOSTUFF

5%


402

MF-LF

0

5%

20%

2.2UF

X5R-CERM

10V

402

NO STUFF

5%

25V

1000PF

402

NP0-C0G

NO STUFF

NO STUFF

402

20%

CERM

10V

0.1UF

QFN

NCP4543IMN5RG-A

CRITICAL

402

10%

10V

1UF

X5R

NO STUFF

74 5%

402

MF-LF

3.3K

1/16W

MF-LF

5%

402

220K

CERM

402

10%

16V

SIA413DJSC70-6L

CRITICAL

10%

X5R

0.033UF

74 1/16W

MF-LF

402

5%

12K

1/16W

5%

MF-LF

402

100K

0.01UF

10%

16V

402

CERM

SIA427DJSC70-6L

CRITICAL

0.033UF10%

16V

X5R

402

PLACE_NEAR=U7880.2:2.54mm 20%

402

CERM

10V

0.1UF

92

402

CERM

10%

16V

0.01UF

SC70-6L

CRITICAL

SIA427DJ

16V

402

10%

0.033UF

X5R

402

MF-LF

5%

1/16W

5.1K

5%

402

220K

MF-LF

1/16W

74

92

0

1/16W5%

MF-LF402

0.1UF

CERM

10V

20%

402

SLG5AP020TDFN

CRITICAL

SC70-6L

CRITICAL

SIA427DJ

SC70-6L

CRITICAL

SIA427DJ

SOD-VESM-HF

SSM3K15FV

SI7108DN

CRITICAL

PWRPK-1212-8-HF

74

MF-LF

100K

402

5%

1/16W

402

5%

1/16W

MF-LF

47K

X5R

402

10%

0.033UF

16V

402

CERM

16V

10%

0.01UF

26 92

1/16W

402

51K5%

1/16W

402

5%

MF-LF

1K0.01UF

402

10%

16V

CERM

402

16V

1/16W

MF-LF402

10%

16V

CERM

0.22UF

P3V3GPU_SS

C7871 1

2

C7870

1 2

R7870

1 2

R78721

2

C7810

1 2

C7811 1

2

R7810

1 2

R78121

2

Q7801

5

4

1 2 3

Q78723

12

Q7810

1

3

47

Q7870

1

3

47

U7801

5

7

4

2

8

6

3

9

1

C7801 1

2

R78011 2

R78021

2R7800

1 2

C7809 1

2

Q7800

1

3

47

C7800

1 2

C7880 1

2

C7821 1

2

Q7820

1

3

47

C7820

1 2

R78221

2

R7820

1 2

C7841 1

2

Q7840

1

3

47

C7840

1 2

R78421

2

R7840

1 2

C7802 1

2

U7880

1

17

4

5

9

10

11

1215

16

3

14

18

13

6

7

8

19

2

C7881 1

2

C7882 1

2 C7843 1

2

R7843

1 2

R78031 2

Q78223

54

Q78126

21

Q78023

12

Q78226

21

C7860

1 2

C7861 1

2

R7860

1 2

R78621

2

Q78653

12

Q7860

5

4

1

2

3

C7830

1 2

Q7830

5

4

1

2

3

C7831 1

2

R7830

1 2

R78321

2

Q78123

54

051-9585

3.0.0

78 OF 132

73 OF 105

7

7

7

7

7

73 7

7

7 73

73 7

73 7

73 7

7

7

7

7

7

7

7

7

7

7

73

7

G

D

SIN

IN

IN

G

D

S IN

OUT

G

DS

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

D

G S

IN

OUT

OUT

IN

IN

IN

IN

NC

NC

Q3

Q2

Q4

Q1

OUT

IN

SENSE

CT

VDD

GND

RESET*

MR*

G

D

S

G

D

S

OUT

OUT

OUT

IN OUT

OUT

NC

VDD

MR*

RST*V4MON

V3MON

V2MON

GND THRM_PAD

D

G S

OUT

VCC

A

Y

GND

B

C

OUT

OUTIN

IN

IN

OUT

OUT

NC

NC

NC

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Worst-Case Thresholds:

3.3V/5.0V S4 ENABLE

PM_RSMRST_L goes to U1800.C21

3.3V SUS Detect

PM_SLP_S5_L:100K pull down on PCH page

(SMC_S4_WAKESRC_EN)

3.3V w/Divider: 2.345V

ENET Enable Generation

Min delay timeNo stuff C7931, 12ms

threhold is 3.07V

3.3V/5.0V Sus ENABLE

PP1V5_S0

Q3: 0.640V

Q4: 0.660V

Thresholds:

353S2310

(IPU)

3.3V ENET FET

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up

on open-drain AP_PWR_EN signal.

(AC_EN_L)

(PM_SLP_S3_L)

0

1

0

0

0

0

0

0

0

PM_SLP_S4_L

0

1

1

1

0

1

1

1

0

1

State

Run (S0)

Sleep (S3)

Deep Sleep (S4)

(PM_SLP_S4_L)PM_SLP_S4_L:100K pull down in PCH page

PM_SLP_S3_LPM_SLP_S5_L

1

353S2809

Q2: 0.XXXV

3.3V,5V S3 ENABLECHGR VFRQ GenerationSMC_PM_G2_ENABLE

S0 ENABLE

VFRQ High: Variable Frequency

VFRQ Low: Fix Frequency

S5 Rail Enables & PGOOD

U7930 Sense input

V3MON: 0.572V-0.630V

V4MON: 0.572V-0.630V

V2MON: 2.815V-3.099V

VDD: 2.734V-3.010V

SMC-->PM_DSW_PWRGD

S0 Rail PGOOD (BJT Version)

S0 Rail PGOOD Circuitry

(ISL Version in development)

Deep Sleep (S5)

Battery Off (G3Hot)

(PM_SLP_S3_R_L)

PM_SLP_S3_L:100K pull down in PCH page

CPUVCORE ENABLE SMC_BATLOW_L:100K pull up on SMC page

S5_PWRGD (old name RSMRST_PWRGD)-->SMC

PM_SLP_SUS_L:100K pull down on PCH page

SOT-3632N7002DW-X-G

17 45 46

19

6 17 26 45 74

402

5%10K

MF-LF1/16W

100K

1/16W

402

5%

MF-LF

2N7002DW-X-GSOT-363

18 23 32

32

X5R402

16V

0.033UF10%

CRITICAL

NTR4101PSOT-23-HF

0.01UF

10%16VCERM402

67

68

73

1/16W

402

5%

MF-LF

0


402

10%

NO STUFF

CERM-X5R

0.47UF

6.3V

69

PLACE_NEAR=U7400.7:5mm1/16W

402

0

5%

MF-LF

73

73

49

71

72

72

66

MF-LF

5%

402

1/16W

5.1K


0.47UF

6.3V

402

10%

CERM-X5R

17 26 32 45


6.3V

0.47UF10%

CERM-X5R

402

5%1/16WMF-LF

PLACE_NEAR=U7720.5:6mm402

5.1K5%


402MF-LF1/16W

20K


5%

MF-LF

20K

1/16W

402

1UF

CERM-X5R402


10%6.3V

0.47UF

6.3V

10%

402

CERM-X5R

PLACE_NEAR=U7600.3:6mmPLACE_NEAR=U7100.15:6mm

0.47UF

402

10%

6.3V

CERM-X5R

33K

MF-LF1/16W

402

5%


5%1/16W

100K

MF-LF402

65

SOD-VESM-HF

SSM3K15FV

6 17 26 45 74

88

NO STUFF

MF-LF402

5%0

1/16W

5%1/16WMF-LF402

10K

23 45 74 89 92

100

1/16WMF-LF402

5%

100

MF-LF

5%

402

1/16W

MF-LF

5%

100

402

1/16W

MF-LF

100

402

5%1/16W

72

67

100

5%

402

1/16WMF-LF

S0PGOOD_ISL

5%

402

330

MF-LF1/16W

71

66

150K

1/16W1%

402MF-LF

5%

402

1/16W

1K

MF-LF

1%1/16W

402MF-LF

15.0K

402MF-LF

1%1/16W

7.15K

CRITICAL

ASMCC0179DFN2015H4-8

402MF-LF1/16W5%

1K

1K

5%

MF-LF402

1/16W

73

17 45

TPS3808G33DBVRG4SOT23-6

CRITICAL

NO STUFF

0.001UF

50V20%

CERM402

402

100K5%

MF-LF

1/16W

PLACE_NEAR=U7930.6:2.3mm

402

10V20%

CERM

0.1uF

SOT-3632N7002DW-X-G

SOT-3632N7002DW-X-G

100

MF-LF402

1/16W5%

5%

402MF-LF1/16W

10K

72

0.47UF

CERM-X5R


6.3V

10%

402

17

67

45 46

CERM

NO STUFF

0.0033UF

402

50V10%

100

402

5%

MF-LF


1/16W

67

45

1/16W

MF-LF402

5%

100K


402

CERM

20%10V

S0PGOOD_ISL

0.1uF

TDFN

ISL88042IRTEZ

CRITICAL

S0PGOOD_ISL

1%

402

1/16WMF-LF

S0PGOOD_ISL

6.04K

15.0K1%

1/16W

402

MF-LF

S0PGOOD_ISL

402

1/16W

1%

MF-LF

6.04K

S0PGOOD_ISL

15.0K

402

MF-LF

1/16W

1%

S0PGOOD_ISL


53


3.3K5%1/16WMF-LF402

SOT891

74AUP1G3208

PLACE_NEAR=U7940.1:2.3mm

402

10V20%

CERM

0.1uF

73

73 17

45 46

NO STUFF

5%1/16W

402MF-LF

0

1/16W

402MF-LF

5%

100K

NOSTUFF

0

5% 402PLACE_NEAR=Q7802.2:5mm

1/16W MF-LF

45 46

402MF-LF

20K

1/16W5%

CERM-X5R

402

6.3V

0.47UF10%


42

88

1%

MF-LF

S0PGOOD_ISL

10K

402

1/16W

1%

MF-LF

S0PGOOD_ISL

10K

1/16W

402

74LVC1G32


SOT891

0201

0.1UF10%10V

X5R-CERM


Power Control 1/ENABLE

SYNC_DATE=06/06/2011SYNC_MASTER=J31_MARY

SMC_BATLOW_L

MAKE_BASE=TRUE

PVCCSA_EN

CPUVCCIOS0_ENMAKE_BASE=TRUE

MAKE_BASE=TRUE

PCHVCCIOS0_EN

=PVCCSA_EN

=CPUVCCIOS0_EN

=TBT_S0_EN

=PBUSVSENS_EN

=P3V3S0_EN

PM_SLP_S3_R_LMAKE_BASE=TRUE

PM_SLP_S3_R_L

MAKE_BASE=TRUE

P1V5S0_EN

P1V2S0_ENMAKE_BASE=TRUE

ALL_SYS_PWRGD

PVCCSA_PGOOD

P5VS3_PGOOD

=PP3V3_S0_PWRCTL

P1V5_DIV_VMON

P5V_DIV_VMON

ALL_SYS_PWRGD_R

=PP3V3_S0_VMON

=PP1V05_S0_VMON

P1V8S0_PGOOD

=P5VS0_EN

CHGR_VFRQ

P3V3ENET_SS

P1V8S0_ENMAKE_BASE=TRUE

P3V3S3_EN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PM_SLP_S4_L

MAKE_BASE=TRUE

DDRREG_EN

=TBTAPWRSW_EN

=P1V2S0_EN

=P1V5S0_EN

=P1V8S0_EN

=USB_PWR_EN

=DDRREG_EN

=P3V3S3_EN

PM_SLP_S3_L

AC_EN_L

CPUVCCIOS0_PGOOD

MAKE_BASE=TRUE

S5_PWRGD

=PP3V3_S3_P3V3ENETFET

VMON_Q3_BASE

=PP3V3_S0_VMON

=PP3V3_S5_VMON

VMON_Q2_BASE

S0PGD_C=PP3V3_SUS_CNTRL

Sus_PGOOD_CT

=PP3V3_SUS_CNTRL

=P3V3SUS_EN

=P5VSUS_EN

MAKE_BASE=TRUE

P3V3S5_EN

PM_SLP_S3_L

=PP3V42_G3H_CHGR

=P5VS3_EN

TPAD_VBUS_EN

PM_SLP_S3_ENET

=P3V3S5_EN

SMC_ADAPTER_EN

=PP5V_S0_VMON

=PP1V05_S0_VMON

P1V05_VID_VMON

AP_PWR_EN

=PP3V3_ENET_FET

PM_WLAN_EN_L

MAKE_BASE=TRUE

SMC_PM_G2_EN

=P5VS5_EN

=PP3V42_G3H_PWRCTL

ALL_SYS_PWRGD CPUIMVP_VR_ON

ALL_SYS_PWRGD

=PP1V5_S0_VMON

P3V3S5_PGOOD

VMON_3V3_DIV

=PP1V5_S0_VMON

=PP3V3_S5_PWRCTL

=PP3V3_S5_PWRCTL

PM_SLP_SUS_L

WOL_EN

MAKE_BASE=TRUE

PM_SUS_EN

S0PGD_BJT_GND_R

VMON_Q4_BASE

PM_SLP_S5_L

PM_RSMRST_L

=P3V3S4_EN

P3V3_S4_ENMAKE_BASE=TRUE

MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN

=PP3V3_S5_PWRCTL

Q79206

2

1

R79211

2 R79221 2

Q79256

2

1

C79211

2

Q7922

3

1

2

C7922

12

R7912

1

2

C79121

2

R79741 2

R7911

1

2

C79101

2

C79861

2

R7986

1

2R79852

1

R7981

1

2

C79851

2

C79811

2

C79871

2

R7987

1

2

R7931

12

Q79313

12

R79291

2

R79671

2

R79571

2

R7966

1 2

R7964

1 2

R7965

1 2

R7963

1 2

R79621 2

R79561

2

R79531 2

R79511

2

R79521

2

Q7950

5

7

1

6 4

8

2

3

R79541 2

R79551 2

U7930

4

2

3

15

6

C79311

2

R79331

2

C7930 1

2

Q79203

5

4

Q79253

5

4

R79781 2

R7988

12

C79881

2

C79421

2

R79401 2

R79411

2

C7960 1

2

U7960

4

1

8

9

3

5

6

2 7

R79721

2

R79731

2

R79601

2

R79611

2

Q79213

12

R7913

12

U7940

1

3

6

2

5

4

C7940 1

2

R79171 2

R79431

2

R79191 2

R7982

12

C79821

2

R79711

2

R79701

2

U79702

1

3

6

4

C7970 1

2

051-9585

3.0.0

79 OF 132

74 OF 105

5

74

7 74

7 74

7

7 74

7

7 74

7 74

7 65

7

7 74

7

7

23 45 74 89 92

23 45 74 89 92

7 74

67

7 74

7 74

7 74

49

7 74

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

NC

NC

NCNC

NCNC

NCNC

NCNC

NCNC

NC

NCNC

NC

NCNC

NCNC

NCNC

NC

NC

NCNC

NCNC

NCNC

NC

IN

OUT

IN

IN

PEX_SVDD_3V3

PEX_TX0*

PEX_TX0PEX_RX0

PEX_RX1

PEX_RX6*

PEX_REFCLK*

PEX_WAKE*

PEX_CLKREQ*

PEX_RST*

PEX_REFCLK

PEX_RX15

PEX_RX15*

PEX_RX14*

PEX_RX14

PEX_RX12*

PEX_RX12

PEX_RX11*

PEX_RX11

PEX_RX10*

PEX_RX10

PEX_RX9*

PEX_RX9

PEX_RX8*

PEX_RX8

PEX_RX7

PEX_RX7*

PEX_RX6

PEX_RX5

PEX_RX5*

PEX_RX4*

PEX_RX4

PEX_RX3*

PEX_RX3

PEX_RX2

PEX_RX2*

PEX_RX1*

PEX_TSTCLK_OUT*

PEX_TERMP

PEX_TX15

PEX_TX15*

PEX_TSTCLK_OUT

PEX_TX14*

PEX_TX14

PEX_TX13*

PEX_TX13

PEX_TX12

PEX_TX12*

PEX_TX11

PEX_TX11*

PEX_TX10

PEX_TX10*

PEX_TX9*

PEX_TX8*

PEX_TX9

PEX_TX8

PEX_TX7

PEX_TX6*

PEX_TX6

PEX_TX5*

PEX_TX5

PEX_TX4

PEX_TX3*

PEX_TX3

PEX_TX2

PEX_TX2*

PEX_TX1*

PEX_TX1

PEX_TX4*

PEX_RX0*

PEX_RX13*

PEX_RX13

PEX_TX7*

(1 OF 10)

NC

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




Page Notes


(NONE)

(NONE)


- =PP3V3_GPU_VDD33

Note: Removed GND voids from AC caps for layout (J31).

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

0.22UF

X5R6.3V20% 0201

8 82

75 82

8 93

X5R6.3V20% 0201

0.22UF

20% 6.3V X5R

0.22UF

0201

X5R20%

0.22UF

02016.3V

20% 6.3V X5R

0.22UF

0201

X5R6.3V20%

0.22UF

0201

20% X5R6.3V

0.22UF

0201

X5R6.3V20%

0.22UF

0201

20% 6.3V X5R

0.22UF

0201

X5R6.3V20%

0.22UF

0201

20% X5R6.3V

0.22UF

0201

8 93

6.3V X5R20% 0201

0.22UF

20% 6.3V X5R

0.22UF

0201

X5R6.3V20%

0.22UF

0201

6.3V20% X5R

0.22UF

0201

X5R6.3V20%

0.22UF

0201

0201

0.22UF

X5R6.3V20%

0201

0.22UF

20% X5R6.3V

0201

0.22UF

20% 6.3V X5R

0201

0.22UF

6.3V20% X5R

0201

0.22UF

X5R6.3V20%

0201

0.22UF

20% 6.3V X5R

0201

0.22UF

X5R6.3V20%

0201

0.22UF

20% 6.3V X5R

0201

0.22UF

X5R20% 6.3V

0201

0.22UF

20% 6.3V X5R

0201

0.22UF

20% 6.3V X5R

0201

0.22UF

X5R6.3V20%

0201

0.22UF

20% 6.3V X5R

0201

0.22UF

20% 6.3V X5R

0201

0.22UF

6.3V X5R20%

0201

0.22UF

20% 6.3V X5R

NV-GK107BGA

OMIT_TABLE

MF1/20W

NOSTUFF

200

1%

201

MF201

1%1/20W

2.49K

10K

MF201

1%1/20W

0

MF 2015% 1/20W

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

8 93

16 96

16 96

8 93

8 93

SYNC_DATE=10/25/2011SYNC_MASTER=J31_SREE

KEPLER PCI-E

PEG_D2R_N<2>

PEG_D2R_C_P<1>

PEG_D2R_C_N<0>

PEG_D2R_C_N<1>

PEG_D2R_C_P<2>

PEG_D2R_C_N<2>

PEG_D2R_C_P<3>

PEG_D2R_C_N<3>

PEG_D2R_C_P<4>

PEG_D2R_C_N<4>

PEG_D2R_C_P<5>

PEG_D2R_C_N<5>

PEG_D2R_C_P<6>

PEG_D2R_C_N<6>

PEG_D2R_C_P<7>

PEG_R2D_C_N<7>

PEG_R2D_C_P<7>

PEG_R2D_C_N<6>

PEG_R2D_C_P<6>

PEG_R2D_C_N<5>

PEG_R2D_C_P<5>

PEG_R2D_C_N<4>

PEG_R2D_C_N<3>

PEG_R2D_C_P<3>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

PEG_R2D_C_N<0>

PEG_R2D_P<0>

PEX_TSTCLK_O_P

PEX_TSTCLK_O_N

PEG_R2D_N<0>

PEG_R2D_N<0>

PEG_R2D_P<2>

PEG_D2R_C_N<7>PEG_R2D_P<5>

PEG_R2D_P<6>

PEG_D2R_C_P<4>

PEG_R2D_P<3>

PEG_R2D_N<6>

PEG_R2D_N<4>

PEG_CLK100M_P

GPU_RESET_L GPU_RESET_R_L

PEX_CLKREQ_L_R

PEG_D2R_P<6>

GPU_PEX_TERMP

PP3V3_GPU_PEX_PLL_HVDD

PEG_D2R_P<3>

PEG_CLK100M_N

PEG_D2R_C_N<4>

PEG_D2R_C_P<1>

PEG_D2R_C_N<1>

PEG_D2R_C_N<2>

PEG_D2R_C_P<2>

PEG_D2R_C_P<3>

PEG_D2R_C_N<3>

PEG_D2R_C_P<5>

PEG_D2R_C_N<5>

PEG_D2R_C_P<6>

PEG_D2R_C_N<6>

PEG_D2R_C_P<7>

PEG_R2D_N<1>

PEG_R2D_N<2>

PEG_R2D_P<2>

PEG_R2D_N<3>

PEG_R2D_P<4>

PEG_R2D_N<5>

PEG_R2D_P<5>

PEG_R2D_P<7>

PEG_R2D_N<6>

PEG_R2D_P<1>

PEG_R2D_P<0> PEG_D2R_C_P<0>

PEG_D2R_C_N<0>

PEG_R2D_P<6>

PEG_D2R_N<3>

PEG_D2R_N<4>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_P<2>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_D2R_N<6>

PEG_R2D_N<3>

PEG_D2R_C_N<7>

PEG_D2R_N<1>

PEG_R2D_P<1>

PEG_R2D_C_N<2>

PEG_R2D_C_P<4>

PEG_D2R_P<4>

PEG_R2D_N<7>

=PP3V3_GPU_VDD33

PEX_CLKREQ_L_R

PEG_D2R_C_P<0>

PEG_R2D_C_N<1> PEG_R2D_N<1>

PEG_R2D_C_P<0>

PEG_R2D_N<2>

PEG_R2D_N<7>

PEG_R2D_P<3>

PEG_R2D_P<4>

PEG_R2D_N<4>

PEG_R2D_N<5>

PEG_R2D_P<7>

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_D2R_P<1>

C8020 1 2

C8021 1 2

C8022 1 2

C80231 2

C8024 1 2

C8025 1 2

C8026 1 2

C8027 1 2

C8028 1 2

C8029 1 2

C8030 1 2

C8031 1 2

C80321 2

C8033 1 2

C8034 1 2

C8035 1 2

C8056 1 2

C8057 1 2

C8058 1 2

C80591 2

C8060 1 2

C8061 1 2

C8063 1 2

C80641 2

C8065 1 2

C8066 1 2

C8068 1 2

C8069 1 2

C8070 1 2

C8062 1 2

C8067 1 2

C8055 1 2

U8000

AK12

AL13

AK13

AJ12

AN12

AM12

AN14

AM14

AN23

AM23

AP23

AP24

AN24

AM24

AN26

AM26

AP26

AP27

AN27

AM27

AP14

AP15

AN15

AM15

AN17

AM17

AP17

AP18

AN18

AM18

AN20

AM20

AP20

AP21

AN21

AM21

AG12

AP29

AJ26

AK26

AK14

AJ14

AH14

AG14

AK21

AJ21

AL22

AK22

AK23

AJ23

AH23

AG23

AK24

AJ24

AL25

AK25

AK15

AJ15

AL16

AK16

AK17

AJ17

AH17

AG17

AK18

AJ18

AL19

AK19

AK20

AJ20

AH20

AG20

AJ11

R8002

1 2

R8005

1 2

R80011

2

R8000

1 2

051-9585

3.0.0

80 OF 132

75 OF 105

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 92 93

96

96

6 75 92 93

6 75 92 93

6 75 93

6 75 93 6 75 92 93

6 75 93

6 75 93

6 75 92 93

6 75 93

6 75 93

83

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 92 93

6 75 93

6 75 92 93

6 75 92 93

6 75 92 93

6 75 93

6 75 93

6 75 92 93 6 75 93

6 75 93

6 75 93

6 75 92 93

6 75 93

6 75 93

6 75 92 93

7 81 82 83

75 82

6 75 93

6 75 93

6 75 93

6 75 92 93

6 75 92 93

6 75 93

6 75 93

6 75 92 93

6 75 92 93

NCNCNCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNCNCNC

NCNC

NCNCNC

NCNC

NCNC

NC

NC

NCNCNCNC

NCNC

NCNCNC

XVDD

VDD

VDD

(10 OF 10)

FBVDDQFBVDDQ

(7 OF 10)

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



EDP = 30 A



GPU VCORE DE-COUPLING

NOTE: ATLEAST 2 GND VIAS & 2 POWER VIAS PER CAP


- =PPVCORE_GPU

- =PP1V35_GPU_FBVDDQ

Page Notes

(NONE)

(NONE)

EDP = 6500 MA

GPU FB DE-COUPLING

20%

X5R

0201

1UF

6.3V

20%

X5R

0201

1UF

6.3V

20%

X5R

0201

1UF

6.3V

20%

6.3V

X5R-CERM1

402

4.7UF20%

6.3V

X5R-CERM1

402

4.7UF20%

6.3V

402

4.7UF

X5R-CERM1

20%

6.3V

X5R-CERM1

402

4.7UF20%

6.3V

X5R-CERM1

402

4.7UF20%

6.3V

X5R-CERM1

402

4.7UF

20%

22UF

402

X5R

4V

20%

22UF

402

X5R

4V

20%

22UF

X5R

4V

402

20%

22UF

X5R

4V

402

X5R

0201

6.3V

1UF20% 20%

X5R

1UF

0201

6.3V

20%

X5R

0201

1UF

6.3V

20%

X5R0201

1UF

6.3V

20%

X5R

0201

1UF

6.3V

10%

201

X5R

0.1UF

6.3V

10%

201

X5R

0.1UF

6.3V

10%

201

X5R

0.1UF

6.3V

10%

201

0.1UF

X5R

6.3V

10%

201

6.3V

0.1UF

X5R

10%

1000PF

0201

X7R-CERM

16V

10%

201

X5R

6.3V

0.1UF10%

201

X5R

0.1UF

6.3V

10%

201

X5R

0.1UF

6.3V

10%

201

X5R

0.1UF

6.3V

10%

201

X5R

0.1UF

6.3V

10%

201

X5R

0.1UF

6.3V

10%

1000PF

0201

X7R-CERM

16V

0402-1

10V

X5R-CERM

10UF20%

10%

201

X5R

6.3V

0.1UF10%

201

X5R

6.3V

0.1UF

OMIT_TABLE

BGANV-GK107

OMIT_TABLE

BGANV-GK107

GPUDEC:NORMAL

47UF

X5R-CERM

20%

0805

6.3V

402

4VX5R

22UF

GPUDEC:EXP

CRITICAL

20%

GPUDEC:EXP

402

CRITICAL

4VX5R

22UF20%

CRITICAL

GPUDEC:EXP

402X5R

22UF20%4V

20%22UF

X5R

GPUDEC:EXP

402

4V

CRITICAL

4V

402

CRITICAL

22UF

NOSTUFF

20%

X5R

22UF20%

CRITICAL

NOSTUFF

X5R402

4V

CRITICAL

0603X5R

20%6.3V

22UF

GPUDEC:NORMAL

6.3VX5R

22UF

0603

CRITICAL

GPUDEC:NORMAL

20%

22UF

CRITICAL

X5R4V20%

GPUDEC:EXP

402

20%

NOSTUFF

CRITICAL

4V

402X5R

22UF

CRITICAL

NOSTUFF

22UF

402

4VX5R

20%

CRITICAL

X5R

NOSTUFF

402

4V

22UF20%

GPUDEC:EXP

402

CRITICAL

4VX5R

20%22UF

GPUDEC:EXP

CRITICAL

402

4VX5R

20%22UF

X5R402

GPUDEC:EXP

22UF

CRITICAL

4V20%

0603

CRITICAL

GPUDEC:NORMAL

X5R

20%6.3V

22UF

6.3V20%

0603

GPUDEC:NORMAL

CRITICAL

22UF

X5R0603

CRITICAL

X5R

20%6.3V

22UF

GPUDEC:NORMAL

22UF

X5R6.3V20%

CRITICAL

0603

GPUDEC:NORMAL

20%

10UF

X5R-CERM

10V

0402-1

20%

X5R-CERM

10V

0402-1

10UF20%

X5R-CERM

10V

0402-1

10UF 10UF

X5R-CERM

20%

10V

0402-1

20%

10UF

X5R-CERM

10V

0402-1

20%

10UF

X5R-CERM

10V

0402-1

20%

10UF

X5R-CERM

10V

0402-1

10UF20%

X5R-CERM

10V

0402-1

10UF20%

X5R-CERM

10V

0402-1

20%

10UF

X5R-CERM

10V

0402-1 0402-1

10V

X5R-CERM

10UF20%

0402-1

10V

X5R-CERM

10UF20%

0402-1

10V

X5R-CERM

10UF20%

0402-1

10V

X5R-CERM

10UF20%

0402-1

10V

X5R-CERM

10UF20%

0402-1

10V

X5R-CERM

10UF20% 20%

10UF

X5R-CERM

10V

0402-1

20%

X5R

4V

10UF

402

20%

X5R

4V

10UF

402

20%

X5R

4V

10UF

402

20%

X5R

4V

10UF

402

20%

X5R

0201

1UF

6.3V

KEPLER CORE/FB POWER

SYNC_MASTER=D2_MLB_2P SYNC_DATE=01/18/2012

=PPVCORE_GPU

=PP1V35_GPU_FBVDDQ

=PP1V35_GPU_FBVDDQ =PP1V35_GPU_FBVDDQ

=PPVCORE_GPU =PPVCORE_GPU

C81041

2

C81031

2

C81021

2

C81011

2

C81141

2

C81131

2

C81121

2

C81111

2

C81101

2

C81091

2

C81081

2

C81071

2

C81061

2

C81051

2

C81251

2

C81261

2

C81271

2

C81281

2

C81861

2

C81871

2

C81881

2

C81891

2

C81901

2

C81911

2

C81921

2

C81931

2

C81941

2

C81951

2

C81961

2

C81191

2

C81201

2

C81211

2

C81221

2

C81231

2

C81241

2

C81971

2

C81661

2

C81151

2

C81181

2

U8000

AA12

AB18

AB20

AB22

AC12

AC14

AC16

AC19

AC21

AC23

M12

AA14

M14

M16

M19

M21

M23

N13

N15

N17

N18

N20

AA16

N22

P12

P14

P16

P19

P21

P23

R13

R15

R17

AA19

R18

R20

R22

T12

T14

T16

T19

T21

T23

U13

AA21

U15

U17

U18

U20

U22

V13

V15

V17

V18

V20

AA23

V22

W12

W14

W16

W19

W21

W23

Y13

Y15

Y17

AB13

Y18

Y20

Y22

AB15

AB17

U1

V2

V3

V4

V5

V6

V7

V8

W2

W3

W4

U2

W5

W7

W8

Y1

Y2

Y3

Y4

Y5

Y6

Y7

U3

Y8

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

U4

U5

U6

U7

U8

V1

U8000

AA27

B13

B16

B19

E13

E16

E19

H10

H11

H12

H13

AA30

H14

H15

H16

H18

H19

H20

H21

H22

H23

H24

AB27

H8

H9

L27

M27

N27

P27

R27

T27

T30

T33

AB33

V27

W27

W30

W33

Y27

AC27

AD27

AE27

AF27

AG27

C81611

2

C81621

2

C81631

2

C81641

2

C81651

2

C81821

2

C81831

2

C81981

2

C81991

2

C81451

2

C81511

2

C81501

2

C81491

2

C81481

2

C81471

2

C81461

2

C81301

2

C81311

2

C81321

2

C81331

2

C81671

2

C81681

2

C81691

2

C81701

2

C81711

2

C81721

2

C81731

2

C81741

2

C81751

2

C81761

2

C81771

2

C81781

2

C81791

2

C81801

2

C81811

2

C81841

2

C81851

2

051-9585

3.0.0

81 OF 132

76 OF 105

7 76 83

7 76 79 80

7 76 79 80 7 76 79 80

7 76 83 7 76 83

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

FBA_CMD5

FBA_CMD0

FBA_CLK1*

FBA_CLK1

FBA_CLK0*

FB_GND_SENSE

FBA_WCKB67

FBA_D0

FBA_WCKB67*

FBA_WCKB45*

FBA_WCKB23*

FBA_WCKB45

FBA_WCKB01*

FBA_WCKB23

FBA_WCK67*

FBA_WCKB01

FBA_WCK67

FBA_WCK45*

FBA_WCK23*

FBA_WCK45

FBA_WCK01*

FBA_WCK23

FBA_WCK01

FBA_D63

FBA_D62

FBA_D60

FBA_D61

FBA_D57

FBA_D58

FBA_D59

FBA_D56

FBA_D55

FBA_D54

FBA_D52

FBA_D53

FBA_D50

FBA_D51

FBA_D47

FBA_D49

FBA_D48

FBA_D45

FBA_D46

FBA_D42

FBA_D43

FBA_D44

FBA_D40

FBA_D41

FBA_D39

FBA_D37

FBA_D38

FBA_D34

FBA_D35

FBA_D36

FBA_D32

FBA_D33

FBA_D31

FBA_D30

FBA_D29

FBA_D27

FBA_D28

FBA_D24

FBA_D25

FBA_D26

FBA_D22

FBA_D19

FBA_D20

FBA_D16

FBA_D17

FBA_D18

FBA_D14

FBA_D15

FBA_D11

FBA_D12

FBA_D13

FBA_D9

FBA_D10

FBA_D8

FBA_D7

FBA_D6

FBA_D4

FBA_D5

FBA_D3

FBA_D2

FBA_D1

FB_VDDQ_SENSE

FBA_CMD_RFU

FB_CLAMP

FBA_CMD_RFU

FB_CAL_PU_GND

FB_CAL_TERM_GND

FBA_DEBUG

FB_CAL_PD_VDDQ

FBA_PLL_AVDD

FBA_DEBUG

FBA_DQS_WP7

FB_DLL_AVDD

FBA_DQS_WP4

FBA_DQS_WP5

FBA_DQS_WP6

FBA_DQS_WP3

FBA_DQS_WP2

FBA_DQS_WP1

FBA_DQS_WP0

FBA_DQS_RN7

FBA_DQS_RN6

FBA_DQS_RN5

FBA_DQS_RN4

FBA_DQS_RN3

FBA_DQS_RN1

FBA_DQS_RN2

FBA_DQS_RN0

FBA_DQM7

FBA_DQM5

FBA_DQM6

FBA_DQM4

FBA_DQM3

FBA_DQM2

FBA_DQM0

FBA_DQM1

FBA_CLK0

FBA_CMD31

FBA_CMD29

FBA_CMD30

FBA_CMD27

FBA_CMD28

FBA_CMD24

FBA_CMD25

FBA_CMD26

FBA_CMD22

FBA_CMD23

FBA_CMD21

FBA_CMD19

FBA_CMD20

FBA_CMD16

FBA_CMD17

FBA_CMD18

FBA_CMD14

FBA_CMD15

FBA_CMD13

FBA_CMD12

FBA_CMD11

FBA_CMD4

FBA_CMD1

FBA_CMD3

FBA_CMD2

FBA_D23

FBA_D21

FBA_CMD6

FBA_CMD7

FBA_CMD8

FBA_CMD9

FBA_CMD10

(3 OF 10)MEM INTERFACE A

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

NCNCNCNCNCNC

NCNC

FBB_CMD31

FBB_CMD10

FBB_CMD14

FBB_CMD24

FBB_CMD25

FBB_CMD_RFU1

FBB_CMD_RFU0

FBB_D12

FBB_D10

FBB_D7

FBB_D1

FBB_D2

FBB_D3

FBB_CMD16

FBB_DQS_RN4

FBB_DQM4

FBB_CLK1

FBB_CMD22

FBB_CLK0

FBB_CLK0*

FBB_CLK1*

FBB_CMD0

FBB_CMD1

FBB_CMD2

FBB_CMD3

FBB_CMD4

FBB_CMD5

FBB_CMD6

FBB_CMD7

FBB_CMD8

FBB_CMD9

FBB_CMD11

FBB_CMD12

FBB_CMD13

FBB_CMD15

FBB_CMD17

FBB_CMD18

FBB_CMD19

FBB_CMD20

FBB_CMD21

FBB_CMD23

FBB_CMD26

FBB_CMD27

FBB_CMD29

FBB_CMD30

FBB_D0

FBB_D4

FBB_D5

FBB_D6

FBB_D8

FBB_D9

FBB_D11

FBB_D13

FBB_D14

FBB_D15

FBB_D16

FBB_D17

FBB_D18

FBB_D19

FBB_D20

FBB_D21

FBB_D22

FBB_D23

FBB_D24

FBB_D25

FBB_D26

FBB_D27

FBB_D28

FBB_D29

FBB_D32

FBB_D33

FBB_D34

FBB_D35

FBB_D36

FBB_D37

FBB_D38

FBB_D39

FBB_D40

FBB_D41

FBB_D42

FBB_D43

FBB_D44

FBB_D45

FBB_D46

FBB_D47

FBB_D48

FBB_D49

FBB_D50

FBB_D51

FBB_D52

FBB_D53

FBB_D54

FBB_D55

FBB_D56

FBB_D57

FBB_D58

FBB_D59

FBB_D60

FBB_D61

FBB_D62

FBB_D63

FBB_DEBUG0

FBB_DEBUG1

FBB_DQM0

FBB_DQM1

FBB_DQM2

FBB_DQM3

FBB_DQM5

FBB_DQM6

FBB_DQM7

FBB_DQS_RN0

FBB_DQS_RN1

FBB_DQS_RN2

FBB_DQS_RN3

FBB_DQS_RN5

FBB_DQS_RN6

FBB_DQS_RN7

FBB_DQS_WP0

FBB_DQS_WP1

FBB_DQS_WP2

FBB_DQS_WP3

FBB_DQS_WP4

FBB_DQS_WP5

FBB_DQS_WP6

FBB_DQS_WP7

FBB_PLL_AVDDFBB_WCK01

FBB_WCK01*

FBB_WCK23

FBB_WCK23*

FBB_WCK45

FBB_WCK45*

FBB_WCK67

FBB_WCK67*

FBB_WCKB01*

FBB_WCKB23

FBB_WCKB23*

FBB_WCKB45

FBB_WCKB45*

FBB_WCKB67

FBB_WCKB67*

FB_VREF

FBB_WCKB01

FBB_D31

FBB_D30

FBB_CMD28

(4 OF 10)MEM INTRERFACE B

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NCNC

NCNC

NCNC

NCNC

NCNC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

NC

NCNCNCNCNCNCNC

NCNC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NCNC

NCNC

NCNC

NCNC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

D

GS

IN

OUT

OUT

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



PLACE CLOSE TO BGA

Power aliases required by this page:- =PP1V35_GPU_S0_REG

- =PP1V05_GPU_PEX_IOVDD

(NONE)

(NONE)

Page Notes



MEM VREFC & VREFD SWITCH

FB PLL & DLL VDD

ESR = 0.05OHM

ESR = 0.05OHM

NOTE:GDDR5 MODE H MAPPING

FB VREF GEN (TEST ONLY)

79 100

79 100

79 100

79 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

PLACE_NEAR=U8000.H26:8.4MM

NOSTUFF

6.3V10%

201X5R

0.1UF

BGA

NV-GK107

OMIT_TABLE

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

BGA

NV-GK107

OMIT_TABLE

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100


60.4 1% 1/20W 201MF


40.2

201

MF

1/20W

1% PLACE_NEAR=U8000.J27:8.4MM

40.2

201

MF

1/20W

1%

60.4

201

MF

1/20W

1%

60.4

201

MF

1/20W

1%

6.3V10%

201X5R

0.1UF

6.3V20%

0201X5R

1UF

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

1/20W1%

201MF

10K

1/20W1%

201MF

10K

201

1/20W1%

MF

10K

1/20W1%

201MF

10K

80 100

80 100

80 100

80 100

6.3V10%

201X5R

0.1UF

6.3V20%

0201X5R

1UF

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

1/20W1%

201MF

60.4

1/20W1%

201MF

60.4

1/20W1%

201MF

10K

1/20W1%

201MF

10K

1/20W1%

201MF

10K

1/20W1%

201MF

10K

1%

201

NOSTUFF

1.33KPLACE_NEAR=U8000.H26:8.4MM

1/20WMF


1/20W1%

201MF

1.33K

NOSTUFF

2011/20W1%MF

10K

79 100

79 100

6 79 100

6 79 100

6 79 100

6 79 100

79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

79 100

77 79 100

77 79 100

79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

6 79 100

79 100

6 79 100

6 79 100

6 79 100

79 100

6 79 100

77 79 100

77 79 100

79 100

6 80 100

6 80 100

80 100

6 80 100

6 80 100

6 80 100

6 80 100

80 100

6 80 100

6 80 100

6 80 100

80 100

6 80 100

77 80 100

77 80 100

80 100

6 80 100

80 100

6 80 100

6 80 100

6 80 100

6 80 100

80 100

6 80 100

6 80 100

6 80 100

6 80 100

6 80 100

77 80 100

80 100

77 80 100

80 100

CRITICAL

SOD-VESM-HF

SSM3K15FV

82

79 80

CRITICAL0603

FERR-220-OHM-2A

FERR-220-OHM-2A

0603

CRITICAL

6.3V20%

0201X5R

1UF

6.3V10%

201X5R

0.1UF

78 101

78 101

100

201

MF

1/20W

5%

100

201

MF

1/20W

5%

0603

22UF20%6.3VX5R-CERM2

0603


SYNC_MASTER=J31_SREE SYNC_DATE=10/25/2011

KEPLER FRAME BUFFER I/F


VOLTAGE=1.05VPP1V05_GPU_FB_DLL_AVDD


VOLTAGE=1.05V PP1V05_GPU_FB_PLL_AVDD

FB_VREF

FB_B1_DQ<16>

FB_A1_DBI_L<1>

FB_A1_CLK_N

FB_A0_DQ<4>

FB_A0_RESET_L

=PP1V35_GPU_S0_FB

=PP1V35_GPU_S0_FB

FB_B1_DQ<26>

FB_B1_DQ<27>

FB_B1_DQ<29>

GPU_FBB_DEBUG1

PP1V05_GPU_FB_PLL_AVDD

FB_CAL_PU_GND

FB_A0_CAS_L

FB_B1_WE_L

GPU_ALT_VREF

FB_A0_DBI_L<3>

FB_A0_DBI_L<2>

FB_A0_CLK_N

FB_A1_A<0>

FB_A0_WCLK_P<0>

FB_CAL_PD_VDDQ

FB_B1_DQ<0>

FB_B0_DQ<19>

GPU_FBA_DEBUG1

FB_A1_DBI_L<3>

FB_A1_A<8>

FB_A1_ABI_L

FB_A1_A<7>

FB_A1_A<5>

FB_B0_DQ<20>

FB_B1_DBI_L<1>

FB_B0_DQ<5>

FB_B1_CAS_L

FB_A1_DQ<17>

FB_A0_EDC<0>

FB_B1_EDC<0>

FB_B1_EDC<1>

FB_B1_EDC<2>

FB_A0_DQ<0>

FB_A0_DQ<1>

FB_A0_DQ<2>

FB_B1_WCLK_N<1>

FB_B1_WCLK_N<0>

FB_B0_WCLK_N<1>

FB_B0_WCLK_N<0>

FB_B1_A<0>

FB_B0_CLK_N

PP1V05_GPU_FB_DLL_AVDD

GPU_FBB_DEBUG0

FB_B0_CKE_L

FB_B0_RAS_L

FB_B0_RESET_L

FB_B0_CKE_L

FB_B0_CAS_L

FB_B1_CS_L

FB_B0_DBI_L<3>

FB_A1_A<1>

FB_B0_A<8>

FB_B1_DBI_L<2>

FB_B0_DQ<31>

FB_A0_DQ<14>

FB_A0_WE_L

FB_A0_A<5>

FB_A0_A<7>

FB_A1_A<6>

FB_A1_WE_L

FB_A1_A<4>

FB_A1_A<2>

FB_A0_RESET_L

FB_A0_RAS_L

FB_A0_A<1>

FB_A0_A<0>

FB_A0_A<8>

FB_A0_A<6>

FB_A0_A<2>

FB_A0_A<3>

FB_A1_CS_L

FB_A0_CS_L

FB_B0_A<6>

FB_B1_A<2>

FB_B1_A<4>

FB_B1_A<5>

FB_B1_A<7>

FB_B1_A<6>

FB_B1_CKE_L

FB_B0_A<7>

FB_A1_CKE_L

FB_B0_DQ<13>

FB_A0_DQ<27>

FB_A0_DQ<28>

FB_A1_DBI_L<0>

FB_A0_DQ<12>

FB_A0_DQ<18>

FB_A0_DQ<19>

FB_A0_DQ<13>

FB_A0_DQ<9>

FB_A0_DQ<11>

FB_A1_DQ<4>

FB_A1_DQ<5>

FB_A0_DQ<10>

FB_A0_CKE_L

FB_A0_DQ<17>

FB_A0_DQ<6>

FB_B1_DBI_L<3>

FB_B0_DBI_L<0>

FB_A0_DBI_L<1>

FB_A1_DBI_L<2>

FB_A0_DBI_L<0>

FB_B1_WCLK_P<0>

FB_B0_RESET_L

FB_CAL_PD_VDDQ

FB_A0_DQ<3>

FB_A0_DQ<5>

FB_A0_DQ<20>

FB_A0_DQ<21>

FB_A0_DQ<22>

FB_A0_DQ<23>

FB_A0_DQ<26>

FB_A0_DQ<29>

FB_A0_DQ<31>

FB_A1_DQ<0>

FB_A1_DQ<1>

FB_A1_DQ<2>

FB_A1_DQ<3>

FB_A1_DQ<6>

FB_A1_DQ<9>

FB_A1_DQ<10>

FB_A1_DQ<11>

FB_A1_DQ<13>

FB_A1_DQ<14>

FB_A1_DQ<15>

FB_A1_DQ<18>

FB_A1_DQ<19>

FB_A1_DQ<20>

FB_A1_DQ<22>

FB_A1_DQ<23>

FB_A1_DQ<24>

FB_A1_DQ<25>

FB_A1_DQ<26>

FB_A1_DQ<27>

FB_A1_DQ<29>

FB_A1_DQ<30>

FB_A1_DQ<31>

FB_A0_DQ<8>

FB_A1_DQ<21>

FB_A1_EDC<2>

FB_A1_DQ<16>

FB_A1_DQ<28>

FB_A0_DQ<25>

FB_A0_DQ<7>

FB_A1_DQ<8>

FB_A1_DQ<12>

FB_A0_DQ<16>

FB_A0_EDC<2>

FB_A0_WCLK_P<1>

FB_A0_WCLK_N<0>

FB_A1_EDC<3>

FB_B0_DQ<30>

FB_B0_WCLK_P<1>

FB_B0_EDC<2>

FB_B1_DQ<31>

FB_B1_DQ<28>

FB_B1_DQ<25>

FB_B1_DQ<22>

FB_B1_DQ<20>

FB_B1_DQ<19>

FB_B1_DQ<18>

FB_B1_DQ<17>

FB_B1_DQ<10>

FB_B1_DQ<7>

FB_B1_DQ<6>

FB_B1_DQ<5>

FB_B1_DQ<4>

FB_B1_DQ<3>

FB_B1_DQ<2>

FB_B0_DQ<29>

FB_B0_DQ<28>

FB_B0_DQ<24>

FB_B0_DQ<23>

FB_B0_DQ<18>

FB_B0_DQ<17>

FB_B0_DQ<16>

FB_B0_DQ<15>

FB_B0_DQ<14>

FB_B0_DQ<11>

FB_B0_DQ<9>

FB_B0_DQ<8>

FB_B0_DQ<6>

FB_B0_DQ<2>

FB_B0_DQ<1>

FB_B0_DQ<7>

FB_B0_DQ<12>

FB_B0_EDC<0>

FB_A1_RESET_L

FB_B1_RESET_L

FB_B1_DQ<24>

FB_B1_DQ<14>

FB_B0_DQ<25>

FB_B0_DQ<22>

FB_B0_DQ<21>

FB_A0_EDC<3>

FB_B1_DQ<21>

FB_A1_EDC<1>

FB_A0_EDC<1>

FB_A0_DQ<30>

FB_B1_DQ<15>

FB_A1_EDC<0>

FB_B0_WCLK_P<0>

FB_B1_DQ<30>

FB_B1_CKE_L

FB_A0_DQ<15>

FB_B1_EDC<3>

FB_A1_WCLK_P<1>

FB_A1_WCLK_N<1>

FB_A1_WCLK_P<0>

GPU_FBB_DEBUG1

GPU_FBB_DEBUG0

FB_B0_EDC<3>

FB_B1_DQ<23>

FB_B1_CLK_N

FB_SW_LEG

FB_A0_ABI_L

FB_B1_DBI_L<0>

FB_B0_DQ<27>

FB_B1_ABI_L

FB_A1_RAS_L

FB_A1_CKE_L

FB_A1_RESET_L

FB_VREF

FB_CLAMP

FB_A0_WCLK_N<1>

FB_A1_WCLK_N<0>

GPU_FBA_DEBUG0

PP1V05_GPU_FB_PLL_AVDD

FB_B1_DQ<13>

FB_B1_A<1>

FB_B1_RESET_L

FB_B1_RAS_L

FB_B0_WE_L

FB_B0_DQ<3>

FB_A1_DQ<7>

FB_B1_DQ<1>

FB_B1_DQ<12>

FB_B1_DQ<11>

=PP1V35_GPU_S0_FB

FB_B1_WCLK_P<1>

FB_A0_CKE_L

FB_A1_A<3>

FB_B0_DQ<4>

FB_B0_A<2>

FB_B0_A<4>

FB_B0_ABI_L

FB_B0_A<1>

FB_B1_A<8>

FB_B0_CLK_P

FB_B1_CLK_P

FB_B0_DBI_L<1>

FB_B0_DBI_L<2>

FB_B1_DQ<9>

FB_A1_CLK_P

FB_A0_CLK_P

FB_A1_CAS_L

FB_A0_DQ<24>

FB_B0_EDC<1>

FB_B1_DQ<8>

FB_B0_DQ<26>

FB_B0_DQ<10>

FB_A0_A<4>

FB_CAL_TERM_GND

=PP1V35_GPU_S0_FB

FB_B1_A<3>

FB_B0_A<0>

FB_B0_A<5>

FB_B0_DQ<0>

FB_B0_A<3>

FB_B0_CS_L

FB_CAL_PU_GND

GPU_FBVDDQ_SENSE_N

GPU_FBVDDQ_SENSE_P



C82601

2

U8000

J27

H27

H25

E1

K27

F2

F1

R30

R31

AB31

AC31

U30

T31

V30

U34

U31

V34

V33

Y32

AA31

AA29

AA28

AC34

U29

AC33

AA32

AA33

Y28

Y29

W31

Y30

AA34

Y31

Y34

R34

Y33

V31

R33

U32

U33

U28

V28

V29

R32

AC32

L28

M29

J29

H28

G29

E31

E32

F30

C34

D32

B33

C33

L29

F33

F32

H33

H32

P34

P32

P31

P33

L31

L34

M28

L32

L33

AG28

AF29

AG29

AF28

AD30

AD29

AC29

AD28

N31

AJ29

AK29

AJ30

AK28

AM29

AM31

AN29

AM30

AN31

AN32

P29

AP30

AP32

AM33

AL31

AK33

AK32

AD34

AD32

AC30

AD33

R29

AF31

AG34

AG32

AG33

P28

J28

H29

R28

AC28

P30

F31

F34

M32

AD31

AL29

AM32

AF34

M30

H30

E34

M34

AF30

AK31

AM34

AF32

M31

G31

E33

M33

AE31

AK30

AN33

AF33

U27K31

L30

H34

J34

AG30

AG31

AJ34

AK34

J30

J31

J32

J33

AH31

AJ31

AJ32

AJ33

U8000

H26

D12

E12

E20

F20

D13

E14

D15

A14

D14

A15

B15

C17

D18

E18

F18

A20

F14

B20

C18

B18

G18

G17

F17

D16

A18

D17

A17

A12

B17

E17

B12

C14

B14

G15

F15

E15

C12

C20

G9

E9

E6

F6

F4

G4

E2

F3

C2

D4

D3

C1

G8

B3

C4

B5

C5

A11

C11

D11

B11

D8

A8

F9

C8

B8

F24

G23

E24

G24

D21

E21

G21

F21

F11

G27

D27

G26

E27

E29

F29

E30

D30

A32

C31

G11

C32

B32

D29

A29

C29

B29

B21

C23

A21

C21

F12

B24

C24

B26

C26

G12

G6

F5

G14

G20

E11

E3

A3

C9

F23

F27

C30

A24

D9

E4

B2

A9

D22

D28

A30

B23

D10

D5

C3

B9

E23

E28

B30

A23

H17F8

E8

A5

A6

D24

D25

B27

C27

D6

D7

C6

B6

F26

E26

A26

A27

R82011 2

R82041

2

R82051

2

R82021

2

R82031

2

C82031

2

C82021

2

R82501

2

R82511

2

R82521

2

R82531

2

C82071

2

C82061

2

R82071

2

R82061

2

R82551

2

R82571

2

R82541

2

R82561

2

R82581

2

R82591

2

R82611 2

Q8265

3

12

L8201

1 2

L8202

1 2

C82041

2

C82051

2

R82701

2

R82711

2

C82011

2

C82081

2

051-9585

3.0.0

82 OF 132

77 OF 105

77

77

77

77 79 100

7 77

7 77

77

77

77

77

77

77

77 80 100

77 79 100

77 79 100

77 80 100

77

77 79 100

77 80 100

77 80 100

77

77

77

77

7 77

7 77

77

7 77 83

7 77 83

IN FB

EN

PVCCVCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGNDGND

SET0

SET1

VID0

VID1

OUT

IN

IN BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC PVCC

GND PGND

EN

FB

IN

OUT

IN

IN

G

D

S

G

D

S

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



GPIO(16) VID1 VID0 FBVDD

0 0 1.5V

1 0 1.35V

5.3A MAX OUTPUT

<Ra>

Vout = 0.5V * (1 + Ra / Rb)

VOUT = 1.05V

11A MAX OUTPUT

F = 500 KHZ

F = 500 KHZ

VOUT = 1.5V / 1.35V

GPU FB SUPPLY

<Rb>

<Ra>

GPU 1V05 SUPPLY

<Rb>

1000PF

NP0-C0G25V

402

5%

603MF-LF1/10W5%1

NO STUFF

0.0033UF

CERM402

10%50V

NO STUFF

GPUFB_SNBR

CRITICAL

0402-1

10VX5R-CERM

20%10UF

402

10VX5R-CERM

2.2UF20%

10PF

0201

5%

COG50V

10PF

0201

50V5%

COG


402

25VX5R

1UF10%

201MF

1/20W

1.62K

1%

201

1%1/20WMF

1.62K

4.64K

201MF1/20W1%

NOSTUFF

4.64K

NOSTUFF

201MF

1%1/20W

1.69K

201MF

1/20W1%

201MF1/20W

1.69K1%

UTQFN

ISL95870AH

CRITICAL

201

10VX5R

10%0.01UF

MF1/20W1%3.01K

201

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

1/20W1%3.01K

MF201

MF1/20W

1%2.74K

201MF

1%

201

2.74K

1/20W

1/20WMF

5%2.2

201

5%2.2

1/20WMF

201

1%845

1/20WMF

201

1%845

1/20WMF201

5%10PF

C0G-NPO25V

0201

5%25V

0201

10PF

C0G-NPO0.047UF10%

X5R6.3V

201

16V10%0.1UF

X5R-CERM0201

X5R

10%2.2UF

16V

603

CRITICAL

0612

1%0.001

1WMF-1

MF-11W1%

0612

0.001

CRITICAL

2.2UH-8.0A

CRITICAL

PCMB065T-SM

SM


CRITICAL

POLY-TANT2.0V20%

330UF

CASE-B2-SM1

CASE-B2-SM1TANT2.5V20%330UF

CRITICAL CRITICAL

330UF20%2.5VTANTCASE-B2-SM1

92

5%0

NOSTUFF

201MF1/20W

83 101

92

ISL95870

CRITICAL

UTQFN

X5R10V20%10UF

CRITICAL

603

201

27K1%1/20WMF

0

5%

201MF

1/20W

1%1/20W

201MF

150K

201MF1/20W1%301K

82

0

1/20W5%

201MF

NOSTUFF

92

92

SM


SM

X7R16V10%

201

1000PF

SM

1000PF

16V10%

201X7R

SM

SM

2.25%

MF-LF1/16W

4020

1/16W5%

MF-LF402

0.1UF

50VX7R

10%

603-1

83 101

1.0UH-13A-5.6MOHM

PCMB065T-SM

CRITICALHVSON-3333

RJK0225DNS

CRITICAL

OMIT_TABLE

CRITICAL

HVSON-333

RJK0226DNS

OMIT_TABLE


68UF

CRITICAL

20%16V 25V


1000PF

NP0-C0G

5%

402

SIZ700DTPOWERPAIR-6X3.7

CRITICAL


16V20%

68UF

CRITICAL


603-1

10%1UF

25VX5R


402

5%

NP0-C0G

1000PF

25V

25V5%

1000PF

402NP0-C0G

603

CRITICAL

10UF

X5R

20%6.3V


1V05 GPU / 1V35 FB POWER SUPPLY


P1V05_GPU_S0_REG_R

VOLTAGE=1.05V


P1V05_GPU_LL

SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.2 mm

DIDT=TRUE


P1V05_GPU_CS_P


MIN_LINE_WIDTH=0.6 mmPP5V_S0GPU_P1V5_VCC

GATE_NODE=TRUE

GPUFB_DRVLMIN_LINE_WIDTH=0.6 mm

DIDT=TRUE


P1V05_GPU_OCSET

P1V05_GPU_PEX_IOVDD_SNS_N

GPUFB_SET1

GPUFB_SET_R

=PP5V_S0GPU_P1V5


GPUFB_VBST

DIDT=TRUE

GPUFB_LL


DIDT=TRUE


SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.3 mmGPUFB_BOOT_RC

MIN_NECK_WIDTH=0.2 mmDIDT=TRUE


DIDT=TRUE

GPUFB_DRVH

GATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mm

FBVDD_ALTVO

P1V05_GPU_VBST



DIDT=TRUE


P1V05_GPU_BOOT_RC

GPUFB_CS_N

VOLTAGE=1.35VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmP1V5_GPU_S0_REG_R

P1V05_GPU_OCSET_R

P1V05_GPU_VO_R

P1V05_S0GPU_PGOOD

=P1V05_GPU_EN

GPUFB_GPU_OCSET_R

GPU_FBVDDQ_SENSE_P

GPU_FBVDDQ_SENSE_N

P1V05_GPU_SREF

=P1V35FB_EN

GPUFB_PGOOD

GPUFB_FSEL

GPUFB_SET0

P1V05_GPU_CS_N

P1V05_GPU_RTN

P1V05_GPU_FSEL

P1V05_GPU_DRVH


DIDT=TRUE

MIN_LINE_WIDTH=0.6 mmP1V05_GPU_FB

P1V05_GPU_PEX_IOVDD_SNS_P

GPU_FBVDDQ_SENSE_DIV

MIN_LINE_WIDTH=0.6 mmP1V05_GPU_DRVL


DIDT=TRUE

GPUFB_SREF

GPUFB_CS_P

P1V05_GPU_VO

GPU_FBGND_SENSE

VOLTAGE=0V


GPUP1V05_AGND

=PPVIN_S0GPU_P1V5

=PPVIN_S0GPU_P1V05


PP5V_S0GPU_P1V05_VCCMIN_LINE_WIDTH=0.6 mm

=PP5V_S0GPU_P1V05

GPUFB_VO

GPUFB_OCSET

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0V

GPUP1V5_AGND

=PP1V05_S0GPU_REG

GPUFB_GPU_VO_R

=PP1V5R1V35_GPU_REG

R83031

2

U8310

123

6

5

1

15

7

16

9

10

14

2

4

11

13

8

C83011

2

R83491

2

R83501 2

R83681

2

R83671

2

R83631

2

XW8350

1 2

XW8302

1

2

C8320

12

XW8301

1

2

C8370

12

XW8352

1

2

XW8351

1

2

R83511

2R83591

2

C83551

2

L8360

1 2

Q8360

5

4

1 2 3

Q8361

5

4

1 2 3

C8390 1

2

C83961

2

Q8310

1

6

4 5

2 3 7

8

C8340 1

2

C83451

2

C83461

2

C8316 1

2

C83651

2

C83661

2

R83611

2

C83621

2

C83711

2

C83721

2

C83761

2

C83521

2

C83951

2

R83811 2

R83531 2

R83541

2

R83521

2

R83711

2

R83721

2

U8350

1815

10

13

3

1

11

2

14

16

20

4

8

9

7

17

19

6

5

12

C8373 1

2

R83041

2

R83051

2

R83061

2

R83071

2

R83011

2

R83251

2

R83211

2

R83221

2

C8304 1

2

C83051

2 C83031

2

C83251

2

C8302 1

2

R8360

1 2

3 4

R8310

12

34

L8310

1 2

XW8310

1 2

C8310 1

2

C83601

2

C83611

2

051-9585

3.0.0

83 OF 132

78 OF 105

6

101 103

6

7

6

6

6

6

6

6

101 103

101 103

6

6

101 103

7

7

7

7

7 103

WCK01

DQ24

DQ31

NC

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7

A9/A1

DBI2*

WE*

BA2/A4

BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

ZQ

(MF=0)

(1 OF 2)

IN IN

IN

IN

WCK01

DQ24

DQ31

NC

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7

A9/A1

DBI2*

WE*

BA2/A4

BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

ZQ

(MF=0)

(1 OF 2)

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NC

NC

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

IN

IN

IN

IN

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

NC

NC

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




CK TERMINATION - A0



CK TERMINATION - A1

PLACE CLOSE TO U8450

- =PP1V5R1V35_S0_FB_VDD

(NONE)

Page Notes


20%

402X5R

4.7UF

6.3V 6.3V20%

402X5R

4.7UF

6.3V20%

402X5R

4.7UF

6.3V20%

402X5R

4.7UF

6.3V20%

402X5R

4.7UF

6.3V20%

402X5R

4.7UF

6.3V20%

402X5R

4.7UF

6.3V20%

402X5R

4.7UF

6.3V20%

402X5R

4.7UF

6.3V20%

402X5R

4.7UF20%6.3V

402X5R

4.7UF

402

6.3V20%

X5R

4.7UF

1/20W1%

201MF

1201/20W

1%

201MF

1201/20W

1%

201MF

120

1/20W1%

201MF

1201/20W

1%

201MF

1201/20W

1%

201MF

120

BGA

H5GQ1H24AFR-T2C

32MX32-1.25GHZ-MFL

OMIT_TABLE

40.2

PLACE_NEAR=U8400.J12:8.4MM

1/20W1%

201MF

201MF

40.2

1%1/20W


X5R-CERM0201

0.01UF10%10V


0201X5R-CERM

0.01UF10%10V


1/20W1%

MF

40.2


201


40.2

201

1/20W1%

MF


1/20W1%

201MF

931


1/20W1%

201MF

549


1/20W1%

201MF

1.33K820PF10%


25VX7R-CERM0201

77 79 80


1/20W1%

201MF

1.33K

77 79 80

1/20W1%

201MF

931



1/20W1%

201MF

549


820PF10%25VX7R-CERM0201

820PF10%

PLACE_NEAR=U8400.U10:8.4MM

25VX7R-CERM0201


1/20W1%

201MF

549

77 79 80


1/20W1%

201MF

931


1/20W1%

201MF

1.33K

10%

PLACE_NEAR=U8400.A10:8.4MM

820PF

0201X7R-CERM25V


1/20W1%

201MF

1.33K

77 79 80

1/20W1%

201MF

931


1/20W1%

201MF

549



10%820PF

25VX7R-CERM0201

10%25VX7R-CERM0201

820PF


6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

1UF

6.3V20%

0201X5R

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

BGA

H5GQ1H24AFR-T2C

32MX32-1.25GHZ-MFL

OMIT_TABLE

H5GQ1H24AFR-T2C

32MX32-1.25GHZ-MFL

OMIT_TABLE

BGA

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

77 100

77 79 100

77 79 100

6 77 100

6 77 100

6 77 100

6 77 100

77 100

77 100

77 100

77 100

77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6 77 100

6 77 100

6 77 100

6 77 100

77 100

77 100

77 100

77 100

77 100

77 79 100

77 79 100

77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

BGA

H5GQ1H24AFR-T2C

32MX32-1.25GHZ-MFL

OMIT_TABLE

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6.3V10%

201X5R

0.1UF

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100


GDDR5 Frame Buffer A

SYNC_MASTER=J31_SREE

FB_A0_DQ<8>

FB_A0_DQ<9>

FB_A1_EDC<3>

FB_A1_EDC<1>

FB_A1_EDC<2>FB_A0_EDC<1>

FB_A0_EDC<2>

FB_A0_EDC<3>

FB_A0_EDC<0>

FB_A0_WCLK_N<1>

FB_A0_ABI_L

FB_A0_WE_L

FB_A0_CKE_L

=PP1V35_GPU_FBVDDQ

=PP1V35_GPU_FBVDDQ

FB_A0_DQ<29>

FB_A1_CLK_P

FB_A0_CLK_N

FB_A0_CLK_P

FB_A0_A<4>

FB_A1_A<8>

FB_A1_DBI_L<0>

FB_A1_CS_L

FB_A1_A<7>

FB_A1_A<1>

FB_A1_WE_L

FB_A1_A<4>

FB_A1_A<3>

FB_A1_A<2>

FB_A1_CKE_L

FB_A1_A<0>

FB_A1_A<5>

FB_A1_A<6>

FB_A1_WCLK_P<0>

FB_A1_WCLK_P<1>

FB_A1_WCLK_N<0>

FB_A0_DBI_L<1>

FB_A0_DBI_L<0>

FB_A0_DQ<13>

FB_A0_A<5>

FB_A0_A<3>

FB_A0_A<2>

FB_A0_CLK_NFB_A0_CLK_P

FB_A1_WCLK_N<1>

FB_SW_LEG

FB_A0_A<8>

FB_SW_LEG

FB_A0_A<1>

FB_A0_VREFC

FB_A0_VREFD

FB_A1_VREFC

FB_A1_VREFD

FB_SW_LEG

FB_SW_LEG

FB_A0_CAS_L

FBA0_CK_MID

FB_A1_CLK_P

FB_A0_DQ<4>

FB_A0_DQ<6>

FB_A0_DQ<7>

FB_A0_DQ<10>

FB_A0_DQ<11>

FB_A0_DQ<12>

FB_A0_DQ<15>

FB_A0_DQ<16>

FB_A0_DQ<14>

FB_A0_RESET_L

FB_A0_DQ<17>

FB_A0_DQ<18>

FB_A0_DQ<19>

FB_A0_DQ<21>

FB_A0_DQ<23>

FB_A0_DQ<24>

FB_A0_DQ<25>

FB_A0_DQ<22>

FB_A0_DQ<26>

FB_A0_DQ<28>

FB_A0_DQ<30>

FB_A0_DQ<27>

FB_A0_DQ<5>

FB_A0_A<7>

FB_A0_DQ<3>

FB_A0_DQ<2>

FB_A0_DQ<1>

FB_A0_DQ<0>

FB_A0_DBI_L<2>

FB_A0_A<0>

FB_A0_A<6>

FB_A0_DBI_L<3>

FB_A0_DQ<20>

FB_A1_DBI_L<1>

FB_A1_DBI_L<2>

FB_A1_DBI_L<3>

FB_A1_CLK_N

FB_A1_CAS_L

FB_A1_DQ<1>

FB_A1_DQ<0>

FB_A1_ZQ

FB_A1_MF

FB_A1_RAS_L

FB_A1_SEN

FB_A1_DQ<16>

FB_A1_RESET_L

FB_A1_EDC<0>

FB_A1_ABI_L

FB_A1_DQ<2>

FB_A1_DQ<3>

FB_A1_DQ<4>

FB_A1_DQ<5>

FB_A1_DQ<6>

FB_A1_DQ<7>

FB_A1_DQ<8>

FB_A1_DQ<9>

FB_A1_DQ<10>

FB_A1_DQ<11>

FB_A1_DQ<12>

FB_A1_DQ<13>

FB_A1_DQ<14>

FB_A1_DQ<15>

FB_A1_DQ<17>

FB_A1_DQ<18>

FB_A1_DQ<19>

FB_A1_DQ<20>

FB_A1_DQ<21>

FB_A1_DQ<22>

FB_A1_DQ<23>

FB_A1_DQ<24>

FB_A1_DQ<25>

FB_A1_DQ<26>

FB_A1_DQ<27>

FB_A1_DQ<28>

FB_A1_DQ<29>

FB_A1_DQ<30>

FB_A1_DQ<31>

FB_A0_WCLK_P<1>

=PP1V35_GPU_FBVDDQ

=PP1V35_GPU_FBVDDQ

=PP1V35_GPU_FBVDDQ

FB_A0_WCLK_N<0>

FB_A0_WCLK_P<0>

FB_A0_SEN

FB_A0_CS_L

FB_A0_ZQ

FB_A0_RAS_L

FB_A0_VREFC

MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.1 mm

FB_A1_VREFC


FB_A0_VREFD


FB_A1_VREFD


FB_A0_DQ<31>

FB_A0_MF

FB_A1_CLK_N

=PP1V35_GPU_FBVDDQ

FBA1_CK_MID

U8400

H4

K5

K4

H5

J4

H11

K10

K11

H10

L3

J12

J11

J3

G12

D2

D13

P13

P2

A4

A2

B11

B13

E11

E13

F11

F13

U11

U13

T11

T13

B4

N11

N13

M11

M13

U4

U2

T4

T2

N4

N2

B2

M4

M2

E4

E2

F4

F2

A11

A13

C2

C13

R13

R2

J1

A5

J5

U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

U8400

C5

C10

L14

P11

R5

R10

D11

G1

G4

G11

G14

L1

L4

L11

B1

B3

F1

F3

F12

F14

G2

G13

H3

H12

K3

K12

B12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

B14

P12

P14

T1

T3

T12

T14

D1

D3

D12

D14

E5

E10

J14

A10

U10

B5

B10

L10

P10

T5

T10

D10

G5

G10

H1

H14

K1

K14

L5

A1

A3

E1

E3

E12

E14

F5

F10

H2

H13

K2

K13

A12

M5

M10

N1

N3

N12

N14

R1

R3

R4

R11

A14

R12

R14

U1

U3

U12

U14

C1

C3

C4

C11

C12

C14

C84161

2

C84171

2

C84181

2

C84191

2

C84201

2

C84211

2

C84221

2

C84231

2

C84241

2

C84251

2

U8450

C5

C10

L14

P11

R5

R10

D11

G1

G4

G11

G14

L1

L4

L11

B1

B3

F1

F3

F12

F14

G2

G13

H3

H12

K3

K12

B12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

B14

P12

P14

T1

T3

T12

T14

D1

D3

D12

D14

E5

E10

J14

A10

U10

B5

B10

L10

P10

T5

T10

D10

G5

G10

H1

H14

K1

K14

L5

A1

A3

E1

E3

E12

E14

F5

F10

H2

H13

K2

K13

A12

M5

M10

N1

N3

N12

N14

R1

R3

R4

R11

A14

R12

R14

U1

U3

U12

U14

C1

C3

C4

C11

C12

C14

C84671

2

C84661

2

C84711

2

C84751

2

C84701

2

C84741

2

C84691

2

C84731

2

C84681

2

C84721

2

C84001

2

C84011

2

C84021

2

C84031

2

C84041

2

C84051

2

C84501

2

C84511

2

C84521

2

C84531

2

C84541

2

C84551

2

R84031

2

R84041

2

R84001

2

R84531

2

R84541

2

R84501

2

U8450

H4

K5

K4

H5

J4

H11

K10

K11

H10

L3

J12

J11

J3

G12

D2

D13

P13

P2

A4

A2

B11

B13

E11

E13

F11

F13

U11

U13

T11

T13

B4

N11

N13

M11

M13

U4

U2

T4

T2

N4

N2

B2

M4

M2

E4

E2

F4

F2

A11

A13

C2

C13

R13

R2

J1

A5

J5

U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

R8401

1 2

R8451

1 2

C84901

2

C84911

2

R8402

1 2

R8452

1 2

R84341

2

R84301

2

R84311

2

C84311

2

R84811

2

R84841

2

R84801

2

C84811

2

C84331

2

R84321

2

R84351

2

R84331

2

C84321

2

R84831

2

R84851

2

R84821

2

C84831

2

C84821

2

C84561

2

C84571

2

C84581

2

C84591

2

C84601

2

C84611

2

C84621

2

C84631

2

C84641

2

C84651

2

C84061

2

C84071

2

C84081

2

C84091

2

C84101

2

C84111

2

C84121

2

C84131

2

C84141

2

C84151

2

051-9585

3.0.0

84 OF 132

79 OF 105

7 76 79 80

7 76 79 80

77 79 100 77 79 100

79

79

79

79

7 76 79 80

7 76 79 80

7 76 79 80

79 79

79

79

77 79

100

7 76 79 80

IN

BI

IN

IN

IN

IN

WCK01

DQ24

DQ31

NC

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7

A9/A1

DBI2*

WE*

BA2/A4

BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

ZQ

(MF=0)

(1 OF 2)

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NC

NC

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

IN

IN

IN

IN

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

NC

NC

WCK01

DQ24

DQ31

NC

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7

A9/A1

DBI2*

WE*

BA2/A4

BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

ZQ

(MF=0)

(1 OF 2)

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




- =PP1V5R1V35_S0_FB_VDD


(NONE)

Page Notes

(NONE)

CK TERMINATION - B0

CK TERMINATION - B1




6 77 100

6 77 100

4.7UF

X5R402

20%6.3V

4.7UF

X5R402

20%6.3V

4.7UF

X5R402

20%6.3V

4.7UF

X5R402

20%6.3V

4.7UF

X5R402

20%6.3V6.3V

4.7UF

X5R402

20%

4.7UF

X5R402

20%6.3V

4.7UF

X5R402

20%6.3V

4.7UF

X5R402

20%6.3V

4.7UF

X5R402

20%6.3V

4.7UF

X5R402

20%6.3V

4.7UF

X5R402

20%6.3V

120

MF201

1%1/20W

120

MF201

1%1/20W

120

MF201

1%1/20W

120

MF201

1%1/20W

120

MF201

1%1/20W

40.2

MF201

1%1/20W


0201X5R-CERM


10%0.01UF

10V


40.2

MF201

1%1/20W

1/20W

40.2

MF201

1%


0201X5R-CERM


0.01UF

10V10%

40.2

MF201

1/20W1%



MF201

1%1/20W

1.33K

77 79 80


MF201

1%1/20W

931


549

MF201

1%1/20W

0201X7R-CERM25V10%820PF



1.33K

MF201

1%1/20W


931

MF201

1%1/20W


549

MF201

1%1/20W

77 79 80

820PF

0201X7R-CERM25V10%


0201X7R-CERM25V10%820PF



549

MF201

1%1/20W

77 79 80


931

MF201

1%1/20W


1.33K

MF201

1%1/20W

0201X7R-CERM25V10%820PF


0201X7R-CERM25V10%820PF


77 79 80


931

MF201

1%1/20W

201


549

MF

1%1/20W

1.33K


MF201

1%1/20W820PF

0201X7R-CERM25V10%


1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

1UF

X5R0201

20%6.3V

OMIT_TABLE

32MX32-1.25GHZ-MFL

H5GQ1H24AFR-T2C

BGA

OMIT_TABLE

32MX32-1.25GHZ-MFL

H5GQ1H24AFR-T2C

BGA

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

77 100

77 80 100

77 80 100

6 77 100

6 77 100

6 77 100

6 77 100

77 100

77 100

77 100

77 100

77 100 120

MF201

1%1/20W

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

6 77 100

6 77 100

6 77 100

6 77 100

77 100

77 100

77 100

77 100

77 100

77 80 100

77 80 100

77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

32MX32-1.25GHZ-MFL

OMIT_TABLE

H5GQ1H24AFR-T2C

BGA

201X5R

0.1UF10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

0.1UF

X5R201

10%6.3V

6.3V

0.1UF

X5R201

10%

0.1UF

X5R201

10%6.3V

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

6 77 100

OMIT_TABLE

32MX32-1.25GHZ-MFL

H5GQ1H24AFR-T2C

BGA


GDDR5 Frame Buffer B

SYNC_MASTER=J31_SREE

=PP1V35_GPU_FBVDDQ

FB_B0_VREFD

MIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.25 MM


FB_B1_VREFD


FB_B1_VREFC


FB_B0_VREFC

FB_B0_VREFD

FB_B0_VREFC

=PP1V35_GPU_FBVDDQ

=PP1V35_GPU_FBVDDQ

FB_B1_CLK_N

FB_B1_WCLK_N<1>

FB_B1_ZQ

FB_B1_A<6>

FB_B1_A<3>

FB_B1_A<4>

FB_B1_A<2>

FB_B0_DQ<17>

FB_B0_DQ<31>

FB_B1_CLK_P

FB_B1_CKE_L

FB_B1_CAS_L

FB_B1_RAS_L

FB_B1_SEN

FB_B0_DQ<23>

FB_B0_DQ<24>

FB_B0_DQ<25>

=PP1V35_GPU_FBVDDQ

=PP1V35_GPU_FBVDDQ

FB_B0_DQ<30>

FB_B0_DQ<29>

FB_B0_DQ<27>

=PP1V35_GPU_FBVDDQ

FB_SW_LEG

FB_SW_LEG

FB_B0_RAS_L

FB_B1_VREFD

FB_B1_VREFC

FB_SW_LEG

FB_B1_RESET_L

FB_B0_CS_L

FB_B0_WE_L

FB_B0_CAS_L

FB_B0_WCLK_N<1>

FB_B0_WCLK_P<1>

FB_B0_A<6>

FB_B0_A<1>

FB_B1_WCLK_P<1>

FB_B1_WCLK_N<0>

FB_B1_WCLK_P<0>

FB_B1_WE_L

FB_B1_A<0>

FB_B1_A<1>

FB_B1_A<7>

FB_B1_A<5>

FB_B1_DBI_L<2>

FB_B1_DBI_L<1>

FB_B1_DBI_L<0>FB_B0_DBI_L<0>

FB_B0_CKE_L

FB_B1_CS_L

FB_B1_CLK_NFB_B0_CLK_P

FB_B0_CLK_N

FB_B0_CLK_P

FB_B0_ABI_L

FB_B1_CLK_P

FB_B0_CLK_N

FB_B0_MF

FBB1_CK_MID

FB_B0_DBI_L<1>

FB_B0_DBI_L<2>

FB_B0_DBI_L<3>

FB_B0_DQ<7>

FB_B0_DQ<8>

FB_B0_DQ<13>

FB_B0_DQ<10>

FB_B0_DQ<15>

FB_B0_DQ<0>

FB_B0_DQ<1>

FB_B0_DQ<2>

FB_B0_DQ<3>

FB_B0_DQ<4>

FB_B0_DQ<5>

FB_B0_DQ<6>

FB_B0_DQ<9>

FB_B0_DQ<11>

FB_B0_DQ<12>

FB_B0_DQ<16>

FB_B0_DQ<18>

FB_B0_DQ<19>

FB_B0_DQ<28>

FB_B1_DQ<0>

FB_B1_DQ<1>

FB_B1_A<8>

FB_B1_DBI_L<3>

FB_B1_DQ<2>

FB_B1_DQ<3>

FB_B1_DQ<4>

FB_B1_DQ<5>

FB_B1_DQ<6>

FB_B1_DQ<7>

FB_B1_DQ<8>

FB_B1_DQ<9>

FB_B1_DQ<10>

FB_B1_DQ<11>

FB_B1_DQ<12>

FB_B1_DQ<13>

FB_B1_DQ<14>

FB_B1_DQ<15>

FB_B1_DQ<16>

FB_B1_DQ<17>

FB_B1_DQ<18>

FB_B1_DQ<19>

FB_B1_DQ<20>

FB_B1_DQ<21>

FB_B1_DQ<22>

FB_B1_DQ<23>

FB_B1_DQ<24>

FB_B1_DQ<25>

FB_B1_DQ<26>

FB_B1_DQ<27>

FB_B1_DQ<28>

FB_B1_DQ<29>

FB_B1_DQ<30>

FB_B1_DQ<31>

FB_B0_DQ<14>

FB_B0_DQ<20>

FB_B0_A<8>

FB_B0_A<3>

FB_B0_A<5>

FB_B0_A<7>

FB_B1_ABI_L

FB_B1_MF

FB_B1_EDC<2>

FB_B1_EDC<1>

FB_B1_EDC<3>

FB_B1_EDC<0>FB_B0_EDC<0>

FB_B0_EDC<2>

FB_B0_EDC<3>

FB_B0_EDC<1>

FB_SW_LEG

FB_B0_A<0>

FB_B0_DQ<26>

FB_B0_DQ<22>

FB_B0_DQ<21>

FB_B0_A<4>

FB_B0_A<2>

FB_B0_WCLK_N<0>

FB_B0_WCLK_P<0>

FB_B0_RESET_L

FB_B0_SEN

FBB0_CK_MID

FB_B0_ZQ

U8500

H4

K5

K4

H5

J4

H11

K10

K11

H10

L3

J12

J11

J3

G12

D2

D13

P13

P2

A4

A2

B11

B13

E11

E13

F11

F13

U11

U13

T11

T13

B4

N11

N13

M11

M13

U4

U2

T4

T2

N4

N2

B2

M4

M2

E4

E2

F4

F2

A11

A13

C2

C13

R13

R2

J1

A5

J5

U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

U8500

C5

C10

L14

P11

R5

R10

D11

G1

G4

G11

G14

L1

L4

L11

B1

B3

F1

F3

F12

F14

G2

G13

H3

H12

K3

K12

B12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

B14

P12

P14

T1

T3

T12

T14

D1

D3

D12

D14

E5

E10

J14

A10

U10

B5

B10

L10

P10

T5

T10

D10

G5

G10

H1

H14

K1

K14

L5

A1

A3

E1

E3

E12

E14

F5

F10

H2

H13

K2

K13

A12

M5

M10

N1

N3

N12

N14

R1

R3

R4

R11

A14

R12

R14

U1

U3

U12

U14

C1

C3

C4

C11

C12

C14

R85001

2

C85161

2

C85171

2

C85181

2

C85191

2

C85201

2

C85211

2

C85221

2

C85231

2

C85241

2

C85251

2

U8550

C5

C10

L14

P11

R5

R10

D11

G1

G4

G11

G14

L1

L4

L11

B1

B3

F1

F3

F12

F14

G2

G13

H3

H12

K3

K12

B12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

B14

P12

P14

T1

T3

T12

T14

D1

D3

D12

D14

E5

E10

J14

A10

U10

B5

B10

L10

P10

T5

T10

D10

G5

G10

H1

H14

K1

K14

L5

A1

A3

E1

E3

E12

E14

F5

F10

H2

H13

K2

K13

A12

M5

M10

N1

N3

N12

N14

R1

R3

R4

R11

A14

R12

R14

U1

U3

U12

U14

C1

C3

C4

C11

C12

C14

C85671

2

C85661

2

C85711

2

C85751

2

C85701

2

C85741

2

C85691

2

C85731

2

C85681

2

C85721

2

U8550

H4

K5

K4

H5

J4

H11

K10

K11

H10

L3

J12

J11

J3

G12

D2

D13

P13

P2

A4

A2

B11

B13

E11

E13

F11

F13

U11

U13

T11

T13

B4

N11

N13

M11

M13

U4

U2

T4

T2

N4

N2

B2

M4

M2

E4

E2

F4

F2

A11

A13

C2

C13

R13

R2

J1

A5

J5

U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

C85001

2

C85011

2

C85021

2

C85051

2

C85041

2

C85031

2

C85501

2

C85511

2

C85521

2

C85531

2

C85541

2

C85551

2

R85041

2

R85031

2

R85531

2

R85541

2

R85501

2

R8502

1 2

C85901

2

R8501

1 2

R8552

1 2

C85911

2

R8551

1 2

R85311

2

R85341

2

R85301

2

C85311

2

R85331

2

R85351

2

R85321

2

C85321

2

C85331

2

R85801

2

R85841

2

R85811

2

C85811

2

C85831

2

R85851

2

R85821

2

R85831

2

C85821

2

C85061

2

C85071

2

C85081

2

C85091

2

C85101

2

C85111

2

C85121

2

C85131

2

C85141

2

C85151

2

C85561

2

C85571

2

C85581

2

C85591

2

C85601

2

C85611

2

C85621

2

C85631

2

C85641

2

C85651

2

051-9585

3.0.0

85 OF 132

80 OF 105

7 76 79 80

80

80

80

80

80

80

7 76 79 80

7 76 79 80

77 80

100

7 76 79 80

7 76 79 80

7 76 79 80

80

80

77 80 100

77 80 100

BI

BI

BI

BI

BI

BI

IN

OUT

IN

OUT

IN

OUT

IN

IN

IN

IN

IN

OUT

BI

OUT

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

NCNC

NCNCNCNC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

NC

NCNC

NCNC

NCNC

NCNC

OUT

OUT

BI

BI

IFPEF_PLLVDD

IFPEF_RSET

IFPD_RSET

IFPD_PLLVDD

I2CA_SDA

IFPF_IOVDD

IFPAB_PLLVDD

IFPAB_RSET

IFPC_PLLVDD

IFPC_RSET

IFPC_L1

IFPC_L0*

IFPC_L0

IFPC_AUX_I2CW_SCL

IFPB_TXD7*

IFPA_TXD3*

IFPB_TXC

DACA_VREF

DACA_RSET

IFPE_IOVDD

I2CA_SCL

IFPC_L3*

IFPF_L3*

IFPF_L3

IFPF_L2*

IFPF_L2

IFPF_L1*

IFPF_L1

IFPF_L0*

IFPF_L0

IFPF_AUX_I2CZ_SDA*

IFPF_AUX_I2CZ_SCL

IFPE_L3*

IFPE_L3

IFPE_L2*

IFPE_L2

IFPE_L1*

IFPE_L1

IFPE_L0*

IFPE_L0

IFPE_AUX_I2CY_SDA*

IFPE_AUX_I2CY_SCL

IFPD_L3*

IFPD_L3

IFPD_L2

IFPD_L1*

IFPD_L1

IFPD_L0*

IFPD_L0

IFPD_IOVDD

IFPC_L3

IFPC_L1*

IFPC_IOVDD

IFPC_AUX_I2CW_SDA*

IFPB_TXD7

IFPB_TXD6*

IFPB_TXD6

IFPB_TXD5*

IFPB_TXD5

IFPB_TXD4*

IFPB_TXD4

IFPB_TXC*

IFPB_IOVDD

IFPA_TXD3

IFPA_TXD2*

IFPA_TXD2

IFPA_TXD1*

IFPA_TXD1

IFPA_TXD0*

IFPA_TXD0

IFPA_TXCIFPA_IOVDD

I2CS_SDA

I2CS_SCL

I2CC_SDA

I2CC_SCL

I2CB_SDA

I2CB_SCL

DACA_VSYNC

DACA_VDD DACA_RED

DACA_HSYNC

DACA_GREEN

DACA_BLUE

CEC

IFPA_TXC*

IFPD_L2*

IFPC_L2

IFPC_L2*

IFPD_AUX_I2CX_SCL

IFPD_AUX_I2CX_SDA*

(5 OF 10)

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NCNC

NCNC

NC

NCNC

THERMDP

THERMDN

JTAG_TRST*

JTAG_TMS

JTAG_TDO

JTAG_TDI

JTAG_TCK

STRAP3

STRAP4

STRAP2

STRAP1

STRAP0

XTAL_SSIN

XTAL_OUTBUFF

XTAL_OUT

XTAL_IN

VID_PLLVDD

PLLVDD

SP_PLLVDD

TESTMODE

MULTI_STRAP_REF0_GND

ROM_SO

ROM_SI

ROM_SCLK

ROM_CS*

VDD33

GPIO20

GPIO16

GPIO0

GPIO1

GPIO2

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO13

GPIO14

GPIO15

GPIO17

GPIO18

GPIO19

GPIO21

GPIO11

GPIO12

GPIO4

GPIO3

(6 OF 10)

IN

IN

IN

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



ESR = 0.05OHM

PD FOR AUX CHANNELS (FOR NVIDIA)

PLACE BELOW GPU NEAR DISPLAY SECTION

Page Notes

GPU 3V3 VDD

GPU PLL VDD

ESR = 0.05OHM

PD FOR RSET



(NONE)


- =PP3V3_GPU_IFPX_PLLVDD

- =PP3V3_GPU_VDD33

- =PP1V8_GPU_IFPAB_IOVDD

- =PP1V8_GPU_DPLL

- =PP1V05_GPU_IFPEF_IOVDD

- =PP1V05_GPU_IFPCD_IOVDD

- =PP1V05_GPU_IFPAB_PLLVDD

- =PP1V05_GPU_DPLL

IFPAB PLLVDD

IFPAB IOVDD

DDC MAPPING

ESR = 0.05OHM

ESR = 0.05OHM

IFP EF IOVDD

IFPX PLLVDD

---------------------I2CA -> LVDS

I2CB -> IFPC

I2CC -> SSC CLK GEN

IFP CD IOVDD

82

82

82

82

82

82

51 101

51 101

82

82

82 100

82 100

MF 02010.1% 1/20W

PLACE_NEAR=U8000.J1:5MM

40.2K

0.1UF

0201

X5R-CERM

16V

10%

0.1UF

0201

X5R-CERM

16V

10%

1UF

402

X5R

25V

10%

0.1UF

0201

X5R-CERM

16V

10%

0.1UF

0201

X5R-CERM

16V

10%

1UF

402

X5R

25V

10%

10UF

603

X5R

10V

20%

1UF

0201

X5R

6.3V

20%

0.1UF

0201

X5R-CERM

16V

10%

0.1UF

0201

X5R-CERM

16V

10%

82

82

82

82

82

10K

PLACE_NEAR=U8000.J4:4MM

1%

1/20W

MF

201


201

MF

1/20W

1%

10K

86

86

100K

201

MF

1/20W

1%

100K

201

MF

1/20W

1%

PLACE_NEAR=U8000.AN2:5MM

1K

MF

1%1/20W

201

PLACE_NEAR=U8000.AD6:5MM

1K

201

MF

1/20W

1%

86

86

82

82

0603

CRITICAL

FERR-220-OHM-2A

CRITICAL0603

FERR-220-OHM-2A

FERR-220-OHM-2A

0603

CRITICAL

603

X5R-CERM

6.3V

10%

4.7UF

1UF

0201

X5R

6.3V

20%

1UF

X5R

6.3V

20%

0201

4.7K

201

MF

1/20W

1%

4.7K

201

MF

1/20W

1%

PLACE_NEAR=U8000.AF8:5MM

1K

201

MF

1/20W

1%

10UF

402

X5R

4V

20%

0201

X5R-CERM

10%

0.1UF

16V

10%

0201

X5R-CERM

16V

0.1UF1UF

0201

X5R

6.3V

20%

87 100

87 100

87 100

87 100

87 100

87 100

87 100

87 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

8 81 86 100

8 81 86 100

100K

201

MF

1/20W

1%

100K

201

MF

1/20W

1%

100K

201

MF

1/20W

1%

100K

201

MF

1/20W

1%

1/20W 2011%

10K

MF

PLACE_NEAR=U8000.AJ8:5MM

1K

201

MF

1/20W

1%

1UF

0201

X5R

6.3V

20% 10%

X5R-CERM

0201

16V

0.1UF10%

0.1UF

0201

X5R-CERM

16V

10UF

402

20%

X5R

4V

CRITICAL

FERR-220-OHM-2A

0603

10UF

402

4V

20%

X5R

CRITICAL0603

FERR-220-OHM-2A

0.1UF

0201

10%

X5R-CERM

16V

0201

X5R

6.3V

20%

1UF

1UF

0201

X5R

6.3V

20%

81

82

402

4.7UF20%4VX5R-1

X5R-14V20%4.7UF

402

X5R-14V20%4.7UF

402

X5R-14V20%4.7UF

402

X5R-CERM16.3V20%4.7UF

402X5R-CERM16.3V20%4.7UF

402

X5R-CERM26.3V20%22UF

0603

6 33 81 98

6 33 81 98

CRITICAL

BGA

NV-GK107

OMIT_TABLE

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 81 98

6 33 81 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

6 33 98

MF201

1%1/20W

10K

0.1UF

0201

X5R-CERM

16V

10%

1UF

402

X5R

25V

10%

10UF

603

X5R

10V

20%

CRITICAL

0603

330-OHM-1.2A

10UF

603

X5R

10V

20%

1UF

402

X5R

10%

25V

1UF

402

X5R

25V

10%

0.1UF

0201

X5R-CERM

16V

10%

0.1UF

0201

X5R-CERM

16V

10%

0.1UF

0201

16V

10%

X5R-CERM

0.1UF

0201

16V

10%

X5R-CERM

10UF

402

X5R

4V

20%

0.1UF

0201

X5R-CERM

16V

10%

0.1UF

0201

X5R-CERM

16V

10%

BGA

NV-GK107

OMIT_TABLE

82

82

82

82

82

82

82

82

82

82

82

82

82

82

82

82

82

82

82

82

82

KEPLER LVDS/DP/GPIO


GPU_SSC_SMB_DAT

GPU_SSC_SMB_CLK

PP3V3_GPU_IFPX_PLLVDD

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 MM


VOLTAGE=1.8V

PP1V8_GPU_IFPAB_IOVDD

IFPC_RSET


IFPEF_RSET


PP1V05_GPU_IFPAB_PLLVDD

VOLTAGE=1.05V

PP1V05_GPU_IFPEF_IOVDDVOLTAGE=1.05V


PP1V05_GPU_IFPCD_IOVDDMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 MM

VOLTAGE=1.05V

DP_EG_DDC_DATA

DP_EG_DDC_CLK

DP_EXTA_ML_C_N<1>

DP_EXTA_ML_C_P<2>

DP_EG_AUX_CH_P


=PP1V05_GPU_IFPAB_PLLVDD




DP_EXTA_ML_C_P<3>

DP_EXTA_ML_C_N<2>

DP_EXTA_ML_C_P<1>

DP_EXTA_ML_C_P<0>

IFPD_RSET

GPU_ROM_CS_L

GPU_ROM_SCLK

=PP1V05_GPU_IFPEF_IOVDD

DP_EG_AUX_CH_N

DP_EG_AUX_CH_N

DP_EG_AUX_CH_P

PP1V05_GPU_VID_PLLVDD

NC_GPU_ROM_CS_LMAKE_BASE=TRUE

GPU_ROM_CS_L

PP1V05_GPU_SP_PLLVDD

MAKE_BASE=TRUE

IFPAB_RSET


LVDS_EG_B_DATA_P<0>

LVDS_EG_B_DATA_P<1>

LVDS_EG_B_DATA_N<2>



DP_EXTA_ML_C_N<0>

DP_EXTA_ML_C_N<3>

PP1V05_GPU_IFPCD_IOVDD

PP1V05_GPU_IFPEF_IOVDD

GPU_ROM_SO

=PP3V3_GPU_VDD33

IFPAB_RSET

PP1V05_GPU_IFPAB_PLLVDD

=PP3V3_GPU_VDD33

=PP1V8_GPU_IFPAB_IOVDD


PP1V05_GPU_IFPEF_IOVDD

=PP1V05_GPU_IFPCD_IOVDD

LVDS_EG_A_CLK_P

LVDS_EG_B_DATA_N<1>



LVDS_EG_A_DATA_N<2>

LVDS_EG_A_DATA_N<1>

LVDS_EG_A_DATA_P<1>

LVDS_EG_B_DATA_N<0>

LVDS_EG_B_DATA_P<2>

LVDS_EG_A_CLK_N

LVDS_EG_A_DATA_P<2>

LVDS_EG_A_DATA_N<0>

LVDS_EG_A_DATA_P<0>

IFPD_RSET

GPU_TESTMODE

IFPC_RSET


DAC_AVDD






GPU_GPIO_0

LVDS_EG_DDC_CLK

GPU_SMB_DAT

GPU_TDIODE_P

MULTI_STRAP_REF

GPU_TDIODE_N

GPU_JTAG_TDI

GPU_JTAG_TMS

GPU_JTAG_TDO

GPU_JTAG_TCK

GPU_GPIO_1

GPU_GPIO_2

GPU_GPIO_5

GPU_GPIO_13

GPU_GPIO_14

GPU_GPIO_15

GPU_JTAG_TRST_L

GPU_GPIO_4

GPU_GPIO_6

GPU_MLS_STRAP4

GPU_GPIO_3

GPU_GPIO_10

GPU_GPIO_11

GPU_GPIO_12

PP1V05_GPU_VID_PLLVDD

IFPEF_RSET

PP1V05_GPU_IFPCD_IOVDD

GPU_GPIO_18

GPU_GPIO_20

GPU_GPIO_21

GPU_GPIO_7

GPU_GPIO_8

GPU_GPIO_9

=PP3V3_GPU_IFPX_PLLVDD






GPU_OSC_27M_XTALIN

GPU_OSC_27M_XTALOUT



LVDS_EG_DDC_DATA

GPU_SMB_CLK


VOLTAGE=1.05V


PP1V05_GPU_PLLVDD=PP1V05_GPU_PEX_PLLVDD

GPU_GPIO_19

GPU_GPIO_17

GPU_GPIO_16

PP1V05_GPU_SP_PLLVDD

PP1V05_GPU_PLLVDD

GPU_ROM_SI

GPU_MLS_STRAP2

GPU_MLS_STRAP3




=PP3V3_GPU_VDD33

GPU_MLS_STRAP1

GPU_MLS_STRAP0

GPU_OSC_27M_SSIN


GPU_OSC_27M_XTAL_BUFFOUT_R

U8000

L3

AL9

AL10

AM9

AK9

AP8

AG10

AP9

AN9

R4

R5

R7

R6

R2

R3

T4

T3

AG8 AM6

AN6

AP3

AN3

AN5

AM5

AL6

AK6

AJ6

AH6

AH8

AJ8

AG9

AJ9

AH9

AP6

AP5

AM7

AL7

AN8

AM8

AK8

AL8

AG3

AG2

AF6

AK1

AJ1

AJ3

AJ2

AH3

AH4

AG5

AG4

AF7

AF8

AK3

AK2

AG6

AM1

AM2

AM3

AM4

AL3

AL4

AK4

AK5

AG7

AN2

AB3

AB4

AC7

AD2

AD3

AD1

AC1

AC2

AC3

AC4

AC5

AB8

AD6

AF3

AF2

AC8

AE3

AE4

AF4

AF5

AD4

AD5

AG1

AF1

R86001

2

C86121

2

C86111

2

C86101

2

L8604

1 2

C86131

2

C86151

2

C86161

2

C86171

2

C86181

2

C86271

2

C86281

2

C86291

2

C86321

2

C86311

2

U8000

P6

M3

L1

M5

N3

M4

N4

P2

R8

M6

R1

P3

L6

P4

P1

P5

P7

L7

M7

N8

M1

M2

AM10

AM11

AP12

AP11

AN11

J1

AD8

H6

H4

H5

H7

AE8

J2

J7

J6

J5

J3

AK11

K4

K3

J8

K8

L8

M8

AD7

H3

H2

J4

H1

R8609

1 2

C86441

2

C86431

2

C86421

2

C86501

2

C86491

2

C86411

2

C86401

2

C86521

2

C86541

2

C86531

2

R86111

2

R86121

2

R86171

2

R86181

2

R86061

2

R86071

2

L8606

1 2

L8605

1 2

L8607

1 2

C86191

2

C86301

2

C86261

2

R86231

2

R86241

2

R86211

2

C86551

2

C86581

2

C86571

2

C86561

2

R86131

2

R86141

2

R86161

2

R86151

2

R8608

12

R86031

2

C86611

2

C86631

2

C86621

2

C86601

2

L8608

1 2

C86651

2

L8609

1 2

C86691

2

C86671

2

C86351

2

C86251

2

C86331

2

C86641

2

C86681

2

C86461

2

C86451

2

C86511

2

051-9585

3.0.0

86 OF 132

81 OF 105

81

81

81

81

81

81

81

81

81

81

8 81 86 100

8 81 86 100

81

81

81 83 81

81

81

81

7 75 81 82 83

81

81

7 75 81 82 83

7

81

81

81 81

6 33 81 98

81

81

81 6 33 81 98

6 33 81 98 81

81 7 83

81 83

81

7 75 81 82 83

OUT

BI

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NCNC

34A Y

34A Y

D

G S

IN

OUT

DSG

DSG

BIBI

INOUT


Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



IFPE

GPIOs

Strap values

-----

0x02

0x01

0x04

0x03

0x00

STUFF R8711 = 15KOHM FOR HYNIX 512MB

CONFIG STRAPS - MLPS

STRAP NOTES:

GP

GP

GPIOs

GP

GP

GPGP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

Native Func

GP

Native Func

GPU XTAL 27 MHz

JTAG signals

GPU internal Temp isolation

IFPD

IFPC

GPU overtemp masking

STUFF R8711 = 10KOHM FOR SAMSUNG 1GB

STUFF R8711 = 24.9KOHM FOR HYNIX 1GB - A die

CURRENTLY STUFFED FOR GK107-GTX (R8705)

GP

GP

STUFF R8711 = 5KOHM FOR HYNIX 1GB - M die

STUFF R8711 = 20KOHM FOR SAMSUNG 512MB

TBT HPD isolation

201MF1/20W5%

0

NO STUFF

1/20W5% MF 201

0

45 46 82

45

5%

1/20W

MF

201

10K

82 89

82 89

78 82

SM-2.5X2.0MM

27MHZ-15PPM-18PF

CRITICAL

81 100

81 100

201MF1/20W5%

0

0

5% 1/20W MF 201

NOSTUFF

8 89

201

MF

1/20W

1%

5.62K

NOSTUFF

81

81

1%

1/20W

MF

201

3.24K

NOSTUFF

81

1%

1/20W

MF

201

NOSTUFF

5.62K

81

81

201

1%

1/20W

MF

3.24K

NOSTUFF

81

1%

1/20W

MF

201

3.24K

NOSTUFF

81

81

1%

1/20W

MF

201

45.3K

1%

1/20W

MF

201

35.7K

1/20W

25.5K

OMIT_TABLE

201

1%

MF

1/20W

35.7K

NOSTUFF

1%

MF

201

NP0-C0G

201

25V

5%

18PF

25V

NP0-C0G

201

5%

18PF

1/20W

34.8K1%

MF

201

201

MF

1/20W

1%

45.3K

NOSTUFF

1%

1/20W

201

15.4K

MF

5.1K

201

MF

1/20W

1%

30K

1/20W

1%

201

MF

5%

MF

201

10K

1/20W

5%

1/20W

MF

201

10K5%

1/20W

MF

201

10K

NO STUFF

5%

1/20W

MF

201

10K

1/20W

1%

201

MF

10.2K

NOSTUFF

1%

1/20W

MF

201

10K

74LVC2G34SOT891

SOT89174LVC2G34

PLACE_NEAR=Y8700.3:4MM

MF1/20W5%201

0

SOD-VESM-HF

SSM3K15FV

MF

5%

1/20W

201

100K

MC74VHC1G08

SOT23-5-LF

45 46

82

SOT563

SSM6N37FEAPE

SSM6N37FEAPE

SOT563

201MF1/20W5%

10K

201MF5% 1/20W

10K

5% MF1/20W

0

NOSTUFF201

5%

1/20W

MF

201

10K

48 81

48 81

10K

201

MF

1/20W

1%


KEPLER GPIOS,CLK & STRAPS

RES, 10.2KOHM, 0201 FB_1G_SAMSUNGCRITICALR87111118S0019

FB_512_HYNIXCRITICALR8711RES,15KOHM, 02011118S0105

FB_1G_HYNIX_M_DIECRITICALR8711RES, 5.1KOHM, 02011118S0414

FB_512_SAMSUNGCRITICALR8711RES, 20KOHM, 02011118S0175

R8711RES, 24.9KOHM, 0201 FB_1G_HYNIX_A_DIECRITICAL1118S0230

GPU_JTAG_TRST_L

TP_GPU_JTAG_TCK

MAKE_BASE=TRUE

GPU_JTAG_TMS

GPU_JTAG_TCK

MAKE_BASE=TRUETP_GPU_JTAG_TMS

MAKE_BASE=TRUEDP_TBTSNK1_HPD_EG

GPU_GPIO_18

GPU_GPIO_17

GFXIMVP_VID<0>MAKE_BASE=TRUE

MAKE_BASE=TRUENC_GPU_GPIO_12

GPU_MLS_STRAP4

MAKE_BASE=TRUEGFXIMVP_VID<5>

EG_LCD_PWR_ENMAKE_BASE=TRUE

GPU_MLS_STRAP0

GPU_GPIO_6


GFXIMVP_PSI_R_LMAKE_BASE=TRUE

GPU_GPIO_15

MAKE_BASE=TRUEEG_BKLT_EN

GPU_GPIO_19

=PP3V3_GPU_VDD33

GPU_GPIO_16

SMC_GFX_OVERTEMP_R_L SMC_GFX_OVERTEMP

GPU_OSC_27M_XTALIN

GPU_GPIO_0

GPU_GPIO_11

GPU_ALT_VREFMAKE_BASE=TRUE

SMC_GFX_THROTTLE_R_LMAKE_BASE=TRUE

MAKE_BASE=TRUEGFXIMVP_VID<1>

GPU_GPIO_7

GPU_GPIO_8

GPU_GPIO_13

=PP3V3_GPU_VDD33


SMC_GFX_OVERTEMP_R_LMAKE_BASE=TRUE

=PP3V3_GPU_VDD33

MAKE_BASE=TRUENC_GPU_GPIO_15

DP_CA_DET_EGMAKE_BASE=TRUE

GPU_ROM_SCLK

=PP3V3_GPU_VDD33

=PP3V3_GPU_VDD33

NO_TEST=TRUENC_GPU_GPIO_7MAKE_BASE=TRUE

GPU_GPIO_4

=PP3V3_GPU_VDD33

GPU_MLS_STRAP1

GPU_JTAG_TDO

GPU_MLS_STRAP2

MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_GPIO_21_RSVD

NC_GPU_GPIO_20_RSVDNO_TEST=TRUEMAKE_BASE=TRUE

GPU_GPIO_12

GPU_GPIO_2

GPU_GPIO_9

GPU_OSC_27M_XTALOUT

GPU_GPIO_14

GPU_GPIO_21

GPU_GPIO_3

=PP3V3_S5_SMC

SMC_GFX_OVERTEMP_Q

GPU_GPIO_5

EG_BKLT_EN

=PP3V3_GPU_VDD33

=PP3V3_GPU_VDD33

SMC_GFX_THROTTLE_R_L

EG_LCD_PWR_EN

GPU_ROM_SI

GPU_MLS_STRAP3

GPU_GPIO_10

FBVDD_ALTVO

SMC_GFX_THROTTLE_L

GPU_SMB_CLK_R

DP_EG_HPDMAKE_BASE=TRUE

MAKE_BASE=TRUEDP_TBTSNK0_HPD_EG

MAKE_BASE=TRUEFBVDD_ALTVO

GPU_JTAG_TDI

PEX_CLKREQ_L_R EG_CLKREQ_IN_L

=PP3V3_GPU_VDD33

GPU_ROM_SO

=PP3V3_GPU_VDD33

GPU_RESET_L

SMC_GFX_OVERTEMP_R_L

GPU_GPIO_1


GPU_GPIO_20

GPU_SMB_DAT_R

=PP3V3_GPU_VDD33

GPU_SMB_DAT

=PP3V3_GPU_VDD33

GPU_SMB_CLK

GPU_OSC_27M_XTALOUT_R

=PP3V3_GPU_VDD33

DP_TBTSNK0_HPD DP_TBTSNK0_HPD_EG

DP_TBTSNK1_HPD DP_TBTSNK1_HPD_EG

SMC_GFX_OVERTEMP

=PP3V3_GPU_VDD33

TP_GPU_JTAG_TDO

MAKE_BASE=TRUETP_GPU_JTAG_TDI

MAKE_BASE=TRUE

R8798 1 2

R8799 1 2

R87971

2

Y8700

2 4

1 3

R8795 1 2

R8781

1 2

R87011

2

R87021

2

R87071

2

R87081

2

R87101

2

R87001

2

R87031

2

R87111

2

R87151

2

C87001

2

C87011

2

R87061

2

R87091

2

R87041

2

R87141

2

R87051

2

R87921

2

R87931

2

R87941

2

R87901

2

R87121

2

R87131

2

U8701

1

2

5

6

U8701

3

2

5

4

R8750

1 2

Q87013

12

R87521

2

U8702

3

2

1

4

5

Q8702

6

21

Q8702

3

54

R87531 2

R87541 2

R8780

1 2

R87961

2

R87551

2

051-9585

3.0.0

87 OF 132

82 OF 105

81

81

81

82

81

81

84

84

82 89

81

84

84

81

82 89

81

7 75 81 82 83

81

82

81

81

77

82

84

81

81

81

7 75 81 82 83

84

82

7 75 81 82 83

89

7 75 81 82 83

7 75 81 82 83

81

7 75 81 82 83

81

81

81

81

81

81

81

7 45 46

81

7 75 81 82 83

7 75 81 82 83

82

81

86

82

78 82

81

75

7 75 81 82 83

7 75 81 82 83

82

81

84

81

7 75 81 82 83

7 75 81 82 83

100

7 75 81 82 83

7 75 81 82 83

33 86

82

33 86

82

NCNC

OUT

OUT

OUT

OUT

GND

(9 OF 10)

GND

(8 OF 10)

GND_SENSE

NC

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_PLLVDD

NC

NC

NC

NC

NC

NC

NC

PEX_IOVDD

PEX_IOVDD

PEX_IOVDD

PEX_IOVDD

PEX_IOVDD

PEX_IOVDDNC

PEX_IOVDDQ

NC

NC

NC

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

BUFRST*

NC

NC

PEX_PLL_HVDD

VDD_SENSE

GND_OPT

GND_OPT

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

(2 OF 10)

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

Apple Inc.


124578

B

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



PEX IOVDD & PEX IOVDDQ

GPU SP PLLVDD

ESR = 0.05OHM



- =PP1V05_GPU_PEX_PLLVDD- =PP1V05_GPU_PEX_IOVDD

Page Notes

(NONE)

(NONE)


- =PP3V3_GPU_VDD33

PLACE XW8800 & XW8804 CLOSE TO C8803

EDP = 2000 MA

402

20%6.3V

4.7UF

X5R-CERM1

6.3V20%4.7UF

X5R-CERM1402

6.3V20%

402

4.7UF

X5R-CERM16.3V20%

402X5R-CERM1

4.7UF

6.3V10%

201X5R

0.1UF

6.3V20%

0201X5R

1UF

1%10K

1/20W

201MF

16V10%

0201X5R-CERM

0.1UF

16V10%

0201X5R-CERM

0.1UF

6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

6.3V20%

402X5R-CERM1

4.7UF

16V10%

0201X5R-CERM

0.1UF

16V10%

0201X5R-CERM

0.1UF

0603

FERR-220-OHM-2A

CRITICAL

5%100PF

CERM201

25V

100PF

CERM201

5%25V

5%

201

100PF

CERM25V

5%

CERM201

25V

100PF

X5R-CERM16.3V20%

402

4.7UF

6.3V20%1UF

0201X5R

6.3V10%

X5R

0.1UF

201

X5R

0.1UF

201

10%6.3V

201

0.1UF

X5R

10%6.3V

X5R6.3V

0201

20%1UF

1UF

X5R0201

20%6.3V

20%4VX5R402

10UF

402

4V20%

X5R

10UF

402

4.7UF

X5R-CERM16.3V20%

6.3VX5R

1UF

0201

20% 10%

X5R201

6.3V

0.1UF10UF

4V20%

402X5R

4V20%

402X5R

10UF

0201X5R6.3V20%1UF

201X5R

10%0.1UF

6.3V

SM

SM

SM

SM


SIGNAL_MODEL=EMPTY

78 101

201

1005%

MF

SIGNAL_MODEL=EMPTY

1/20W

1005%1/20W

201

SIGNAL_MODEL=EMPTY

MF

SIGNAL_MODEL=EMPTY SM


78 101

MF-LF1/10W5%

0

603

1/16W5%

0

402MF-LF

0603

20%6.3V

22UF

X5R-CERM2

GPUDEC:NORMAL

0603


GPUDEC:NORMAL

22UF

6.3V20%

0603X5R-CERM2

GPUDEC:NORMAL

6.3V

0603X5R-CERM2

20%22UF

GPUDEC:NORMAL

X5R-CERM26.3V20%22UF

0603

X5R4V20%

GPUDEC:EXP

22UF

402

20%

402

4VX5R

22UF

GPUDEC:EXP

402

20%4VX5R

22UF

GPUDEC:EXP

4V

GPUDEC:EXP

402X5R

20%22UF

OMIT_TABLE

BGANV-GK107

OMIT_TABLE

BGA

NV-GK107

BGA

NV-GK107

OMIT_TABLE


KEPLER PEX PWR/GNDS


P1V05_GPU_PEX_IOVDD_SNS_N

PP3V3_GPU_PEX_PLL_HVDD

VOLTAGE=3.3V


VOLTAGE=0VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MMGND_GPU_PEX_PLL_HVDD



VOLTAGE=1.05V

PP1V05_GPU_PEX_PLLVDD



GPU_BUFRSTN

GND_GPU_SP_PLLVDDVOLTAGE=0VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MM

PP1V05_GPU_SP_PLLVDDMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05V

GPUVCORE_SENSE_N

=PPVCORE_GPU

GPUVCORE_SENSE_P GND_GPU_PEX_PLLVDDMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MM

VOLTAGE=0V


=PP3V3_GPU_VDD33

P1V05_GPU_PEX_IOVDD_SNS_P

U8000

C7

D2

D31

D33

E10

E22

E25

E5

E7

F28

F7

G10

G13

G16

G19

G2

G22

G25

G28

G3

G30

G32

G33

G5

G7

K2

K28

K30

K32

K33

K5

K7

M13

M15

M17

M18

M20

M22

N12

N14

N16

N19

N2

N21

N23

N28

N30

N32

N33

N5

N7

P13

P15

P17

P18

P20

P22

R12

R14

R16

R19

R21

R23

T13

T15

T17

T18

T2

T20

T22

T28

T32

T5

T7

U12

U14

U16

U19

U21

U23

V12

V14

V16

V19

V21

V23

W13

W15

W17

W18

W20

W22

W28

Y12

Y14

Y16

Y19

Y21

Y23

AH11

U8000

AG11

AB12

C28

AB14

AB16

AB19

AB2

AB21

AB23

AB28

AB30

AB32

A2

AB5

AB7

AC13

AC15

AC17

AC18

AC20

AC22

AE2

AE28

A33

AE30

AE32

AE33

AE5

AE7

AH10

AH13

AH16

AH19

AH2

AA13

AH22

AH24

AH28

AH29

AH30

AH32

AH33

AH5

AH7

AJ7

AA15

AK10

AK7

AL12

AL14

AL15

AL17

AL18

AL2

AL20

AL21

AA17

AL23

AL24

AL26

AL28

AL30

AL32

AL33

AL5

AM13

AM16

AA18

AM19

AM22

AM25

AN1

AN10

AN13

AN16

AN19

AN22

AN25

AA20

AN30

AN34

AN4

AN7

AP2

AP33

B1

B10

B22

B25

AA22

B28

B31

B34

B4

B7

C10

C13

C19

C22

C25

U8000

L2

C16

W32

L5

P8

D23

D26

H31

T8

V32

AC6

AJ28

AJ4

AJ5

AL11

C15

D19

D20

AG19

AG21

AG22

AG24

AH21

AH25

AG13

AG15

AK27

AL27

AM28

AN28

AG16

AG18

AG25

AH15

AH18

AH26

AH27

AJ27

AH12

AG26

L4

C88021

2

C88221

2

C88271

2

C88261

2

C88291

2

C88281

2

R88001

2

C88341

2

C88351

2

C88331

2

C88321

2

C88311

2

C88371

2

C88361

2

L8804

1 2

C88191

2

C88201

2

C88211

2

C88181

2

C88231

2

C88241

2

C88251

2

C88141

2

C88081

2

C88131

2

C88071

2

C88121

2

C88061

2

C88051

2

C88161

2

C88171

2

C88151

2

C88091

2

C88101

2

C88111

2

XW8801

1 2

XW8802

1 2

XW8803

1 2

XW8800

1 2

R88101

2

R88111

2

XW8804

1 2

R88031 2

R88021 2

C88001

2

C88011

2

C88031

2

C88041

2

C88301

2

C88931

2

C88941

2

C88901

2

C88911

2

051-9585

3.0.0

88 OF 132

83 OF 105

7 77 83

75

7 81 83

7 77 83

7 77 83

81

7 76

7 81 83

7 75 81 82

NC

IN

IN

IMON

THRM

ISUM-

ISUM+

ISEN1

VSSP1

LGATE1A

UGATE1

BOOT1

PHASE1

ISEN2

LGATE1B

VSSP2

LGATE2

PHASE2

UGATE2

BOOT2

RTN

VSEN

FB

FB2

COMP

VW

VR_ON

DPRSLPVR

VID6

VID5

VID4

VID1

VID2

VID0

CLK_EN*

VR_TT*

PGOOD

VINVDD

NTC

RBIAS

VCCP

PSI*

VID3

PAD

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

NCNC

D

S

G

D

S

G

S

D

G

S

D

G

Apple Inc.


124578

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



R8971 AND R8974 CANNOT BE STUFFED AT THE SAME TIME

Stuff option for GPIO control

R8981 = PSI Control

R8982 = VID6 control (old connection)

on all DIDT nets

(GND_GFXIMVP_AGND)

R8982 = DPSLP Control

GPU VCORE VID STRAPS

DEFAULT = 0.9 V

353S3679

25A max per phase

Need to confirm

Line Width & DIDT

68UF

CRITICAL


16V20%

CRITICAL

68UF


20%16V

2V20%

CASE-B2-SM

CRITICAL

270UF

TANT2V20%

TANT

270UF

CASE-B2-SM

CRITICAL

CASE-B2-SMTANT

270UF20%2V

CRITICAL

270UF

CASE-B2-SM

CRITICAL

2V20%

TANT

10K

201

1/20WMF

1%

NOSTUFF

10K

201

1/20WMF

1%

NOSTUFF

10K

201

1/20WMF

1%

NOSTUFF

10K

201

1/20WMF

1%

NOSTUFF

10K

201

1/20WMF

1%10K

201

1/20WMF

NOSTUFF

1%10K

201

1/20WMF

1%

10K

201

1/20WMF

1%10K

201

1/20WMF

1%10K

201

1/20WMF

1%10K

201

1/20WMF

NOSTUFF

1%10K

201

1/20WMF

NOSTUFF

1%10K

201

1/20WMF

1%10K

201

1/20WMF

1%

CRITICAL

68UF20%


16V

SM PLACE_NEAR=U8900.41:1mm

5%

201

1/20WMF

100K

5%

201

1/20WMF

100K

NOSTUFF

92

5%

201

1/20WMF

0

5%

201

1/20WMF

0

NOSTUFF

82

TQFNISL62882C

CKPLUS_WAIVE=PdifPr_badTerm


SM

1/10W5%0

603MF-LF

402

0.22UF

10VCERM

10%

5%

MF-LF

0

603

1/10W

0.22UF

CERM

10%

402

10V

SM


SIGNAL_MODEL=EMPTY

201

1/20WMF

1.001%

1/20WMF

1%1K

201

SIGNAL_MODEL=EMPTY

201

SIGNAL_MODEL=EMPTY

1/20WMF

1%10K

SIGNAL_MODEL=EMPTY

201

1/20WMF

1%10K

MF

1%

201

1/20W

SIGNAL_MODEL=EMPTY

10K

1/20W

201MF

1%

SIGNAL_MODEL=EMPTY

1.001K1%

SIGNAL_MODEL=EMPTY

201MF

1/20W

SIGNAL_MODEL=EMPTY

1%

MF1/20W

201

10K

1.24K

1%1/20W

201MF NOSTUFF

201

1/20WMF

1.15K

1%

201

0.1UF

NOSTUFF

X5R6.3V10%

201X5R6.3V10%0.1UF

201CERM

5600PF

10V10%

X5R6.3V20%

0.22UF

0201

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

6.3V

0201X5R

20%

0.22UF


10%25VX5R402

1UF

1

5%

MF1/20W

201

5%0

201MF1/20W

201

6.3VX5R

0.1UF10%

SIGNAL_MODEL=EMPTY

49

83 101

83 101

0201

SIGNAL_MODEL=EMPTY

1000PF10%16VX7R-CERM

0201X7R-CERM

16V10%

SIGNAL_MODEL=EMPTY

1000PF

0201X7R-CERM

1000PF

16V10%

1%49.9

NOSTUFF

MF1/20W

201

201

10V

5600PF

NOSTUFF

CERM

10%

1/20W

201MF

3011%

SIGNAL_MODEL=EMPTY201

1/20WMF

49.91%

16VX7R-CERM0201

330PF10%

5%

NOSTUFF

22PF

0201NP0-C0G-CERM

50V

82 84

82 84

82 84

82 84

82 84

82 84

92

201

1/20WMF

1%

147K

201

1/20WMF

1%499

NOSTUFF

5%

201

1/20WMF

0

NOSTUFF

CRITICAL

PIMB063T-SM

0.2UH-41A-2.4MOHM

CRITICAL

PIMB063T-SM

0.2UH-41A-2.4MOHM

10%

X5R25V

402

1UF10%

X5R25V

1UF

402

CRITICAL

MF

1%

0612

1W

0.00075

CRITICAL

1W1%

0.00075

MF0612

X7R201

3300PF

10V10%

SIGNAL_MODEL=EMPTY

201

1/20WMF

8.06K1%

16V

CRITICAL

SM

15UF20%

TANT

5%

201

1/20WMF

NOSTUFF

100K

5%

201

1/20WMF

100K

201

1/20WMF

1%5.11K

1%10K

201

1/20WMF

SIGNAL_MODEL=EMPTY

10%25VX7R0402

0.22UF


X7R-CERM

560PF

0201

50V10%

68UF

POLY-TANT

CRITICAL

20%16V

CASE-D2E-SM

201

30.1K

1%1/20WMF

X5R402

10%25V

1UF


10%

X7R-CERM50V

0.001UF

0402

0.001UF

50VX7R-CERM

10%

0402

CRITICAL

649135PBFDIRECTFET_S3C

649135PBF

CRITICAL

DIRECTFET_S3C

DIRECTFET-SAIRF6802SDTRPBF

CRITICAL


CRITICAL

GFX IMVP VCore Regulator

SYNC_DATE=01/18/2012SYNC_MASTER=D2_MLB_2P


GFXIMVP_BOOT2DIDT=TRUE


=PP5V_S3_GFXIMVP

PPVIN_S0_GFXIMVP_RVOLTAGE=12.8VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

GFXIMVP_UGATE2GATE_NODE=TRUE

SWITCH_NODE=TRUE

GFXIMVP_PHASE2

GATE_NODE=TRUE

GFXIMVP_LGATE2

MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0V

GFXIMVP_VSSP2

GFXIMVP_ISEN2

GFXIMVP_UGATE1GATE_NODE=TRUE

SWITCH_NODE=TRUE

GFXIMVP_PHASE1GATE_NODE=TRUE

GFXIMVP_LGATE1

GFXIMVP_ISUMP



GND_GFXIMVP_AGND

GPUVCORE_SENSE_P

GFXIMVP_BOOT1

GFXIMVP_BOOT2_RDIDT=TRUEMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

VOLTAGE=1.05V

PPVCORE_S0_GFX_PH1


GFXIMVP_FB2

GFXIMVP_COMP

GFXIMVP_NTC

GFXIMVP_ISUMP

GFXIMVP_ISNS2_P

PPVCORE_S0_GFX_PH2VOLTAGE=1.05VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

GFXIMVP_ISNS2_N

GFXIMVP_VID<3>

GFXIMVP_VID<6>

GFXIMVP_VID<1>

GFXIMVP_DPSLP_EN

GFXIMVP_FB_SNS_R

GFXIMVP_VID<1>

GFXIMVP_VID<2>

GFXIMVP_VID<4>

GFXIMVP_PSI_L

GFXIMVP_ISNS1_NGFXIMVP_ISNS1_P

GFXIMVP_FB_GND_R

GFXIMVP_VR_TT_L

GFXIMVP_PSI_L

GFXIMVP_VID<6>

GFXIMVP_VID<5>

GFXIMVP_VID<2>

GFXIMVP_VID<0>

GFXIMVP_DPSLP_EN

GFXIMVP_VID<0>

GFXIMVP_PSI_R_L

GFXIMVP_VID<5>

GFXIMVP_PSI_L

GFXIMVP_VID<6>

GFXIMVP_DPSLP_EN

GFXIMVP_COMP_R


GFXIMVP_VID<4>

GFXIMVP_VID<3>

GFXIMVP_VW

GFXIMVP_ISUMP_C

GFXIMVP_VR_TT_L

GFXIMVP_BOOT1_R

MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMDIDT=TRUE

GFXIMVP6_IMON

GPUVCORE_SENSE_N

GPUVCORE_PGOOD

=GPUVCORE_EN

GFXIMVP_RBIAS

GFXIMVP_ISUMN_RGFXIMVP_ISNS2_N

GFXIMVP_ISUMP

GFXIMVP_ISUMN

GFXIMVP_ISEN1

GFXIMVP_ISUMN

GFXIMVP_FB

GFXIMVP_ISNS1_N

PPVCORE_S0_GFX_PH1_L


VOLTAGE=1.05V


VOLTAGE=5V


PP5V_S0_GFXIMVP_VDD


GFXIMVP_ISUMN

=PPVIN_S0_GFXIMVP

=PPVCORE_S0_GFX_REG

=PPVIN_S0_GFXIMVP

VOLTAGE=0V

GFXIMVP_VSSP1



C8920 1

2

C8921 1

2

C89621

2

C89631

2

C89641

2

C89611

2

R89431

2

R89441

2

R89461

2

R89451

2

R89481

2

R89491

2

R89471

2

R89521

2

R89531

2

R89561

2

R89551

2

R89541

2

R89511

2

R89501

2

C8922 1

2

XW8900

12

R89711

2

R89721

2

R89811 2

R89821 2

U8900

19

30

40

7

39

8

9

18

11

10

14

15

23

24

26

5

1

21

28

2

3

13

41

20

29

25

16

31

32

33

34

35

36

37

17

38

4

12

22

27

6

XW8930

12

R89301

2

C8930 1

2

R89601

2

C8965 1

2

XW8931

12

R89641

2

R89631

2

R89611

2

R89621

2

R89311

2

R89341

2

R89331

2

R89321

2

R89101 2

R89111 2

C8912 1

2C89111

2

C89101

2

C8966

1 2

C8931

1 2

C8902 1

2

R89011 2

R89001

2

C89131

2

C89141

2

C8915 1

2

C89191

2

R89171

2

C89411

2

R8915 1

2

R89161

2

C89171

2

C8918 1

2

R89401 2

R89701

2

R89831 2

L8930

1 2

L8960

1 2

C8923 1

2

C8924 1

2

R8999

1 2

3 4

R8998

12

34

C89401

2

R8913 1

2

C8925 1

2

R89741

2

R89731

2

R89141

2

R89121

2

C89001

2

C8916 1

2

C8926 1

2

R89181 2

C8901 1

2

C8927 1

2

C8928 1

2

Q8931

1 2 8 7

4

3 5 6

Q8961

1 2 8 7

4

3 5 6

Q8930

5 6

1

4

Q8930

7 8

2

3

051-9585

3.0.0

89 OF 132

84 OF 105

7

84

84

101 84 101

82 84

84

82 84

84

84

84 101 101

84

84

84

82 84

82 84

82 84

84

84

84

84

7 84

82 84

84

84 101

84

84

84

84 101

84

7 84

7

7 84

7 84

IN

SYM_VER-1

SYM_VER-1

NC

NC

GND THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



100K pull-ups are for

LCD (LVDS) INTERFACE

Place close to the connector

Panel has 2K pull-ups

no-panel case (development).

Place close to the connector

518S0852

0.001UF

402X7R50V10%

402-1

16VX5R

10%0.1UF

SM

FERR-250-OHM

CRITICAL

MF-LF1/16W

5%10K

402

MF-LF

100K5%1/16W

402402

100K

1/16W5%

MF-LF

89

DLP11S90-OHM-100MA

CRITICAL

CRITICAL

90-OHM-100MADLP11S

X7R402

10%50V

0.001UF

0.1UF

16VX5R402-1

10%

MFET-2X2-8IN

FPF1009

CRITICAL

16VX5R402-1

0.1UF10%

10UF

603X5R

20%6.3V

50VCERM

0.001UF

402

10%

CRITICAL

F-RT-SM20525-140E-01


LVDS Display Connector

PPVOUT_S0_LCDBKLT

LED_RETURN_1

LVDS_CONN_A_CLK_F_P

LVDS_CONN_B_DATA_N<1>

LED_RETURN_2

LED_RETURN_3

LED_RETURN_4

LED_RETURN_5

LED_RETURN_6

LVDS_CONN_B_CLK_F_P

LVDS_CONN_B_CLK_F_N

LVDS_CONN_B_DATA_P<2>




LVDS_CONN_A_CLK_F_N


LVDS_CONN_A_DATA_P<2>

LVDS_CONN_A_DATA_N<1>





LVDS_DDC_DATA

LVDS_DDC_CLK


VOLTAGE=3.3V

PP3V3_SW_LCD

=PP3V3_S0_DDC_LCD

PP3V3_SW_LCD_UFMIN_LINE_WIDTH=0.5 mm


LCD_PWR_EN

=PP3V3_S5_LCD

LVDS_CONN_A_CLK_P

LVDS_CONN_A_CLK_N

LVDS_CONN_B_CLK_N

LVDS_CONN_B_CLK_P

C9010 1

2

C9001 1

2

L9000

1 2

R90941

2

R90111

2

R90101

2

L9010

1 2

34

L9011

1 2

34

C9002 1

2

C90091

2

U9000

6

1

7

2

3

4

5

C90111

2

C90121

2

C9000 1

2

J9000

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

45

46

47

48

49

5

50

51

52

6

7

8

9

051-9585

3.0.0

90 OF 132

85 OF 105

6 8 104

6 90

6 100

6 86 100

6 90

6 90

6 90

6 90

6 90

6 100

6 100

6 86 100

6 86 100

6 86 100

6 86 100

6 100

6 86 100

6 86 100

6 86 100

6 86 100

6 86 100

6 86 100

6 86 100

6 86

6 86

6

7

7

86 100

86 100

86 100

86 100

VCC

C1

C2

C3

C4

A1B1

A2B2

A3B3

A4B4

GND THRM

IN

IN

OUT

IN

IN

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

HPD_2

DAUX2-

DAUX2+

DDC_CLK1

DDC_DAT1

DDC_CLK2

DDC_DAT2

HPD_1

GPU_SEL

XSD*

AUX-

AUX+DAUX1-

DAUX1+

DDC_CLK

DDC_DAT

GND

HPDIN

VDD

BI

OUT

BI

BI

IN

BI

BI

IN

BI

BI

BI

BI

IN

OUT

OUT

IN

D

GS

OUT

IN

IN

Y

B

A

Y

B

A

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



DP AUX, DDC, & HPD muxing to IG/EG

(DP_EXTA_HPD)

All emulated LVDS outputs require this termination

LVDS Transmitter Termination

LVDS DDC MUX

(DP_EXTA_HPD)TBT/DP HOT PLUG IN

CRITICAL

SN74LV4066A

QFN189

89

6 85

81

17

81

17

6 85

0.1UF

402

10VCERM

20%5%

402

1/16WMF-LF

20K

402MF-LF

5%1/16W

20K

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

89 100

357

PLACE_NEAR=U9600.A5:7mm1%

MF1/20W

201

357


1%

MF1/20W

201357

PLACE_NEAR=U9600.C5:7mm1%

MF1/20W

201

PLACE_NEAR=U9600.A1:7mm1%

357

MF1/20W

201

PLACE_NEAR=U9600.A3:7mm

357

1%

MF1/20W

201

357

PLACE_NEAR=U9600.C9:7mm

1%

MF1/20W

201

1%1/20W

201MF

357


1%


357

MF1/20W

201


357

1%

MF1/20W

201


357

1%

MF1/20W

201

PLACE_NEAR=U9600.B10:7mm1%

1/20W

201MF

357

PLACE_NEAR=U9600.A9:7mmMF201

357

1%1/20W

357

1%

MF1/20W

201


89 100

89 100

89 100


357

1%

MF1/20W

201


357

201

1%

MF1/20W


357

1%

MF1/20W

201

85 100

85 100

6 85 100

6 85 100

6 85 100

6 85 100

6 85 100

6 85 100

85 100

85 100

6 85 100

6 85 100

6 85 100

6 85 100

6 85 100

6 85 100

100K

402MF-LF1/16W

5%

CRITICAL

CBTL03062BGA

87

87

87 100

87 100

402CERM10V20%0.1UF

402

10V20%

CERM

0.1UF

8

8

81

81

8 95

8 95

8 81 100

8 81 100

89

1/16WMF-LF

5%

402

100K

8

82

89

402

10K5%

1/16WMF-LF

T29_DP_HPD:MUX_GMUX

402

0

5%

MF-LF1/16W

T29_DP_HPD:MCU_GMUX

402MF-LF

100K5%1/16W

SOD-VESM-HF

T29_DP_HPD:MCU_GMUX

SSM3K15FV

10V20%

CERM

0.1UF

402

T29_DP_HPD:ALL_OR

89

46 87

87

CRITICAL T29_DP_HPD:ALL_OR74LVC2G32GTSOT833

74LVC2G32GTSOT833

T29_DP_HPD:ALL_OR

402

1/16W5%20K

MF-LF

5%

402MF-LF1/16W

20K


Muxed Graphics Support

SYNC_MASTER=K92_MLB

DP_TBTSNK1_HPD

DP_TBTSNK0_HPD

=PP3V3_S0_GMUX

TBT_HOTPLUG_DET_OR

DP_EXTA_DDC_CLK

DP_EXTA_AUXCH_C_N

DP_EXTA_DDC_DATA

DP_A_EXT_HPD

DP_IG_DDC_DATA

DP_IG_DDC_CLK

LVDS_IG_DDC_DATA

LVDS_EG_DDC_DATA

LVDS_IG_DDC_CLK

LVDS_EG_DDC_CLK

LVDS_DDC_SEL_IG

LVDS_DDC_SEL_EG

=PP3V3_S0_LVDSDDCMUX

LVDS_DDC_DATA

LVDS_DDC_CLK

=PP3V3_GPU_LVDS_DDC

LVDS_A_CLK_P

LVDS_A_CLK_N


LVDS_A_DATA_N<0>

LVDS_B_DATA_P<1>

LVDS_B_DATA_N<1>

LVDS_B_DATA_P<2>

LVDS_B_DATA_N<2>

LVDS_B_CLK_N



LVDS_CONN_B_CLK_N


LVDS_A_DATA_N<2>

LVDS_A_DATA_P<2>


LVDS_CONN_B_CLK_P

LVDS_B_DATA_P<0>

DP_IG_AUX_CH_P


LVDS_B_DATA_N<0> LVDS_CONN_B_DATA_N<0>




LVDS_B_CLK_P

LVDS_A_DATA_N<1>

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_CONN_A_CLK_N



LVDS_CONN_A_CLK_P

DP_IG_AUX_CH_N

DP_MUX_SEL_EG

DP_EG_DDC_CLK

DP_EG_HPD

DP_HOTPLUG_DET

DP_EXTA_AUXCH_C_P

=PP3V3_S0_GMUX

DP_EG_AUX_CH_P

DP_EG_DDC_DATA

DP_MUX_EN

DP_EG_AUX_CH_N

DP_EXTA_HPD

DP_IG_HPD

=PP3V3_S0_DPMUX

R92711

2

R92701

2

U92701

4

8

11

2

3

9

10

13

5

6

12

7 15

14

C9270 1

2

R92731

2

R92721

2

R92571 2

R92521 2

R92551 2

R92501 2

R92471 2

R92421 2

R92451 2

R92401 2

R92371 2

R92321 2

R92351 2

R92301 2

R92271 2

R92221 2

R92251 2

R92201 2

R92051

2

U9220

1

2016

17

13

14

2

12

93

11

8

19

5

10

7

4

6 18

15

C92301

2

C92201

2

R92041

2

R92021

2

R920612

R92811

2

Q9280

3

12

C9210 1

2

U9210

5

6

4

8

3

U9210

1

2

4

8

7

051-9585

3.0.0

92 OF 132

86 OF 105

33 82

33 82

7 86 89

7

7

7 86 89

7

OUT

OUT

OUT

OUT

IN

IN

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

THMPADGND

VDD

OUT_D0P

OUT_D0N

OUT_D1P

OUT_D2P

OUT_D1N

OUT_D3P

OUT_D2N

OUT_D3N

AC_AUXP

AC_AUXN

OUT_HPD

CEXT

IN_D0P

IN_D0N

IN_D1N

IN_D2N

IN_D3P

IN_SDA

IN_AUXP

IN_AUXN

IN_HPD

I2C_CTL_EN

I2C_ADDR0

I2C_ADDR1

SCL_CTL

SDA_CTL

REXT

AUXDDC_OFF

PD

CA_DET

IN_SCL

IN_D3N

IN_D2P

IN_D1P

OUT_AUXN_SDA

OUT_AUXP_SCL

IN

OUT

OUT

OUT

VDD

PIO1_8/CT16B1_CAP0

PIO1_7/TXD

XTALIN

PIO1_4/AD5/WAKEUP

PIO1_6/RXD

SWDIO/PIO1_3/AD4

R/PIO1_2/AD3

R/PIO1_1/AD2

R/PIO1_0/AD1RESET#/PIO0_0

PIO0_1/CLKOUT

SWCLK/PIO0_10/SCK/CT16B0_MAT2

PIO0_9/MOSI/CT16B0_MAT1

PIO0_8/MISO/CT16B0_MAT0

PIO0_2/SSEL/CT16B0_CAP0

R/PIO0_11/AD0

PIO0_7/CTS#

PIO0_6/SCK

PIO0_4/SCL

PIO0_5/SDA

VSSTHRMPAD

BI

OUT

IN

IN

IN

IN

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

BI

BI

IN

OUT

BI

OUT

BI

IN

NC

IN

OUT

IN

BI

AUX-

AUX+

DOUT_1+

DOUT_1-

NC

GNDTHMPAD

GPU_SEL

HPD_2

AUX2-

AUX2+

DIN2_1-

DIN2_1+

DIN2_0-

HPD_1

AUX1-

AUX1+

DIN1_1-

DOUT_0-

DIN1_0+

DIN1_0-

DIN1_1+

HPD_IN

DOUT_0+

DIN2_0+

VDD

AUX_SEL

IN

Apple Inc.


124578

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D

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C

B

A


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Parade (pin is 5V-tolerant).

pin even when VCC=0V per

PS8301 has internal

~150K pull-down on PD

pin. Okay to drive this

Port A MCU

AUXCH Snoop Port, used by

(TBT_A_LSX_P2R)

(TBT_A_LSX_R2P)

R2P = Receptacle to Plug

DP A Super-Driver

Must be V3P3 output from U9410

I2C Addr:

DP/TBT A Low-Speed MUX

(D9360/D9361)

(D9382/D9383)

caps to improve layout.

P/N-swapped after AC

(IPD)

TBT signals are

(IPD)

PS8301 I2C Addresses:

(DP_SDRVA_AUXCH_P)

0x26/0x27 (Wr/Rd)

(IPD)

(IPU)

(All 4 D’s)

D9372/D9373:

vendor recommendation.

(OD)

Mobiles use S4 WAKE#

=TBT_WAKE_L:

=DP_A_BIAS.

specific guidelines for

See Bill C. for layout-

SWDIO

(OD)

P2R = Plug to Receptacle

on layout. 4.99K is

Biasing

TBT A High-Speed Signals

(IPD)

(IPU)

D9364/D9365:

(D9360.2)

(D9382/D9383)

(D9361.2)

(D9364.2)

used for this part.

(D9365.2)

(D9372/D9373)

TBT: TX_0

TBT: TX_1

0 0 0x96/0x97

(C9372.1&2)

TBT Path

R9319 value depends

(All 4 D’s)

(OD)

DP Path Biasing

PS8301 during training.

(OD)

(IPD)

Must be 3.3V DP A port power

SWCLK

10-pin programming header it should be used.

please make accessible. If project has space for

R9330 provides pads for programming/debug of MCU,

IC supports input

(C9373.1&2)

(C9370/C9371)

(C9380/C9381)

(C9383.1&2)

(C9383.1&2)

(DP_SDRVA_ML_N<3>)

(DP_SDRVA_ML_P<3>)

(DP_SDRVA_AUXCH_N)

high while Vcc = 0V.

Desktops use PCIe WAKE#

(DP_SDRVA_ML_N<1>)

(DP_SDRVA_ML_P<1>)

(DP_SDRVA_HPD)

If GPU uses common pins for AUX_CH

and DDC, alias nets together at GPU.

A1 A0 Addr (W/R)

0 1 0xB6/0xB7

1 0 0x94/0x95

1 1 0xB4/0xB5

Note: Other Parade

devices use 96/B6,

so only 94/B4 are

33 98

33 98

88 98

MF-LF1/16W

1K

402

5%

4.99K1%

1/16WMF-LF402

86

NO STUFF

1K5%

1/16WMF-LF402

MF-LF1/16W

1K5%

402

10VCERM

0.1UF20%

402

0.1UF

402

20%10VCERM

PLACE_NEAR=U9310.11:2 mm

402-LF

20%6.3VCERM

2.2UF

6 33 98

6 33 98

6 33 98

6 33 98

33 98

33 98

81 100

81 100

81 100

81 100

81 100

81 100

81 100

81 100

48

48

0.1uF 40216V

X5R10%

16V0.1uF

10%X5R 402

86 100

86 100

PS8301TQFN40GTR-A2QFN

CRITICAL

402-LFCERM

20%2.2UF

6.3V

0.1UF X5R10%

2016.3V

87 89 X5R16V

0.1uF10%

402

4020.1uF10%X5R

16V

18

17

33

LPC1112A

OMIT_TABLE

HVQFN25

CRITICAL

48

33

48

33

1/16W5%1K

MF-LF402

10K

1/16W

402

5%

MF-LF

10V

0.1UF20%

402CERM

33

88

10V20%0.1UF

402CERM

402

1M

1/16WMF-LF

5%

10K

402

1/16WMF-LF

5%

402MF-LF

5%0

1/16W

OMIT

35 88 10K

MF-LF402

5%1/16W

05%

402

1/16W

SDRV_PD

MF-LF

88 98

88 98

88 98

88 98

88 98

88 98

SIGNAL_MODEL=EMPTY

CRITICAL

BAR90-02LRHGND_VOID=TRUE

TSLP-2-7

SIGNAL_MODEL=T29PIN

TSLP-2-7BAR90-02LRHGND_VOID=TRUE

CRITICAL

SIGNAL_MODEL=T29PIN

TSLP-2-7

GND_VOID=TRUE

BAR90-02LRH

CRITICAL

TSLP-2-7BAR90-02LRH

CRITICAL

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

CRITICAL

GND_VOID=TRUETSLP-2-7BAR90-02LRH

SIGNAL_MODEL=EMPTY

TSLP-2-7

GND_VOID=TRUE

BAR90-02LRH

CRITICAL

SIGNAL_MODEL=T29PIN


TSLP-2-7

CRITICAL

SIGNAL_MODEL=T29PIN


SIGNAL_MODEL=EMPTY

CRITICAL

TSLP-2-7

0.47UF

GND_VOID=TRUE

201

20% 4VCERM-X5R-1

1.5K5%

201MF1/20W

GND_VOID=TRUE

1.5KGND_VOID=TRUE

MF1/20W5%201

GND_VOID=TRUE

1.5K MF 2011/20W5%

GND_VOID=TRUE

1/20W5%

1.5K

201MF

GND_VOID=TRUE 4V20%

GND_VOID=TRUE0.47UF

201CERM-X5R-1

0.47UF

GND_VOID=TRUE

4V20%

201CERM-X5R-1

GND_VOID=TRUE 0.47UF

GND_VOID=TRUE

4V20%

201CERM-X5R-1

GND_VOID=TRUE

CERM-X5R-1201

20% 4V0.47UF

20%CERM-X5R-1

4V

2010.47UF

GND_VOID=TRUE

0.47UF CERM-X5R-1201

20% 4V

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE 201

20% 4V

GND_VOID=TRUE

0.47UF CERM-X5R-1

MF

GND_VOID=TRUE

5%201

1/20W

1.5K MF

GND_VOID=TRUE

5%201

1/20W

1.5K

88 98

88 98

1.5KGND_VOID=TRUE 1/20W

201MF5%

GND_VOID=TRUE

1.5K

2011/20W

MF5%

305%

2011/20W

MF

1/20W201

5%

30

MF

1/20W201MF

5%

30

1/20W

30

201MF5%

MF5%

1.5K

2011/20W

2011/20W

MF5%

1.5K

2011/20W5%

MF

1.5K MF 2011/20W5%

1.5K

SC70

CRITICAL

74LVC1G04DBDCK

16V

0.1UF10%

X5R402

270

1/20WMF

201

5%

201MF1/20W5%270

8

8

8

8

201

1/20WMF

5%100K

402CERM

0.1UF

10V20%

CERM10V

402

20%0.1UF

201

1/20WMF

100K5%

88 98

88 98

46 86 87

88 98

88 98

8

6.3V10%201X5R0.1UF

X5R0.1UF10% 6.3V

201

X5R6.3V2010.1UF

10%

6.3V201X5R

10%0.1UF

0.1UF6.3V201

10%X5R

6.3V10%X5R0.1UF 201

X5R 2016.3V10%

0.1UF

0.1UF6.3V201

10%X5R

X5R 2016.3V10%

0.1UF

201X5R0.1UF6.3V10%

X5R10%

0.1UF6.3V201

1M1/20W201MF

5%

1/20W5%MF 201

1M

88 98

88

51

402

1/16WMF-LF

5%5%1/16W

51

402MF-LF

402

1/16WMF-LF

5%1K

1K

402

1/16WMF-LF

5%

88

8 87

86

86

20%X5R

6.3V02010.22UF

0.22UF20%X5R

6.3V0201

X5R6.3V0201

20%0.22UF

20%X5R

6.3V02010.22UF

HVQFN

CRITICAL

CBTL04DP081

OMIT_TABLE

SIGNAL_MODEL=T29DP_MUX

16 23

SYNC_DATE=06/20/2011SYNC_MASTER=J31_WILL

Thunderbolt MUXing A

DP_EXTA_AUXCH_C_N

DP_EXTA_ML_C_N<3>

DP_SDRVA_AUXCH_P

DP_SDRVA_ML_R_N<0>

DP_SDRVA_ML_R_N<2>

DP_SDRVA_ML_N<3>

DP_SDRVA_HPD

TBT_A_RSVDP

DP_EXTA_AUXCH_P

=TBT_A_BIAS

PP3V3_SW_TBTAPWRDP_A_PWRDWN

DP_A_CA_DET

TBT_A_ML_P<3>

TBT_LSEO<1>

VOLTAGE=3.3VDP_A_BIAS0

=PP3V3_S0_DPSDRVA

TBT_R2D_C_P<1>

DP_SDRVA_ML_R_P<0>

DP_EXTA_ML_N<3>

DP_SDRVA_ML_C_N<2>

DP_EXTA_ML_P<2>

TBT_D2R_P<0>

TBT_R2D_C_P<0>

TBT_A_BIAS0PVOLTAGE=3.3V

TBT_D2R_N<0>

TBT_R2D_C_N<0>

DP_SDRVA_ML_C_P<2>

=TBT_A_BIAS

TBT_A_HPD

TBT_LSEO<0>

TBT_LSOE<0>

=I2C_TBTAMCU_SDA

=I2C_TBTAMCU_SCL

DP_EXTA_ML_N<1>

TBT_PWR_REQ_L

TBT_A_HV_EN

TBT_A_CONFIG1_RC

DPSDRVA_CEXT

=TBT_WAKE_L

TBT_A_ML_C_P<2>

DP_EXTA_ML_P<3>

DP_EXTA_ML_C_P<0>

DP_EXTA_ML_P<1>

DP_EXTA_ML_C_P<3>

DP_EXTA_ML_C_P<1>

DP_EXTA_ML_C_N<2> DP_EXTA_ML_N<2>

DP_EXTA_ML_P<2>

DP_EXTA_ML_C_N<0> DP_EXTA_ML_N<0>

TBT_D2R_C_P<1>

VOLTAGE=3.3VTBT_A_BIAS2P

TBT_D2R_C_N<1>

TBT_R2D_N<0>

TBT_A_BIAS0NVOLTAGE=3.3V

TBT_R2D_N<1>

VOLTAGE=3.3VTBT_A_BIAS2N

VOLTAGE=3.3VDP_A_BIAS2

DP_EXTA_ML_P<1>

DP_EXTA_AUXCH_C_P

TBT_R2D_P<0>

TBT_D2R_C_P<0>

TBT_A_UC_ADDR

=PP3V3_S0_DPSDRVA

TBT_A_UC_ADDR

TBT_LSOE<1>

=DP_A_BIAS

TBT_A_ML_C_N<2>

TBT_A_ML_C_P<0>

TBT_A_ML_C_N<0>

TBT_R2D_P<1>

TBT_D2R_C_N<0>

DP_EXTA_AUXCH_N

DPSDRVA_I2C_CTL_EN

DP_EXTA_AUXCH_N

DP_SDRVA_AUXCH_C_N

DP_EXTA_HPD

DP_EXTA_ML_P<3>

DP_EXTA_ML_N<0>

DP_EXTA_AUXCH_P

DP_EXTA_DDC_CLK

DP_EXTA_DDC_DATA

DP_A_EXT_HPD

TBT_R2D_C_N<1>

TBT_D2R_N<1>

DP_EXTA_ML_P<0>

DP_EXTA_ML_N<2>

DP_EXTA_ML_N<3>

DP_SDRVA_ML_C_P<0>

DP_SDRVA_ML_C_N<0>

DP_A_CA_DET

DP_SDRVA_ML_P<0>

TBT_D2R_P<1>

DP_SDRVA_ML_N<0>

DP_SDRVA_ML_P<2>

TBT_A_ML_N<3>

PP3V3_SW_TBTAPWR

TBT_A_LSX_R2P

TBT_A_HV_EN_R

TBT_A_CONFIG2_RC

TBT_A_ML_P<1>

DP_A_EXT_HPD

TBT_A_ML_N<1>

DP_SDRVA_ML_N<2>

DP_EXTA_ML_C_P<2>

DP_EXTA_ML_C_N<1>

DP_EXTA_ML_P<0>

DP_EXTA_ML_N<1>

DP_A_PWRDWN

TBT_D2R1_BIASN

TBT_D2R1_BIASP

TBT_A_LSX_P2R

DP_SDRVA_AUXCH_N

DP_SDRVA_ML_R_P<2>

DP_A_EXT_AUXCH_N

DP_A_EXT_AUXCH_P

TBT_A_RSVDN

DP_SDRVA_ML_P<3>

DP_SDRVA_ML_N<1>

DP_SDRVA_ML_P<1>

DP_SDRVA_ML_C_N<3>

DP_SDRVA_ML_C_N<1>

DP_SDRVA_ML_C_P<3>

DP_SDRVA_AUXCH_C_P

DP_SDRVA_ML_C_P<1>

=PP3V3_S0_DPSDRVA

=I2C_DPSDRVA_SDA

DP_AUXCH_ISOL

=I2C_DPSDRVA_SCL

DPSDRVA_I2C_ADDR0

DP_A_PWRDWN_R

DPSDRVA_REXT

DPSDRVA_I2C_ADDR1

R93121

2

R93191

2

R93111

2

R93101

2

C93111

2

C93121

2

C9319 1

2

C9308 1 2

C9309 1 2

U9310

19

20

39

32

11

6

33

36

35

26

15

16

2

1

5

4

8

7

10

9

3

14

13

17

18

29

30

27

28

24

25

22

23

31

34

12

38

37

41

21

40

C9310 1

2

C9367 1 2

C9369 1 2

C9368 1 2

U9330

2

7

8

9

10

11

12

13

20

23

24

6

15

16

17

18

1

14

19

25

5 22

3 21

4R93351

2

R9336 1

2

C9330 1

2

C93311

2

R93391

2

R93381

2

R93301

2

R93341 2

R93182

1

D9364 A K

D9373 A K

D9372 A K

D9365 A K

D9360 A K

D9382 A K

D9383 A K

D9361 A K

C9370 1 2

R93721 2

R9373

1 2

R93821 2

R9383

1 2

C9373 1 2

C9372 1 2

C9371 1 2

C9381 1 2

C9380 1 2

C9382 1 2

C9383 1 2

R9385 1 2

R9384 1 2

R9375 1 2

R9374 1 2

R9355 1 2

R9354 1 2

R9350 1 2

R9351 1 2

R9360 1 2

R9361 1 2

R9364 1 2

R9365 1 2

U93592

3

5

4

C93591

2

R93521

2

R93531

2

R93981

2

C9390 1

2

C9391 1

2

R93991

2

C9366 1 2

C9363 1 2

C9362 1 2

C9300 1 2

C9301 1 2

C9302 1 2

C9303 1 2

C9304 1 2

C9305 1 2

C9306 1 2

C9307 1 2

R9309 1 2

R9308 1 2

R93921

2

R93931

2

R93961

2

R93971

2

C9364 1 2

C9365 1 2

C9360 1 2

C9361 1 2

U9390

18

19

14

15

7

6

32

30

31

26

27

24

25

22

23

2

1

5

4

21

28

10

17

13

8

33

3912

16

20

29

051-9585

3.0.0

93 OF 132

87 OF 105

11

98

98

98

98

87 100

8 87

87 88 87

87 89

8

7 87

98

87 100

87 100

87 100

87 100

87 100

87 100

87 100

87 100

98

98

8

87 100

98

87

7 87

87

98

87 100

87 100

98

87 100

87 100

87 100

46 86 87

87 100

87 100

87 100

6 98

6 98

6 98

87 88

6 98

87 100

87 100

87

98

98

98

98

98

98

98

98

98

98

7 87

OUT

OUT

IN

IN

BI

IN

OUT

OUT

BI

BI

BI

GND

GND

ML_LANE0N

ML_LANE0P

ML_LANE1P

GND

ML_LANE1N

GND

GND

DP_PWR

ML_LANE2PAUX_CHP

RETURN

HOT_PLUG_DETECT

AUX_CHN

ML_LANE3P

ML_LANE3N

ML_LANE2N

CONFIG1

CONFIG2

BOT ROW TOP ROWTH PINS SM PINS

SHIELD PINS

OUT

OUT

OUT

BI

IN

IN

IN

IN

IN

IN

IN ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

RSVD

GND THRM

OUT

VHV

ISET_V3P3

RSVD

V3P3

PAD

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




IHVS0 1120mA 1090mA 1170mA (12W minimum)

IHVS3 125mA 124mA 126mA (1W minimum)

DP Source must pull

greater than or equal

to 100K (DPv1.1a).

IHVS3 890mA 830mA 930mA (assumes 3S - 9-12.6V, 1W minimum)

3.3V/HV Power MUXV3P3 must be S4 to support

wake from Thunderbolt devices.

Nominal Min Max

IV3P3 1100mA 1030mA 1200mA

12V: See

below

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

Thunderbolt Connector A

<RHVS3> <RV3P3><RHVS0>

ILIM = 40000 / RISET

Nominal Min Max

For 12V systems:

TBT: LSX_R2P/P2R (P/N)

For J9400 TBT SMT pads

TBT: TX_1

DP Dir

Thunderbolt: Unused

TBT Dir

(0-20V)

on AC-coupled signals.

470k R’s for ESD protection

High: 2.0 - 5.0V

down HPD input with

Sink HPD range:

Low: 0 - 0.8V

20V Max

DP Dir

(Both C’s)

TBT Dir

TBT: TX_0

(0-20V)

(3, 5, 17 & 19):(Both C’s)

50V

0.01UF10%

X7R402

87 98

87 98

87 98

87 98

87 98

87 98

0.01UF10%50VX7R402

MF-LF402

12

1/16W5%

0.01UF10%

402X7R50V

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

1K5%

MF1/20W

201

1K

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

5%

MF1/20W

201

5%25V

30PF

0201C0G-CERM

30PF5%25VC0G-CERM0201

402

1/16WMF-LF

5%100K

650NH-5%-0.430MA-0.52OHM

SIGNAL_MODEL=EMPTY

CRITICAL

0603

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

CRITICAL

GND_VOID=TRUE0603

650NH-5%-0.430MA-0.52OHM

87 98

87 98

87 98

87 98

87 98

GND_VOID=TRUE

CRITICAL

DSPLYPRT-M97-1F-RT-THSM

GND_VOID=TRUEGND_VOID=TRUEGND_VOID=TRUE

20%

603X5R6.3V

10UF0.1UF

10V20%

CERM402

0.1UF20%10V

402CERMX5R-CERM-1

22UF20%6.3V

603

CRITICALCRITICAL

6.3V

100UF

POLY-TANTCASE-B2-SM

20%

1M5%

1/16WMF-LF

402 402

1/16W

1M

MF-LF

5%

402CERM

10%50V

330PF10%

CERM

330PF

50V

402

2.2K5%

MF1/20W

201GND_VOID=TRUE

1/20W5%

MF201

2.2K

GND_VOID=TRUE

0603

FERR-120-OHM-3A

87

87

87

87 98

X7R

10%50V

603-1

0.1UF

CRITICAL

GND_VOID=TRUE

BAR90-02LRH

SIGNAL_MODEL=T29PIN

TSLP-2-7

SIGNAL_MODEL=T29PIN

BAR90-02LRH TSLP-2-7

CRITICALGND_VOID=TRUE

201

1/20WMF

5%

GND_VOID=TRUE

470K

201

1/20WMF

470K

GND_VOID=TRUE

5%

GND_VOID=TRUE

20%

201CERM-X5R-1

4V0.47UF

CERM-X5R-10.47UF

GND_VOID=TRUE

4V

201

20%

87 98

87 98

20%

201CERM-X5R-1

4V

GND_VOID=TRUE

0.47UF

20%

201CERM-X5R-1

4V0.47UF

GND_VOID=TRUE

201

1/20WMF

GND_VOID=TRUE

5%470K

201

1/20WMF

GND_VOID=TRUE

5%470K

8

8

10%50VX7R402

0.01UFGND_VOID=TRUE

GND_VOID=TRUE

402X7R50V10%

0.01UF

35 87

74

74

1%

402

1/16WMF-LF

TBTHV:P15V

22.6K

MF-LF1/16W

402

1%22.6K

TBTHV:P15V

402

36.5K

MF-LF1/16W1%

X7R603-1

0.1UF

50V10%

10%25V

X5R-CERM0603

4.7UF

402MF-LF

1%1/16W

TBTHV:P15V

22.6K

1%

402

1/16WMF-LF

22.6K

TBTHV:P15V

QFN

CRITICAL

CD3210A0RGP

RES,MTL FILM,1/16W,384K,1,0402,SMD,LF R9410114S0464 1 TBTHV:P12V

TBTHV:P12VRES,MTL FILM,1/16W,36.5K,1,0402,SMD,LF114S0368 R94111

Thunderbolt Connector A

SYNC_DATE=06/14/2011SYNC_MASTER=T29_REF

DP_A_EXT_AUXCH_P

TBT_A_CONFIG2_RC

TBT_A_D2R1_AUXCH_P

DP_A_EXT_AUXCH_N

TBT_A_CONFIG1_RC

TBT_A_HPD

TBT_A_ML_P<0>

TBT_A_ML_N<0>

TBT_A_ML_C_P<0>

TBT_A_ML_C_N<0>

TBT_A_ML_N<1>

TBT_A_ML_P<1>


TBTACONN_1_CMIN_LINE_WIDTH=0.38 MM

TBT_A_ML_C_P<2>

TBT_A_ML_C_N<2>

TBTACONN_7_CMIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MMVOLTAGE=3.3V

VOLTAGE=15VMIN_NECK_WIDTH=0.20 MM

PP3V3RHV_SW_TBTAPWRMIN_LINE_WIDTH=0.38 MM

TBT_D2R_C_P<0>

TBT_A_ML_N<3>

TBTACONN_20_RCMIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MMVOLTAGE=18V

TBT_A_ML_N<2>

TBT_A_ML_P<2>

TBT_A_ML_P<3>

TBT_D2R_C_N<0>

TBTAPWRSW_ISET_S0_R

TBTAPWRSW_ISET_S3_R

=PP3V3_S4_TBTAPWRSW

TBTAPWRSW_ISET_V3P3

=PPHV_SW_TBTAPWRSW PPHV_SW_TBTAPWRMIN_LINE_WIDTH=0.38 MM

VOLTAGE=15VMIN_NECK_WIDTH=0.20 MM

TBT_A_HV_EN

=TBT_S0_EN

=TBTAPWRSW_EN

TBTAPWRSW_ISET_S0


VOLTAGE=3.3V

PP3V3_SW_TBTAPWR


TBTAPWRSW_ISET_S3

TBT_A_D2R1_AUXCH_N

TBT_A_BIAS1PVOLTAGE=3.3V

TBT_D2R_C_N<1>

TBT_D2R_C_P<1>

VOLTAGE=3.3VTBT_A_BIAS1N

J9400

18

16

4

6

20

1

78

1314

2

2122

5

3

11

9

17

15

12

10

19

L9400

1 2

C9400 1

2

C9402 1

2

R94011 2

C94011

2

R94941

2

R94951

2

C9498 1

2

C94991

2

R94411

2

L9498

12

L9499

12

C94861

2

C9485 1

2

C94811

2

C9480 1

2

C9487 1

2

R94521

2

R94511

2

C9494 1

2

C94951

2

R94981

2

R94991

2

C9410 1

2

D9499 A K

D9498 A K

R94701

2

R94711

2

C9471 1 2

C9470 1 2

C9472 1 2

C9473 1 2

R94731

2

R94721

2

C9405

1 2

C9406

1 2

R94101

2

R94111

2

R94121

2

C94111

2

C9415 1

2

R94131

2

R94141

2

U9410

5

1 2 3 4

13

11 10

9

8

12

14

1516

17

21

19

20

18

6

7

051-9585

3.0.0

94 OF 132

88 OF 105

98

98

98

98

98

7

7

87

98

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

OUT

IN

IN

IN

IN

D

SG

D

SG

D

SG

D

SG

IN

IN

IN

IN

IN

IN

IN

IN

IN

PB14B

PB15A

PB15B

PB16A

PB17A

PT19A

PT16A

PB18B

PT7A

PR11B

PR24A

PR24B

PR14A

PR14B

PR12B

PR12A

PR11A

PR10B

PR10A

PR6A

PR6B

PR7A

PR7B

PR8A

PR9A

PR9B

PR8B

PT28A

PT8B

PT8A

PT7B

PT9A

PT9B

PL25A

PL25B

PL15A

PL14B

PL14A

PL12B

PL11B

PL12A

PL9A

PL8A

PL8B

PL6B

PL7B

PL7A

PL6A

PB28B

PB27A

PB28A

PB27B

PB26A

PB7B

PB7A

VCCIO2

PT17B

PT17A

PT16B

PT15A

PT14B

PT20B

PT19B

CFG0

GND GNDIO0

GNDIO1

GNDIO2

GNDIO3

GNDIO4

GNDIO5

GNDIO6

GNDIO7

LRC_GNDPLL

LRC_VCCPLL

PB18A

PB19A

PB19B

PB20A

PB20B

PL2A

PL2B

PR2A

PR2B

PT14A

PT15B

PT18B

PT20A

TCK

TDI

TDO

TMS

TOE

ULC_GNDPLL

ULC_VCCPLLVCCAUX

VCCIO0

VCCIO1

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7 VCCJ

PT18A

VCC

PT28B

PB26B

PL11A

PL10B

PL10A

PL9B

PB16B

PL15B

PB14A

PB17B

BANK6

BANK2

BANK0

BANK5

BANK7

BANK4

BANK3

BANK1

(OD)

(OD)

IN

IN

OUT

IN

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Required Pulldowns

(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)

LVDS Receiver Termination

Required Pullups

GMUX CPLD

(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)

81 89 100

86

87

86 100

86 100

86 100

86 100

86 100

86 100

86 100

402

4V20%4.7UF

X5R-1

86 100

86 100

86 100

89

89

86 100

86 100

86 100

86 100

86 100

86 100

2011/20W MF

100K5%

2011/20W MF5%

NO STUFF100K

2011/20W MF

10K5%

2011/20W MF

10K5%

8

2011/20W MF5%

10K

2011/20W MF5%

1K

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

1%PLACE_NEAR=U9600.H12:5mm100

MF1/20W 201

SIGNAL_MODEL=EMPTYSIGNAL_MODEL=EMPTY

1%100 PLACE_NEAR=U9600.G13:5mm

MF1/20W 201

SIGNAL_MODEL=EMPTY


MF1/20W 201

SIGNAL_MODEL=EMPTY

1%100 PLACE_NEAR=U9600.F12:5mm

MF1/20W 201

8 82

SIGNAL_MODEL=EMPTY

1%100 PLACE_NEAR=U9600.B2:5mm

MF1/20W 201

SIGNAL_MODEL=EMPTY

1%100 PLACE_NEAR=U9600.E14:5mm

MF1/20W 201

SIGNAL_MODEL=EMPTY

100 PLACE_NEAR=U9600.D13:5mm1% MF1/20W 201

SIGNAL_MODEL=EMPTY

1001%PLACE_NEAR=U9600.J12:5mm

MF1/20W 201

SIGNAL_MODEL=EMPTY


MF1/20W 201

SIGNAL_MODEL=EMPTY

1%PLACE_NEAR=U9600.E1:5mm100

MF1/20W 201

SIGNAL_MODEL=EMPTY

1%PLACE_NEAR=U9600.E3:5mm100

MF1/20W 201

SIGNAL_MODEL=EMPTY


MF1/20W 201

SIGNAL_MODEL=EMPTY

1001%PLACE_NEAR=U9600.G2:5mm

MF1/20W 201

SIGNAL_MODEL=EMPTY

1%100 PLACE_NEAR=U9600.H3:5mm

MF1/20W 201

NO STUFF

MF1/20W

5%10K

201

SILK_PART=GMUX_RST

24

17 89 95

4.7K5%

201

1/20WMF

0402

FERR-220-OHM

0402

FERR-220-OHM

8

5%100K

MF201

1/20W

5%0

NO STUFF

1/20W

201MF

17 89 95

4.7K5%

MF1/20W

201

23 45 74 92

CRITICAL

1909782

GMUX_JTAG_CONN

M-RT-SM

402

0

5%

MF-LF1/16W

402

0

5%

MF-LF1/16W

2011/20W MF

1K5%

17 89 95

5%

201

1/20WMF

4.7K

4.7K5%

201

1/20WMF

MF1/20W

201

5%4.7K

1/20W MF

10K5% 201

1/20W MF

10K5% 201

17 89 95

1K

1/20W

201

5%

MF

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

SOT563

SOT563

SSM6N37FEAPE

SSM6N37FEAPE

SOT563

17 89 95

17 89 95

17 89 95

17 89 95

17 89 95

17 89 95

17 89 95

17 89 95

17 89 95

XP25-5CSBGA

OMIT

CRITICAL

17 89 95

24

8

24 96

6 16 45 47 96

6 16 45 47 96

6 16 45 47 96

6 16 45 47 96

10K

201

NO STUFF

MF

1%1/20W

6 16 45 47 96

85 89

82

8

89 92

89 92

89 92

89 92

8 89

86 89

86

0.1UF10%

201X5R6.3V

10%

201X5R6.3V

0.1UF

86 89

86 89

6 89 90

8 90

1%

MF1/20W

NO STUFF

10K

201

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

10%

201X5R6.3V

0.1UF 0.1UF10%

201X5R6.3V

0.1UF10%

201

6.3VX5R

0.1UF10%

201X5R6.3V

NO STUFF

10K

201MF

1/20W1%

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

10K1%

MF1/20W

201

0.1UF10%

201X5R6.3V

0.1UF10%

201X5R6.3V

82

8

82

8

81 89 100

81 89 100

81 89 100

1%

MF1/20W

10K

201

81 89 100

81 89 100

81 89 100

81 89 100

81 89 100

81 89 100

81 89 100

81 89 100

81 89 100

81 89 100

Graphics MUX (GMUX)

SYNC_MASTER=K91_MARY SYNC_DATE=08/03/2010

EG_CLKREQ_IN_L

TP_GMUX_PL15B

LVDS_EG_A_DATA_N<1>

LVDS_EG_A_DATA_P<1>

LVDS_EG_A_DATA_P<0>

DP_HOTPLUG_DET

DP_A_CA_DET

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_N<1>

LVDS_IG_A_CLK_P

DP_MUX_SEL_EG

LVDS_DDC_SEL_IG

LCD_BKLT_EN

DP_MUX_SEL_EG

LPC_CLK33M_GMUX

LCD_BKLT_PWM

JTAG_GMUX_TDO

GMUX_CFG0

EG_BKLT_EN

JTAG_GMUX_TDI

LVDS_EG_B_DATA_P<2>

LVDS_EG_B_DATA_P<1>

LVDS_EG_B_DATA_P<0>

PP3V3_S0_GMUX_LRC_VCCPLL



MIN_LINE_WIDTH=0.4 mmPP3V3_S0_GMUX_ULC_VCCPLL

ALL_EG_PGOOD

LVDS_IG_B_DATA_N<2>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>

TP_GMUX_PL6B

LVDS_IG_B_DATA_P<1>

LVDS_IG_A_DATA_P<1>

LPC_FRAME_L

JTAG_GMUX_TDO

EG_RESET_L

LVDS_DDC_SEL_EG

=PP3V3_S0_GMUX

EG_PWRSEQ_EN

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_N<2>

GMUX_DEBUG_RESET_L

LVDS_A_CLK_P

LVDS_A_CLK_N

LVDS_B_CLK_N

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<2>

=PP3V3_S0_GMUX

GMUX_INT

LVDS_IG_B_DATA_P<2>

LVDS_B_DATA_N<1>

LVDS_A_DATA_N<2>

LVDS_A_DATA_N<1>

EG_RAIL3_EN

LCD_PWR_EN

LVDS_B_CLK_P

=PP3V3_S3_GMUX

LVDS_EG_A_CLK_P

LVDS_EG_A_DATA_N<0>

LVDS_EG_B_DATA_P<2>

LVDS_EG_B_DATA_N<2>

EG_RAIL4_EN

JTAG_GMUX_TMS

EG_RAIL2_EN

EG_RAIL1_EN

LVDS_EG_B_DATA_N<2>

LVDS_EG_A_DATA_N<2>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_DATA_P<1>

LVDS_IG_B_DATA_P<0>

IG_BKLT_EN

LVDS_EG_A_DATA_N<0>

LVDS_B_DATA_N<2>

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<0>

LVDS_B_DATA_P<1>

IG_LCD_PWR_EN

LVDS_EG_B_DATA_N<1>

LVDS_EG_A_DATA_P<2>

JTAG_GMUX_TDO

LVDS_IG_B_DATA_P<0>

TP_GMUX_PL14B

LPC_AD<1>

LVDS_EG_A_CLK_N

LPC_AD<2>

LPC_RESET_L

LVDS_A_DATA_N<0>

LVDS_B_DATA_N<0>

LVDS_EG_B_DATA_P<1>

LVDS_A_DATA_P<0>

JTAG_GMUX_TDI

LVDS_IG_A_DATA_N<2>

TP_GMUX_PT20A

EG_PWRSEQ_EN

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<2>

LVDS_EG_B_DATA_N<0>

EG_LCD_PWR_EN

LVDS_EG_A_DATA_P<0>

LVDS_EG_A_DATA_P<1>

LVDS_IG_A_CLK_N

LVDS_EG_B_DATA_N<1>

LVDS_EG_A_CLK_P

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<0>

LVDS_IG_A_DATA_N<2>

LVDS_IG_B_DATA_P<1>

LVDS_EG_B_DATA_P<0>

LVDS_EG_A_DATA_P<2>

LVDS_EG_B_DATA_N<0>

LVDS_EG_A_DATA_N<2>

EG_RAIL2_EN

=PP3V3_S0_GMUX

EG_RAIL3_EN

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_N<1>

LVDS_EG_A_CLK_N

LVDS_EG_A_DATA_N<1>

JTAG_GMUX_TCK

JTAG_GMUX_TMS

LPC_AD<0>

LVDS_IG_A_CLK_N

LVDS_MUX_SEL_EG

=GMUX_PCIE_RESET_L

LPC_AD<3>

TP_GMUX_PT20B

TP_GMUX_PT32A

TP_GMUX_PT32B

JTAG_ISP_TDI

JTAG_GMUX_TDI

T29_JTAG_FET

JTAG_ISP_TDO

JTAG_GMUX_TDO

ALL_SYS_PWRGD

GMUX_S3_PD_EN

GMUX_S3_PD_GND

=PP3V3_T29_JTAG

JTAG_GMUX_TCK

EG_RAIL4_EN

GMUX_PL6A

EG_RAIL1_EN

DP_MUX_EN

=PP3V3_S0_GMUX

LCD_PWR_EN

DP_CA_DET_EG

EG_CLKREQ_OUT_L

EG_RESET_L

LVDS_DDC_SEL_IG

LVDS_DDC_SEL_EG

LCD_BKLT_PWM

GMUX_TOE

JTAG_GMUX_TDI

PP3V3_S0_GMUX_R


=PP1V8_S0_GMUX

=PP1V2_S0_GMUX

GMUX_DEBUG_RESET_L

PP1V8_S0_GMUX_RMIN_LINE_WIDTH=0.4 mm


R96471

2

R9641 1

2

R96461

2

R9640 1

2

R96451

2

C96001

2

U9600K1

J1

B8

C6

C12

C13

E13

M14

N10

N6

P3

M2

C1

E2

M11

P11

P4

N4

N3

M4

P5

M5

P6

M6

P7

M7

N7

N8

P9

N9

P10

M10

P12

P13

N12

P14

P2

N2

F3

G2

H2

G3

H1

H3

L1

L3

K3

L2

N1

P1

B1

B2

C2

D3

D1

E1

D2

E3

F1

G1

G12

G13

H13

H12

H14

J12

L14

M13

N14

N13

A14

B14

D12

D13

D14

E14

E12

F12

F14

G14

B6

C7

A6

A7

C8

C9

A8

B9

A9

C10

B10

A10

A11

B12

B13

A13

A2

A3

A1

B3

C5

A5

K14

L13

K13

L12

K2

B4

A4

B11

C4

J3

J13

N11

P8

C11

J2

J14

M8

B5

B7

A12

C14

F13

M12

M9

M3

N5

M1

C3

F2

K12

C96041

2

C96051

2

C96061

2

C96071

2

C96081

2

C96091

2

C96101

2

C96111

2

C96211

2

C96221

2

C96121

2

C96131

2

C96231

2

C96241

2

C96141

2

C96251

2

C96151

2

C96161

2

C96261

2

C96271

2

C96171

2

C96281

2

C96291

2

R9693 1 2

R9691 1 2

R9683 1 2

R9682 1 2

R9681 1 2

R9680 1 2

C96301

2

C96311

2

R9666 1 2

R9665 1 2

R9664 1 2

R9663 1 2

R9656 1 2

R9662 1 2

R9661 1 2

R9660 1 2

R9655 1 2

R9651 1 2

R9652 1 2

R9653 1 2

R9654 1 2

R9650 1 2

R96791

2

R96711

2

L9621

1 2

L9620

1 2

R96761

2

R96751

2

R96781

2

J9600

7

8

1

2

3

4

5

6

R96001 2

R96101 2

R9684 1 2

R96721

2

R96731

2

R96741

2

R9685 1 2

R9686 1 2

R96051 2

Q96053

54

Q96056

21

Q96076

21

Q96073

54

051-9585

3.0.0

96 OF 132

89 OF 105

86 89

86 89

6 89 90

89

89

81 89 100

81 89 100

81 89 100

6

89

8 89

86 89

7 86 89

89

17 89 95

17 89 95

7 86 89

89 92

85 89

7

89 92

18 89

89 92

89 92

81 89 100

81 89 100

17 89 95

17 89 95

17 89 95

17 89 95

17 89 95

81 89 100

89

89

8

81 89 100

81 89 100

17 89 95

81 89 100

81 89 100

17 89 95

17 89 95

17 89 95

17 89 95

81 89 100

81 89 100

7 86 89

17 89 95

17 89 95

81 89 100

81 89 100

8 89

18 89

8

8

8

8 19

89

8 19

89

7

8 89

7 86 89

89

7

7

89

VDDIO VINVLDO

SW_0

SW_1

FB

OUT3

OUT2

OUT1

OUT4

OUT5

OUT6

GND_SW

GND_S

GND_L

GND_SW

VSYNC

ISET

FILTER

FSET

SCLK

PWM

SDA

FAULT

EN

IN

IN

D

SG

D

SG

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

BI

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




Addr: 0x58(Wr)/0x59(Rd)

FDC638APZ

see spec for others

ON THE SENSOR PAGE

AND PPBUS_SW_BKL

0.715 A (EDP)

43 mOhm @4.5V

P-TYPE

PPBUS S0 LCDBkLT FET

I_LED=369/Riset

Fpwm=9.62kHz

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

CHANNEL

MOSFET

measurement on LED strings.

10.2 ohm resistors for current

THERE IS A SENSE RESISTOR BETWEEN

LOADING

RDS(ON)

(EEPROM should set EN_I_RES=1)

I_LED=22.7mA


*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS

1/16W5%

402MF-LF

10K

402

5%

10K

MF-LF1/16W

10%10UF

CRITICAL

50V

1210-1X5R

PLACE_NEAR=D9701.2:5mm

PLACE_NEAR=D9701.2:3mm

10UF10%

CRITICAL

50V

1210-1X5R

CRITICAL

33UH-1.8A-110MOHM

1217AS-2SM

33

1/16W5%

402MF-LF

25-BUMP-MICRO

LP8550

CRITICAL

24

8 89

402

1/16W1%

MF-LF

147K

3AMP-32V-467

603-HF

BOTTOM

402

1/16W1%

MF-LF

301K16V10%

402X5R

0.1UF

SSOT6-HF

FDC638APZ_SBMS001

CRITICAL


SM

SOT563SSM6N15AFE

SSM6N15AFESOT563

1/16W5%

402MF-LF

0

X5R25V10%

805

10UF

CRITICAL

PLACE_NEAR=L9701.1:4mm PLACE_NEAR=L9701.1:3mm

25V10%

402X5R

0.1UF


220PF

50V10%

402X7R-CERM

CRITICAL

SOD-123

RB160M-60G


1/16W5%

402MF-LF

0

BKLT:PROD

BOTTOM

PLACE_NEAR=U9701.E1:10mm

1/16W5%

402MF-LF

0

BKLT:PROD

BOTTOM


1/16W5%

402MF-LF

0

BKLT:PROD

BOTTOM


6 85

6 85

1/16W5%

402MF-LF

0

6 85

6 85

6 85

6 85

1/16W5%

402MF-LF

0

BKLT:PROD

PLACE_NEAR=U9701.D5:10mm

BOTTOM

1/16W5%

402MF-LF

0

BKLT:PROD

BOTTOM



BOTTOM402

BKLT:PROD

1/16W5%

MF-LF

0

MF-LF1/16W1%

402

100K

1/16W1%

402MF-LF

301K

25V10%

603-1X5R

1UF


16V10%

402X5R

0.1UF


SM

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)


CERM16V10%

402

0.01UF

6 89

CERM50V5%

402

33PF

1/16W1%

402MF-LF

16.2K

48

48

1/16W1%

402MF-LF

90.9K

R9720,R9721,R97223103S0198 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM BKLT:ENG

R9717,R9718,R97193103S0198 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM BKLT:ENG

SYNC_DATE=03/21/2011SYNC_MASTER=J31_KIRAN

LCD Backlight Driver


PPVOUT_SW_LCDBKLT

VOLTAGE=50V



BKL_ISEN3

=PPBUS_SW_BKL

PPVOUT_SW_LCDBKLT_FB


VOLTAGE=40V

=PP3V3_S0_BKL_VDDIO

=PP5V_S0_BKL


SWITCH_NODE=TRUE

PPBUS_SW_LCDBKLT_PWR_SW

VOLTAGE=40V

DIDT=TRUE

BKL_VSYNC_R



VOLTAGE=0V

GND_BKL_SGND

MIN_NECK_WIDTH=0.075 mm BKL_SCLMIN_LINE_WIDTH=0.075 mm

BKL_PWM

BKL_EN

TP_BKL_FAULT

PLACE_SIDE=BOTTOM


BKL_ISET


BKL_FSET


=PPBUS_S0_LCDBKLTMIN_LINE_WIDTH=0.4 mmPPBUS_S0_LCDBKLT_FUSED


MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mmLED_RETURN_5


LED_RETURN_1





LCDBKLT_EN_DIV

BKL_ISEN6


BKL_ISEN5


BKL_ISEN4


BKL_ISEN2


BKL_ISEN1


VOLTAGE=12.6VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.4 mmPPBUS_SW_LCDBKLT_PWR

=I2C_BKL_1_SCL

MIN_LINE_WIDTH=0.075 mmBKL_SDAMIN_NECK_WIDTH=0.075 mm=I2C_BKL_1_SDA


BKL_FLTRMIN_NECK_WIDTH=0.075 mmMIN_LINE_WIDTH=0.075 mm

LCD_BKLT_PWM

LCD_BKLT_EN

LCDBKLT_EN_L

BKLT_PLT_RST_L

LCDBKLT_DISABLE

R97571 2

R97531 2

C9712 1

2

C97131

2

C97961

2

D9701

A K

R97221 2

R97211 2

R97201 2

R97181 2

R97191 2

R97171 2

R97152

1

R9731

1 2

C9710 1

2

C9711 1

2

XW9710

1 2

C97141

2

C97041

2

R97141

2

R97161

2

R97551 2

R97411 2

C97991

2

C97971

2

L9701

1 2

R97041 2

U9701

A3

C3

A5

C2

B4

E4

B5

A1

A2

B3

E5

D5

C5

E3

E2

E1

A4

D3

D4

B1

B2

C4

C1

D1

D2

R97891

2

F9700

1 2

R97881

2

C9782 1

2

Q9706

12

56

3

4

XW9720

1 2

Q9707 6

21

Q9707 3

54

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7

7

6

7

90 104

90 104

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Vout = 1.05V

12A MAX OUTPUT

f = 300 kHz

PCH VCCIO (1.05V S0) REGULATOR

CRITICAL

270UF

TANTCASE-B4-SM

20%2V

2V20%

270UF

CASE-B4-SM

CRITICAL

TANT


PCH VCCIO (1.05V) POWER SUPPLY

=PPPCHVCCIO_S0_REG

C98481

2

C9849 1

2

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IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

Y

A

B 08

Y

A

B 08

OUT

OUT

NC

NC

IN

IN

IN

OUT

OUT

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PLACE R9910 - R9917 CLOSE TO U8000

KEPLER GPU REQUIRES RAILS TO COMEup in the following order:

GPU Rail Sequencing

1) GPU_3.3V

5) PEXVDD/Q

PCH S0 PWRGD

-->SMC_DELAYED_PWRGDSMC delayed 99 msALL_SYS_PWRGD-->

Unused PGOOD signal

PCIE TEST STRUCTURES (FOR LAB USE)

EXT GPU PWRGD Pullup

OR IFPY IOVDD - 1.05V

4) FBVDDQ/GDDR5 1.35V

3) GPUVCORE

2) IFPX IOVDD - 1.8V

402

1/16WMF-LF

5%1K

23 45 74 89

69

0

201MF1/20W5%

CERM-X5R

0.47UF

402

6.3V

10%

402

CERM-X5R

6.3V

10%

0.47UF

20

5%

1/20W

MF

201

69

68 100K

5%

1/16W

MF-LF

402

PLACE_NEAR=U8000.AH16:7mm

78

84

73

73

73

PLACE_NEAR=U1800.p12:7mm

74LVC2G08GTSOT833

74LVC2G08GTSOT833

78

1/16WMF-LF

5%

402

NO STUFF

10K

5%1/16WMF-LF402

0

8

5%

1/20W

MF

201

PLACE_NEAR=U8000.AP17:10MM

82

NOSTUFF

5%

1/20W

MF

201


82

NOSTUFF

5%

1/20W

MF

201


82

NOSTUFF

5%

1/20W

MF

201


82

NOSTUFF

0

201MF1/20W5%

5% 1/20W MF 201

0

201MF1/20W5%

0

84

78

78

402

0.001UF

CERM

50V

20%

NO STUFF

17 23 45

17 24

402

5%

MF-LF1/16W

1K

402

10VCERM

20%0.1UF


Power Sequencing EG/PCH S0

=GPUVCORE_EN

MAKE_BASE=TRUE

P1V05GPU_EN

P1V35FB1V05GPU_R_EN

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

GPUVCORE_PGOOD_R

=PP3V3_S0_PWRCTL

SMC_DELAYED_PWRGD

=P1V8GPU_EN

EG_RAIL3_EN GPUVCORE_EN

MAKE_BASE=TRUE

=P1V35FB_EN

PEG_R2D_N<3>

PEG_R2D_N<0>

TP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

P1V5S3RS0_RAMP_DONE

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

DDRREG_PGOOD

CPUIMVP_AXG_PGOOD

=PP3V3_S0_PWRCTL

PM_PCH_APWROK

MAKE_BASE=TRUE

PM_PCH_PWROK

PM_PCH_SYS_PWROKSYS_PWROK_R

ALL_SYS_PWRGD

CPUIMVP_PGOOD

=PP3V3_S5_PCHPWRGD

SMC_DELAYED_PWRGD

=PP3V3_S0_SB_PM

PM_S0_PGOOD

=P1V05_GPU_EN

=P3V3GPU_EN

P1V35FB_EN

MAKE_BASE=TRUE

EG_RAIL4_EN

EG_RAIL2_EN

P3V3GPU_EN

MAKE_BASE=TRUE

P1V05_S0GPU_PGOOD_R

GPUFB_PGOOD_R

P1V05_S0GPU_PGOOD

GPUFB_PGOOD

GPUVCORE_PGOOD

P1V8GPU_EN

MAKE_BASE=TRUE

EG_RAIL1_EN

PEG_R2D_N<7>

PEG_R2D_P<3>

PEG_R2D_P<5>

PEG_R2D_N<5>

PEG_R2D_P<7>

PEG_R2D_P<0>

R99621 2

C99501

2

R99501

2

R9931

1 2

C99311

2

C99321

2

R9932

1 2

R99901

2

U9950

1

2

4

8

7

U9950

5

6

4

8

3

R99911

2

R99601 2

R99151

2

R99171

2

R99101

2

R99131

2

R9901

1 2

R9902

1 2

R9903

1 2

C99051

2

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89

6 75 93

6 75 93

7 74 92

17

7

35 45 46 92

7 24

89

89

89

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

6 75 93

AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM



TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM













MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD






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PEG

NET_TYPE

PHYSICAL SPACINGELECTRICAL_CONSTRAINT_SET

CPU Net Properties

Most CPU signals with impedance requirements are 50-ohm single-ended.

SOURCE: IVB PLATFORM DG , Tables 205-207

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

CPU Signal Constraints

PCI-Express

Some signals require 27.4-ohm single-ended impedance.

I115

I120

I121

I122

I123

I125

I126

I127

I128

I129

I130

I131

I132

I133

I134

I135

I136

I137

I138

I139

I140

I141

I144

I145

I146

I147

I148

I149

I150

* ?PEG_TXRX =10X_DIELECTRIC

?*PEG_TXTX =3X_DIELECTRIC

?*PEG_RXRX =3X_DIELECTRIC

=85_OHM_DIFF=85_OHM_DIFFPCIE_85D =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF* =85_OHM_DIFF

=80_OHM_DIFFPEG_80D =80_OHM_DIFF =80_OHM_DIFF* =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

SYNC_MASTER=K92_MLB

CPU Constraints


* ?CPU_COMP 20 MIL

20 MILCLK_PCIE * ?

PCIE * 15 MIL ?

* ?25 MILCPU_VCCSENSE

CPU_ITP ?* =2:1_SPACING

* 8 MILCPU_8MIL ?

TOP,BOTTOM 15 MILPCIE ?

?TOP,BOTTOM =2x_DIELECTRICCPU_AGTL

* ?0.457 MMCPU_VID

* 7 MILCPU_27P4S 7 MIL=27P4_OHM_SE =27P4_OHM_SE=27P4_OHM_SE=27P4_OHM_SE

=50_OHM_SE* =50_OHM_SECPU_50S =STANDARD=50_OHM_SE =STANDARD=50_OHM_SE

* =STANDARDCPU_55S =STANDARD=55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE

?*CPU_VREF 12 MIL

=90_OHM_DIFFCLK_PCIE_90D =90_OHM_DIFF* =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFF

=STANDARD*CPU_AGTL ?

PEG_R2DPEG_D2R PEG_TXRX*

PEG_R2DPEG_R2D * PEG_TXTX

PEG_D2RPEG_D2R PEG_RXRX*

DPLL_REF_CLKNCLK_PCIE_90D CLK_PCIEDPLL_REF_CLK120M

DPLL_REF_CLKPCLK_PCIECLK_PCIE_90DDPLL_REF_CLK120M

XDP_CPU_TDICPU_50SXDP_TDI CPU_ITP

XDP_CPU_TDOCPU_50SXDP_TDO CPU_ITP

CPU_50S XDP_CPU_TMSCPU_ITPXDP_TMS

CPU_50S CPU_ITPXDP_BPM_L XDP_BPM_L<7..4>

CPU_ITPXDP_PREQ_L CPU_50S XDP_CPU_PREQ_L

XDP_CPU_PWRGDCPU_50S CPU_ITPXDP_CPU_PWRGD

CPU_50S CPU_8MILPM_THRMTRIP_L PM_THRMTRIP_L

CPU_50SPM_MEM_PWRGD CPU_AGTL PM_MEM_PWRGD

CPU_PWRGD CPU_PWRGDCPU_50S CPU_AGTL

CPU_27P4SCPU_SM_RCOMP CPU_COMP CPU_SM_RCOMP<2..0>

CPU_VIDCPU_50S CPU_VIDSOUT

CPU_50S CPU_VIDSCLKCPU_VID

SENSE_1TO1_55S CPU_VCC_VALSENSE_PSENSE_DIFFPAIR SENSE

CPU_VIDALERT_LCPU_VIDCPU_50S

CPU_VCCSA_VID<1..0>CPU_VIDCPU_55S

CPU_AXG_SENSE_NSENSESENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S SENSE CPU_AXG_SENSE_PSENSE_DIFFPAIR

XDP_PRDY_L XDP_CPU_PRDY_LCPU_ITPCPU_50S

XDP_TRST_L CPU_50S XDP_CPU_TRST_LCPU_ITP

DP_INT_IG_AUX_PDISPLAYPORTDP_85DDP_INT_AUX

CLK_PCIE_90DXDP_CLK_ITP CLK_PCIE XDP_CPU_CLK100M_N

CPU_MEM_VREF CPU_VREF PPCPU_MEM_VREFDQ_B

CLK_PCIE_90D CLK_PCIE ITPCPU_CLK100M_PXDP_CLK_CPU

DMI_CLK100M_CPU_PDMI_CLK100M CLK_PCIE_90D CLK_PCIE

DMI_S2N PCIEPCIE_85D DMI_S2N_P<3:0>

FDI_INTCPU_50S CPU_AGTLFDI_INT

ITPXDP_CLK100M_PCLK_PCIEXDP_CLK_PCH CLK_PCIE_90D

PCIE_85D PCIE DMI_N2S_N<3:0>DMI_N2S

CPU_50S CPU_AGTL FDI_FSYNC<1..0>FDI_FSYNC

CPU_AGTL FDI_LSYNC<1..0>CPU_50SFDI_LSYNC

PCIEPCIE_85D DMI_S2N_N<3:0>DMI_S2N

PCIE_85D PCIE DMI_N2S_P<3:0>DMI_N2S

CPU_50S CPU_AGTL CPU_CATERR_LCPU_CATERR_L

CLK_PCIE_90D XDP_CPU_CLK100M_PXDP_CLK_ITP CLK_PCIE

CPU_VREF PP0V75_S3_MEM_VREFCA_BCPU_MEM_VREF

PM_SYNC CPU_50S CPU_AGTL PM_SYNC

CPU_50S CPU_AGTL CPU_PROC_SEL_LCPU_PROC_SEL_L

CPU_PECI CPU_50S CPU_VID CPU_PECI

CPU_VCCSENSE_PSENSESENSE_1TO1_55SSENSE_DIFFPAIR

CPU_VCCIOSENSE_PSENSESENSE_1TO1_55SSENSE_DIFFPAIR

CPU_PROCHOT_L CPU_50S CPU_AGTL CPU_PROCHOT_L

CPU_VCCIOSENSE_NSENSESENSE_DIFFPAIR SENSE_1TO1_55S

CLK_PCIECLK_PCIE_90D DMI_CLK100M_CPU_NDMI_CLK100M

ITPCPU_CLK100M_NCLK_PCIEXDP_CLK_CPU CLK_PCIE_90D

CPU_CFG<17..0>CPU_CFG CPU_ITPCPU_50S

CPU_27P4S CPU_PEG_COMPCPU_COMPCPU_PEG_COMP

CPU_27P4S CPU_EDP_COMPCPU_COMPCPU_EDP_COMP

DP_85D DISPLAYPORT DP_INT_IG_ML_P<3:0>

DP_INT_IG_ML_N<3:0>DISPLAYPORTDP_85D

DP_85D DP_INT_IG_AUX_NDISPLAYPORTDP_INT_AUX

FDI_DATA_N<7:0>FDI_DATA PCIE_85D PCIE

FDI_DATA_P<7:0>PCIE_85D PCIEFDI_DATA

XDP_TCK CPU_50S CPU_ITP XDP_CPU_TCK

ITPXDP_CLK100M_NCLK_PCIE_90D CLK_PCIEXDP_CLK_PCH

CPU_50S XDP_BPM_L<3..0>XDP_BPM CPU_ITP

CPU_ITPXDP_BDRESET_L CPU_50S XDP_DBRESET_L

SENSE CPU_VCCSENSE_NSENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_1TO1_55S CPU_VCC_VALSENSE_NSENSE_DIFFPAIR SENSE

SENSE_1TO1_55S CPU_AXG_VALSENSE_PSENSE_DIFFPAIR SENSE

SENSE_1TO1_55S CPU_AXG_VALSENSE_NSENSE_DIFFPAIR SENSE

CPU_50S CPU_AGTLCPU_VCCSASENSE CPU_VCCSASENSE

PPCPU_MEM_VREFDQ_ACPU_MEM_VREF CPU_VREF

CPU_MEM_VREF PP0V75_S3_MEM_VREFDQ_ACPU_VREF

PP0V75_S3_MEM_VREFCA_ACPU_VREFCPU_MEM_VREF

PEG_D2R PEG_D2R_C_N<7..0>PEG_80D

PEG_D2R PEG_D2R_P<7..0>PEG_D2R PEG_80D

PEG_R2D PEG_R2D_P<7..0>PEG_80D

CPU_MEM_VREF PP0V75_S3_MEM_VREFDQ_BCPU_VREF

PEG_R2D PEG_R2D_N<7..0>PEG_80D

PEG_R2D PEG_R2D_C_N<7..0>PEG_80D

PEG_R2D PEG_R2D_C_P<7..0>PEG_80DPEG_R2D

PEG_D2R PEG_D2R_N<7..0>PEG_80D

PEG_D2R PEG_D2R_C_P<7..0>PEG_80D

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10

12 69

12 69

12

12 69

12 66

12 69

12 69

10 23

10 23

8 9

23

9 31

10 16

10 16

6 9 17

6 9 17

16 23

6 9 17

6 9 17

6 9 17

6 9 17

6 9 17

10 45

23

29 31

10 17

10 19

10 19 46

12 69

12 71

10 45 46 69

12 71

10 16

10 16

9 23

9

9

8 9

8 9

8 9

6 9 17

6 9 17

10 23

16 23

10 23

10 23 24

12 69

12

12

12

12 66

9 31

27 31

27 31

6 75

8 75

6 75 92

29 31

6 75 92

8 75

8 75

8 75

6 75




















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Memory Bus Spacing Group Assignments

Maximum length of any signal from die pad to SODIMM pad is 139.7mm, from procesor ball to SODIMM pad is 114.3mm.

Memory Bus Constraints

DQ/DM signals should be matched within 0.508mm of associated DQS pair.

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.

DQS to clock matching should be within [CLK-12.7mm] and [CLK+25.4mm].

CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.

CONTROL signals should be matched within [CLK-12.7mm] to [CLK+0.0mm] of CLK pairs.

A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs.

DDR3:

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.

SOURCE: Calpella SFF Platform DG, Rev 1.5 (#407364), Section 2.2

PHYSICAL SPACING

NET_TYPE

=1.5:1_SPACING* ?MEM_DATA2DATA

MEM_CMD2MEM =3:1_SPACING ?*

=37_OHM_SE =37_OHM_SE* =STANDARD =STANDARDMEM_37S =37_OHM_SE =37_OHM_SE

MEM_40S =STANDARD* =STANDARD=40_OHM_SE =40_OHM_SE=40_OHM_SE =40_OHM_SE

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF* =85_OHM_DIFFMEM_85D =85_OHM_DIFF

* MEM_CLK2MEMMEM_*MEM_CLK

25 MILS*MEM_2OTHER ?

=3:1_SPACINGMEM_DQS2MEM * ?

=4:1_SPACING* ?MEM_CLK2MEM

?=1.5:1_SPACING*MEM_CMD2CMD

MEM_50S =50_OHM_SE=50_OHM_SE=50_OHM_SE =STANDARD* =STANDARD=50_OHM_SE

MEM_72D =72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF*


Memory Constraints

MEM_CMD MEM_CMD2MEM*MEM_*

MEM_CMDMEM_CMD MEM_CMD2CMD*

=3:1_SPACING ?*MEM_DATA2MEM

=2.5:1_SPACINGMEM_CTRL2MEM * ?

=3:1_SPACINGMEM_CTRL2CTRL * ?

MEM_* MEM_DATA2MEMMEM_DATA *

* * MEM_2OTHERMEM_*

MEM_*MEM_CTRL * MEM_CTRL2MEM

MEM_CTRL2CTRL*MEM_CTRL MEM_CTRL

*MEM_DQS MEM_DQS2MEMMEM_*

MEM_DATA * MEM_DATA2DATAMEM_DATA

MEM_40SMEM_A_CMD MEM_A_CAS_LMEM_CMD

MEM_85DMEM_A_DQS5 MEM_DQS MEM_A_DQS_N<5>MEM_85D MEM_DQSMEM_A_DQS5 MEM_A_DQS_P<5>MEM_85DMEM_A_DQS4 MEM_DQS MEM_A_DQS_N<4>MEM_85DMEM_A_DQS4 MEM_DQS MEM_A_DQS_P<4>

MEM_85DMEM_A_DQS2 MEM_DQS MEM_A_DQS_N<2>MEM_85D MEM_DQSMEM_A_DQS2 MEM_A_DQS_P<2>

MEM_A_DQS0 MEM_85D MEM_A_DQS_N<0>MEM_DQS

MEM_DATAMEM_50SMEM_A_DQ_BYTE7 MEM_A_DQ<63..56>

MEM_DATAMEM_50SMEM_A_DQ_BYTE5 MEM_A_DQ<47..40>MEM_DATAMEM_50SMEM_A_DQ_BYTE4 MEM_A_DQ<39..32>

MEM_85DMEM_A_DQS1 MEM_DQS MEM_A_DQS_P<1>

MEM_85DMEM_A_DQS1 MEM_DQS MEM_A_DQS_N<1>



MEM_CLKMEM_72DMEM_B_CLK MEM_B_CLK_N<5..0>

MEM_B_CNTL MEM_CTRLMEM_37S MEM_B_CS_L<3..0>MEM_CTRLMEM_37SMEM_B_CNTL MEM_B_CKE<3..0>

MEM_B_CLK_P<5..0>MEM_CLKMEM_72DMEM_B_CLK

MEM_B_CMD MEM_CMDMEM_40S MEM_B_RAS_L

MEM_B_CMD MEM_CMDMEM_40S MEM_B_CAS_L

MEM_B_CMD MEM_CMDMEM_40S MEM_B_WE_L

MEM_50SMEM_B_DQ_BYTE0 MEM_DATA MEM_B_DQ<7..0>






MEM_85DMEM_B_DQS1 MEM_B_DQS_N<1>MEM_DQS

MEM_B_DQS2 MEM_B_DQS_P<2>MEM_85D MEM_DQS


MEM_85DMEM_B_DQS3 MEM_B_DQS_P<3>MEM_DQS

MEM_B_DQS3 MEM_B_DQS_N<3>MEM_85D MEM_DQS

MEM_85D MEM_B_DQS_P<5>MEM_DQSMEM_B_DQS5


MEM_CTRL MEM_A_ODT<3..0>MEM_37SMEM_A_CNTL

MEM_A_BA<2..0>MEM_A_CMD MEM_40S MEM_CMD

MEM_50S MEM_DATAMEM_A_DQ_BYTE1 MEM_A_DQ<15..8>

MEM_85D MEM_DQS MEM_A_DQS_P<6>MEM_A_DQS6

MEM_85DMEM_A_DQS6 MEM_A_DQS_N<6>MEM_DQS


MEM_85DMEM_B_DQS0 MEM_DQS MEM_B_DQS_N<0>MEM_85DMEM_B_DQS0 MEM_DQS MEM_B_DQS_P<0>




MEM_85D MEM_B_DQS_N<5>MEM_DQSMEM_B_DQS5




MEM_85D MEM_B_DQS_N<6>MEM_DQSMEM_B_DQS6

MEM_A_CLK_N<5..0>MEM_A_CLK MEM_CLKMEM_72D

MEM_A_CLK_P<5..0>MEM_A_CLK MEM_CLKMEM_72D

MEM_85D MEM_B_DQS_N<7>MEM_B_DQS7 MEM_DQS


MEM_B_CMD MEM_CMDMEM_40S MEM_B_A<15..0>

MEM_B_CMD MEM_40S MEM_CMD MEM_B_BA<2..0>

MEM_B_CNTL MEM_CTRLMEM_37S MEM_B_ODT<3..0>

MEM_50SMEM_A_DQ_BYTE0 MEM_A_DQ<7..0>MEM_DATA

MEM_DATAMEM_50SMEM_A_DQ_BYTE6 MEM_A_DQ<55..48>

MEM_DATAMEM_50SMEM_A_DQ_BYTE3 MEM_A_DQ<31..24>MEM_DATAMEM_50SMEM_A_DQ_BYTE2 MEM_A_DQ<23..16>

MEM_40SMEM_A_CMD MEM_A_WE_LMEM_CMD

MEM_40S MEM_A_RAS_LMEM_A_CMD MEM_CMD

MEM_A_CMD MEM_A_A<15..0>MEM_CMDMEM_40S

MEM_A_CNTL MEM_CTRL MEM_A_CS_L<3..0>MEM_37S

MEM_A_CNTL MEM_A_CKE<3..0>MEM_CTRLMEM_37S

MEM_A_DQS0 MEM_85D MEM_DQS MEM_A_DQS_P<0>

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SATA Interface Constraints

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

Digital Video Signal Constraints

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

USB 2.0 Interface Constraints

USB 3.0 Interface Constraints

SOURCE: CR SFF PLATFORM DESIGN GUIDE V0.7, TABLE 4-211, 1X1+

PHYSICAL

NET_TYPE

SPACINGELECTRICAL_CONSTRAINT_SET

PCH Net Properties

I213

I220

I221

I222

I223

I224

I225

I226

I227

I228

I229

I230

I231

I232

I233

I234

I235

I236

I237

I242

I243

I246

I247

I248

I249

I250

I251

I252

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I263

I264

I265

I266

I267

I268

I269

I270

I271

I272

I273

I274

I275

I276

I277

I278

I279


PCH Constraints 1

=50_OHM_SE=50_OHM_SE=50_OHM_SESATA_50SE * =50_OHM_SE =50_OHM_SE=50_OHM_SE

=37_OHM_SE=37_OHM_SE=37_OHM_SE=37_OHM_SE=37_OHM_SESATA_37SE * =37_OHM_SE

=90_OHM_DIFF_ALTSATA_90D_ALT * =90_OHM_DIFF_ALT =90_OHM_DIFF_ALT =90_OHM_DIFF_ALT =90_OHM_DIFF_ALT =90_OHM_DIFF_ALT

TOP,BOTTOM =4:1_SPACING ?LVDS

?*USB3 =5:1_SPACING

=STANDARD =STANDARD =STANDARDPCH_USB_RBIAS =STANDARD* =STANDARD =STANDARD

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFFUSB_85D * =85_OHM_DIFF =85_OHM_DIFF

* =4:1_SPACINGUSB ?

?* 15 MILUSB_RBIAS

ISL3,ISL4,ISL9,ISL10 =4:1_SPACINGDISPLAYPORT ?

ISL3,ISL4,ISL9,ISL10 ?LVDS =4:1_SPACING

15 MIL* ?SATA_ICOMP

?SATA * =5:1_SPACING

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFFSATA_90D * =90_OHM_DIFF

?DISPLAYPORT TOP,BOTTOM =4:1_SPACING

LVDS_85D =90_OHM_DIFF=90_OHM_DIFF* =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF*DP_85D =90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFF

USBUSB_85D USB_EXTA_MUXED_F_N

USB_EXTA_MUXED_F_PUSB_85D USBUSB_EXTA

USBUSB_85D USB_EXTA_MUXED_NUSB_EXTA USB_85D USB USB_EXTA_MUXED_P

USB_SMC_NUSBUSB_85DUSB_SMC

USB_SMC_PUSBUSB_85DUSB_SMC

USB3USB3_EXT_TX USB_85D USB3_EXTB_TX_F_P

USB3USB_85D USB3_EXTB_TX_F_N

USB3_EXT_RX USB3USB_85D USB3_EXTB_RX_P

USB_EXTB_EHCI_PUSBUSB_85D

USB_85D USB3_EXTB_RX_NUSB3

USB3_EXT_RX USB_85D USB3 USB3_EXTB_RX_F_P

USB3USB_85D USB3_EXTB_RX_F_N

USB3_EXTB_TX_NUSB3USB_85D

USB_85D USB_EXTB_EHCI_NUSB

USB_85D USB USB_EXTB_XHCI_N

USB_EXTB_F_NUSBUSB_EXTB_MUX USB_85D

USB_EXTB_F_PUSB_EXTB_MUX USB_85D USB

USB3 USB3_EXTA_RX_PUSB_85DUSB3_EXT_RX

USB3USB_85D USB3_EXTA_TX_F_PUSB3_EXT_TX

USB3 USB3_EXTA_TX_F_NUSB_85D

USB_85D USB USB_EXTB_XHCI_P

SATA_90D_ALT SATA SATA_HDD_R2D_C_P

SATA_90D_ALT SATA SATA_HDD_R2D_N

USB_CAMERA USBUSB_85D USB_CAMERA_CONN_P

USB_85D USB3 USB3_EXTA_TX_N

SATA_ODD_D2R_C_NSATA_90D SATA

PCH_SATA3COMPSATA_ICOMPSATA_50SEPCH_SATA3_ICOMP

SATA_37SE PCH_SATAICOMPSATA_ICOMPPCH_SATA_ICOMP

USB_EXTA_PUSB_85D USBUSB_EXTA

USB_EXTB_MUX USB_EXTB_MUX_NUSB_85D USB

USB_EXTC USB_EXTC_PUSBUSB_85D

USB_EXTC_NUSBUSB_85D

USB_85D USB_CAMERA_NUSB

USBUSB_85DUSB_BT USB_BT_CONN_P

USBUSB_85D USB_BT_CONN_N

USBUSB_TPAD USB_TPAD_PUSB_85D

USB USB_TPAD_NUSB_85D

USBUSB_85D USB_EXTD_XHCI_PUSBUSB_85D USB_TPAD_R_N

USBUSB_85D USB_HUB_UP_P

PCH_USB_RBIAS USB_RBIASPCH_USB_RBIAS PCH_USB_RBIAS

USB_TPAD USB_85D USB_TPAD_R_PUSB

USB_85D USB USB_IR_N

USB_85D USB USB_BT_N

USB_EXTB_MUX_PUSBUSB_85DUSB_EXTB_MUX

USB_85D USB3_EXTA_RX_NUSB3

USB_85DUSB3_EXT_RX USB3 USB3_EXTA_RX_F_P

USB_85D USB3 USB3_EXTA_TX_C_N

USB3_EXT_TX USB3USB_85D USB3_EXTB_TX_P

USB_BT USB_85D USB USB_BT_P

USB_EXTA_NUSBUSB_85D

SATA_90D_ALT SATA SATA_HDD_D2R_C_P

SATA_90D_ALTSATA_HDD_D2R SATA SATA_HDD_D2R_P

SATA_90D_ALT SATA SATA_HDD_D2R_C_N

LVDS_IG_A_DATA3 LVDS_IG_A_DATA_P<3>LVDS_85D LVDS

LVDS_IG_A_DATA LVDS_85D LVDS LVDS_IG_A_DATA_N<2..0>LVDS_IG_A_DATA LVDS_85D LVDS LVDS_IG_A_DATA_P<2..0>LVDS_IG_A_CLK LVDSLVDS_85D LVDS_IG_A_CLK_N

LVDS_85D LVDS LVDS_IG_A_CLK_PLVDS_IG_A_CLK

USB3USB_85D USB3_EXTB_TX_C_N

DP_85D DISPLAYPORT DP_IG_AUX_CH_NDP_AUX_CH

DP_85D DISPLAYPORT DP_IG_AUX_CH_PDP_AUX_CH

LVDS_IG_B_DATA LVDS_IG_B_DATA_P<2..0>LVDS_85D LVDS

USB3USB_85DUSB3_EXT_TX USB3_EXTA_TX_P

USB3USB3_EXT_TX USB3_EXTB_TX_C_PUSB_85D

USB_IR USB_85D USB USB_IR_P

USBUSB_85D USB_EXTD_XHCI_N

SATA_90D_ALT SATA SATA_HDD_D2R_N

LVDS_IG_B_DATA LVDS_IG_B_DATA_N<2..0>LVDSLVDS_85D

LVDS_IG_A_DATA3 LVDSLVDS_85D LVDS_IG_A_DATA_N<3>

SATA_90D_ALT SATA_HDD_R2D_C_NSATA

SATA_90D_ALT SATA SATA_HDD_R2D_RC_P

SATA_90D_ALT SATA SATA_HDD_R2D_RC_N

SATA_90D_ALT SATA SATA_HDD_R2D_PSATA_HDD_R2D

SATA_90D_ALT SATA_HDD_D2R_RC_PSATA

SATA_90D_ALT SATA_HDD_D2R_RC_NSATA

SATA_90D_ALT SATA_HDD_R2D_RDROUT_PSATA

SATASATA_90D_ALT SATA_HDD_R2D_RDROUT_N

USB3 USB3_EXTA_RX_F_NUSB_85D

USB3_EXT_TX USB3USB_85D USB3_EXTA_TX_C_P

USB_85D USB USB_HUB_UP_N

SATA SATA_HDD_D2R_RDRIN_PSATA_90D_ALT

SATA SATA_HDD_D2R_RDRIN_NSATA_90D_ALT

SATA SATA_HDD_D2R_RDROUT_PSATA_90D_ALT

SATA SATA_HDD_D2R_RDROUT_NSATA_90D_ALT

SATA SATA_HDD_R2D_RDRIN_PSATA_90D_ALT

SATA SATA_HDD_R2D_RDRIN_NSATA_90D_ALT

SATA_ODD_R2D SATA_ODD_R2D_C_PSATASATA_90D

SATA_ODD_R2D SATA_ODD_R2D_PSATASATA_90D

SATA_ODD_R2D_C_NSATASATA_90D

SATA_ODD_R2D_NSATA_90D SATA

SATA_ODD_D2R SATA_ODD_D2R_PSATA_90D SATA

SATA_ODD_D2R_NSATA_90D SATA

SATA_ODD_D2R SATA_ODD_D2R_C_PSATA_90D SATA

USB_CAMERA_PUSB_85D USBUSB_CAMERA

USBUSB_85D USB_CAMERA_CONN_N

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SMBus Interface Constraints

SPI Interface Constraints

SIO Signal Constraints

SPACINGPHYSICALELECTRICAL_CONSTRAINT_SET

PCH Net PropertiesNET_TYPE

LPC Bus Constraints

HD Audio Interface Constraints

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I263

I264

I266

I268

I269

I270

I273

I274

I275

I276

I277

I278

*CLK_SLOW 8 MIL ?

*CLK_LPC 8 MIL ?

=50_OHM_SE* =STANDARD =STANDARD=50_OHM_SE =50_OHM_SE=50_OHM_SESMB_50S

?=2x_DIELECTRICSMB *

8 MIL ?SPI *

*HDA ?=2x_DIELECTRIC

=STANDARD=50_OHM_SE =50_OHM_SE=50_OHM_SE =STANDARD* =50_OHM_SECLK_LPC_50S

=STANDARD=STANDARD*SPI_55S =55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE

=STANDARD=50_OHM_SE =50_OHM_SE* =STANDARD=50_OHM_SELPC_50S =50_OHM_SE

=STANDARD=STANDARD* =50_OHM_SEHDA_50S =50_OHM_SE =50_OHM_SE=50_OHM_SE

=STANDARD* =STANDARDCLK_SLOW_45S =45_OHM_SE =45_OHM_SE =45_OHM_SE=45_OHM_SE

6 MIL ?*LPC

PCH Constraints 2


LPC_CLK33M_LPCPLUSCLK_LPCCLK_LPC_50S

LPC_AD<3..0>LPC_50S LPC

LPC_50SLPC_FRAME_L LPC LPC_FRAME_L

LPC_RESET_L LPCLPC_50S LPC_RESET_L

PCH_LPC_CLK0 CLK_LPC_50S CLK_LPC LPC_CLK33M_SMC_R

CLK_LPC_50S LPC_CLK33M_SMCCLK_LPC

SMB_50S SML_PCH_1_CLKSMBSMBUS_PCH_1_CLK

SMBUS_PCH_DATASMB_50S SMBSMBUS_PCH_DATA

SMB_50S SMB SML_PCH_0_CLKSMBUS_PCH_0_CLK

SMB_50S SMB SML_PCH_0_DATASMBUS_PCH_0_DATA

HDAHDA_50S HDA_BIT_CLK_R

HDA_SYNC HDA_SYNCHDAHDA_50S

HDAHDA_50S HDA_SYNC_R

HDA_50S HDA HDA_BIT_CLKHDA_BIT_CLK

HDA_50S HDA HDA_RST_L

HDA_SDIN0 HDA_50S HDA HDA_SDIN0

HDA_SDOUT HDA_50S HDA HDA_SDOUT

PCIE_85D PCIE PCIE_ENET_R2D_P

PCIE PCIE_ENET_R2D_C_NPCIE_85D

PCIE_ENET_D2R_C_NPCIEPCIE_85D

PCIE_AP_D2R_PPCIE_85D PCIEPCIE_AP_D2R

PCIE_85D PCIE_ENET_D2R_C_PPCIE

SPI_55S SPI SPI_CS0_LSPI_55SSPI_CS0 SPI SPI_CS0_R_L

SPI_55S SPI_CLK_RSPISPI_CLK

SMB_50S SMBSMBUS_PCH_1_DATA SML_PCH_1_DATA

SMBUS_PCH_CLKSMB_50S SMBSMBUS_PCH_CLK

HDA_50S HDA_RST_R_LHDA_RST_L HDA

HDA_50S HDA HDA_SDOUT_R

PCH_CLK100M_SATA_NCLK_PCIECLK_PCIE_90D

CPU_50S PCH_CLK33M_PCIINCLK_PCIE

CLK_PCIE_90D PCIE_CLK100M_PCH_PCLK_PCIE

SPI_55SSPI_MISO SPI SPI_MISO

PCIE_AP_R2D_C_PPCIEPCIE_85DPCIE_AP_R2D

PCIE_AP_R2D_C_NPCIE_85D PCIE

PCIE_AP_D2R_NPCIE_85D PCIE

SPI_MOSISPISPI_55S

PCIE PCIE_ENET_R2D_NPCIE_85D

PCIE_ENET_R2D PCIEPCIE_85D PCIE_ENET_R2D_C_P

PCIEPCIE_85D PCIE_ENET_D2R_N

PCIE_CLK100M_TBT_NCLK_PCIECLK_PCIE_90D

PCIE_85D PCIE_FW_R2D_NPCIE

PCIE_FW_R2D_PPCIEPCIE_85D

PCIE_AP_D2R_R_NPCIEPCIE_85D

CLK_PCIE_90D CLK_PCIE PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_NCLK_PCIE_90D CLK_PCIE

CLK_PCIE_90D CLK_PCIE PCH_CLK96M_DOT_P

PCIE_CLK100M_TBT_PPCIE_CLK100M_T29_ CLK_PCIECLK_PCIE_90D

PCIE_CLK100M_PCH_NCLK_PCIE_90D CLK_PCIE

AUD_SDI_RHDAHDA_50S

SPI_55S SPI_CLKSPI

SPI_MOSI SPI_MOSI_RSPISPI_55S

PCIE_85D PCIE_ENET_D2R_PPCIEPCIE_ENET_D2R

PCIE_AP_R2D_PPCIEPCIE_85D

PCIE_AP_R2D_NPCIEPCIE_85D

PCIE_AP_D2R_R_PPCIE_85D PCIE

CLK_PCIE PCIE_CLK100M_ENET_PCLK_PCIE_90DPCIE_CLK100M_ENET

CLK_PCIE_90D CLK_PCIEPCIE_CLK100M_AP PCIE_CLK100M_AP_PCLK_PCIE PCIE_CLK100M_ENET_NCLK_PCIE_90D

CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_FW_PPCIE_CLK100M_FW

CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_AP_N

CLK_PCIECLK_PCIE_90D PCIE_CLK100M_FW_N

CLK_PCIE PCIE_CLK100M_EXCARD_NCLK_PCIE_90D

CLK_PCIEPCIE_CLK100M_EXCARD PCIE_CLK100M_EXCARD_PCLK_PCIE_90D

PCIE_TBT_R2D_C_P<3..0>PCIE_T29_R2D PCIE_85D PCIE

PCIEPCIE_T29_R2D PCIE_85D PCIE_TBT_R2D_C_N<3..0>

PCIE_TBT_D2R_P<3..0>PCIE_T29_D2R PCIEPCIE_85D

PCIE_TBT_D2R_N<3..0>PCIE_T29_D2R PCIEPCIE_85D

PCIE_T29_R2D PCIEPCIE_85D PCIE_TBT_R2D_P<3..0>

PCIE_T29_R2D PCIE_85D PCIE PCIE_TBT_R2D_N<3..0>

PCIE_85D PCIEPCIE_T29_D2R PCIE_TBT_D2R_C_P<3..0>

PCIEPCIE_T29_D2R PCIE_85D PCIE_TBT_D2R_C_N<3..0>

PCIE PCIE_FW_D2R_C_NPCIE_85D

PCIE_85D PCIE_FW_D2R_C_PPCIE

PCIE PCIE_FW_D2R_NPCIE_85D

PCIE_FW_D2R PCIEPCIE_85D PCIE_FW_D2R_PPCIEPCIE_85D PCIE_FW_R2D_C_N

PCIE_FW_R2D PCIE_FW_R2D_C_PPCIEPCIE_85D

CLK_PCIE_90D PEG_CLK100M_NCLK_PCIE

CLK_PCIECLK_PCIE_90D PEX_TSTCLK_O_NCLK_PCIE_90D CLK_PCIE PEX_TSTCLK_O_PPCIE_CLK100M

CLK_PCIECLK_PCIE_90DPCIE_CLK100M PEG_CLK100M_P

CPU_50S PCH_CLK14P3M_REFCLKCLK_PCIE

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36

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FireWire Net Properties

PHYSICAL

FireWire Interface Constraints

CAESAR IV (Ethernet PHY) Constraints

SOURCE: Attila Farkas Email - 8/2/10

SOURCE: Broadcom 5764-DS04-RDS Page 38

SOURCE: Broadcom 5764-DS04-RDS Page 38

SPACING

NET_TYPE

SPACING

NET_TYPE

PHYSICAL

Port 2 Not Used

CAESAR IV (Ethernet) Constraints


Ethernet Net Properties


I158

I159

I160

I161

I162

I163

I164

I165

I169

I170

I171

I172

I173

I174

SYNC_MASTER=K91_ERIC SYNC_DATE=08/03/2010

Ethernet/FW Constraints

=50_OHM_SE =50_OHM_SE* =STANDARD=50_OHM_SEENET_50S =50_OHM_SE =STANDARD

=110_OHM_DIFF=110_OHM_DIFF* =110_OHM_DIFF =110_OHM_DIFF=110_OHM_DIFF =110_OHM_DIFFFW_110D

0.6 MM ?*ENET_MDI

* =3:1_SPACING ?ENET_3X

=3X_DIELECTRICENET_CR * ?

=100_OHM_DIFF=100_OHM_DIFF* =100_OHM_DIFF =100_OHM_DIFFENET_100D =100_OHM_DIFF=100_OHM_DIFF

?=3:1_SPACING*FW_TP

SDCONN_CLK_RENET_CRENET_50S

ENET_50S ENET_CR SDCONN_CLK_R_L

SDCONN_DATA<7..0>ENET_CRENET_50S

ENET_MDI ENET_MDI_N<3..0>ENET_100DENET_MDI

CR_DATA_A0 SDCONN_CMDENET_50S ENET_CR

CR_CLK ENET_CR SDCONN_CLKENET_50S

SDCONN_R_DATA<7..0>ENET_50S ENET_CR

FW_P1_TPA_PFW_110DFW_P1_TPA FW_TP

ENET_RESET_LENET_3XENET_50SENET_RESET_L

ENET_MDI_P<3..0>ENET_MDIENET_100DENET_MDI

FW_TPFW_110D FW_P0_TPA_PFW_P0_TPA

FW_110D FW_TP FW_P0_TPB_NFW_P0_TPB

FW_TPFW_110D FW_P0_TPA_NFW_P0_TPA

FW_110D FW_TP FW_P0_TPB_PFW_P0_TPB

FW_P1_TPB_NFW_110D FW_TPFW_P1_TPB

FW_P1_TPB_PFW_110D FW_TPFW_P1_TPB

FW_P1_TPA_NFW_110D FW_TPFW_P1_TPA

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PHYSICAL

Thunderbolt I2C Signal Constraints


Thunderbolt SPI Signal Constraints

Thunderbolt/DP Connector Signal Constraints

SOURCE: Bill Cornelius’s Thunderbolt Routing Notes

Only used on hosts supporting Thunderbolt video-in

NET_TYPE

SPACING

PHYSICAL

NET_TYPE

SPACING

Thunderbolt IC Net Properties

Thunderbolt/DP Net Properties


NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

DisplayPort Signal Constraints

I276

I277

I278

I279

I280

I281

TOP,BOTTOM =7x_DIELECTRIC ?TBTDP

=55_OHM_SE =STANDARD=STANDARD* =55_OHM_SE =55_OHM_SE=55_OHM_SETBT_SPI_55S

=100_OHM_DIFF* =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFFTBTDP_100D

=2x_DIELECTRIC ?*TBT_I2C

?* =2x_DIELECTRICTBT_SPI

=5x_DIELECTRIC* ?TBTDP

=80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF*TBTDP_80D

=STANDARD=55_OHM_SE =55_OHM_SE=55_OHM_SE =STANDARD*TBT_I2C_55S =55_OHM_SE


Thunderbolt Constraints

DP_TBTSNK0_AUXCH_PDP_85D DISPLAYPORTDP_TBTSNK0_AUXCH

DP_TBTSNK0_AUXCH_C_NDISPLAYPORTDP_85D

DP_TBTSNK0_AUXCH_C_PDISPLAYPORTDP_85D

DP_TBTSNK0_ML_N<3..0>DISPLAYPORTDP_85DDP_TBTSNK0_ML

DP_TBTSNK0_ML_P<3..0>DP_85D DISPLAYPORTDP_TBTSNK0_ML

DP_TBTSNK0_ML_C_N<3..0>DP_85D DISPLAYPORT

DP_TBTSNK0_ML_C_P<3..0>DP_85D DISPLAYPORT

DP_SDRVA_AUXCH_C_PTBTDPTBTDP_80D

TBT_A_ML_P<3..0>TBTDPTBTDP_80D

TBTDP_80D TBT_A_ML_C_P<3..0>TBTDP

TBTDP DP_SDRVA_AUXCH_PTBTDP_80D

DP_SDRVA_AUXCH_NTBTDPTBTDP_80D

TBT_A_ML_N<3..0>TBTDPTBTDP_80D

DP_85D DISPLAYPORT DP_TBTSNK1_AUXCH_NDP_TBTSNK1_AUXCH

DP_TBTSRC_AUXCH_C_NDP_85D DISPLAYPORT

DP_TBTSRC_AUXCH_C_PDP_85D DISPLAYPORT

DP_85D DISPLAYPORT DP_TBTSNK1_AUXCH_PDP_TBTSNK1_AUXCH

DP_85D DISPLAYPORT DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_N<3..0>DP_85D DISPLAYPORTDP_TBTSNK1_ML

DP_A_EXT_AUXCH_NTBTDPTBTDP_80D

DP_A_EXT_AUXCH_PTBTDPTBTDP_80D

TBT_A_ML_C_N<3..0>TBTDPTBTDP_80D

DP_85D DISPLAYPORT DP_TBTSNK1_AUXCH_C_N

DP_TBTSRC_ML_C_N<3..0>DP_85D DISPLAYPORT

I2C_TBT_SCLTBT_I2C_55S TBT_I2C

I2C_TBT_SDATBT_I2C_55S TBT_I2C

TBT_SPI_CS_LTBT_SPI_CS_L TBT_SPI_55S TBT_SPI

TBT_R2D_C_P<3..0>TBTDP_80D TBTDP

TBT_R2D_C_N<3..0>TBTDP_80D TBTDP

TBT_SPI_MOSITBT_SPI_MOSI TBT_SPI_55S TBT_SPI

TBT_SPI_MISOTBT_SPI_MISO TBT_SPI_55S TBT_SPI

TBT_SPI_CLKTBT_SPI_CLK TBT_SPI_55S TBT_SPI

DP_TBTSRC_ML_C_P<3..0>DISPLAYPORTDP_85D

TBT_D2R_P<3..0>TBTDP_100D TBTDP

TBT_D2R_N<3..0>TBTDP_100D TBTDP

DP_TBTSNK0_AUXCH_NDP_85D DISPLAYPORTDP_TBTSNK0_AUXCH

DP_TBTSNK1_ML_C_P<3..0>DP_85D DISPLAYPORT

DP_TBTSNK1_ML_C_N<3..0>DP_85D DISPLAYPORT

DP_TBTSNK1_ML_P<3..0>DP_85D DISPLAYPORTDP_TBTSNK1_ML

TBTDP DP_SDRVA_ML_R_P<3..0>TBTDP_80D

DP_SDRVA_ML_R_N<3..0>TBTDPTBTDP_80D

TBTDP_100D TBTDP TBT_A_D2R1_AUXCH_PTBT_D2R1 TBTDP_100D TBTDP TBT_D2R_C_N<1>

TBTDPTBTDP_80D DP_SDRVA_AUXCH_C_N

DP_SDRVA_ML_EVEN DP_SDRVA_ML_N<2>TBTDP_80D TBTDP

DP_SDRVA_ML_EVEN DP_SDRVA_ML_N<0>TBTDP_80D TBTDP

DP_SDRVA_ML_EVEN TBTDP_80D DP_SDRVA_ML_P<0>TBTDP

DP_SDRVA_ML_ODD DP_SDRVA_ML_P<3>TBTDPTBTDP_80D

DP_SDRVA_ML_ODD DP_SDRVA_ML_N<3>TBTDPTBTDP_80D

DP_SDRVA_ML_ODD DP_SDRVA_ML_P<1>TBTDPTBTDP_80D

DP_SDRVA_ML_EVEN TBTDP DP_SDRVA_ML_P<2>TBTDP_80D

DP_SDRVA_ML_ODD TBTDP DP_SDRVA_ML_N<1>TBTDP_80D

TBTDP TBT_A_D2R1_AUXCH_NTBTDP_100D

DP_SDRVA_ML_C_N<3..0>TBTDP_80D TBTDP

TBTDP DP_SDRVA_ML_C_P<3..0>TBTDP_80D

TBTDP_100D TBTDP TBT_D2R_C_P<0>TBT_D2R0

TBTDP_80D TBTDP TBT_R2D_N<0>TBT_R2D0

TBTDP_80D TBTDP TBT_R2D_N<1>TBT_R2D1

TBT_R2D_P<0>TBTDPTBTDP_80DTBT_R2D0

TBTDP_80D TBTDP TBT_R2D_P<1>TBT_R2D1

TBT_D2R1 TBTDP_100D TBTDP TBT_D2R_C_P<1>TBT_D2R0 TBTDP_100D TBT_D2R_C_N<0>TBTDP

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SMBus Charger Net Properties

PHYSICAL


NET_TYPE

PHYSICAL SPACING

SMC SMBus Net Properties

SPACING

NET_TYPE


1TO1_DIFFPAIR =STANDARD =STANDARD* 0.1 MM=STANDARD=STANDARD 0.1 MM


SMC Constraints

1TO1_DIFFPAIR CHGR_CSO_NCHGR_CSO 1TO1_DIFFPAIR CHGR_CSO_P

CHGR_CSI CHGR_CSI_P1TO1_DIFFPAIR

CHGR_CSI_N1TO1_DIFFPAIR

SMB_50S SMB SMBUS_SMC_0_S0_SDASMBUS_SMC_0_S0_SDA

SMB_50S SMB SMBUS_SMC_0_S0_SCLSMBUS_SMC_0_S0_SCL

SMB_50S SMB SMBUS_SMC_1_S0_SCLSMBUS_SMC_1_S0_SCL

SMB SMBUS_SMC_1_S0_SDASMB_50SSMBUS_SMC_1_S0_SDA

SMB_50S SMBUS_SMC_3_SCLSMBSMBUS_SMC_3_SCL

SMB_50S SMB SMBUS_SMC_2_S3_SDASMBUS_SMC_2_S3_SDA

SMB SMBUS_SMC_2_S3_SCLSMB_50SSMBUS_SMC_2_S3_SCL

SMB_50S SMB SMBUS_SMC_3_SDASMBUS_SMC_3_SDA

SMB_50S SMB SMBUS_SMC_5_G3_SCLSMBUS_SMC_5_G3_SCL

SMB_50S SMB SMBUS_SMC_5_G3_SDASMBUS_SMC_5_G3_SDA

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GDDR5 FB B Net Properties

MUXGFX Net Properties


GDDR5 Frame Buffer Signal Constraints

PHYSICAL


Digital Video Signal Constraints

NET_TYPE

SPACING

PHYSICAL

NET_TYPE

SPACING SPACING

NET_TYPE

PHYSICALELECTRICAL_CONSTRAINT_SET

SPACINGPHYSICAL

GDDR5 FB A Net Properties

NET_TYPE

LVDS intra-pair matching should be 0.127 mm. Pairs should be within 0.508mm of entire channel.

DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.

Max length of LVDS/DisplayPort/TMDS traces: 13 inches.

SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.

DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.

Kepler Net Properties


I293

I294

I295

I296

I297

I298

I299

I300

I301

I302

I303

I304

I305

I306

I307

I308

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?LVDS TOP,BOTTOM =4x_DIELECTRIC

?DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC

=3x_DIELECTRIC ?*LVDS

* ?DISPLAYPORT =3x_DIELECTRIC

=85_OHM_DIFF =85_OHM_DIFFDP_85D * =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

TOP,BOTTOM ?GDDR5_DATA =5x_DIELECTRIC* ?GDDR5_DATA =3x_DIELECTRIC

GDDR5_EDC ?* =5x_DIELECTRIC

* ?GDDR5_CMD =3x_DIELECTRIC

?*GDDR5_CLK =5x_DIELECTRIC

=STANDARD=45_OHM_SE* =STANDARD=45_OHM_SEGDDR5_45SE =45_OHM_SE =45_OHM_SE

=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF*GDDR5_80D =80_OHM_DIFF =80_OHM_DIFF

TOP,BOTTOM =5x_DIELECTRIC ?GDDR5_EDC

?GDDR5_CMD TOP,BOTTOM =4x_DIELECTRIC

TOP,BOTTOM =5x_DIELECTRIC ?GDDR5_CLK

=85_OHM_DIFF=85_OHM_DIFFLVDS_85D * =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

GPU (Kepler) CONSTRAINTS


=50_OHM_SE =STANDARD12.7 MM=50_OHM_SE =STANDARD=50_OHM_SEGDDR5_45R50SE *

DISPLAYPORT DP_EXTA_ML_N<3..0>DP_85D

DP_EXTA_AUXCH_PDISPLAYPORTDP_85D

DP_EXTA_AUXCH_NDISPLAYPORTDP_85D

DISPLAYPORT DP_EXTA_ML_P<3..0>DP_85D

DP_EG_AUX_CH_NDISPLAYPORTDP_85D

DP_AUX_CH DP_85D DISPLAYPORT DP_EG_AUX_CH_PDISPLAYPORTDP_85D DP_EXTA_AUXCH_C_N

DP_AUX_CH DP_85D DISPLAYPORT DP_EXTA_AUXCH_C_PDP_85D DP_EXTA_ML_C_N<3..0>DISPLAYPORTDP_EXTA_ML

LVDS_EG_B_DATA3 LVDSLVDS_85D LVDS_EG_B_DATA_N<3>

DISPLAYPORTDP_85D DP_EXTA_ML_C_P<3..0>DP_EXTA_ML

LVDS LVDS_EG_B_DATA_P<3>LVDS_EG_B_DATA3 LVDS_85D

LVDS LVDS_EG_B_DATA_N<2..0>LVDS_EG_B_DATA LVDS_85D

LVDSLVDS_EG_B_DATA LVDS_EG_B_DATA_P<2..0>LVDS_85D

LVDS_EG_A_DATA3 LVDS_EG_A_DATA_N<3>LVDSLVDS_85D

LVDS_EG_A_DATA3 LVDS_EG_A_DATA_P<3>LVDSLVDS_85D

LVDS_EG_A_DATA LVDS_EG_A_DATA_N<2..0>LVDSLVDS_85D

LVDS_EG_A_CLK LVDS_85D LVDS_EG_A_CLK_NLVDS

LVDS_EG_A_DATA LVDS_85D LVDS_EG_A_DATA_P<2..0>LVDS

LVDS_EG_A_CLK LVDSLVDS_85D LVDS_EG_A_CLK_P

GPU_OSC_27M_XTALINGPU_CLK27M_IN CLK_SLOW_45S CLK_SLOW

CLK_SLOW_45S CLK_SLOW GPU_OSC_27M_XTALOUTGPU_CLK27M_OUT

LVDS_CONN_A_CLK_F_NLVDSLVDS_85D

LVDS_85D LVDSLVDS_B_CLK LVDS_B_CLK_P

GPU_OSC_27M_XTALOUT_RCLK_SLOWCLK_SLOW_45S

GDDR5_45SEFB_B0_DBI_L3 GDDR5_DATA FB_B0_DBI_L<3>

GDDR5_45SEFB_B1_DBI_L0 GDDR5_DATA FB_B1_DBI_L<0>

GDDR5_CMD FB_A0_WCLK_P<0>GDDR5_80DFB_A0_WCLK0

GDDR5_45SE GDDR5_DATA FB_A1_DBI_L<2>FB_A1_DBI_L2

GDDR5_80DFB_B0_WCLK0 GDDR5_CMD FB_B0_WCLK_P<0>

LVDS_CONN_A_CLK_F_PLVDS_85D LVDS

FB_B1_EDC<0>GDDR5_45SEFB_B1_EDC0 GDDR5_EDC

FB_A1_DBI_L<1>GDDR5_DATAGDDR5_45SEFB_A1_DBI_L1

LVDS_CONN_A_DATA_P<2..0>LVDSLVDS_85D

LVDS_B_CLK_NLVDS_B_CLK LVDS_85D LVDS

LVDS_CONN_A_DATA_N<2..0>LVDS_85D LVDS

LVDS_CONN_B_CLK_F_PLVDSLVDS_85D

GDDR5_45SEFB_B1_CMD GDDR5_CMD FB_B1_A<8..0>

FB_B1_CLK FB_B1_CLK_NGDDR5_CLKGDDR5_80D

FB_B1_CLK FB_B1_CLK_PGDDR5_CLKGDDR5_80D

FB_B0_CLK FB_B0_CLK_NGDDR5_CLKGDDR5_80D

FB_B1_CMD GDDR5_45SE FB_B1_RAS_LGDDR5_CMD

FB_A0_CLK GDDR5_80D GDDR5_CLK FB_A0_CLK_P


FB_B0_CMD GDDR5_45SE FB_B0_ABI_LGDDR5_CMD

GDDR5_45SEFB_B1_CMD FB_B1_ABI_LGDDR5_CMD

FB_B0_EDC<2>FB_B0_EDC2 GDDR5_45SE GDDR5_EDC

GDDR5_CMD FB_B0_WCLK_P<1>GDDR5_80DFB_B0_WCLK1

GDDR5_80DFB_A1_CLK FB_A1_CLK_PGDDR5_CLK

FB_A0_CLK GDDR5_80D FB_A0_CLK_NGDDR5_CLK

FB_A1_EDC<3>FB_A1_EDC3 GDDR5_45SE GDDR5_EDC


GDDR5_45SE FB_B0_DBI_L<1>GDDR5_DATAFB_B0_DBI_L1

FB_B1_EDC<3>FB_B1_EDC3 GDDR5_EDCGDDR5_45SE

GDDR5_80D GDDR5_CMDFB_B0_WCLK1 FB_B0_WCLK_N<1>


GDDR5_80D GDDR5_CMD FB_A0_WCLK_P<1>FB_A0_WCLK1

FB_B1_DBI_L<3>GDDR5_45SEFB_B1_DBI_L3 GDDR5_DATA

GDDR5_45SEFB_B0_DBI_L0 FB_B0_DBI_L<0>GDDR5_DATA


GDDR5_45SEFB_B0_CMD FB_B0_WE_LGDDR5_CMD

FB_B1_CMD GDDR5_45SE FB_B1_CAS_LGDDR5_CMD

GDDR5_45SEFB_B0_CMD FB_B0_RAS_LGDDR5_CMD

GDDR5_45SEFB_B0_CMD FB_B0_A<8..0>GDDR5_CMD

FB_A1_A<8..0>GDDR5_CMDFB_A1_CMD GDDR5_45SE

FB_A0_CMD FB_A0_RAS_LGDDR5_45SE GDDR5_CMD

LVDS_A_DATA_P<2..0>LVDS_A_DATA LVDS_85D LVDS

GDDR5_80D GDDR5_CMD FB_A1_WCLK_N<0>FB_A1_WCLK0


GDDR5_CMD FB_A0_WCLK_N<1>FB_A0_WCLK1 GDDR5_80D

GDDR5_80D FB_A0_WCLK_N<0>GDDR5_CMDFB_A0_WCLK0


FB_A1_EDC<2>FB_A1_EDC2 GDDR5_EDCGDDR5_45SE

GDDR5_CMDFB_A1_CMD GDDR5_45SE FB_A1_CAS_L

FB_A1_RAS_LGDDR5_45SE GDDR5_CMDFB_A1_CMD

FB_A0_A<8..0>GDDR5_45SE GDDR5_CMDFB_A0_CMD

FB_A1_CLK_NGDDR5_CLKFB_A1_CLK GDDR5_80D

FB_A0_ABI_LGDDR5_45SEFB_A0_CMD GDDR5_CMD

FB_A1_ABI_LGDDR5_45SEFB_A1_CMD GDDR5_CMD

GDDR5_45SE GDDR5_CMDFB_A0_CMD FB_A0_WE_L

GDDR5_45SE FB_A0_DQ<23..16>GDDR5_DATAFB_A0_DQ_BYTE2

LVDS_A_CLK_PLVDS_A_CLK LVDS_85D LVDS

LVDS_B_DATA LVDS_B_DATA_P<2..0>LVDS_85D LVDS

FB_B0_CLK GDDR5_CLKGDDR5_80D FB_B0_CLK_P


FB_A0_DQ<15..8>GDDR5_DATAFB_A0_DQ_BYTE1 GDDR5_45SE

FB_A1_DQ<7..0>FB_A1_DQ_BYTE0 GDDR5_DATAGDDR5_45SE

GDDR5_45SE FB_A1_DQ<15..8>FB_A1_DQ_BYTE1 GDDR5_DATA

GDDR5_45SE FB_A1_DQ<23..16>FB_A1_DQ_BYTE2 GDDR5_DATA

LVDS_A_DATA_N<2..0>LVDS_A_DATA LVDS_85D LVDS

LVDS_B_DATA_N<2..0>LVDS_B_DATA LVDSLVDS_85D

LVDS_85D LVDS LVDS_CONN_B_CLK_F_N

LVDS_85D LVDS LVDS_CONN_A_CLK_N

LVDSLVDS_85D LVDS_CONN_B_CLK_P

LVDS LVDS_CONN_B_DATA_N<2..0>LVDS_85D

LVDS_CONN_B_DATA_P<2..0>LVDSLVDS_85D

LVDS_CONN_B_CLK_NLVDSLVDS_85D

LVDSLVDS_85D LVDS_CONN_A_CLK_P

LVDS_A_CLK_NLVDS_A_CLK LVDS_85D LVDS

FB_A1_DQ<31..24>FB_A1_DQ_BYTE3 GDDR5_45SE GDDR5_DATA


GDDR5_45SE GDDR5_DATA FB_A0_DBI_L<2>FB_A0_DBI_L2

FB_A0_DBI_L0 GDDR5_DATA FB_A0_DBI_L<0>GDDR5_45SE

FB_A1_EDC<0>FB_A1_EDC0 GDDR5_EDCGDDR5_45SE

FB_A0_EDC<3>GDDR5_EDCGDDR5_45SEFB_A0_EDC3


GDDR5_45SEFB_B0_CMD FB_B0_CAS_LGDDR5_CMD

GDDR5_45SEFB_B1_CMD FB_B1_WE_LGDDR5_CMD

FB_B0_EDC<1>GDDR5_45SEFB_B0_EDC1 GDDR5_EDC

GDDR5_45SE GDDR5_CMD FB_A0_CS_LFB_A0_CMD

GDDR5_CMDGDDR5_45SEFB_A1_CMD FB_A1_CS_L

GDDR5_EDC FB_A0_EDC<0>GDDR5_45SEFB_A0_EDC0


FB_A1_EDC<1>GDDR5_EDCFB_A1_EDC1 GDDR5_45SE

GDDR5_80D GDDR5_CMD FB_A1_WCLK_N<1>FB_A1_WCLK1

GDDR5_45SE GDDR5_DATA FB_A0_DQ<7..0>FB_A0_DQ_BYTE0

FB_A0_DQ<31..24>GDDR5_DATAGDDR5_45SEFB_A0_DQ_BYTE3

GDDR5_45SE FB_A1_RESET_LFB_A1_CMD_R GDDR5_CMD

FB_A0_RESET_LGDDR5_CMDFB_A0_CMD_R GDDR5_45SE

GDDR5_80DFB_B1_WCLK1 GDDR5_CMD FB_B1_WCLK_N<1>

GDDR5_80D GDDR5_CMDFB_B1_WCLK0 FB_B1_WCLK_P<0>


GDDR5_80D FB_B1_WCLK_P<1>GDDR5_CMDFB_B1_WCLK1

GDDR5_45SE FB_B0_DQ<7..0>FB_B0_DQ_BYTE0 GDDR5_DATA

GDDR5_45SEFB_B0_DQ_BYTE1 GDDR5_DATA FB_B0_DQ<15..8>

GDDR5_45SEFB_B0_DQ_BYTE2 GDDR5_DATA FB_B0_DQ<23..16>

GDDR5_DATAGDDR5_45SEFB_B1_DQ_BYTE0 FB_B1_DQ<7..0>

FB_B1_DQ_BYTE2 FB_B1_DQ<23..16>GDDR5_DATAGDDR5_45SE

FB_B0_RESET_LFB_B0_CMD_R GDDR5_45SE GDDR5_CMD

FB_B1_DQ<31..24>GDDR5_45SE GDDR5_DATAFB_B1_DQ_BYTE3

FB_B1_DQ_BYTE1 FB_B1_DQ<15..8>GDDR5_DATAGDDR5_45SE

GDDR5_DATAGDDR5_45SEFB_B0_DQ_BYTE3 FB_B0_DQ<31..24>


GDDR5_45SEFB_B1_DBI_L2 FB_B1_DBI_L<2>GDDR5_DATA

FB_B1_EDC2 FB_B1_EDC<2>GDDR5_EDCGDDR5_45SE

GDDR5_45SE FB_B1_EDC<1>FB_B1_EDC1 GDDR5_EDC

FB_B0_EDC3 FB_B0_EDC<3>GDDR5_EDCGDDR5_45SE

FB_B0_EDC<0>GDDR5_45SE GDDR5_EDCFB_B0_EDC0

FB_B1_CS_LGDDR5_45SE GDDR5_CMDFB_B1_CMD

FB_B0_CMD FB_B0_CS_LGDDR5_45SE GDDR5_CMD

FB_B1_CMD_R FB_B1_RESET_LGDDR5_45SE GDDR5_CMD

FB_B0_CKE_LFB_B0_CMD_R GDDR5_45SE GDDR5_CMDFB_A0_CMD_R FB_A0_CKE_LGDDR5_45SE GDDR5_CMD

FB_A1_CKE_LFB_A1_CMD_R GDDR5_45SE GDDR5_CMD

GDDR5_CMD FB_A1_WE_LGDDR5_45SEFB_A1_CMD

FB_A0_CAS_LGDDR5_45SE GDDR5_CMDFB_A0_CMD

FB_B1_CMD_R GDDR5_45SE GDDR5_CMD FB_B1_CKE_L

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PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM














Apple Inc.


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J31 Specific Net Properties

PHYSICAL

Memory Constraint Relaxations

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

J31 Specific Net PropertiesNET_TYPE

PHYSICAL

NET_TYPE

SPACINGELECTRICAL_CONSTRAINT_SETSPACING

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

Graphics ,SATA Constraint Relaxations


I250

I255

I256

I283

I284

I287

I288

I291

I292

I299

I300

I301

I302

I303

I304

I305

I306

I307

I308

I311

I312

I313

I314

I315

I316

I317

I318

I319

I320

I321

I322

I323

I324

I325

I326

I327

I328

I329

I330

I331

I332

I333

I334

I335

I336

I337

I338

I341

I342

I345

I346

I347

I348

I349

I350

I351

I352

I353

I354

I355

I356

I357

I358

I359

I360

I361

I362

I363

I364

I365

I366

I367

I368

I369

I370

I371

I372

I373

I374

I375

I376

I377

I378

I379

I380

I381

I382

I383

I384

I387

I388

I389

I390

I391

I392

I393

I394

I395

I396

I397

I398

Project Specific Constraints


6.35 MMMEM_85D TOP 0.1 MM

MEM_CTRL * GND_P2MMGND

?*AUDIO =2:1_SPACING

* ?=2:1_SPACINGTHERM

* 25 MILSENETCONN ?

MEM_CMD * GND_P2MMGND

GND_P2MMMEM_CLK *GND

0.127 MMBOTTOM 6.35 MMMEM_72D

BGA 100_DIFF_BGACLK_PCIE_90D

100_DIFF_BGABGASATA_90D

DP_85D 100_DIFF_BGABGA

BGALVDS_85D LVDS_85D

10000.20 MM*GND_P2MM

*ENET_MDI GND GND_P2MM

GND * GND_P2MMCLK_PCIE

GND_P2MMGNDSATA *

USB * PWR_P2MMSB_POWER

GND_P2MMGNDUSB *

CLK_PCIE PWR_P2MM*SB_POWER

SATA PWR_P2MM*SB_POWER

GND_P2MM*MEM_DQS GND

GND *PCIE GND_P2MM

0.1 MMTOP 500 MILUSB_85D

PCIE_85D 10 mm0.09 MM*

MEM_72D * 100 MIL0.09 MM

0.20 MM 1000PWR_P2MM *

=1:1_DIFFPAIR=1:1_DIFFPAIR =1:1_DIFFPAIR=1:1_DIFFPAIR=1:1_DIFFPAIR=1:1_DIFFPAIR*DIFFPAIR

*GND ?=STANDARD

* ?=2:1_SPACINGSENSE

=1:1_DIFFPAIR=55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR* =55_OHM_SESENSE_1TO1_55S =1:1_DIFFPAIR

=1:1_DIFFPAIR =55_OHM_SE =1:1_DIFFPAIR=55_OHM_SE =1:1_DIFFPAIR=55_OHM_SETHERM_1TO1_55S *

10 MM0.1 MMAUDIODIFF * 0.1 MM=1:1_DIFFPAIR 0.1 MM 0.1 MM

BOTTOMCPU_27P4S 0.23 MM 100 MIL

MEM_40S 100 MIL* 0.09 MM

GND * GND_P2MMLVDS

CPU_COMP *GND GND_P2MM

ISNS_PP1V0_S0GPU_NSENSESENSE_1TO1_55S

SENSESENSE_DIFFPAIR SENSE_1TO1_55S ISNS_PP3V3_S3_P

SENSE_1TO1_55S SENSE CPU_VCORE_RMC_PSENSE_DIFFPAIR

SENSE_1TO1_55S CPU_VCORE_RMC_NSENSE

ISNS_PP1V5_S3_NSENSESENSE_1TO1_55S

ISNS_GPU_R_PSENSESENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_1TO1_55S ISNS_GPU_R_NSENSE

SENSE_1TO1_55S ISNS_CPUVCCSA_R_PSENSESENSE_DIFFPAIR

ISNS_CPUVCCSA_R_NSENSESENSE_1TO1_55S

SENSE ISNS_CPUVCCIO_R_PSENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_CPUVCCIO_R_NSENSESENSE_1TO1_55S

CPUIMVP_ISUM_R_NSENSE_1TO1_55S SENSE

CPUIMVP_ISUMG_R_NSENSESENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR SENSE ISNS_PP1V5_S3_R_P

GPUFB_CS_PSENSE_DIFFPAIR SENSESENSE_1TO1_55S

SENSESENSE_1TO1_55S ISNS_AIRPORT_R_N

P1V05_GPU_PEX_IOVDD_SNS_NSENSE_1TO1_55S SENSE

GPU_FBVDDQ_SENSE_PSENSESENSE_1TO1_55SSENSE_DIFFPAIR

GPU_FBVDDQ_SENSE_NSENSESENSE_1TO1_55S

P1V05_GPU_PEX_IOVDD_SNS_PSENSE_1TO1_55S SENSESENSE_DIFFPAIR

SENSE_DIFFPAIR ISNS_TBT_R_PSENSESENSE_1TO1_55S

ISNS_TBT_R_NSENSE_1TO1_55S SENSE

SENSE_1TO1_55S SENSE GPUFB_CS_N

SENSE_1TO1_55S SENSESENSE_DIFFPAIR ISNS_AIRPORT_R_P

CPUIMVP_ISUMG_R_PSENSE_DIFFPAIR SENSE_1TO1_55S SENSE

SENSE_1TO1_55S SENSE ISNS_PP1V5_S3_R_N

SENSE P1V05_GPU_CS_NSENSE_1TO1_55S

ISNS_PPGPUFB_S0_R_NSENSESENSE_1TO1_55S

P1V05_GPU_CS_PSENSE_1TO1_55SSENSE_DIFFPAIR SENSE

ISNS_PPGPUFB_S0_R_PSENSE_1TO1_55S SENSESENSE_DIFFPAIR

SENSE_1TO1_55S ISNS_PP3V3_S3_NSENSE

SENSE ISNS_PP1V0_S0GPU_PSENSE_1TO1_55SSENSE_DIFFPAIR

CPUIMVP_ISNS_PSENSE_DIFFPAIR SENSESENSE_1TO1_55S

SENSESENSE_1TO1_55S ISNS_HS_OTHER_N

SENSE_1TO1_55S ISNS_AIRPORT_NSENSESENSE_DIFFPAIR

SENSESENSE_1TO1_55S GFXIMVP6_CS_N

SENSE ISNS_1V5_S3_DDR_NSENSE_1TO1_55S

SENSE_DIFFPAIR SENSE ISNS_1V5_S3_DDR_PSENSE_1TO1_55S

SENSE CPUVCCIOS0_CS_NSENSE_1TO1_55S

SENSESENSE_1TO1_55S ISNS_PP3V3_S0GPU_N

SENSE CPUIMVP_ISNS2_NSENSE_1TO1_55S

SENSESENSE_1TO1_55SSENSE_DIFFPAIR ISNS_HS_OTHER_P

SENSESENSE_1TO1_55S CPUIMVP_ISNS3_N

SENSE_DIFFPAIR SENSESENSE_1TO1_55S CPUIMVP_ISNS2_P

SENSE_1TO1_55S ISNS_AIRPORT_PSENSE

CPUTHMSNS_D2_NTHERMTHERM_1TO1_55S

ENETCONN ENETCONN_N<3..0>ENET_100D

THERMTHERM_1TO1_55S GPU_TDIODE_N

CPUTHMSNS_D1_PTHERMTHERM_1TO1_55SSENSE_DIFFPAIR

PP1V5_S3RS0SB_POWER

AUDIOSPK_OUT SPKRCONN_L_OUT_P

AUDIO SPKRCONN_L_OUT_N

USB USB_TPAD_R_PUSB_85D

USB_85D USB_TPAD_R_NUSB

AUDIO SPKRCONN_R_OUT_NAUDIOSPK_OUT SPKRCONN_R_OUT_P

AUDIO AUD_LO2_L_NAUDIODIFF

AUDIO AUD_LO1_R_PAUDIODIFFAUDIO_DIFFPAIR

AUD_LO1_L_PAUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR BI_MIC_PAUDIODIFF AUDIO

BI_MIC_NAUDIODIFF AUDIO

1TO1_DIFFPAIR CHGR_CSO_R_P

CHGR_CSO_R_N1TO1_DIFFPAIR

1TO1_DIFFPAIR CHGR_CSI_R_P

1TO1_DIFFPAIR CHGR_CSI_R_N

CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_AP_CONN_N

SB_POWER PP3V3_S5

PP3V3_S0SB_POWER

CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_AP_CONN_PPCIE_CLK100M_AP

AUDIO AUD_LO2_R_PAUDIO_DIFFPAIR AUDIODIFF

AUDIO_DIFFPAIR AUDIO AUD_LO2_L_PAUDIODIFF

AUDIODIFFAUDIO_DIFFPAIR AUDIO AUD_SPKRAMP_LIN_P

SENSE CPUIMVP_ISNS2G_NSENSE_1TO1_55S

SENSESENSE_1TO1_55S ISNS_HS_GPU_N

AUDIO SPKRCONN_S_OUT_PSPK_OUT

CPUIMVP_ISUM_R_PSENSESENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_PP1V5_S3_PSENSE_DIFFPAIR SENSESENSE_1TO1_55S

THERMTHERM_1TO1_55S CPUTHMSNS_D1_N

THERM CPUTHMSNS_D2_PSENSE_DIFFPAIR THERM_1TO1_55S

ENETCONN ENETCONN_P<3..0>ENET_100D

AUDIOAUDIODIFF AUD_SPKRAMP_SUBIN_N

AUDIO AUD_LO2_R_NAUDIODIFF

AUDIOAUDIODIFFAUDIO_DIFFPAIR AUD_SPKRAMP_SUBIN_P

AUD_LO1_L_NAUDIOAUDIODIFF

AUDIO AUD_LO1_R_NAUDIODIFF

AUDIOAUDIODIFF AUD_SPKRAMP_RIN_N

AUDIOAUDIO_DIFFPAIR AUDIODIFF SSM2375L_P

AUDIOAUDIODIFF SSM2375L_N

AUDIO_DIFFPAIR AUDIOAUDIODIFF SSM2375S_P

AUDIOAUDIODIFF SSM2375R_N

AUDIODIFFAUDIO_DIFFPAIR AUDIO AUD_SPKRAMP_RIN_P

AUDIO AUD_SPKRAMP_LIN_NAUDIODIFF

CPUIMVP_ISNS2G_PSENSE_DIFFPAIR SENSESENSE_1TO1_55S

ISNS_HS_COMPUTING_PSENSESENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_HS_COMPUTING_NSENSESENSE_1TO1_55S

CPUIMVP_ISNS_NSENSE_1TO1_55S SENSE

SENSESENSE_1TO1_55S ISNS_HS_GPU_PSENSE_DIFFPAIR

SENSESENSE_1TO1_55SSENSE_DIFFPAIR CPUIMVP_ISNS3_P

SENSE_1TO1_55S SENSE CPUIMVP_ISNS1_N

SENSE_DIFFPAIR SENSESENSE_1TO1_55S CPUIMVP_ISNS1_P

SENSESENSE_1TO1_55S CPUIMVP_ISNS1G_R_N

SENSE_DIFFPAIR THERM_1TO1_55S THERM GPU_TDIODE_P

THERMTHERM_1TO1_55S GPUTHMSNS_D_N

THERM GPUTHMSNS_D_PTHERM_1TO1_55SSENSE_DIFFPAIR

GPUVCORE_SENSE_PSENSE_1TO1_55S SENSESENSE_DIFFPAIR

SENSE_1TO1_55S SENSE GFXIMVP6_CS_R_N

SENSE_DIFFPAIR GPUVCORE_SENSE_NSENSE_1TO1_55S SENSE

AUDIO SPKRCONN_S_OUT_N

CPUIMVP_ISNS1G_R_PSENSE_DIFFPAIR SENSESENSE_1TO1_55S

SSM2375S_NAUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF SSM2375R_P

CPUVCCIOS0_CS_PSENSESENSE_DIFFPAIR SENSE_1TO1_55S

SENSE VCCSAS0_CS_NSENSE_1TO1_55S

VCCSAS0_CS_PSENSE_1TO1_55S SENSESENSE_DIFFPAIR

SENSESENSE_1TO1_55S CPUIMVP_ISNS1G_N

SENSESENSE_DIFFPAIR SENSE_1TO1_55S CPUIMVP_ISNS1G_P

SENSESENSE_1TO1_55S ISNS_TBT_N

SENSE_1TO1_55SSENSE_DIFFPAIR SENSE ISNS_TBT_P

SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_PP3V3_S0GPU_P

SENSESENSE_1TO1_55S ISNS_LCDBKLT_P

GFXIMVP6_CS_PSENSE_1TO1_55S SENSESENSE_DIFFPAIR

SENSE_DIFFPAIR SENSESENSE_1TO1_55S GFXIMVP6_CS_R_P

SENSE_1TO1_55S SENSESENSE_DIFFPAIR ISNS_PP1V5_S3_P

SENSE_1TO1_55S SENSE ISNS_PP1V05_S0GPU_R_N

SENSESENSE_DIFFPAIR SENSE_1TO1_55S ISNS_PP1V05_S0GPU_R_P

SENSE_1TO1_55S SENSE ISNS_PP1V5_S3_N

SENSESENSE_1TO1_55S ISNS_PP1V0_S0GPU_N

SENSE_1TO1_55S SENSE GFXIMVP_ISNS2_N

SENSE_DIFFPAIR SENSESENSE_1TO1_55S GFXIMVP_ISNS2_P

SENSE_1TO1_55S SENSE GFXIMVP_ISNS1_N

SENSE_DIFFPAIR SENSE_1TO1_55S SENSE GFXIMVP_ISNS1_P

SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_PP1V0_S0GPU_P

ISNS_LCDBKLT_NSENSESENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_HDD_PSENSESENSE_1TO1_55S

SENSE_DIFFPAIR SENSE_1TO1_55S ISNS_HDD_NSENSE

GND GND

051-9585

3.0.0

108 OF 132

101 OF 105

101

105

105

101

49

49

49

49

50

50

103

78 103

103

78 83

77 78

77 78

78 83

104

104

78 103

103

50

103

78 103

103

78 103

103

101

50

50

103

49

49

49 71

50 70

50

50 70

50 69 70

103

51

37

51 81

51

7

6 61 62

6 61 62

25 53 95

25 53 95

6 61 62

6 61 62

57 61

57 61

6 62 63

6 62 63

65

65

65

65

6 32

6 7

6 7

6 32

57 61

57 61

61

50 70

50

6 61 62

50

101

51

51

37

61

57 61

61

57 61

61

61

61

61

61

61

61

50 70

50

50

50

50

50 69 70

50 69 70

50 69 70

50

51 81

51

51

83 84

83 84

6 61 62

50

61

61

49 71

49 66

49 66

50 70

50 70

101

103

103

101

101

84

84

84

84

101

41 103

41 103





































TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS
















































Apple Inc.


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J31 Board-Specific Spacing & Physical Constraints

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

=STANDARD=STANDARD =STANDARD* =STANDARD80_OHM_DIFF =STANDARDN

Y 0.120 MMISL3,ISL4,ISL9,ISL10 0.105 MM80_OHM_DIFF 0.091 MM 0.080 MM

0.200 MM0.175 MM 0.200 MM0.175 MM72_OHM_DIFF YTOP,BOTTOM

0.200 MMY 0.200 MM0.154 MM72_OHM_DIFF 0.154 MMISL2,ISL11

ISL2,ISL11 Y 0.105 MM80_OHM_DIFF 0.120 MM 0.080 MM0.091 MM

0.160 MM80_OHM_DIFF 0.160 MM0.135 MM 0.135 MMYTOP,BOTTOM

=STANDARD =STANDARD85_OHM_DIFF * =STANDARDN =STANDARD=STANDARD

85_OHM_DIFF TOP,BOTTOM Y 0.190 MM0.125 MM 0.190 MM0.090 MM

=STANDARD90_OHM_DIFF N* =STANDARD=STANDARD=STANDARD=STANDARD

ISL2,ISL11 0.090 MM 0.220 MM90_OHM_DIFF Y 0.220 MM0.102 MM

TOP,BOTTOM 0.230 MM 0.230 MM0.090 MM90_OHM_DIFF Y 0.115 MM

PCB Rule Definitions


ISL3,ISL4,ISL9,ISL10 0.220 MM90_OHM_DIFF 0.220 MMY 0.090 MM0.102 MM

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFF100_DIFF_BGA

0.090 MMY =STANDARD=STANDARD0.155 MM* =STANDARD37_OHM_SE

=STANDARDY 0.1 MM =STANDARD0.250 MM* =STANDARD27P4_OHM_SE

=STANDARD=STANDARD=STANDARD =STANDARD=STANDARD72_OHM_DIFF * N

0.154 MM 0.200 MMYISL3,ISL4,ISL9,ISL10 0.200 MM0.154 MM72_OHM_DIFF

=DEFAULTSTANDARD =DEFAULT* Y =DEFAULT10 MM=DEFAULT

0.280 MM0.280 MM0.099 MM0.099 MM90_OHM_DIFF_ALT ISL2,ISL11 Y

0.280 MM0.280 MM0.099 MM0.099 MM90_OHM_DIFF_ALT ISL3,ISL4,ISL9,ISL10 Y

=STANDARD90_OHM_DIFF_ALT =STANDARDN* =STANDARD=STANDARD=STANDARD

0.300 MM0.130 MM 0.300 MM0.130 MM90_OHM_DIFF_ALT TOP,BOTTOM Y

ISL3,ISL4 0.075 MM 0.125 MM 0.125 MMY 0.075 MM100_DIFF_BGA

ISL9,ISL10 0.075 MM100_DIFF_BGA 0.125 MM 0.125 MMY 0.075 MM

85_OHM_DIFF 0.090 MM0.110 MMY 0.180 MM 0.180 MMISL2,ISL11

ISL3,ISL4,ISL9,ISL1085_OHM_DIFF Y 0.090 MM 0.180 MM0.180 MM0.110 MM

=STANDARD110_OHM_DIFF N* =STANDARD =STANDARD=STANDARD =STANDARD

27P4_OHM_SE Y 0.310 MM 0.095 MMTOP,BOTTOM

37_OHM_SE 0.185 MMYTOP,BOTTOM 0.095 MM

=STANDARD* Y =STANDARD0.076 MM =STANDARD55_OHM_SE 0.076 MM

YTOP,BOTTOM40_OHM_SE 0.095 MM0.165 MM

=STANDARD45_OHM_SE * Y =STANDARD =STANDARD0.099 MM 0.099 MM

TOP,BOTTOM45_OHM_SE Y 0.13 MM 0.13 MM

?4:1_SPACING 0.4 MM*

0.090 MMY50_OHM_SE * =STANDARD0.090 MM =STANDARD =STANDARD

TOP,BOTTOM 0.110 MM50_OHM_SE 0.095 MMY

16.2NO_TYPE,BGA MMTOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

Y* =STANDARD40_OHM_SE =STANDARD0.135 MM =STANDARD0.090 MM

0.071 MM ?*P072_SPACE

5X_DIELECTRIC ?* 0.350 MM

7X_DIELECTRIC 0.490 MM* ?

0.700 MM10X_DIELECTRIC ?*

* ?0.280 MM4X_DIELECTRIC

3X_DIELECTRIC 0.210 MM* ?

0.3 MM* ?3:1_SPACING

0.25 MM ?*2.5:1_SPACING

0.15 MM* ?1.5:1_SPACING

2X_DIELECTRIC ?* 0.140 MM

* BGA P072_SPACE*

Y55_OHM_SE 0.090 MM0.090 MMTOP,BOTTOM

1:1_DIFFPAIR =STANDARD =STANDARD 0.1 MM 0.1 MMY =STANDARD*

0.080 MM 0.200 MMY100_OHM_DIFF 0.080 MMISL2,ISL11 0.200 MM

100_OHM_DIFF Y 0.220 MM0.089 MM0.089 MMTOP,BOTTOM 0.220 MM

110_OHM_DIFF 0.065 MM 0.065 MM 0.2 MMISL3,ISL4,ISL9,ISL10 Y 0.2 MM

0.080 MM 0.200 MMY 0.200 MM100_OHM_DIFF ISL3,ISL4,ISL9,ISL10 0.080 MM

110_OHM_DIFF 0.075 MM 0.075 MMY 0.330 MM 0.330 MMTOP,BOTTOM

Y110_OHM_DIFF 0.065 MM 0.065 MM 0.2 MM 0.2 MMISL2,ISL11

=STANDARD =STANDARD* =STANDARD=STANDARDN100_OHM_DIFF =STANDARD

* 0.5 MM ?5:1_SPACING

0.2 MM2:1_SPACING ?*

?=DEFAULT*STANDARD

?BGA_P2MM =DEFAULT*

* =50_OHM_SEYDEFAULT 0 MM0 MM=50_OHM_SE 10 MM

?* =DEFAULTBGA_P1MM

DEFAULT * ?0.1 MM

051-9585

3.0.0

109 OF 132

102 OF 105

OUTV+

V-THRM

OUT

OUTV+

V-THRM

OUT

OUT

OUT

IN

OUT

V-

V++

-

V+

REFIN+

IN- OUT

GND

OUT

IN

V-

V++

-

OUTIN-

IN+ REF

V+

GND

IN

IN

IN

IN

OUT


Apple Inc.


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Rsense: 0.005 (R3552)

Airport Current Sense (IAPC)

V accross Rsense: 5 mV

Gain needed: 660x

Gain: 606x, EDP: 1 A

DDR 1.5V S3 (CPU & Memory) Current Sense (IM1C)Gain: 231.4x, EDP: 14.1 A

Rsense: 0.001 (RD010)

Rsense: 0.001 (R4599)

V accross Rsense: 14.1 mV

Gain needed: 234.1x


GPU 1.05V Current Sense (IG1C)Gain: 649.35x, EDP: 4.9 A

GPU FB (1.35V/1.5V) Current Sense (IG3C)


Gain needed: 144.7x

Rsense: 0.002 (R9840)

Gain: 100x, EDP: 11.4 A

Gain: 294.12x, EDP: 11 A

Rsense: 0.001 (R8360)

V accross Rsense: 11 mV

Gain needed: 673.47x

Gain needed: 1320x

Gain: 1000x, EDP: 2.5 A (12.5 W)

HDD Current Sense (IHDC)

PCH Core (PCH VCCIO) Current Sense (ISBC)

Gain needed: 300x

GPU FB (1.35V/1.5V) Voltage Sense (VG3C)

Rsense: 0.001 (RD8310)


XWLOADISNS:YES

XWLOADISNS:NOCD019,CD039,CD069117S0008 RES,100K,2013

CD029,CD049

SIGNAL_MODEL=EMPTY

XWLOADISNS:YES

ISNS_AIRPORT_IOUT

XWLOADISNS:YES

XWLOADISNS:YES

XWLOADISNS:YES

0.1UF

ISNS_HDD_IOUT

0.1UF

ISNS_PP1V5_S3_IOUT



XWLOADISNS:YES

XWLOADISNS:YES

XWLOADISNS:YESXWLOADISNS:YES

SIGNAL_MODEL=EMPTY

402

1/20W1%

LOADISNS:YES

4.53K

MF201

DFN

OPA2333

LOADISNS:YES

LOADISNS:YES1/20W

SIGNAL_MODEL=EMPTY

1%

201MF

1M

SIGNAL_MODEL=EMPTY

LOADISNS:YES

1%1M

MF201

1/20W

LOADISNS:YES

201

1%1/20WMF

1.54K

1.54K

1%

201MF

1/20W

LOADISNS:YES

402CERM10V20% 46

1%1/20W

201

4.53K

MF

46

MF201

1%

4.53K

1/20W

LOADISNS:YES201

1M

MF

1%1/20W

SIGNAL_MODEL=EMPTY

LOADISNS:YES

DFN

OPA2333

LOADISNS:YES

3.40K

MF201

1%1/20W

3.40K

MF201

1%1/20W

LOADISNS:YES

1/20W

SIGNAL_MODEL=EMPTY

1M

MF201

1%

LOADISNS:YES

46

1/20W

4.53K

MF201

1%


MF-LF1/16W

1M

402

1%

1%1/16WMF-LF402

1.65K

SIGNAL_MODEL=EMPTY

MF-LF402

MF-LF402

0.1UF

CERM402

20%10V

201MF

4.53K

1%1/20W


46

7

7

4.32K

MF-LF402

1%1/16W

1M

MF-LF402

1/16W1%

1M

MF-LF

1%1/16W

402

1/16W

4.32K

1%

MF-LF1/20W

4.53K

MF

1%

201

46

SC70-5

20%

402CERM10V

INA212SC70

10V20%

402CERM

41 101

41 101

SC70-5

10V

0.1UF

CERM402

20%

SC70INA214

0201

20%6.3V


20%

X5R

LOADISNS:YES


0201X5R6.3V

0.22UF20%

0201

6.3V20%

X5R

0.22UF



0.22UF

X5R

20%6.3V

0201

0.22UF

0201


6.3V20%

X5R

78 101

78 101

78 101

78 101

SM



1/20W1%

201MF

4.53K


0201X5R6.3V20%0.22UF

46

SM

Power Sensors: SMC Extended


LOADISNS:NO

NC_ISNS_PP1V5_S3P

=PP1V5_S3_ISNS

GPUFB_CS_N

=PP3V3_S3_ISNS

ISNS_PP1V05_S0GPU_R_N

GND_SMC_AVSS

SMC_GPU_FB_VSENSE

GND_SMC_AVSS

GPUFBVSENSE_IN=PP1V5R1V35_GPU_REG

GND_SMC_AVSS

SMC_PCH_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS

ISNS_PP1V05_S0PCH_IOUT

SMC_HDD_ISENSE

SMC_AIRPORT_ISENSE

SMC_GPU_FB_ISENSE

SMC_GPU_1V05_ISENSE

=PP3V3_S0_ISNS

=PP3V3_S0_ISNS

ISNS_PPGPUFB_S0_R_N

ISNS_PPGPUFB_S0_R_P

=PP5V_S0_ISNS

GND_SMC_AVSS

ISNS_PP1V5_S3_R_P

ISNS_PPGPUFB_S0_IOUT

GPUFB_CS_P

P1V05_GPU_CS_P

P1V05_GPU_CS_N

ISNS_PP1V05_S0GPU_IOUT

NC_PCHVCCIOS0_CSN

=PP3V3_S3_ISNS

=PP3V3_S0_ISNS

=PP1V5_S3_ISNS_R

GND_SMC_AVSS

ISNS_PP1V05_S0GPU_R_P

X5R

0.22UF

ISNS_HDD_P

NC_ISNS_AIRPORTP

1.65K

1%1/16W

LOADISNS:YESPLACE_NEAR=U4900.H2:5MM

LOADISNS:YES

OPA333DCKG4

ISNS_HDD_N

ISNS_AIRPORT_R_P

1M1%

117S0008 RES,100K,201

SIGNAL_MODEL=EMPTY

0.1UF

0.22UF

6.3V

0201


ISNS_PP1V5_S3_R_N

XWLOADISNS:YES

XWLOADISNS:YES

XWLOADISNS:YES

XWLOADISNS:YES

SMC_CPUMEM_ISENSE


XWLOADISNS:YES

XWLOADISNS:YES

NC_ISNS_PP1V5_S3N

XWLOADISNS:YES

NC_PCHVCCIOS0_CSP

N0STUFF

N0STUFF

N0STUFF

ISNS_AIRPORT_R_N

1/16W

OPA333DCKG4

2

NC_ISNS_AIRPORTN

46

XWLOADISNS:YES

LOADISNS:YES

RD0291 2

UD020

5

6

7

9

4

8

RD0241 2

RD0231

2

RD0211 2

RD0221 2

CD0201

2

RD0591 2

RD0491 2

RD0441 2

UD020

3

2

1

9

4

8

RD0421 2

RD0411 2

RD0431

2

RD0691 2

RD0641 2

RD0611 2

RD0631

2

RD0621 2

CD0301

2

RD0391 2

RD0121 2

RD0141

2

RD0151 2

RD0111 2 RD019

1 2

UD010

1

3

4

2

5

CD0151

2

UD050

2

5

4

6

1

3

CD0501

2

UD060

1

3

4

2

5

CD0601

2

UD030

2

5

4

6

1

3

CD0191

2

CD0291

2

CD0691

2

CD0591

2

CD0491

2

CD0391

2

XWD080

1 2

RD0891 2

CD0891

2

XWD010

1

2

051-9585

3.0.0

130 OF 132

103 OF 105

7 49 103

45 46 50

45 46 49 50 103

7 78

45 46 49 50 103

45 46 49 50 103

45 46 49 50 103

7 49 50 103 104

7 49 50 103 104

101

101

7

45 46 49 50

101

7 49 103 104

7 49 50 103 104

45 46 49 103

101

103

103

50

49

104

OUT

COM

GNDTHRM

DVDDAVDD

AD0

AD1

SDA

SCL

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

VREF

REFCOMP

PAD

IN

BI

IN

OUT

OUT

OUT

OUT

IN

OUT

V-

V++

-

OUT

IN

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

IN

OUT

V+

REFIN+

IN- OUT

GND

OUT

Apple Inc.


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REVISION

BRANCH

6 3



3.3V S3 Current Sense (IR1C)Gain: 500x. EDP: 1.8 A

Rsense: 0.005 (RD170)


ADC Range: 0V to 4.096V

Rsense: 0.003 (RD164)

Debug ADCI2C Address: 0x10 / 0x11

Divider: ~1/22

Gain needed: 611x


LSB: 0.001V

Rsense: 0.005 (RD120)

Gain: 500x. EDP: 0.7 A

LCD Backlight Current Sense (IBLC)

Gain needed: 942x


LCD Backlight Voltage Sense (VBLC)

Gain: 500x. EDP: 1.0 A

GPU 3.3V S0 Current Sense (IG2C)

Gain needed: 660x

Rsense: 0.005 (RD140)

Gain needed: 220x

T29 Current Sense (IHSP)Gain: 215.5x. EDP: 3 A


PLACE_NEAR=UD100.1:5MMDEBUG_ADC

1/20W1%

201MF

324K

0201-MUR


1.0UF

X5R

20%6.3V

104

DEBUG_ADC

10

MF-LF

5%1/16W

402

CERM

DEBUG_ADC

0.1UF

402

20%10V

DEBUG_ADC

10UF

X5R603

20%6.3V

LTC2309

DEBUG_ADC

QFN

DEBUG_ADC

0.1UF

CERM402

20%10V

10UF

603

20%6.3VX5R

DEBUG_ADC

PLACE_NEAR=U4900.K8:10MMDEBUG_ADC

33

402

5%

MF-LF1/16W

DEBUG_ADC

0.1UF

CERM402

20%10V

DEBUG_ADC

10UF

X5R603

20%6.3V

DEBUG_ADC

2.2UF

CERM402-LF

20%6.3V

DEBUG_ADCPLACE_NEAR=U4900.L8:10MM

33

MF-LF1/16W5%

402

48

48

DEBUG_ADC

10

MF-LF402

5%1/16W

90

7 90

DEBUG_ADC

46.4K

MF-LF402

1%1/16W

20%

DEBUG_ADC

0.1UF

CERM402

10V

X5R6.3V20%1.0UF

0201-MUR


PLACE_NEAR=UD100.22:5MM

324K

MF201

1%1/20W

DEBUG_ADC

104

SM

1M

MF-LF402

1%1/16W

DEBUG_ADC

324K


1/20W1%

201MF

0201-MUR

20%1.0UF


X5R6.3V

104

7 34

7

4.64K

1/20W1%

201MF

DEBUG_ADC

4.64K

1/20W1%

201MF

DEBUG_ADC 1/20W1%

201MF

1M

DEBUG_ADC

SIGNAL_MODEL=EMPTY DEBUG_ADC

SIGNAL_MODEL=EMPTY201

1/20W1%

MF

1M


1/20W1%

324K

201MF

0201-MUR

1.0UF20%6.3V


X5R

104

SC70-5

DEBUG_ADC

OPA333DCKG4

10V20%

402CERM

0.1UF

DEBUG_ADC

10V20%

402CERM

0.1UF

DEBUG_ADC7 49 103 104

7 DEBUG_ADC

SC70INA211

DEBUG_ADC

INA211SC70

7

7

DEBUG_ADC

SC70INA211

201

324K

MF

1%1/20W


DEBUG_ADC402CERM

20%0.1UF

10V

0201-MUR

1.0UF

6.3V20%

X5R

PLACE_NEAR=UD100.3:5MM

DEBUG_ADC

104

SM

SM

SM

SM


Power Sensors: Debug ADC

NC_ISNS_TBTN

NC_ISNS_TBTP

NC_ISNS_PP3V3_S3N

NC_ISNS_PP3V3_S3P

=PP1V05_TBT_RTR_R

=PP1V05_TBT_RTR

=PP3V3_S3_ISNS

=PP3V3_S3_ISNS_R

NC_ISNS_PP3V3_S0GPUN

ADC_CH3

NC_ISNS_PP3V3_S0GPUP

=PP3V3_S0_ISNS

=PP3V3_S0GPU_ISNS

=PP3V3_S0GPU_ISNS_R

VOUT_S0_LCDBKLT_XW

=PP3V3_S0_ISNS

NC_ISNS_LCDBKLTP

NC_ISNS_LCDBKLTN

=PPBUS_SW_BKL


VOUT_S0_LCDBKLT_DIV

ADC_CH4

ADC_CH2

ISNS_PP3V3_S3_IOUT ADC_CH3

ADC_CH2

ISNS_TBT_R_N

ISNS_TBT_R_P

=PP3V3_S0_ISNS

ISNS_TBT_IOUT

ADC_VREF

ISNS_LCDBKLT_IOUT

ADC_CH7

ADC_CH6

ADC_CH5

=I2C_SMC_ADCS_SDA

PP5V_S5_DEBUG_ADC_DVDD_FILT

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2 MM

ADC_SDA

ADC_REFCOMP

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2 MM

PP5V_S5_DEBUG_ADC_AVDD_FILT =PP5V_S5_DEBUG_ADC_DVDD

ADC_SCL =I2C_SMC_ADCS_SCL

ADC_CH0

PPVOUT_S0_LCDBKLT

ADC_CH5ISNS_PP3V3_S0GPU_IOUT

=PP5V_S5_DEBUG_ADC_AVDD

ADC_CH0

=PP3V3_S3_ISNS

ADC_CH1

ADC_CH4

RD1691 2

CD1691

2

RD1031 2

CD1001

2

CD1011

2

UD100

14

15

12

13

22

23

24

1

2

3

4

5

6

21

9

10

11

18

19

20

8

16

17

25

7

CD1041

2

CD1051

2

RD1011 2

CD1021

2

CD1031

2

CD1061

2

RD1021 2

RD1041 2

RD1571

2

CD1201

2

CD1291

2

RD1291 2

XWD150

1 2

RD1561

2

RD1591 2

CD1591

2

RD1411 2

RD1421 2

RD1431

2

RD1441 2

RD1491 2

CD1491

2

UD140

1

3

4

2

5

CD1401

2

CD1601

2

UD160

2

5

4

6

1

3

UD120

2

5

4

6

1

3

UD170

2

5

4

6

1

3

RD1791 2

CD1701

2

CD1791

2

XWD120

1

2

XWD170

1

2

XWD160

1

2

XWD140

1

2

051-9585

3.0.0

131 OF 132

104 OF 105

104

7 49 50 103 104

7 49 50 103 104

104

104

101

7 49 50 103 104

8

8

104

7

105

6 8 85

7

104

7 49 103 104

OUTV-

V+

V-

V+

Apple Inc.


124578

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SHEET


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DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



CPU Rippler Voltage Sense (VCRP)

MF402

0.1%11K

1/16W

CPURIPPLE_ENGCPURIPPLE_ENG

0.1UF

X5R402-1

10%16V

CPURIPPLE_ENG

10UF

CERM-X5R0402

20%6.3V

PLACE_NEAR=UD100.23:5MMCPURIPPLE_ENG

1.0UF6.3V20%

X5R0201-MUR

PLACE_NEAR=UD100.23:5MMCPURIPPLE_ENG

1/20W

324K

1%

MF201

100

MF-LF402

5%1/16W

CPURIPPLE_ENG

CPURIPPLE_ENG

1K

MF-LF402

1%1/16W

CPURIPPLE_ENG

PLACE_NEAR=RD305.1:5MM

10

MF-LF402

5%1/16W

0.1UF

CPURIPPLE_ENG

16V10%

402-1X5R

CPURIPPLE_ENG

10UF

CERM-X5R0402

20%6.3V

BAT54XV2T1

SOD-523CPURIPPLE_ENG

104

CPURIPPLE_ENG

1UF

X5R402

10%16V

PLACE_NEAR=RD305.1:5MM

CPURIPPLE_ENG

OPA2365SO-8

CPURIPPLE_ENG

OPA2365SO-8

SIGNAL_MODEL=EMPTY

SM

PLACE_NEAR=CD310.1:2MM

CPURIPPLE_ENG

BAT54XV2T1

SOD-523

402

0.1%1/16W

MF

1.00K

CPURIPPLE_ENG

CPURIPPLE_ENG

402

1.00K0.1%

1/16WMF

120OHM-0.3A

0402

CPURIPPLE_ENG

CPURIPPLE_ENG

10.2

TF402

0.1%1/16W

CPURIPPLE_ENG

0.1%

10.2

402TF

1/16W

CPURIPPLE_ENG

11K

MF402

0.1%1/16W


Power Sensors: CPU Ripple


PP1V05_S0_RMC_R

VOLTAGE=1.05V

VOLTAGE=5VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMPP5V_S0_RMC_FLT=PP5V_S0_RMC

NO_TEST=TRUECOMP_CPU_VCORE_RMC

1V05_S0_RMC_DIVNO_TEST=TRUE

CPU_VCORE_C

NO_TEST=TRUECPU_VCORE_RMC_DIV

CPU_VCORE_RMC_NNO_TEST=TRUE

=PPVCORE_S0_CPU

VSNS_CPU_VCORE_RMC_OUTNO_TEST=TRUE

ADC_CH1

VOLTAGE=1.1VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMPPVCORE_S0_RMC

=PP1V05_S0_RMC

CPU_VCORE_RMC_P

DD200A K

DD201A KRD205

1 2

RD2061 2

RD2011

2

RD2021

2

CD205 1

2

CD204 1

2

CD2201

2

RD2201 2

RD2001 2

RD2081 2

RD2071 2

CD201 1

2

CD2001

2

CD210

1 2

UD2003

2

1

4

8UD200

5

6

7

4

8

XWD200

12

RD2031

2

RD2041

2

LD200

1 2

051-9585

3.0.0

132 OF 132

105 OF 105

7

101

7 12 14 49

7

101

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