sc integrators

7/27/2019 SC Integrators

1/13

PRG, Gain blocks, 1

Switched-Capacitor Integrator/Gain Blocks

Idealized view

Fundamental Performance Limitations

Practical Performance Limitations

Gain Blocks for Low Voltage/Low Power


2/13

PRG, Gain blocks, 2

Basic Integrator/Gain Functions

Integrating Gain Block:

Vi2

Vi1

C1 C2

Von = -[Von-1 + (Vi1n-Vi1n-1)]C1/C2 + Vi2n-1(Cs/C2)]

C1 C2

Vi

Von = -C1/C2 (Vin-1)

2

1

1

1

2

2

1

2

Reset Gain Block:

1

1


3/13

PRG, Gain blocks, 3

Important Deviations from Ideality:

Gain Errors

Capacitor Ratio Errors

Capacitive Parasitics in Feedback Path

Finite Op Amp Gain

DC. Offset Errors

Op amp offset

Charge Injection offsets

Transient Errors

Operational Amplifier Settling


4/13

PRG, Gain blocks, 4

Key Issue: What is the fastest attainable settling?

Simplest possible op amp:

Cs

Cf

Cl

Cs

Cgs

Cl Cp

Cf+Cgd=Cft

Cl+Cp =CLtThis is a single-time-constant circuit!

1g

m

Cs

Cgs

+( ) 1 1C

FtC

gs

C

s

++

C

LtC

Ft

+=

12f

t1

Cs

Cgs

+

1 1C

FtC

gsC

s+

+

C

LtC

Ft+=

12f

t1

CLt

CFt

+=

Device Width and Drain Current

Fixed Vgs-Vt


5/13

PRG, Gain blocks, 5

Max Attainable Speed, Contd

Assume Cgs=Cs as a practical design choice

22f

t1 1

CFt

2Cs

+

C

LtC

Ft+=

22f

t1 1

2A

v+

CLt

CS

+= Where Av = Voltage Gain of circuit

1.0u 1.5u 3u

0.1ns0.2ns

0.5ns

Assumptions:

1. Square law applies

2. No slewing

3. Vgs-Vt = 0.5V

4. Neglects all second order device

effects.

5. Av = 1, Cl=Cf

0.8u


6/13

PRG, Gain blocks, 5.1

Two Important Limiting Cases

Cs/Cf>>1, As in Reset Gain Blocks in Pipelines

22ft

1

C

LCF

+

22ft

1 aq+( )= =

Cs/Cf


7/13

PRG, Gain blocks, 6

Max Attaninable Speed, Contd

Shortcomings of 1-T Op Amp

Not enough gain

No level shift

Single-ended- PSRR=0

Other Important Points:

Slew rate will degrade 2-5x

Time constants of external switches will degrade speed

Short-channel effects have major effect on channel mobility

Key Question: Can more complex op amps go faster?


8/13

PRG, Gain blocks, 7

Max Attainable Speed, Contd

What about multi-stage realizations?

av

gmro

av(gmro)

3

2 ft

2

CS

CL

2

f

t2

C

SC

L

Cs CL

CsCL

fu

fu

Key Points:

Unity current gain at same freq for multistage as singlestage

If CL>>CS or Av>1, then multistage is useful


9/13

PRG, Gain blocks, 8

Improving Gain in Gain Block Amplifiers

For 1-T amp,

av

gm

ro

2VAV

gsV

T

2 Leffdx

ddV

ds

Vgs

VT

( ) 1 2 10V( )0.5V

40= = = =

Approaches to the Gain Problem:

1. CascodingBias

Bias

Bias

Vin

Voutav = [Va / (Vgs-VT)]2

Not really enough for 8 bit applications, at high

speeds where channel lengths are short and

Vgs-Vt has to be reasonably high.


10/13

PRG, Gain blocks, 9

Gain improvements, Contd

rout

gm

ro

( )2

ro

Bias or Vin

2. Series Feedback

Challenge is getting enough swingfor low-voltage operation

Works well in BICMOS to get Hi-ZPMOS current sources.

Sackinger- JSC 2/90

Bult, ISSCC90


11/13

PRG, Gain blocks, 10

Circuit Improvements, Contd

Bias

Bias

Bias

Bias

Vi+

Vi-

Vo+

Vo-

Unfolded Cascode Op Amp

Best raw speed at lowclosed-loop gains

Limited Swing- no goodfor low voltage

Level Shift in Input C-Mcaps

Requires CMFB

Input Preamp improvesspeed for Acl>1 or 2


12/13


Gain Block Approaches for Low Voltage (3V)

Design Issues:

Clock Swing/Transmission Gate Design

Amplifier Output Swing

Degradation of Dynamic Range

Potential Solutions:

Low- VT devices in technology

Bootstrapped clocks for xmission gates

Two-stage op amps, Optimized Pole Split Compensation

Three-Stage op amps, Nested Compensation

Current-mode operation


13/13


Summary of Performance Limitations

Sample/Hold

Comparator

Gain Block

DAC

VL

2

2=

SN

s i g n a lkT

=

td

L2

Vgd VT( )lnG=

td

L2

Vgd

VT

( )1 A

Q+( )=

td

gm

C

gs

C

L

+

=

di

ao

sc integrators

Documents