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Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residues
Seyed Hamed Fatemi Langroudi & Ghassem Jaberipur
Computer Science & Engineering Department
Shahid Beheshti University, Tehran, Iran
1
SBU - Tehran ENSL - Lyon
22 th IEEE symposium on Computer Arithmetic
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
• Contribution
• RNS in General
• Summery of Modulo Addition
• New Modulo 2𝑛 − 2𝑞 − 1 Adders
• Comparison
• Conclusion
2 ARITH 22
Outline
3
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Contribution
ARITH 22
Modulo Delay(∆𝑮) Area(𝓐𝑮) EM Encoding
2𝑛 − 1 ,3- 3 + 2 log 𝑛 3𝑛 log 𝑛 + 4𝑛 0
3
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo-addition
Contribution
ARITH 22
Modulo Delay(∆𝑮) Area(𝓐𝑮) EM Encoding
2𝑛 − 1 ,3- 3 + 2 log 𝑛 3𝑛 log 𝑛 + 4𝑛 0
3
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo-addition
Contribution
ARITH 22
2𝑛 − 3 ,13- 4 + 2 log 𝑛 3 𝑛 − 1 log(𝑛 − 1) + 8𝑛 − 1 *0, 1, 2+
Modulo Delay(∆𝑮) Area(𝓐𝑮) EM Encoding
2𝑛 − 1 ,3- 3 + 2 log 𝑛 3𝑛 log 𝑛 + 4𝑛 0
3
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo-addition
Contribution
ARITH 22
2𝑛 − 3 ,13- 4 + 2 log 𝑛 3 𝑛 − 1 log(𝑛 − 1) + 8𝑛 − 1 *0, 1, 2+
2𝑛 − 2𝑞 − 1 ,10- 7 + 2 log 𝑛 ≤ 3𝑛 log 𝑛 + 7𝑛 − 1 + 1.5(𝑛 − 3) log(𝑛 − 3) none
Modulo Delay(∆𝑮) Area(𝓐𝑮) EM Encoding
2𝑛 − 1 ,3- 3 + 2 log 𝑛 3𝑛 log 𝑛 + 4𝑛 0
3
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo-addition
Contribution
ARITH 22
2𝑛 − 3 ,13- 4 + 2 log 𝑛 3 𝑛 − 1 log(𝑛 − 1) + 8𝑛 − 1 *0, 1, 2+
2𝑛 − 2𝑞 − 1 ,10- 7 + 2 log 𝑛 ≤ 3𝑛 log 𝑛 + 7𝑛 − 1 + 1.5(𝑛 − 3) log(𝑛 − 3) none
2𝑛 − 2𝑞 − 1 5 + 2 log 𝑛 ≤ 3𝑛 log 𝑛 + 7𝑛 − 1 + 1.5 𝑛 − 3 log 𝑛 − 3
+𝑛 − 3 log 𝑛 − 4 ,0,2𝑞-
Modulo Delay(∆𝑮) Area(𝓐𝑮) EM Encoding
2𝑛 − 1 ,3- 3 + 2 log 𝑛 3𝑛 log 𝑛 + 4𝑛 0
3
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo-addition
Contribution
ARITH 22
2𝑛 − 3 ,13- 4 + 2 log 𝑛 3 𝑛 − 1 log(𝑛 − 1) + 8𝑛 − 1 *0, 1, 2+
2𝑛 − 2𝑞 − 1 ,10- 7 + 2 log 𝑛 ≤ 3𝑛 log 𝑛 + 7𝑛 − 1 + 1.5(𝑛 − 3) log(𝑛 − 3) none
2𝑛 − 2𝑞 − 1 5 + 2 log 𝑛 ≤ 3𝑛 log 𝑛 + 7𝑛 − 1 + 1.5 𝑛 − 3 log 𝑛 − 3
+𝑛 − 3 log 𝑛 − 4 ,0,2𝑞-
𝐴 new ≤ 𝐴(,10-) 𝑛 ≤ 16
• RNS in General
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• RNS in General
• e.g.
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
• RNS in General
• e.g.
• RNS Architecture
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
X
z1 z2 z3
Z
Binary to RNS
x1 x2 x3 y1 y2 y3
Modulo 3
operation
Modulo 4
operation
Modulo 5
operation
RNS to Binary
Y
(e.g.,{3,4,5})
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
• RNS in General
• e.g.
• RNS Architecture
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
X
z1 z2 z3
Z
Binary to RNS
x1 x2 x3 y1 y2 y3
Modulo 3
operation
Modulo 4
operation
Modulo 5
operation
RNS to Binary
Y7 23
(e.g.,{3,4,5})
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
• RNS in General
• e.g.
• RNS Architecture
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
X
z1 z2 z3
Z
Binary to RNS
x1 x2 x3 y1 y2 y3
Modulo 3
operation
Modulo 4
operation
Modulo 5
operation
RNS to Binary
Y7
2 3 3 1 3 2
23
(e.g.,{3,4,5})
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
• RNS in General
• e.g.
• RNS Architecture
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
X
z1 z2 z3
Z
Binary to RNS
x1 x2 x3 y1 y2 y3
Modulo 3
operation
Modulo 4
operation
Modulo 5
operation
RNS to Binary
Y7
2 3 3 1 3 2
Modulo 3
Addition
Modulo 4
Addition
Modulo 5
Addition
23
(e.g.,{3,4,5})
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
• RNS in General
• e.g.
• RNS Architecture
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
X
z1 z2 z3
Z
Binary to RNS
x1 x2 x3 y1 y2 y3
Modulo 3
operation
Modulo 4
operation
Modulo 5
operation
RNS to Binary
Y7
2 3 3 1 3 2
Modulo 3
Addition
Modulo 4
Addition
Modulo 5
Addition
0 2 0
30
23
(e.g.,{3,4,5})
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
• RNS in General
• e.g.
• RNS Architecture
• RNS Advantage
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
• RNS in General
• e.g.
• RNS Architecture
• RNS Advantage
Addition & Multiplication
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
• RNS in General
• e.g.
• RNS Architecture
• RNS Advantage
Addition & Multiplication
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
O log(𝑛
𝑘)
• RNS in General
• e.g.
• RNS Architecture
• RNS Advantage
Addition & Multiplication
• RNS Disadvantage
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
O log(𝑛
𝑘)
• RNS in General
• e.g.
• RNS Architecture
• RNS Advantage
Addition & Multiplication
• RNS Disadvantage
Comparison & Division
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
O log(𝑛
𝑘)
• RNS in General
• e.g.
• RNS Architecture
• RNS Advantage
Addition & Multiplication
• RNS Disadvantage
Comparison & Division
• RNS In Application
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
O log(𝑛
𝑘)
• RNS in General
• e.g.
• RNS Architecture
• RNS Advantage
Addition & Multiplication
• RNS Disadvantage
Comparison & Division
• RNS In Application
Digital Signal Processing
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
O log(𝑛
𝑘)
• RNS in General
• e.g.
• RNS Architecture
• RNS Advantage
Addition & Multiplication
• RNS Disadvantage
Comparison & Division
• RNS In Application
Digital Signal Processing
Fault Tolerant System
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
O log(𝑛
𝑘)
• RNS in General
• e.g.
• RNS Architecture
• RNS Advantage
Addition & Multiplication
• RNS Disadvantage
Comparison & Division
• RNS In Application
Digital Signal Processing
Fault Tolerant System
Cryptography
4
𝑅 = *𝑚𝑘−1, … ,𝑚1, 𝑚0}, 𝐷𝑅 = 𝑚𝑘𝑖=𝑘−1𝑖=0
𝑋𝜖𝑅, 𝑋 = ( 𝑋 𝑚𝑘−1, … , 𝑋 𝑚1
, 𝑋 𝑚0)
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑹 = *𝟐𝒏 − 𝟏, 𝟐𝒏, 𝟐𝒏 + 𝟏+
O log(𝑛
𝑘)
5
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 1
ARITH 22
5
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 1
𝑋 + 𝑌 2𝑛−1 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛 − 1𝑋 + 𝑌 + 1 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛 − 1
Conventional
ARITH 22
5
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 1
𝑋 + 𝑌 2𝑛−1 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛 − 1𝑋 + 𝑌 + 1 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛 − 1
Conventional
Adder A
Adder B
Mux
2 nX Y
2 21 n nX Y
AC
BC
X Y
1 0
1
2 1 nX Y
RCA
ARITH 22
5
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 1
𝑋 + 𝑌 2𝑛−1 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛 − 1𝑋 + 𝑌 + 1 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛 − 1
Conventional EM Encoding
𝑋 + 𝑌 2𝑛−1 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛
𝑋 + 𝑌 + 1 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛
Adder A
Adder B
Mux
2 nX Y
2 21 n nX Y
AC
BC
X Y
1 0
1
2 1 nX Y
RCA
ARITH 22
5
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 1
𝑋 + 𝑌 2𝑛−1 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛 − 1𝑋 + 𝑌 + 1 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛 − 1
Conventional EM Encoding
𝑋 + 𝑌 2𝑛−1 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛
𝑋 + 𝑌 + 1 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛
Adder A
Adder B
Mux
2 nX Y
2 21 n nX Y
AC
BC
X Y
1 0
1
2 1 nX Y
AdderoutC
X Y
n2 1X Y
RCA RCA
ARITH 22
6
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
6
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Parallel Prefix Network(PPN) pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0
(g0,p0)(g1,p1)(g2,p2)(g3,p3)(g4,p4)(g5,p5)(g6,p6)(g7,p7)
G7:0
6
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Parallel Prefix Network(PPN) pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0
(g0,p0)(g1,p1)(g2,p2)(g3,p3)(g4,p4)(g5,p5)(g6,p6)(g7,p7)
G7:0
p g h
x yxyx y
x y
6
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Parallel Prefix Network(PPN) pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0
(g0,p0)(g1,p1)(g2,p2)(g3,p3)(g4,p4)(g5,p5)(g6,p6)(g7,p7)
G7:0
,G P
,G P
p g h
x yxyx y
x y
6
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Parallel Prefix Network(PPN) pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0
(g0,p0)(g1,p1)(g2,p2)(g3,p3)(g4,p4)(g5,p5)(g6,p6)(g7,p7)
G7:0
,G P
,G P
p g h
x yxyx y
x y ,G P ,r rG P
( )rG P G
6
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Parallel Prefix Network(PPN) pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0
(g0,p0)(g1,p1)(g2,p2)(g3,p3)(g4,p4)(g5,p5)(g6,p6)(g7,p7)
G7:0
,G P
,G P
p g h
x yxyx y
x y
( , )r rG P G P P
,G P ,r rG P ,G P ,r rG P
( )rG P G
6
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Parallel Prefix Network(PPN)
Modulo- 2𝑛 − 1 EM Encoding
Parallel prefix Adder
pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0
(g0,p0)(g1,p1)(g2,p2)(g3,p3)(g4,p4)(g5,p5)(g6,p6)(g7,p7)
G7:0
,G P
,G P
p g h
x yxyx y
x y
( , )r rG P G P P
,G P ,r rG P ,G P ,r rG P
( )rG P G
6
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Parallel Prefix Network(PPN)
Modulo- 2𝑛 − 1 EM Encoding
Parallel prefix Adder
pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0
(g0,p0)(g1,p1)(g2,p2)(g3,p3)(g4,p4)(g5,p5)(g6,p6)(g7,p7)
G7:0
pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
c3c4c5c6
h3
c7
h4h5h6h7 h2
c2 c1
h1
pgh pgh pghh0
G7:0 (G6:0,P6:0) (G5:0,P5:0)(G4:0,P4:0) (G3:0,P3:0) (G2:0,P2:0) (G1:0,P1:0) (G0:0,P0:0)
s0s1s2s3s4s5s6s7
,G P
,G P
p g h
x yxyx y
x y
( , )r rG P G P P
,G P ,r rG P ,G P ,r rG P
( )rG P G
6
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Parallel Prefix Network(PPN)
Modulo- 2𝑛 − 1 EM Encoding
Parallel prefix Adder
pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
G6:0 G5:0 G4:0 G3:0 G2:0 G1:0 G0:0
(g0,p0)(g1,p1)(g2,p2)(g3,p3)(g4,p4)(g5,p5)(g6,p6)(g7,p7)
G7:0
pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
c3c4c5c6
h3
c7
h4h5h6h7 h2
c2 c1
h1
pgh pgh pghh0
G7:0 (G6:0,P6:0) (G5:0,P5:0)(G4:0,P4:0) (G3:0,P3:0) (G2:0,P2:0) (G1:0,P1:0) (G0:0,P0:0)
s0s1s2s3s4s5s6s7
,G P
,G P
p g h
x yxyx y
x y
( , )r rG P G P P
,G P ,r rG P ,G P ,r rG P
( )rG P G
7
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
7
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 3
ARITH 22
7
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 3
Conventional
𝑋 + 𝑌 2𝑛−3 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛 − 3𝑋 + 𝑌 + 3 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛 − 3
ARITH 22
7
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 3
Conventional
𝑋 + 𝑌 2𝑛−3 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛 − 3𝑋 + 𝑌 + 3 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛 − 3
Adder A
Adder B
Mux
2 nX Y
2 23 n nX Y
AC
BC
X Y
1 0
3
2 3 nX Y
RCA
ARITH 22
7
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 3
Conventional EM Encoding
𝑋 + 𝑌 2𝑛−3 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛 − 3𝑋 + 𝑌 + 3 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛 − 3
𝑋 + 𝑌 2𝑛−3 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛
𝑋 + 𝑌 + 3 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛
Adder A
Adder B
Mux
2 nX Y
2 23 n nX Y
AC
BC
X Y
1 0
3
2 3 nX Y
RCA
ARITH 22
7
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 3
Conventional EM Encoding
𝑋 + 𝑌 2𝑛−3 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛 − 3𝑋 + 𝑌 + 3 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛 − 3
𝑋 + 𝑌 2𝑛−3 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛
𝑋 + 𝑌 + 3 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛
Adder A
Adder B
Mux
2 nX Y
2 23 n nX Y
AC
BC
X Y
1 0
3
2 3 nX Y
n-bit Adder
(n,2)-bit Adder
outC
YX
n2X Y
n2 3X Y
RCA RCA
ARITH 22
8
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
8
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
8
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Modulo- 2𝑛 − 3 EM Encoding Parallel prefix Adder
8
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Modulo- 2𝑛 − 3 EM Encoding Parallel prefix Adder
pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
pgh pgh pghpghpgh
000000 w0w1w2w3w4w5w6w7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
s0s1s2s3s4s5s6s7
1ac2
ac3ac4
ac5ac6
ac7ac
aaaaaaaa
bbbbbbbb
1bc2
bc3bc4
bc5bc6
bc7bc
7:0G
7:0G 7:0G
7:0G
8
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Modulo- 2𝑛 − 3 EM Encoding Parallel prefix Adder
pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
pgh pgh pghpghpgh
000000 w0w1w2w3w4w5w6w7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
s0s1s2s3s4s5s6s7
1ac2
ac3ac4
ac5ac6
ac7ac
aaaaaaaa
bbbbbbbb
1bc2
bc3bc4
bc5bc6
bc7bc
7:0G
7:0G 7:0G
7:0G
8
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Modulo- 2𝑛 − 3 EM Encoding Parallel prefix Adder
HA
pgh pgh pgh pghpghpg′h
HAHA HA HA HA HAHA
x0x1x2x3x4x5x6x7 y0y1y2y3y4y5y6y7
u1u2u3u4u5u6u7 v1v2v3v4v5v6v7
(g2,p2)(g3,p3)(g4,p4)(g5,p5)(g6,p6)(g 7,p7) (g1,p′1)
(G2:0,P′2:0)(G3:0,P
′3:0)(G4:0,P
′4:0)(G5:0,P
′5:0)(G6:0,P
'6:0)
G' 7:0
c3c4c5c6
h3
c7
h4h5h6h7
s2s3s4s5s6s7
(G1:0,P′1:0)
c2
p´gh
s1
c1
h2 h1
h0
s0
u0v8
HA p g h
x yxy u vuvu v1 1u v
x u1uy v1v ,G P ,r rG P
,r rG P G P PrG P G
,G P ,r rG P ,G P
,G P 0 1 1 u v u
0u
1 1u v
p´ g h p g´ h
7u 7v8v
7 7u v7 7u v 7 7 8u v v
8
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Modulo- 2𝑛 − 3 EM Encoding Parallel prefix Adder
HA
pgh pgh pgh pghpghpg′h
HAHA HA HA HA HAHA
x0x1x2x3x4x5x6x7 y0y1y2y3y4y5y6y7
u1u2u3u4u5u6u7 v1v2v3v4v5v6v7
(g2,p2)(g3,p3)(g4,p4)(g5,p5)(g6,p6)(g 7,p7) (g1,p′1)
(G2:0,P′2:0)(G3:0,P
′3:0)(G4:0,P
′4:0)(G5:0,P
′5:0)(G6:0,P
'6:0)
G' 7:0
c3c4c5c6
h3
c7
h4h5h6h7
s2s3s4s5s6s7
(G1:0,P′1:0)
c2
p´gh
s1
c1
h2 h1
h0
s0
u0v8
HA p g h
x yxy u vuvu v1 1u v
x u1uy v1v ,G P ,r rG P
,r rG P G P PrG P G
,G P ,r rG P ,G P
,G P 0 1 1 u v u
0u
1 1u v
p´ g h p g´ h
7u 7v8v
7 7u v7 7u v 7 7 8u v v
9
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
9
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 2𝑞 − 1
ARITH 22
9
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 2𝑞 − 1
Conventional
𝑋 + 𝑌 2𝑛−2q−1 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛 − (2𝑞 + 1)
𝑋 + 𝑌 + 2q + 1 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛 − (2𝑞 + 1)
ARITH 22
9
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 2𝑞 − 1
Conventional
𝑋 + 𝑌 2𝑛−2q−1 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛 − (2𝑞 + 1)
𝑋 + 𝑌 + 2q + 1 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛 − (2𝑞 + 1)
Adder A
Adder B
Mux
2 nX Y
2 22 1n n
qX Y
AC
BC
X Y
1 0
2 1q
2 2 1n qX Y
RCA
ARITH 22
9
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 2𝑞 − 1
EM Encoding Conventional
𝑋 + 𝑌 2𝑛−2q−1 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛 − (2𝑞 + 1)
𝑋 + 𝑌 + 2q + 1 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛 − (2𝑞 + 1) 𝑋 + 𝑌 2𝑛−2q−1 =
𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛
𝑋 + 𝑌 + 2q + 1 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛
Adder A
Adder B
Mux
2 nX Y
2 22 1n n
qX Y
AC
BC
X Y
1 0
2 1q
2 2 1n qX Y
RCA
ARITH 22
9
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo 2𝑛 − 2𝑞 − 1
EM Encoding Conventional
𝑋 + 𝑌 2𝑛−2q−1 = 𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛 − (2𝑞 + 1)
𝑋 + 𝑌 + 2q + 1 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛 − (2𝑞 + 1) 𝑋 + 𝑌 2𝑛−2q−1 =
𝑋 + 𝑌, if 𝑋 + 𝑌 < 2𝑛
𝑋 + 𝑌 + 2q + 1 2𝑛 , if 𝑋 + 𝑌 ≥ 2𝑛
Adder A
Adder B
Mux
2 nX Y
2 22 1n n
qX Y
AC
BC
X Y
1 0
2 1q
2 2 1n qX Y
n-bit Adder
(n,q+1)-bit Adder
outC
YX
n2X Y
n q2 2 1X Y
RCA RCA
ARITH 22
10
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
10
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Modulo- 2𝑛 − 2𝑞 − 1 EM Parallel prefix Adder(𝑛 = 8, 𝑞 = 4)
pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
pgh pgh pghpghpgh
000000 w0w1w2w3w4w5w6w7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
s0s1s2s3s4s5s6s7
1ac2
ac3ac4
ac5ac6
ac7ac
aaaaaaaa
bbbbbbbb
1bc2
bc3bc4
bc5bc6
bc7bc
7:0G
7:0G 7:0G
7:0G
10
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Modulo- 2𝑛 − 2𝑞 − 1 EM Parallel prefix Adder(𝑛 = 8, 𝑞 = 4)
pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
pgh pgh pghpghpgh
000000 w0w1w2w3w4w5w6w7
h3h4h5h6h7 h2 h1
pgh pgh pghh0
s0s1s2s3s4s5s6s7
1ac2
ac3ac4
ac5ac6
ac7ac
aaaaaaaa
bbbbbbbb
1bc2
bc3bc4
bc5bc6
bc7bc
7:0G
7:0G 7:0G
7:0G
10
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Parallel Prefix Realization
Modulo- 2𝑛 − 2𝑞 − 1 EM Parallel prefix Adder(𝑛 = 8, 𝑞 = 4)
11
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑿 𝒙𝒏−𝟏 … 𝒙𝒒 … 𝒙𝟏 𝒙𝟎
𝒀 𝒚𝒏−𝟏 … 𝒚𝒒 … 𝒚𝟏 𝒚𝟎
11
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑿 𝒙𝒏−𝟏 … 𝒙𝒒 … 𝒙𝟏 𝒙𝟎
𝒀 𝒚𝒏−𝟏 … 𝒚𝒒 … 𝒚𝟏 𝒚𝟎
𝑬𝑨𝑪 = 𝑿 + 𝒀 𝐰𝐧−𝟏 … 𝐰𝐪 … 𝐰𝟏 𝒘𝟎 𝒘𝒏
11
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑿 𝒙𝒏−𝟏 … 𝒙𝒒 … 𝒙𝟏 𝒙𝟎
𝒀 𝒚𝒏−𝟏 … 𝒚𝒒 … 𝒚𝟏 𝒚𝟎
𝑺 𝐒𝐧−𝟏 … 𝐒𝐪 … 𝐒𝟏 𝑺𝟎
𝜹 𝑬𝑨𝑪 𝒘𝒏
𝜹 = 2q + 1 𝒘𝒏
11
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑿 𝒙𝒏−𝟏 … 𝒙𝒒 … 𝒙𝟏 𝒙𝟎
𝒀 𝒚𝒏−𝟏 … 𝒚𝒒 … 𝒚𝟏 𝒚𝟎
𝑺 𝐒𝐧−𝟏 … 𝐒𝐪 … 𝐒𝟏 𝑺𝟎
𝜹 𝑬𝑨𝑪
(𝑒. 𝑔. 𝑛 = 8 𝑞 = 4)
𝜹 = 2q + 1 𝒘𝒏
𝒘𝒏
11
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑿 𝒙𝒏−𝟏 … 𝒙𝒒 … 𝒙𝟏 𝒙𝟎
𝒀 𝒚𝒏−𝟏 … 𝒚𝒒 … 𝒚𝟏 𝒚𝟎
𝑺 𝐒𝐧−𝟏 … 𝐒𝐪 … 𝐒𝟏 𝑺𝟎
𝜹 𝑬𝑨𝑪
Input Collective value
(𝑥𝑞 , 𝑦𝑞 , 𝑤𝑛 , 𝐶𝑞) 𝐶𝑞+1
𝑋 = 10010001 4 2
𝑌 = 10011111
(𝑒. 𝑔. 𝑛 = 8 𝑞 = 4)
𝜹 = 2q + 1 𝒘𝒏
𝒘𝒏
11
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑿 𝒙𝒏−𝟏 … 𝒙𝒒 … 𝒙𝟏 𝒙𝟎
𝒀 𝒚𝒏−𝟏 … 𝒚𝒒 … 𝒚𝟏 𝒚𝟎
𝑺 𝐒𝐧−𝟏 … 𝐒𝐪 … 𝐒𝟏 𝑺𝟎
𝜹 𝑬𝑨𝑪
Input Collective value
(𝑥𝑞 , 𝑦𝑞 , 𝑤𝑛 , 𝐶𝑞) 𝐶𝑞+1
𝑋 = 10010001 4 2
𝑌 = 10011111
𝑋 = 10010000 3 1
𝑌 = 10011110
(𝑒. 𝑔. 𝑛 = 8 𝑞 = 4)
𝜹 = 2q + 1 𝒘𝒏
𝒘𝒏
11
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
𝑿 𝒙𝒏−𝟏 … 𝒙𝒒 … 𝒙𝟏 𝒙𝟎
𝒀 𝒚𝒏−𝟏 … 𝒚𝒒 … 𝒚𝟏 𝒚𝟎
𝑺 𝐒𝐧−𝟏 … 𝐒𝐪 … 𝐒𝟏 𝑺𝟎
𝜹 𝑬𝑨𝑪
Input Collective value
(𝑥𝑞 , 𝑦𝑞 , 𝑤𝑛 , 𝐶𝑞) 𝐶𝑞+1
𝑋 = 10010001 4 2
𝑌 = 10011111
𝑋 = 10010000 3 1
𝑌 = 10011110
(𝑒. 𝑔. 𝑛 = 8 𝑞 = 4)
Problem: Variable -weight
carry on position 4
𝜹 = 2q + 1 𝒘𝒏
𝒘𝒏
12
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• How to solve variable-weight carry problem?
12
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• How to solve variable-weight carry problem?
Devise a partial carry-save preprocessing stage
12
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• How to solve variable-weight carry problem?
Devise a partial carry-save preprocessing stage
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝑿
𝒀 𝑋 + 𝑌 2𝑛−2𝑞−1
12
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• How to solve variable-weight carry problem?
Devise a partial carry-save preprocessing stage
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝑿′
𝒀′
𝑿
𝒀 𝑋 + 𝑌 2𝑛−2𝑞−1
ℎ𝑖 = 𝑥𝑖⨁𝑦𝑖
𝑔𝑖 = 𝑥𝑖𝑦𝑖
12
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• How to solve variable-weight carry problem?
Devise a partial carry-save preprocessing stage
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝑿′
𝒀′
𝑿
𝒀 𝑋 + 𝑌 2𝑛−2𝑞−1
ℎ𝑖 = 𝑥𝑖⨁𝑦𝑖
𝑔𝑖 = 𝑥𝑖𝑦𝑖
12
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• How to solve variable-weight carry problem?
Devise a partial carry-save preprocessing stage
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒉𝒏−𝟏 … 𝒉𝒒
𝒈𝒏−𝟏 𝒈𝒏−𝟐 … 0
𝑿′
𝒀′
𝑿
𝒀 𝑋 + 𝑌 2𝑛−2𝑞−1
ℎ𝑖 = 𝑥𝑖⨁𝑦𝑖
𝑔𝑖 = 𝑥𝑖𝑦𝑖
12
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• How to solve variable-weight carry problem?
Devise a partial carry-save preprocessing stage
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒉𝒏−𝟏 … 𝒉𝒒
𝒈𝒏−𝟏 𝒈𝒏−𝟐 … 0
𝑿′
𝒀′
𝑿
𝒀 𝑋 + 𝑌 2𝑛−2𝑞−1
ℎ𝑖 = 𝑥𝑖⨁𝑦𝑖
𝑔𝑖 = 𝑥𝑖𝑦𝑖
𝑒 = 𝑔𝑛−1 ∨ 𝐺𝑛−1:0′
12
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• How to solve variable-weight carry problem?
Devise a partial carry-save preprocessing stage
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒉𝒏−𝟏 … 𝒉𝒒
𝒈𝒏−𝟏 𝒈𝒏−𝟐 … 0
𝑿′
𝒀′
𝑿′ 𝒉𝒏−𝟏 … 𝒉𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒀′′ 𝒈𝒏−𝟐 … 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝜹 𝑬𝑨𝑪 𝒆 𝒆
𝑿
𝒀 𝑋 + 𝑌 2𝑛−2𝑞−1
ℎ𝑖 = 𝑥𝑖⨁𝑦𝑖
𝑔𝑖 = 𝑥𝑖𝑦𝑖
𝑒 = 𝑔𝑛−1 ∨ 𝐺𝑛−1:0′
12
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• How to solve variable-weight carry problem?
Devise a partial carry-save preprocessing stage
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒉𝒏−𝟏 … 𝒉𝒒
𝒈𝒏−𝟏 𝒈𝒏−𝟐 … 0
𝑿′
𝒀′
𝑿′ 𝒉𝒏−𝟏 … 𝒉𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒀′′ 𝒈𝒏−𝟐 … 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝜹 𝑬𝑨𝑪 𝒆 𝒆
𝒉𝐧−𝟏′ … 𝒉𝒒
′ 𝒉𝐪−𝟏′ … 𝒉𝟏
′ 𝒉𝟎′
𝒄𝒏−𝟏 … 𝒄𝒒 𝒄𝒒−𝟏 … 𝒄𝟏 𝒄𝟎
𝑿
𝒀 𝑋 + 𝑌 2𝑛−2𝑞−1
ℎ𝑖 = 𝑥𝑖⨁𝑦𝑖
𝑔𝑖 = 𝑥𝑖𝑦𝑖
𝑒 = 𝑔𝑛−1 ∨ 𝐺𝑛−1:0′
12
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• How to solve variable-weight carry problem?
Devise a partial carry-save preprocessing stage
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒉𝒏−𝟏 … 𝒉𝒒
𝒈𝒏−𝟏 𝒈𝒏−𝟐 … 0
𝑿′
𝒀′
𝑿′ 𝒉𝒏−𝟏 … 𝒉𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒀′′ 𝒈𝒏−𝟐 … 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝜹 𝑬𝑨𝑪 𝒆 𝒆
𝒉𝐧−𝟏′ … 𝒉𝒒
′ 𝒉𝐪−𝟏′ … 𝒉𝟏
′ 𝒉𝟎′
𝒄𝒏−𝟏 … 𝒄𝒒 𝒄𝒒−𝟏 … 𝒄𝟏 𝒄𝟎
𝑺 𝒔𝒏−𝟏 … 𝒔𝒒 𝒔𝒒−𝟏 … 𝒔𝟏 𝒔𝟎
𝑿
𝒀 𝑋 + 𝑌 2𝑛−2𝑞−1
ℎ𝑖 = 𝑥𝑖⨁𝑦𝑖
𝑔𝑖 = 𝑥𝑖𝑦𝑖
𝑒 = 𝑔𝑛−1 ∨ 𝐺𝑛−1:0′
12
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• How to solve variable-weight carry problem?
Devise a partial carry-save preprocessing stage
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒉𝒏−𝟏 … 𝒉𝒒
𝒈𝒏−𝟏 𝒈𝒏−𝟐 … 0
𝑿′
𝒀′
𝑿′ 𝒉𝒏−𝟏 … 𝒉𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒀′′ 𝒈𝒏−𝟐 … 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝜹 𝑬𝑨𝑪 𝒆 𝒆
𝒉𝐧−𝟏′ … 𝒉𝒒
′ 𝒉𝐪−𝟏′ … 𝒉𝟏
′ 𝒉𝟎′
𝒄𝒏−𝟏 … 𝒄𝒒 𝒄𝒒−𝟏 … 𝒄𝟏 𝒄𝟎
𝑺 𝒔𝒏−𝟏 … 𝒔𝒒 𝒔𝒒−𝟏 … 𝒔𝟏 𝒔𝟎
𝑿
𝒀
𝑐𝑖 =
𝑔𝑛−1 ∨ 𝐺𝑛−1:0′ , if 𝑖 = 0
𝐺𝑖−1:0′ ∨ 𝑃𝑖−1:0
′ (𝑔𝑛−1 ∨ 𝐺𝑛−1:0′ ), if 1 ≤ 𝑖 ≤ 𝑞
ℎ𝑞 ∨ 𝑒 𝑐𝑞 ∨ ℎ𝑞𝑒, if 𝑖 = 𝑞 + 1
𝐺𝑖−1:𝑞+1′ ∨ 𝑃𝑖−1:𝑞+1
′ 𝑐𝑞+1, if 𝑖 > 𝑞 + 1
𝑋 + 𝑌 2𝑛−2𝑞−1
ℎ𝑖 = 𝑥𝑖⨁𝑦𝑖
𝑔𝑖 = 𝑥𝑖𝑦𝑖
𝑒 = 𝑔𝑛−1 ∨ 𝐺𝑛−1:0′
𝑋′ + 𝑌′′ 2𝑛−2𝑞−1
12
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
• How to solve variable-weight carry problem?
Devise a partial carry-save preprocessing stage
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝒉𝒏−𝟏 … 𝒉𝒒
𝒈𝒏−𝟏 𝒈𝒏−𝟐 … 0
𝑿′
𝒀′
𝑿′ 𝒉𝒏−𝟏 … 𝒉𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒀′′ 𝒈𝒏−𝟐 … 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝜹 𝑬𝑨𝑪 𝒆 𝒆
𝒉𝐧−𝟏′ … 𝒉𝒒
′ 𝒉𝐪−𝟏′ … 𝒉𝟏
′ 𝒉𝟎′
𝒄𝒏−𝟏 … 𝒄𝒒 𝒄𝒒−𝟏 … 𝒄𝟏 𝒄𝟎
𝑺 𝒔𝒏−𝟏 … 𝒔𝒒 𝒔𝒒−𝟏 … 𝒔𝟏 𝒔𝟎
𝑿
𝒀
𝑐𝑖 =
𝑔𝑛−1 ∨ 𝐺𝑛−1:0′ , if 𝑖 = 0
𝐺𝑖−1:0′ ∨ 𝑃𝑖−1:0
′ (𝑔𝑛−1 ∨ 𝐺𝑛−1:0′ ), if 1 ≤ 𝑖 ≤ 𝑞
ℎ𝑞 ∨ 𝑒 𝑐𝑞 ∨ ℎ𝑞𝑒, if 𝑖 = 𝑞 + 1
𝐺𝑖−1:𝑞+1′ ∨ 𝑃𝑖−1:𝑞+1
′ 𝑐𝑞+1, if 𝑖 > 𝑞 + 1
Problem: Carry-save
Stage is on the
critical delay path
𝑋 + 𝑌 2𝑛−2𝑞−1
ℎ𝑖 = 𝑥𝑖⨁𝑦𝑖
𝑔𝑖 = 𝑥𝑖𝑦𝑖
𝑒 = 𝑔𝑛−1 ∨ 𝐺𝑛−1:0′
𝑋′ + 𝑌′′ 2𝑛−2𝑞−1
IWSSIP 2014 81
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22 13
IWSSIP 2014 82
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22 13
• How to solve Carry Save Stage Delay problem?
IWSSIP 2014 83
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22 13
• How to solve Carry Save Stage Delay problem?
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝑿
𝒀
𝑿′ 𝒉𝒏−𝟏 … 𝒉𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒀′′ 𝒈𝒏−𝟐 … 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝜹 𝑬𝑨𝑪 𝒆 𝒆
Finding a relative between the 𝐺, 𝑃 of 𝑋 + 𝑌 2𝑛−2𝑞−1 and 𝐺′, 𝑃′ of 𝑋′ + 𝑌′′ 2𝑛−2𝑞−1
(𝐺, 𝑃)
(𝐺′, 𝑃′)
IWSSIP 2014 84
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22 13
• How to solve Carry Save Stage Delay problem?
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝑿
𝒀
𝑿′ 𝒉𝒏−𝟏 … 𝒉𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒀′′ 𝒈𝒏−𝟐 … 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝜹 𝑬𝑨𝑪 𝒆 𝒆
Finding a relative between the 𝐺, 𝑃 of 𝑋 + 𝑌 2𝑛−2𝑞−1 and 𝐺′, 𝑃′ of 𝑋′ + 𝑌′′ 2𝑛−2𝑞−1
(𝑮𝒊:𝒋+𝟏′ , 𝑷𝒊:𝒋+𝟏
′ 𝒉𝒋) = (𝒉𝒊𝑮𝒊−𝟏:𝒋, 𝑯𝒊:𝒋)
𝒋 ≥ 𝒒
(𝐺, 𝑃)
(𝐺′, 𝑃′)
IWSSIP 2014 85
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22 13
• How to solve Carry Save Stage Delay problem?
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝑿
𝒀
𝑿′ 𝒉𝒏−𝟏 … 𝒉𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒀′′ 𝒈𝒏−𝟐 … 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝜹 𝑬𝑨𝑪 𝒆 𝒆
Finding a relative between the 𝐺, 𝑃 of 𝑋 + 𝑌 2𝑛−2𝑞−1 and 𝐺′, 𝑃′ of 𝑋′ + 𝑌′′ 2𝑛−2𝑞−1
𝑐𝑖 =
𝑔𝑛−1 ∨ 𝐺𝑛−1:0′ , if 𝑖 = 0
𝐺𝑖−1:0′ ∨ 𝑃𝑖−1:0
′ (𝑔𝑛−1 ∨ 𝐺𝑛−1:0′ ), if 1 ≤ 𝑖 ≤ 𝑞
ℎ𝑞 ∨ 𝑒 𝑐𝑞 ∨ ℎ𝑞𝑒, if 𝑖 = 𝑞 + 1
𝐺𝑖−1:𝑞+1′ ∨ 𝑃𝑖−1:𝑞+1
′ 𝑐𝑞+1, if 𝑖 > 𝑞 + 1
(𝑮𝒊:𝒋+𝟏′ , 𝑷𝒊:𝒋+𝟏
′ 𝒉𝒋) = (𝒉𝒊𝑮𝒊−𝟏:𝒋, 𝑯𝒊:𝒋)
𝒋 ≥ 𝒒
(𝐺, 𝑃)
(𝐺′, 𝑃′)
IWSSIP 2014 86
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22 13
• How to solve Carry Save Stage Delay problem?
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝑿
𝒀
𝑿′ 𝒉𝒏−𝟏 … 𝒉𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒀′′ 𝒈𝒏−𝟐 … 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝜹 𝑬𝑨𝑪 𝒆 𝒆
Finding a relative between the 𝐺, 𝑃 of 𝑋 + 𝑌 2𝑛−2𝑞−1 and 𝐺′, 𝑃′ of 𝑋′ + 𝑌′′ 2𝑛−2𝑞−1
𝑐𝑖 =
𝑔𝑛−1 ∨ 𝐺𝑛−1:0′ , if 𝑖 = 0
𝐺𝑖−1:0′ ∨ 𝑃𝑖−1:0
′ (𝑔𝑛−1 ∨ 𝐺𝑛−1:0′ ), if 1 ≤ 𝑖 ≤ 𝑞
ℎ𝑞 ∨ 𝑒 𝑐𝑞 ∨ ℎ𝑞𝑒, if 𝑖 = 𝑞 + 1
𝐺𝑖−1:𝑞+1′ ∨ 𝑃𝑖−1:𝑞+1
′ 𝑐𝑞+1, if 𝑖 > 𝑞 + 1
(𝑮𝒊:𝒋+𝟏′ , 𝑷𝒊:𝒋+𝟏
′ 𝒉𝒋) = (𝒉𝒊𝑮𝒊−𝟏:𝒋, 𝑯𝒊:𝒋)
𝒋 ≥ 𝒒
(𝐺, 𝑃)
(𝐺′, 𝑃′)
IWSSIP 2014 87
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22 13
• How to solve Carry Save Stage Delay problem?
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝑿
𝒀
𝑿′ 𝒉𝒏−𝟏 … 𝒉𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒀′′ 𝒈𝒏−𝟐 … 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝜹 𝑬𝑨𝑪 𝒆 𝒆
Finding a relative between the 𝐺, 𝑃 of 𝑋 + 𝑌 2𝑛−2𝑞−1 and 𝐺′, 𝑃′ of 𝑋′ + 𝑌′′ 2𝑛−2𝑞−1
𝑐𝑖 =
𝑔𝑛−1 ∨ 𝐺𝑛−1:0′ , if 𝑖 = 0
𝐺𝑖−1:0′ ∨ 𝑃𝑖−1:0
′ (𝑔𝑛−1 ∨ 𝐺𝑛−1:0′ ), if 1 ≤ 𝑖 ≤ 𝑞
ℎ𝑞 ∨ 𝑒 𝑐𝑞 ∨ ℎ𝑞𝑒, if 𝑖 = 𝑞 + 1
𝐺𝑖−1:𝑞+1′ ∨ 𝑃𝑖−1:𝑞+1
′ 𝑐𝑞+1, if 𝑖 > 𝑞 + 1
𝑐𝑖 =
𝐺𝑛−1:0, if 𝑖 = 0𝐺𝑖−1:0 ∨ 𝑃𝑖−1:0𝐺𝑛−1:0, if 1 ≤ 𝑖 ≤ 𝑞
ℎ𝑞𝐺𝑞−1:0 ∨ 𝑃𝑞:0′′ 𝐺𝑛−1:0, if 𝑖 = 𝑞 + 1
ℎ𝑖−1𝐺𝑖−2:0 ∨ 𝑃𝑖−1:0′′ 𝐺𝑛−1:0, if 𝑖 > 𝑞 + 1
(𝑮𝒊:𝒋+𝟏′ , 𝑷𝒊:𝒋+𝟏
′ 𝒉𝒋) = (𝒉𝒊𝑮𝒊−𝟏:𝒋, 𝑯𝒊:𝒋)
𝒋 ≥ 𝒒
𝑃𝑞:0′′ = ℎ𝑞 ∨ 𝑃𝑞−1:0 ∨ 𝐺𝑞−1:0
𝑃𝑖−1:0′′ = 𝑃′
𝑖−1:𝑞+1𝑃𝑞:0′′
(𝐺, 𝑃)
(𝐺′, 𝑃′)
IWSSIP 2014 88
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22 13
• How to solve Carry Save Stage Delay problem?
𝒙𝒏−𝟏 … 𝒙𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒚𝒏−𝟏 … 𝒚𝒒 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝑿
𝒀
𝑿′ 𝒉𝒏−𝟏 … 𝒉𝒒 𝒙𝒒−𝟏 … 𝒙𝟏 𝒙𝟎
𝒀′′ 𝒈𝒏−𝟐 … 𝒚𝒒−𝟏 … 𝒚𝟏 𝒚𝟎
𝜹 𝑬𝑨𝑪 𝒆 𝒆
Finding a relative between the 𝐺, 𝑃 of 𝑋 + 𝑌 2𝑛−2𝑞−1 and 𝐺′, 𝑃′ of 𝑋′ + 𝑌′′ 2𝑛−2𝑞−1
𝑐𝑖 =
𝑔𝑛−1 ∨ 𝐺𝑛−1:0′ , if 𝑖 = 0
𝐺𝑖−1:0′ ∨ 𝑃𝑖−1:0
′ (𝑔𝑛−1 ∨ 𝐺𝑛−1:0′ ), if 1 ≤ 𝑖 ≤ 𝑞
ℎ𝑞 ∨ 𝑒 𝑐𝑞 ∨ ℎ𝑞𝑒, if 𝑖 = 𝑞 + 1
𝐺𝑖−1:𝑞+1′ ∨ 𝑃𝑖−1:𝑞+1
′ 𝑐𝑞+1, if 𝑖 > 𝑞 + 1
𝑐𝑖 =
𝐺𝑛−1:0, if 𝑖 = 0𝐺𝑖−1:0 ∨ 𝑃𝑖−1:0𝐺𝑛−1:0, if 1 ≤ 𝑖 ≤ 𝑞
ℎ𝑞𝐺𝑞−1:0 ∨ 𝑃𝑞:0′′ 𝐺𝑛−1:0, if 𝑖 = 𝑞 + 1
ℎ𝑖−1𝐺𝑖−2:0 ∨ 𝑃𝑖−1:0′′ 𝐺𝑛−1:0, if 𝑖 > 𝑞 + 1
(𝑮𝒊:𝒋+𝟏′ , 𝑷𝒊:𝒋+𝟏
′ 𝒉𝒋) = (𝒉𝒊𝑮𝒊−𝟏:𝒋, 𝑯𝒊:𝒋)
𝒋 ≥ 𝒒
𝑃𝑞:0′′ = ℎ𝑞 ∨ 𝑃𝑞−1:0 ∨ 𝐺𝑞−1:0
𝑃𝑖−1:0′′ = 𝑃′
𝑖−1:𝑞+1𝑃𝑞:0′′
(𝐺, 𝑃)
(𝐺′, 𝑃′)
The carry-save stage is effectively off the critical delay path
14
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
14
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
pghp′h′ pgh pgh pgh pghp′h′
x0x1x2x3x4x5x6 y0y1y2y3y4y5y6
(g2,p2)(g3,p3)(g5,p4)(g5,p5)(g6,p6) (g1,p1)
c3c4c5c6c7
s2s3s4s5s6s7
c2
pgh
s1
c1
s0
pgh pghh′
x7y7
(g0,p0)
h6 h5
G7:0
(g7,p7)
y4x4y5x5
y6 x6
P3:0 G3:0
ℎ7′ ℎ6
′ ℎ5′ ℎ4
ℎ4
ℎ0 ℎ1 ℎ3 ℎ2
(𝑮𝟎:𝟎, 𝑷𝟎:𝟎) (𝑮𝟏:𝟎, 𝑷𝟏:𝟎) (𝑮𝟐:𝟎, 𝑷𝟐:𝟎) (𝑮𝟑:𝟎,𝑷𝟑:𝟎) (𝑮𝟑:𝟎, 𝑷𝟒:𝟎′′ ) (𝑮𝟒:𝟎, 𝑷𝟓:𝟎
′′ ) (𝑮𝟓:𝟎, 𝑷𝟔:𝟎′′ )
Eqn.8
𝑝5′ 𝑝6
′
𝑝6′
𝑝5′
𝑝5′
𝑷𝟒:𝟎′′
𝑷𝟓:𝟎′′
𝑷𝟔:𝟎′′
p g h h′
1 1i i i ix y x y i ix yi ix y
ix iy
p g h
1ix 1iy
i ix y
p g h p’ h′
i ix yi ix y
1ix 1iy
i ix y
iyix
,G P ,r rG P
,r rG P G P PrG P G
,G P ,r rG P4h 5
p6p
3:0P3:0G
4:0P
5:0P6:0
P
,G P ,r rG P
i rh G P G
ih
Eqn.8
1 1i i i ix y x y 1 1i i i ix y x y
ix iy
i ix yi ix y i ix y
,G P
,G P
Modulo (28−24 − 1)
14
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
pghp′h′ pgh pgh pgh pghp′h′
x0x1x2x3x4x5x6 y0y1y2y3y4y5y6
(g2,p2)(g3,p3)(g5,p4)(g5,p5)(g6,p6) (g1,p1)
c3c4c5c6c7
s2s3s4s5s6s7
c2
pgh
s1
c1
s0
pgh pghh′
x7y7
(g0,p0)
h6 h5
G7:0
(g7,p7)
y4x4y5x5
y6 x6
P3:0 G3:0
ℎ7′ ℎ6
′ ℎ5′ ℎ4
ℎ4
ℎ0 ℎ1 ℎ3 ℎ2
(𝑮𝟎:𝟎, 𝑷𝟎:𝟎) (𝑮𝟏:𝟎, 𝑷𝟏:𝟎) (𝑮𝟐:𝟎, 𝑷𝟐:𝟎) (𝑮𝟑:𝟎,𝑷𝟑:𝟎) (𝑮𝟑:𝟎, 𝑷𝟒:𝟎′′ ) (𝑮𝟒:𝟎, 𝑷𝟓:𝟎
′′ ) (𝑮𝟓:𝟎, 𝑷𝟔:𝟎′′ )
Eqn.8
𝑝5′ 𝑝6
′
𝑝6′
𝑝5′
𝑝5′
𝑷𝟒:𝟎′′
𝑷𝟓:𝟎′′
𝑷𝟔:𝟎′′
p g h h′
1 1i i i ix y x y i ix yi ix y
ix iy
p g h
1ix 1iy
i ix y
p g h p’ h′
i ix yi ix y
1ix 1iy
i ix y
iyix
,G P ,r rG P
,r rG P G P PrG P G
,G P ,r rG P4h 5
p6p
3:0P3:0G
4:0P
5:0P6:0
P
,G P ,r rG P
i rh G P G
ih
Eqn.8
1 1i i i ix y x y 1 1i i i ix y x y
ix iy
i ix yi ix y i ix y
,G P
,G P
pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
c3c4c5c6
h3
c7
h4h5h6h7 h2
c2 c1
h1
pgh pgh pghh0
G7:0 (G6:0,P6:0) (G5:0,P5:0)(G4:0,P4:0) (G3:0,P3:0) (G2:0,P2:0) (G1:0,P1:0) (G0:0,P0:0)
s0s1s2s3s4s5s6s7
p g h
x yxyx y
x y ,G P ,r rG P
, r rG P G P P rG P G
,G P ,r rG P ,G P
,G P
Modulo (28−24 − 1) Modulo (28−1)
14
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
pghp′h′ pgh pgh pgh pghp′h′
x0x1x2x3x4x5x6 y0y1y2y3y4y5y6
(g2,p2)(g3,p3)(g5,p4)(g5,p5)(g6,p6) (g1,p1)
c3c4c5c6c7
s2s3s4s5s6s7
c2
pgh
s1
c1
s0
pgh pghh′
x7y7
(g0,p0)
h6 h5
G7:0
(g7,p7)
y4x4y5x5
y6 x6
P3:0 G3:0
ℎ7′ ℎ6
′ ℎ5′ ℎ4
ℎ4
ℎ0 ℎ1 ℎ3 ℎ2
(𝑮𝟎:𝟎, 𝑷𝟎:𝟎) (𝑮𝟏:𝟎, 𝑷𝟏:𝟎) (𝑮𝟐:𝟎, 𝑷𝟐:𝟎) (𝑮𝟑:𝟎,𝑷𝟑:𝟎) (𝑮𝟑:𝟎, 𝑷𝟒:𝟎′′ ) (𝑮𝟒:𝟎, 𝑷𝟓:𝟎
′′ ) (𝑮𝟓:𝟎, 𝑷𝟔:𝟎′′ )
Eqn.8
𝑝5′ 𝑝6
′
𝑝6′
𝑝5′
𝑝5′
𝑷𝟒:𝟎′′
𝑷𝟓:𝟎′′
𝑷𝟔:𝟎′′
pgh pgh pghpghpgh
y0y1y2y3y4y5y6y7 x0x1x2x3x4x5x6x7
c3c4c5c6
h3
c7
h4h5h6h7 h2
c2 c1
h1
pgh pgh pghh0
G7:0 (G6:0,P6:0) (G5:0,P5:0)(G4:0,P4:0) (G3:0,P3:0) (G2:0,P2:0) (G1:0,P1:0) (G0:0,P0:0)
s0s1s2s3s4s5s6s7
Modulo (28−24 − 1) Modulo (28−1)
Problem : for 𝒒 > 𝒏/𝟐 the critical delay path is one ∆𝑮 more than other case
15
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
15 ARITH 22
15
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
• How to solve extra delay critical problem for 𝑞 >𝑛
2 problem?
15 ARITH 22
15
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
• How to solve extra delay critical problem for 𝑞 >𝑛
2 problem?
Devise a mixed KS/Lander-Fischer PPN architecture ((n-1) levels use
KS architecture and the bottom level use LF )
pgh pgh pgh pghpghp h′
x0x1x2x3x4x5x6 y0y1y2y3y4y5y6
(g2,p2)(g3,p3)(g5,p4)(g5,p5)(g6,p6) (g1,p1)
c3c4c5c6c7
s2s3s4s5s6s7
c2
pgh
s1
c1
s0
pgh pghh′
x7y7
(g0,p0)
h6
G7:0
(g7,p7)
y5 x5y6 x6
p4
g4
ℎ0 ℎ1 ℎ2 ℎ3 ℎ4 ℎ5 ℎ6′ ℎ7
′
(𝑮𝟎:𝟎, 𝑷𝟎:𝟎) (𝑮𝟏:𝟎, 𝑷𝟏:𝟎) (𝑮𝟐:𝟎, 𝑷𝟐:𝟎) (𝑮𝟑:𝟎, 𝑷𝟑:𝟎) (𝑮𝟒:𝟎, 𝑷𝟒:𝟎) (𝑮𝟒:𝟎, 𝑷𝟓:𝟎′′ ) (𝑮𝟓:𝟎, 𝑷𝟔:𝟎
′′ )
𝑮𝟑:𝟎 ∨ 𝑷𝟑:𝟎
𝑮𝟏:𝟎 ∨ 𝑷𝟏:𝟎
𝑮𝟏:𝟎 ∨ 𝑷𝟏:𝟎
𝒑𝟎
Eqn.9
ℎ5 𝑝6
′
𝑷𝟓:𝟎′′
𝑷𝟔:𝟎′′
𝐺3:0⋁𝑃3:0
𝑝6′
p g h h′
1 1i i i ix y x y
i ix yi ix y
ix iy
p g h
1ix 1iy
i ix y
p g h p’ h′
i ix yi ix y
1ix 1iy
i ix y
iyix
,G P ,r rG P
,r rG P G P PrG P G
,G P ,r rG P ,G P ,r rG P
i rh G P G
ih
1 1i i i ix y x y
1 1i i i ix y x y
ix iy
i ix yi ix y i ix y
,G P
,G P
5h 6p
4P
5:0P
6:0P
Eqn.9
,G P ,r rG P
( )r rG P G P rG P G
r rG P 4g
3:0 3:0G P
15 ARITH 22
15
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
• How to solve extra delay critical problem for 𝑞 >𝑛
2 problem?
Devise a mixed KS/Lander-Fischer PPN architecture ((n-1) levels use
KS architecture and the bottom level use LF )
pgh pgh pgh pghpghp h′
x0x1x2x3x4x5x6 y0y1y2y3y4y5y6
(g2,p2)(g3,p3)(g5,p4)(g5,p5)(g6,p6) (g1,p1)
c3c4c5c6c7
s2s3s4s5s6s7
c2
pgh
s1
c1
s0
pgh pghh′
x7y7
(g0,p0)
h6
G7:0
(g7,p7)
y5 x5y6 x6
p4
g4
ℎ0 ℎ1 ℎ2 ℎ3 ℎ4 ℎ5 ℎ6′ ℎ7
′
(𝑮𝟎:𝟎, 𝑷𝟎:𝟎) (𝑮𝟏:𝟎, 𝑷𝟏:𝟎) (𝑮𝟐:𝟎, 𝑷𝟐:𝟎) (𝑮𝟑:𝟎, 𝑷𝟑:𝟎) (𝑮𝟒:𝟎, 𝑷𝟒:𝟎) (𝑮𝟒:𝟎, 𝑷𝟓:𝟎′′ ) (𝑮𝟓:𝟎, 𝑷𝟔:𝟎
′′ )
𝑮𝟑:𝟎 ∨ 𝑷𝟑:𝟎
𝑮𝟏:𝟎 ∨ 𝑷𝟏:𝟎
𝑮𝟏:𝟎 ∨ 𝑷𝟏:𝟎
𝒑𝟎
Eqn.9
ℎ5 𝑝6
′
𝑷𝟓:𝟎′′
𝑷𝟔:𝟎′′
𝐺3:0⋁𝑃3:0
𝑝6′
p g h h′
1 1i i i ix y x y
i ix yi ix y
ix iy
p g h
1ix 1iy
i ix y
p g h p’ h′
i ix yi ix y
1ix 1iy
i ix y
iyix
,G P ,r rG P
,r rG P G P PrG P G
,G P ,r rG P ,G P ,r rG P
i rh G P G
ih
1 1i i i ix y x y
1 1i i i ix y x y
ix iy
i ix yi ix y i ix y
,G P
,G P
5h 6p
4P
5:0P
6:0P
Eqn.9
,G P ,r rG P
( )r rG P G P rG P G
r rG P 4g
3:0 3:0G P
KS
LF
15 ARITH 22
15
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
• How to solve extra delay critical problem for 𝑞 >𝑛
2 problem?
Devise a mixed KS/Lander-Fischer PPN architecture ((n-1) levels use
KS architecture and the bottom level use LF )
pgh pgh pgh pghpghp h′
x0x1x2x3x4x5x6 y0y1y2y3y4y5y6
(g2,p2)(g3,p3)(g5,p4)(g5,p5)(g6,p6) (g1,p1)
c3c4c5c6c7
s2s3s4s5s6s7
c2
pgh
s1
c1
s0
pgh pghh′
x7y7
(g0,p0)
h6
G7:0
(g7,p7)
y5 x5y6 x6
p4
g4
ℎ0 ℎ1 ℎ2 ℎ3 ℎ4 ℎ5 ℎ6′ ℎ7
′
(𝑮𝟎:𝟎, 𝑷𝟎:𝟎) (𝑮𝟏:𝟎, 𝑷𝟏:𝟎) (𝑮𝟐:𝟎, 𝑷𝟐:𝟎) (𝑮𝟑:𝟎, 𝑷𝟑:𝟎) (𝑮𝟒:𝟎, 𝑷𝟒:𝟎) (𝑮𝟒:𝟎, 𝑷𝟓:𝟎′′ ) (𝑮𝟓:𝟎, 𝑷𝟔:𝟎
′′ )
𝑮𝟑:𝟎 ∨ 𝑷𝟑:𝟎
𝑮𝟏:𝟎 ∨ 𝑷𝟏:𝟎
𝑮𝟏:𝟎 ∨ 𝑷𝟏:𝟎
𝒑𝟎
Eqn.9
ℎ5 𝑝6
′
𝑷𝟓:𝟎′′
𝑷𝟔:𝟎′′
𝐺3:0⋁𝑃3:0
𝑝6′
p g h h′
1 1i i i ix y x y
i ix yi ix y
ix iy
p g h
1ix 1iy
i ix y
p g h p’ h′
i ix yi ix y
1ix 1iy
i ix y
iyix
,G P ,r rG P
,r rG P G P PrG P G
,G P ,r rG P ,G P ,r rG P
i rh G P G
ih
1 1i i i ix y x y
1 1i i i ix y x y
ix iy
i ix yi ix y i ix y
,G P
,G P
5h 6p
4P
5:0P
6:0P
Eqn.9
,G P ,r rG P
( )r rG P G P rG P G
r rG P 4g
3:0 3:0G P
Using twin nodes (Computing 𝐺𝑖:0 and 𝐺𝑖:0 ∨ 𝑃𝑖:0 as a same time)
15 ARITH 22
16
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
16
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Design Delay (∆𝑮) Area (𝓐𝑮)
[4] 4 log 𝑛 + 8 6𝑛 log 𝑛 + 5𝑛 + 1
[5] 4 log 𝑛 + 12 3𝑛 log 𝑛 + 10𝑛 + 1
[6] 2 log (𝑛 − 1) + 7 3 𝑛 − 1 log 𝑛 +
3 𝑛 − 1 log 𝑛 − 1 + 5𝑛 + 1
[7] 2 log 𝑛 − 1 +
2 log (𝑛 − 2) + 8
3 𝑛 − 2 log 𝑛 − 2 −
log (𝑛 − 1) + 7𝑛 + 27
[8] 2 log (𝑛 − 1) + 7 3 𝑛 log (𝑛 − 1) + 13𝑛 − 5
[9] 2 log 𝑛 + 7 3𝑛 − 1 log𝑛 + 11.5𝑛 + 1
[10] 2 log 𝑛 + 7 3𝑛 log 𝑛 + 6𝑛 − 3𝑞 + 2 + 𝒜𝑐
[11] (𝒒 = 𝒏 − 𝟐) 2 log 𝑛 + 5 3𝑛 log𝑛 + 1.5𝑛 log 𝑛 − 1
+ 7𝑛 + 2 log 𝑛−1 −1
[13]-RPP (𝒒 = 𝟏) 2 log (𝑛 − 1) + 6 3 𝑛 − 1 log(𝑛 − 1) + 8𝑛 − 1
New (𝒒 ≤ 𝒏/𝟐) 2 log 𝑛 + 5 3 𝑛 − 1 log 𝑛 +
7𝑛 − 3𝑞 − 1 + 𝒜𝑃′′
New (𝒒 > 𝒏/𝟐) 2 log 𝑛 + 5 3(𝑛 − 1) log 𝑛 + 5.5𝑛 −
3𝑞 + 2 log 𝑛 + 𝒜𝑃′′
[3]-RPP 2 log 𝑛 + 5 3𝑛 log 𝑛 + 4𝑛
∆𝑮: Delay of Simple Gate
𝓐𝑮: Area of Simple Gate
Analytical gate Level Evaluation
ARITH 22
16
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Design Delay (∆𝑮) Area (𝓐𝑮)
[4] 4 log 𝑛 + 8 6𝑛 log 𝑛 + 5𝑛 + 1
[5] 4 log 𝑛 + 12 3𝑛 log 𝑛 + 10𝑛 + 1
[6] 2 log (𝑛 − 1) + 7 3 𝑛 − 1 log 𝑛 +
3 𝑛 − 1 log 𝑛 − 1 + 5𝑛 + 1
[7] 2 log 𝑛 − 1 +
2 log (𝑛 − 2) + 8
3 𝑛 − 2 log 𝑛 − 2 −
log (𝑛 − 1) + 7𝑛 + 27
[8] 2 log (𝑛 − 1) + 7 3 𝑛 log (𝑛 − 1) + 13𝑛 − 5
[9] 2 log 𝑛 + 7 3𝑛 − 1 log𝑛 + 11.5𝑛 + 1
[10] 2 log 𝑛 + 7 3𝑛 log 𝑛 + 6𝑛 − 3𝑞 + 2 + 𝒜𝑐
[11] (𝒒 = 𝒏 − 𝟐) 2 log 𝑛 + 5 3𝑛 log𝑛 + 1.5𝑛 log 𝑛 − 1
+ 7𝑛 + 2 log 𝑛−1 −1
[13]-RPP (𝒒 = 𝟏) 2 log (𝑛 − 1) + 6 3 𝑛 − 1 log(𝑛 − 1) + 8𝑛 − 1
New (𝒒 ≤ 𝒏/𝟐) 2 log 𝑛 + 5 3 𝑛 − 1 log 𝑛 +
7𝑛 − 3𝑞 − 1 + 𝒜𝑃′′
New (𝒒 > 𝒏/𝟐) 2 log 𝑛 + 5 3(𝑛 − 1) log 𝑛 + 5.5𝑛 −
3𝑞 + 2 log 𝑛 + 𝒜𝑃′′
[3]-RPP 2 log 𝑛 + 5 3𝑛 log 𝑛 + 4𝑛
∆𝑮: Delay of Simple Gate
𝓐𝑮: Area of Simple Gate
Analytical gate Level Evaluation
ARITH 22
16
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
Design Delay (∆𝑮) Area (𝓐𝑮)
[4] 4 log 𝑛 + 8 6𝑛 log 𝑛 + 5𝑛 + 1
[5] 4 log 𝑛 + 12 3𝑛 log 𝑛 + 10𝑛 + 1
[6] 2 log (𝑛 − 1) + 7 3 𝑛 − 1 log 𝑛 +
3 𝑛 − 1 log 𝑛 − 1 + 5𝑛 + 1
[7] 2 log 𝑛 − 1 +
2 log (𝑛 − 2) + 8
3 𝑛 − 2 log 𝑛 − 2 −
log (𝑛 − 1) + 7𝑛 + 27
[8] 2 log (𝑛 − 1) + 7 3 𝑛 log (𝑛 − 1) + 13𝑛 − 5
[9] 2 log 𝑛 + 7 3𝑛 − 1 log𝑛 + 11.5𝑛 + 1
[10] 2 log 𝑛 + 7 3𝑛 log 𝑛 + 6𝑛 − 3𝑞 + 2 + 𝒜𝑐
[11] (𝒒 = 𝒏 − 𝟐) 2 log 𝑛 + 5 3𝑛 log𝑛 + 1.5𝑛 log 𝑛 − 1
+ 7𝑛 + 2 log 𝑛−1 −1
[13]-RPP (𝒒 = 𝟏) 2 log (𝑛 − 1) + 6 3 𝑛 − 1 log(𝑛 − 1) + 8𝑛 − 1
New (𝒒 ≤ 𝒏/𝟐) 2 log 𝑛 + 5 3 𝑛 − 1 log 𝑛 +
7𝑛 − 3𝑞 − 1 + 𝒜𝑃′′
New (𝒒 > 𝒏/𝟐) 2 log 𝑛 + 5 3(𝑛 − 1) log 𝑛 + 5.5𝑛 −
3𝑞 + 2 log 𝑛 + 𝒜𝑃′′
[3]-RPP 2 log 𝑛 + 5 3𝑛 log 𝑛 + 4𝑛
∆𝑮: Delay of Simple Gate
𝓐𝑮: Area of Simple Gate
Analytical gate Level Evaluation
ARITH 22
17
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
17
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Synthesis: Synopsys Design Compiler Technology file: 130 nm
17
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Synthesis: Synopsys Design Compiler Technology file: 130 nm
𝑞 1 2 3 4 5 6
Least delay (𝒏𝒔) 0.71 0.71 0.72 0.71 0.70 0.70
Area (𝝁𝒎𝟐) 1405 1268 1224 1129 1110 910
Power (𝝁𝒘) 449 408 383 353 326 264
Performance measures of the New design (𝑛 = 8, 1 ≤ 𝑞 ≤ 6)
17
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Design Least delay
(𝒏𝒔) Ratio Area
(𝝁𝒎𝟐) Ratio AT
Power
𝝁𝒘 Ratio PDP
[6] 0.77 1.08 1828 1.30 1.41 577 1.28 1.39
[8] 0.84 1.18 1501 1.07 1.26 499 1.11 1.31
[9] 0.83 1.17 1524 1.08 1.27 500 1.11 1.30
[10] 0.84 1.18 1504 1.07 1.27 500 1.11 1.32
[13] 0.80 1.12 1400 1.00 1.12 446 0.99 1.12
New 0.71 1.00 1405 1.00 1.00 449 1.00 1.00
Synthesis: Synopsys Design Compiler Technology file: 130 nm
(n=8,q=1)
17
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Design Least delay
(𝒏𝒔) Ratio Area
(𝝁𝒎𝟐) Ratio AT
Power
𝝁𝒘 Ratio PDP
[6] 0.77 1.08 1828 1.30 1.41 577 1.28 1.39
[8] 0.84 1.18 1501 1.07 1.26 499 1.11 1.31
[9] 0.83 1.17 1524 1.08 1.27 500 1.11 1.30
[10] 0.84 1.18 1504 1.07 1.27 500 1.11 1.32
[13] 0.80 1.12 1400 1.00 1.12 446 0.99 1.12
New 0.71 1.00 1405 1.00 1.00 449 1.00 1.00
Synthesis: Synopsys Design Compiler Technology file: 130 nm
(n=8,q=6)
(n=8,q=1)
Design Least delay
(𝒏𝒔) Ratio
Area
(𝝁𝒎𝟐) Ratio AT
Power
𝝁𝒘 Ratio PDP
[6] 0.77 1.10 1825 2.00 2.21 550 2.08 2.29
[8] 0.84 1.20 1404 1.54 1.85 434 1.64 1.97
[9] 0.88 1.26 1338 1.47 1.85 454 1.72 2.16
[10] 0.75 1.07 1480 1.63 1.74 452 1.71 1.83
[11] 0.73 1.04 1394 1.53 1.60 442 1.67 1.75
New 0.70 1.00 910 1.00 1.00 264 1.00 1.00
17
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Synthesis: Synopsys Design Compiler Technology file: 130 nm
Desig
n
Least delay
(𝒏𝒔) Ratio
Area
(𝝁𝒎𝟐) Ratio AT
Power
𝝁𝒘 Ratio PDP
[6] 0.88 1.03 4589 1.41 1.46 1383 1.40 1.44
[8] 0.90 1.06 3725 1.15 1.21 1190 1.20 1.27
[9] 0.92 1.08 3828 1.18 1.28 1295 1.31 1.41
[10] 0.97 1.14 3394 1.04 1.19 1075 1.08 1.24
[13] 0.89 1.05 3414 1.05 1.10 1018 1.03 1.08
New 0.85 1.00 3248 1.00 1.00 991 1.00 1.00
(n=16,q=1)
17
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Synthesis: Synopsys Design Compiler Technology file: 130 nm
Desig
n
Least delay
(𝒏𝒔) Ratio
Area
(𝝁𝒎𝟐) Ratio AT
Power
𝝁𝒘 Ratio PDP
[6] 0.88 1.03 4589 1.41 1.46 1383 1.40 1.44
[8] 0.90 1.06 3725 1.15 1.21 1190 1.20 1.27
[9] 0.92 1.08 3828 1.18 1.28 1295 1.31 1.41
[10] 0.97 1.14 3394 1.04 1.19 1075 1.08 1.24
[13] 0.89 1.05 3414 1.05 1.10 1018 1.03 1.08
New 0.85 1.00 3248 1.00 1.00 991 1.00 1.00
Desig
n
Least delay
(𝒏𝒔) Ratio
Area
(𝝁𝒎𝟐) Ratio AT
Power
𝝁𝒘 Ratio PDP
[6] 0.90 1.06 4538 2.18 2.31 1360 2.34 2.48
[8] 0.91 1.07 3988 1.91 2.05 1262 2.17 2.32
[9] 0.90 1.06 3855 1.85 1.96 1341 2.31 2.44
[10] 0.89 1.05 3394 1.63 1.71 940 1.62 1.69
[11] 0.87 1.02 3829 1.84 1.88 1226 2.11 2.16
New 0.85 1.00 2083 1.00 1.00 581 1.00 1.00
(n=16,q=1)
(n=16,q=14)
18
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
18
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Conclusion
• Design and implement a new Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 parallel prefix adder
based on only one interim sum which has the same delay complexity as
the modulo- 𝟐𝒏 − 𝟏 adder .
18
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Conclusion
• Design and implement a new Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 parallel prefix adder
based on only one interim sum which has the same delay complexity as
the modulo- 𝟐𝒏 − 𝟏 adder .
• Future work
18
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22
Conclusion
• Design and implement a new Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 parallel prefix adder
based on only one interim sum which has the same delay complexity as
the modulo- 𝟐𝒏 − 𝟏 adder .
• Future work
Design and implement Modulo-(𝟐𝒏 − 𝟐𝒒 − 𝟏) multiplier
Questions
19
Modulo- 𝟐𝒏 − 𝟐𝒒 − 𝟏 Parallel Prefix Addition
via Excess-Modulo Encoding of Residue
ARITH 22