samsung scx 1150 mfp service manual

Repair ManualRepair Manual

1. Block Diagram

2. Connection Diagram

3. Circuit Description

4. Schematic Diagrams

CONTENTS

INKJET PRINTER(MFP)

SCX-1150F

1

1-1Samsung Electronics

BLOCK DIAGRAM

Repair Manual

1. Block Diagram

AC

(110

~240

(64M

bit)

V)

SM

PS

(30V

,3.3

V)

Jupi

ter3

UAR

T3

I/O

PORT

INT.

CNTR

USB

FLAS

H

Thun

derb

olt

MOT

OR

CC

DM

odul

e

SCAN

STEP

PER

SC

AN

MO

TOR

(UN

I-PO

LAR

STEP

)

CO

LOR

MO

NO

CA

RTR

IDG

E

RE

SE

T

US

B

PC

10M

Hz

48M

Hz

P128

4CO

NN

SCAN

NE

R

BUF

FE60

0//6

00

Tx/R

x

SPE

AK

ER

SD

RAM

AFE

BACK

UP

(Sup

erca

p1F

)

ADF

MO

DULE A

DF

RTC

Cloc

k

SD

RA

M

MO

DEM

Spit

fire

/REQ

/AC

KAD

C

DOC.

POS

SEN

SOR

DOC.

DET

SEN

SOR

OP

E

PO

WE

R+

5V

+11.

75V

+30V +3

.3V

LIU

MA

IN

PRIN

T HEA

D(2P

EN)

600D

PI D

OUBL

E

HEIG

HT

ENCO

RDER

SE

NSOR LI

NE

FEED

CAR

RIA

GE

RET

UR

N M

OTO

R

COVE

R OP

EN S

ENSO

R

PA

PE

R

EX

IT

SE

NS

OR

IMAGE

PR

OCES

SOR

OA-98

0

IEEE

1284

TIMER

S

REAL

TIME

CLO

CK

ARM7

TDMI

MEM.

SNT

RHe

ad C

ontro

l I/F

SCAN

SNT

R

DERA

STER

IZER

MODE

M CL

OCK

28.22

4MHz

MAIN

CLO

CK

ADF

STEP

PER

MOTO

R DR

IVER

KEY

PANN

EL

TELE

PHON

ELIN

E

MODEM &

EXT_PHO

NESEPE

RATING

PART

EXTE

RNAL

LIN

E

RING

DE

TECT

ION

PART

EXTE

RNAL

PH

ONE

DE

TECT

ION

PART

TRAN

SFOR

MER

(64M

bit)

(8M

bit)

(33.

6Kbp

s)

2


CONNECTION DIAGRAM

Repair Manual

2. Connection Diagram

Refer to the Schematic diagram(See page 4-2)

3


CIRCUIT DESCRIPTION

Repair Manual

3. Circuit Description

3-1. GENERAL DESCRIPTION

Main circuit consists of mainly consists of CPU and the controller part with various types of built-in I/O device driver(built-inRISC Processor Core: ARM7TDMI), system memory part, OA980 controlling input of image received from media and con-version, CF(COMPACT storage card) interface part. The following nomenclatures by section is the same as those listed inthe circuit diagram.

3-2. MEMORY MAP

The entire Addressing area provided by MAIN CONTROLLER(S3C46MOX(Jupiter3)) is 256MBytes from 0x00000000 to0x10000000, and the Max. Address Range for each External Chip Select is 32M Byte or Half word from 0x000000 to0x01FFFFFF and embodied with Big-Endian Bus interface. MEMORY area is divided into EXTERNAL ROM and RAMareas(See (Figure 1)), and the areas actually used are 8M/8M BYTES SDRAM and 1M BYTES ROM(FLASH MEMORY).

0x0FFF_FFFFGCS 7 Area

0x0E00_00000x0DFF_FFFF

GCS6 Area - DRAM(8MB)0x0C00_00000x0BFF_FFFF

Reserved0x0A00_00000x09FF_FFFF

GCS 4 Area - OA980 PO CS0x0800_00000x07FF_FFFF

GCS 3 Area - EXTENDED GPIO0x0600_00000x05FF_FFFF

GCS 2 Area - MODEM0x0400_00000x03FF_FFFF

GCS 1 Area - OA9800x0200_00000x01FF_FFFF

Special Registers0x01C0_00000x000F_FFFF

Program Area(1MB

used)

0x0000_0000

USER MEMORY(3MB Start ~ )0xC300000

PIXEL TO LINE BUFFER(30KB)0xC2CBC20

Chunk Buffer(8KByte)0xC2C9C20

Read Print Buffer (32Byte)0xC2C9C00

Swath Buffer(300KByte)0xC27EC00

Scan Buffer(810KB)0xC1B4400

RGB Buffer(30KB)0xC1ACC00

ECM Buffer(64KB)0xC19CC00

RCP PC FAX Buffer(15KB)0xC199000

JPEG DECODE BUFFER(64KB)0xC099000

MDM Out Buffer(20KB)0xC094000

MDM In Buffer(28KB)0xC08D000

JPEG INPUT Buffer(220KB)0xC056000

System AREA(344K)0xC000000

OASIS Rom Code : 256KB(Sector 15 ~ Sector 18)

J3 ROM Code :704KB(Sector 4 ~ Sector 14)

Backup Data(Sector 3:32KB)

Not Used(Sector 1,2: 16 KB)

Boot Rom Code(Sector 0 : 16KB)

Flash memory(1MB)

SDRAM(8MB)

<Figure 1. S3C46MOX(Jupiter3) MEMORY MAP>

◊ MAIN PBA

3-2

CIRCUIT DESCRIPTION

Samsung ElectronicsRepair Manual

3-3.DETAILED DESCRIPTION

3-3-1 BLOCK DIAGRAM and MAIN CONTROLLER description

3-3-1-1 General descriptionMAIN CONTROLLER(S3C46MOX(Jupiter3),U15) consists of this system consists of CPU(ARM7TDMI RISC PROCES-SOR), 8K BYTES CACHE, DATA and ADDRESS BUS, PLL deriding input frequency and CLOCK CONTROL part,SERIAL COMMUNICATION part supporting UART, PRINT HEAD control part, PARALLEL PORT INTERFACE part,USB INTERFACE part, External DMA part for receiving data from external COLOR IMAGE PROCESSOR(OA-980,U21), MEMORY and EXTERNAL BANK control part, SYNCHRONOUS SERIAL INTERFACE control part for inter-facing Thunderbolt, and LF/CR Motor drive control and general purpose I/O control parts.(See Figure 2 )

3-3-2 S3C46MOX(Jupiter3) FUNCTION DESCRIPTION

3-3-2-1 SYSTEM CLOCKThere are two ways of Clock input method. One is the method to make Master Clock(MCLK) at the internal PLL by con-necting X-tal and Capacitor to the outside, and another method is to use MCLK(When inputting 40MHz) directly, whichsupplies maximum 40MHz Clock to the EXTCLK terminal(PIN65). The range of frequency being input in case of usingX-tal is limited to 4MHz~10MHz. This system uses SSCG(FS781) with a 10MHZ X-tal outside to make MCLK, and sup-plies Clock to the XIN terminal(PIN67) of ASIC by expanding Spectrum with bandwidth about 1.5% in comparison withthe basic frequency by using this IC. Inside the ASIC, the PLL makes 66MHz MCLK signal, which is the basic operationfrequency of the System. Also, this PLL makes 48MHz, the operation frequency of USB Controller.

3-3-2-2 DATA and ADDRESS BUS CONTROL

1. /RD & /WR

/RD & /WR SIGNAL are synchronized with the inside MCLK(66MHZ) and becomes active to Low. These signal are Strobe Signal used to Read or Write data when each Chip Select becomes active connected to/RD,/WR PIN of RAM, ROM, OA-980.

2. CHIP SELECT (/ROMCS, /IP_CS,/MED_CS,/SCS0,/SCS1)

- /ROMCS : FLASH MEMORY(U7) CHIP SELECT (LOW ACTIVE)- /IP_CS : OA-980(U21) CHIP SELECT

(LOW ACTIVE)- /SCS1 : SDRAM(OPTION)(U12) CHIP SELECT (LOW ACTIVE)

In case each Chip Select is low, it may Read or Write data.

3. D0 ~ D15

- 16BIT DATA BUS

4. A0 ~ A24

- ADDRESS BUS (A23 ~ A24 RESERVED)


CIRCUIT DESCRIPTION

Repair Manual

<Figure 2. Block Diagram of Main Part>

AC(1

10~2

40

(64M

bit)

V)

SMPS

(30V

,3.3

V)

Jupi

ter3

UAR

T3

I/O

PORT

INT.

CNTR

USB

FLAS

H

Thun

derb

olt

MOT

OR

CCD

Mod

ule

SCAN

STEP

PER

SC

AN

MO

TOR

(UNI

-POL

ARST

EP)

CO

LOR

MO

NO

CA

RTR

IDG

E

RE

SE

T

US

B

PC

10M

Hz

48M

Hz

P128

4CO

NN

SCAN

NER

BUFF

E60

0//6

00

Tx/R

x

SPE

AK

ER

SD

RAM

AFE

BACK

UP

(Sup

erca

p1F

)

ADF

MOD

ULE A

DF

RTC

Cloc

k

SD

RA

M

MOD

EM

Spit

fire

/REQ

/AC

KAD

C

DOC.

POS S

ENSO

RDO

C. DE

T SEN

SOR

OP

E

PO

WE

R+

5V

+11.

75V

+30V +3

.3V

LIU

MA

IN

PRIN

T HEA

D(2P

EN)

600D

PI D

OUBL

E

HEIG

HT

ENCO

RDER

SE

NSOR LI

NE F

EED

CARR

IAG

ERE

TURN

MO

TOR

COVE

R OP

EN SE

NSOR

PAP

ER

E

XIT

S

EN

SO

R

IMAGE

PR

OCES

SOR

OA-98

0

IEEE 1

284

TIMER

S

REAL

TIME

CLO

CK

ARM7

TDMI

MEM.

SNTR

Head

Con

trol I/

F

SCAN

SNTR

DERA

STER

IZER

MODE

M CL

OCK

28.22

4MHz

MAIN

CLO

CK

ADF S

TEPP

ER

MOTO

R DR

IVER

KEY P

ANNE

L

TELE

PHON

ELIN

E

MODEM &

EXT_PHO

NESEPE

RATING PA

RT

EXTE

RNAL

LIN

E

RING

DE

TECT

ION

PART

EXTE

RNAL

PH

ONE

DETE

CTIO

NPA

RT

TRAN

SFOR

MER

(64M

bit)

(8M

bit)

(33.

6Kbp

s)

3-4

CIRCUIT DESCRIPTION


<Figure 3. Flash Memory Read Timing>

<Figure 4. Flash Memory Write Timing>

EXTCLK

nGCSx

nGCSx

ADDR

tRWD

tRAD

Tacs

tRCD

nWE

DATA

nBEx

Tacc Toch

Tcah

Tocs

tRCD

tRWD

tRDD

tRAD

tRDH

’1’

EXTCLK

nGCSx

nGCSx

ADDR

tRWD

tRAD

Tacs

tRCD

nWE

DATA

nBEx

Tacc Toch

Toch

Tcah

Tocs

tRWBED

Tcos

tRDD

tRWBED

tRCD

tRWD

tRDD

tRAD


CIRCUIT DESCRIPTION

Repair Manual

<Figure 5. SDRAM Read Timing>

SCLK

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

’1’tSAD

tSAD

tSCSD

tSRD

Trp Trcd tSCD

tSBED

TcltSWD

tSDS

tSDH

3-6

CIRCUIT DESCRIPTION


<Figure 6. SDRAM Write Timing>

SCLK

’1’SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

tSAD

tSAD

tSCSD

tSRD

Trp Trcd

tSWD

tSDD

tSDD

tSBED

tSCD


CIRCUIT DESCRIPTION

Repair Manual

<Figure 7. SDRAM Write Timing>

SCLK

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

tSAD

’1’

’1’

’HZ’

tSAD

tSCSD

tSRD tSRD

tSCD

tSWD

tSCSD

tSAD

Trp Trc

3-8

CIRCUIT DESCRIPTION


<Figure 8. SDRAM auto Refresh Timing>

SCLK

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

tSAD

’1’

’1’

’HZ’

tSAD

tSCSD

tSRD tSRD

tSCD

tSWD

tSCSD

tSAD

Trp Trc


CIRCUIT DESCRIPTION

Repair Manual

<Figure 9. SDRAM Self Refresh Timing>

SCLK

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA’HZ’

tSWD

’HZ’

’1’

’1’ ’1’

’1’

’1’’1’

’1’

tCKED

tSAD

tSAD

tSCSD

tSRD tSRD

tSCD

tSCSD

tSAD

tCKED

TrcTrp

3-10

CIRCUIT DESCRIPTION


Parameter Symbol Min Typ. Max Unit

ROM/SRAM Address Delay tRAD - 12 - ns

ROM/SRAM Chip select Delay tRCD - 11 - ns

ROM/SRAM Output enable Delay tROD - 11 - ns

ROM/SRAM read Data Setup time tRDS - 1 - ns

ROM/SRAM read Data Hold time tRDH - 5 - ns

ROM/SRAM Byte Enable Dalay tRBED - 13 - ns

ROM/SRAM Write Byte Enable Delay tRWBED - 14 - ns

ROM/SRAM output Data Delay tRDD - 14 - ns

ROM/SRAM external Wait Setup time tWS - 1 - ns

ROM/SRAM external Wait Hold time tWH - 5 - ns

ROM/SRAM Write enable Delay tRWD - 14 - ns

DRAM Address Delay tDAD - 12 - ns

DRAM Row active Delay tDRD - 11 - ns

DRAM Read Column active Delay tDRCD - 11 - ns

DRAM Output enable Delay tDOD - 12 - ns

DRAM read Data Setup time tDDS - 1 - ns

DRAM read Data Hold time tDDH - 5 - ns

DRAM Write Cas active Delay tDWCD - 14 - ns

DRAM Cbr Cas active Delay tDCCD - 12 - ns

DRAM Write enable Delay tDWD - 13 - ns

DRAM output Data Delay tDDD - 14 - ns

SDRAM Address Delay tSAD - 4 - ns

SDRAM Chip Select Delay tSCSD - 4 - ns

SDRAM Row active Delay tSRD - 4 - ns

SDRAM Column active Delay tSCD - 4 - ns

SDRAM Byte Enable Delay tSBED - 5 - ns

SDRAM Write enable Delay tSWD - 5 - ns

SDRAM read Data Setup time tSDS - 4 - ns

SDRAM read Data Hold time tSDH - 0 - ns

SDRAM output Data Delay tSDD - 8 - ns

SDRAM Clock Enable Delay tCKED - 5 - ns

< ROM/SRAM Bus Timing Constants >

(VDDP : 3.3V, VDDI : 2.5V, Ta =25˚C, PLCAP=70pf, Max/Min=typ. ±30%)


CIRCUIT DESCRIPTION

Repair Manual

3-3-2-3 EXTERNAL DMA part

The function of this part is to bring data from externalDEVICE(OASIS:U21) by using GENERAL DMA. If DMAREQUEST(/IP_REQ) is sent from external DEVICE toS3C46MOX(JUPITER3:U15), DMA ACKNOWLEDGESIGNAL(/IP_ACK) is activated and the GENERAL DMA isdriven, so READ STROBE(/RD) in the external DEVICE tobring data from the external DEVICE requiring CHANNEL.To transfer this DATA to the DESTINATION MEMORY, theADDRESS of the DESTINATION MEMORY, CHIPSELECT and WRITE STROBE(/WR) are generated tostore.

That is, if the EXTERNAL DMA is required by the externalDEVICE, S3C46MOX(Jupiter3:U15) responds to drive theinside DMA CONTROLLER and then allocate GENERALDMA to external CHANNEL so that the data may be trans-ferred to MEMORY TO MEMORY or external DEVICE TOMEMORY.

• For more details, see the circuit description, see the circuitdescription part of IMAGE PROCESSOR (5.3).

3-3-2-4 DRAM control part

Since S3C46MOX(Jupiter3) has the DRAM CON-TROLLER build-in, it may be used by connecting DRAMwith external memory.

The Control mode of DRAM CONTROLLER provided byS3C46MOX(Jupiter3) is available for EARLY WRITE,NORMAL READ, PAGE MODE, and BYTE/HALF WORDACCESS, and is supported even by EDO DRAM,andSDRAM as well as, Fast page DRAM.

This system uses SDRAM, and the signal used forREAD/WRITE uses /RD,/WR signal used for SYSTEMBUS CONTROL. It is supported with auto REFRESH andalso by the Self-refresh mode for DRAM BACK UP. It con-sists of 2 Banks connected to common /SCS[1:0], /SCAS,/SRAS, /SCLK, /SCKE, /DQM[1:0], each of them may useup to 2M ~ 32M HALF WORD.

In this system, 2 MB is applied as system memory. Thearea of DRAM is specified in the DRAM MEMORY MAP ofFig. 1, while the related TIMING DIAGRAM in Fig. 5, 6, 7,8, 9.

3-3-2-5 RTC (REAL TIME CLOCK) part

RTC Circuit is logic for maintaining information of the cur-rent time, and it is operated in both conditions, PrimaryPower and Battery Back-up. Additional RTC IC is not usedbecause RTC is built-in at MFP Controller.

RTC Logic at inner part of ASIC accepts Crystal(32.768KHz:X3), which is inputted from outside, as a ClockSource, and it divides the Clock by every minute for mak-

ing hour, minute, second, year, month, and day. While thepower is on and the Crystal is being oscillation, the RTCLogic independently counts the time without control bySoftware and marks the value of hour, minute, second,year, month, and day at the appropriated Register.

Software confirms the value of the Register and displays itat LCD.

3-3-2-6 PARALLEL PORT INTERFACE division

S3C46MOX(Jupiter3) has the Parallel Port Interface partenabling Parallel Interface with PC. This part is connected to PC through Centronics Connectorin this system, which consists of /ERROR, PE, BUSY,/ACK, SLCT, /INIT, /SLCTIN, /AUTOFD, /STB and 245DIRas the part generating the main control signal used to drivePARALLEL COMMUNICATION. Data transmissionmethod between this part and PC supports the methodspecified in P1284 Parallel Port Standard(http://www.fapo.com/ieee1284.html) of IEEE. That is, the Compatibility mode, the fundamental transmis-sion method of print data, supports the Nibble Mode(4bitsdata) supporting the Data Uploading to PC, ByteMode(8bits data), and ECP(Enhanced Capabilities Port : 8bits data transmission & receiving) supporting two-wayhigh speed transmission to PC. The Compatibility modeand ECP mode may be simply explained as follows. The Compatibility mode is generally called Centronicsmode and is the protocol used for transmitting data by mostof PC. The ECP mode provides two-way high speed com-munication as the protocol suggested for improved com-munication with peripheral equipments such as printer andscanner. The ECP mode provides two types of cycles in two-waytransmission. They are data and command cycles.Command cycle again has Run-length count and Channeladdressing types. First, RLE (Run Length Encoding) type, having 64-foldcompressibility, is available for the real time data compres-sion, and is used usefully for printer and scanner, whichhave to transmit large capacity of raster image having aseries of same data. Next, Channel Addressing is pro-posed for addressing single structure of multi-device. For example, although the printer channel is processingthe printer image when the fax/printer/scanner have onestructure like this system, they may use parallel port foranother use. This system does not apply to the parallel portInterface.

3-12

CIRCUIT DESCRIPTION


<Figure 10. Compatibility Hardware Handshaking Timing>

1. Write the data to the data register.2. Program reads the status register to check that the printer is not BUSY.3. If not BUSY, then Write to the Control Register to assert the STROBE line.4. Write to the Control register to de-assert the STROBE line.

<Figure 10-1. ECP Hardware Handshaking Timing (forward)>

1. The host places data on the data lines and indicates a data cycle by setting nAUTOFD.2. Host asserts nSTROBE low to indicate valid data.3. Peripheral acknowledges host by setting BUSY high.4. Host sets nSTROBE high. This is the edge that should be used to clock the data into the Peripheral.5. Peripheral sets BUSY low to indicate that it is ready for the next BYTES.6. The cycle repeats, but this time it is a command cycle because nAUTOFD is low.

BYTE 0 BYTE 1


CIRCUIT DESCRIPTION

Repair Manual

<Figure 10-2. ECP Hardware Handshaking Timing (reverse)>

1. The host request a reverse channel transfer by setting nINIT low.2. The peripheral signals that it is OK to proceed by setting PE low.3. The peripheral places data on the data lines and indicates a data cycle by setting BUSY high.4. Peripheral asserts nACK low to indicate valid data.5. Host acknowledges by setting nAUTOFD high.6. Peripheral sets nACK high. This is the edge that should be used to clock the data into the host.7. Host sets nAUTOFD low to indicate that it is ready for the next BYTES.8. The cycle repeats, but this time it is a command cycle because BUSY is low.

BYTE 0 BYTE 1

3-14

CIRCUIT DESCRIPTION


3-3-2-7 USB INTERFACE PART

1. USB function description

As the mode of implementing low cost express PCInterface, USB was applied. At USB, PC plays the role ofroute hub simultaneously by existing in the highest level asthe host. That is, the device supporting each USB is con-nected centering on PC.

The device is available for Interface for the maximum of127. USB cable is composed of total of a set of twisted pairand 2 power lines. Cables have two types.

One is used for express transmission of 12Mbps and maybe extended as long as 5m. The part for implementing USBfunction is included in S3C46MOX(Jupiter3).

For Interface of USB, pull-up of 15KΩ is interfaced to thedata line of high level instruments, and, among data linesof lower level instruments, pull-up resistance of 1.5KΩ isinterfaced to any one.

At this time, D+ line is pulled up for Full Speed device, and,for Low Speed device, D-line is pulled up. For upper levelinstruments(Host, HUB) speed of device is classified inter-faced to low level by detecting any one among D+ and D-.If both lines are in the level of GND at the same time, deviceis judged that low device is not interfaced. In the transmis-sion mode of USB, there are

(1) Control transmission,

(2) Interrupt transmission,

(3) Bulk transmission, isochronous transmission.

Control transmission is for Host to find out configurationinformation from USB device. This is conducted whendevice is interfaced. Interrupt transmission is used whensmall quantity of data is sent periodically. Interval valuemay be known from device in the case of initial setting. Bulktransmission is valid in case of trying to transmit data inlarge quantities or in case of transmitting them accurately.Isochronous transmission should be assured of bandwidth,and is used when transmitting large quantities of informa-tion. Data in voice is used where delay is not allowed butsmall error is allowed. At USB coding mode and bit step-ping are being conducted. First, in case original data is 1,bit shall not change, and only when original data is 001, itshall be inverted. Only while data is 1, 1 and 0 shall berepeated. Also, in case 1, original data, is continued in 6 bit,0 shall be inserted, Also, in the 1st phase of packet, data inthe synchronized pattern shall be sent. About moredetailed information regarding USB, see http//:www.usb.org.

2. operation description

This system, when Host and USB cables are connected,and when +5V is detected in power detector inside chipand Vbus(U15-98), 3.3V comes out through Pull-uP termi-nal. This is also connected to D+ in pattern of hardware andsupports Full-speed. Utilizing Configuration Endpoint,EPO, in USB controller, Plug & Play function is operated.Exchange of information between PCs is accomplishedthrough D+(U15-95) and D-(U15-96) terminals. This termi-nal decides transmission speed depending on connectionof regulator output in USB controller, and decides size ofsignal following USB and SPFC. Signal of general D+ andD- terminals are same as Figure 10-3.

D+

D-

< Figure 10-3. USB Signal Line DIAGRAM >


CIRCUIT DESCRIPTION

Repair Manual

3-3-2-8 HEAD control part

1. Entire description

As part to drive INKJET HEAD, it is composed of ACLK,AGATE, LDCS, LATCHCTL, PCLK, PDATA[3:0], PLOAD,PENABLE signals for controlling Spitfire of CR B’D gener-ating signal, which is driving Nozzle of Head, andPH_ID[1:0] and OK2Print signals receiving from Spitfire.

Here,HEAD being used here is DOUBLE HEIGHT PRINTHEAD, and MONO is configured with 208 NOZZLE, andCOLOR is with 192 NOZZLE.

<Figure 11 HEAD Control Part Timing Diagram>

2. A-LINE driving circuit

13 Address Lines are input into 13 Address Counters insequence at Rising edge of ACLK signal, which is inputserially into Spitfire. Output of this Counter was connectedto each A-line driver, and this driver output becomes A-linesignal. The sequence of signal input into Address Counteris decided by ADIR, and if it is ADIR=0, it is input insequence of A13A1, and if it is ADIR=1, in sequence of A1=> A13. AGATE signal is used to reset Address Counter. Ifit becomes AGATE=1, A-Line output becomes Low state.The cycle of ACLK is 1.5ß¡ in minimum, and Sink current ofeach Driver is 60mA.

3. P-LINE drive circuit

P-Line values are clocked to 4-bit Serial to Parallel ShiftRegister Clock in Spitfire ASIC, and ASIC shall clock-in P-line NO. of fitting value at Rising Edge of PCLK. These val-ues are latched to Holding register at Rising Edge ofPLOAD. PLOAD Pulse Duration is 50n, and P-line value ofHolding Register is done AND with PENABLE signal inorder to generate appropriate Fire Pulse. PLCK is availablefor handling as much as 4MHz. Drive Current of P-line is400mA. Data of P1°≠P4 is shifted to PDATAO, that of P5-P8 shifted to PDATA1, that of P9-P12 shifted to PDATA2,and that of P13-P16 shifted to PDATA3.

4. Control Signal

• The signal loaded on PDATAO - PDATA2 at Rising edgeof LATCHCTL(Latch Control Nibble) is used as functionas follows in Spitfire.

- PDATA0 == ADIR —> Low : ACLK is operated in CountDown, High : ACLK is operated in CountUp.

- PDATA1 == When Fault Test —> High, check whetherP-Line of Head became short with GND.

- PDATA2 == When Print Head ID Check —> high,make sure that Check mode is set, and,after that, by using the PDATA0~PDATA2LIne, make A1-A3 signal for sending, andHead ID shall come out with PH_IDn out-put. At this time ID could be displayed onlyif each Substrate heater is turned on.

• The signal loaded into PDATAO-PDATA3 at Risingedge of LDCS(LoadHtrcs) signal is used in the follow-ing functions in Spitfire.

- PDATA0 == BLKHTR—> High : Turn on SubstrateHeater of Mono Head.

- PDATA1 == COLHTR—> High : Turn on SubstrateHeater of Color Head.

- PDATA2 == nHSM—> Low : Enable Select Signal ofMono Head.

- PDATA3 == nHSC—> Low : Enable Select Signal ofColor Head.

When Substrate Heater is turned on, Over-current Checkcircuit is operated, automatically, and,if the current is above750mA, the printer stops operation after OK2PRTbecomes low.

The Timing diagam below shows signal timin for the P-line blockACLK

An

PCLK

PDATA

PLOAD

PENABLE

Pn

3-16

CIRCUIT DESCRIPTION


3-3-2-9 SYNCHRONOUS SERIAL INTERFACE part

As the part interfacing with THUNDERBOLT ASIC, it con-sists of /TBCS,TBCLK,TBDO. In sending SERIAL DATAof 13 BIT to Thunderbolt ASIC, meaning of each bit is asfollows. BIT 1 is the bit to do On/Off VPH(+11.82V), BIT[2:7] is the bit for driving MOTOR 1, BIT [8:13] is the bit todrive MOTOR 2. MOTORs are available for being used asSTEPPER MOTOR and DC MOTOR respectively.

3-3-2-10 MOTOR control part (DIR, PWM, LFPHA,LFPHB, LFIA[0:1],LFIB[0:1])

S3C46MOX(Jupiter3) is arranged to support one Stepmotor and one DC motor. This system does not use theMotor control part provided by S3C46MOX(Jupiter3).

< Figure 12 SYNCHRONOUS SERIAL INTERFACE TIMING DIAGRAM >

/ TBCS

TBCLK

TBDO

Tcs-sclkTcs-sclk

bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13SDI stays at last value

MSBLSB

Data Latcked on the rising edge of SCLK

time

TdhdTdsu

STEPPER MOTOR DC MOTORBIT 1 VPH_ENABLE VPH_ENABLEBIT 2 MOTOR1_CURR_I1_PHASEB Not used in this mode.BIT 3 MOTOR1_CURR_I0_PHASEB Not used in this mode.BIT 4 MOTOR1_DIR_PH_B Not used in this mode.BIT 5 MOTOR1_CURR_I1_PHASEA Not used in this mode.BIT 6 MOTOR1_CURR_I0_PHASEA Not used in this mode.BIT 7 MOTOR1_DIR_PH_A MOTOR1_DIRECTIONBIT 8 MOTOR2_CURR_I1_PHASEB Not used in this mode.BIT 9 MOTOR2_CURR_I0_PHASEB Not used in this mode.BIT 10 MOTOR2_DIR_PH_B Not used in this mode.BIT 11 MOTOR2_CURR_I1_PHASEA Not used in this mode.BIT 12 MOTOR2_CURR_I0_PHASEA Not used in this mode.BIT 13 MOTOR2_DIR_PH_A MOTOR2_DIRECTION


CIRCUIT DESCRIPTION

Repair Manual

3-3-2-11 GENERAL PURPOSE I/O PORT of S3C46MOX(Jupiter3)

1. J3 Assigned GCS Ports

2. J3 Assigned GPI Ports

3-18

CIRCUIT DESCRIPTION


3. J3 Assigned GPO


CIRCUIT DESCRIPTION

Repair Manual

3-3-3 RESET circuit

This system is configured with PRIMARY RESET(/POR) ofPower Reset, Reset by WATCH DOG TIMER, externalPRIMARY RESET, and SECOND RESET(/_F_POR)which was done AND. PRIMARY RESET SYSTEM is usedfor resetting MAIN CONTROLLER(U15) when SystemPower is authorized, and SECOND RESET resets FLASHMEMORY(U7). Figure 15 below is BLOCK DIAGRAMrelated to the reset of entire system.

When +3.3V reaches 3.1V so that system may operate,POWER MONITOR(U13) moves to High(+3.3V) aftermaintaining low(OV) in the degree of 50mS-200mS outputwhile monitoring it. This Reset signal is input into MFPCONTROLLER(S3C46MOX(Jupiter3 : U15) right away,and MFP CONTROLLER becomes awake. And it releases/F_POR after MCLK 1 clock.

3-3-3-1 POWER MONITOR ( U13 )Since +3.3V power supplied to XC61FN3112MR is unsta-ble, when it becomes 3.1V(3.038V~3.162V), it is checkedas the POWER FAILURE. And the output terminal ofXC61FN3112MRF becomes LOW(0V),it is applied toS3C46MOX(Jupiter3)(U15), and RESET(LOW ACTIVE) isoperated When S3C46MOX(Jupiter3) Reset is cancelled,FLASH MEMORY connected to /F_POR ofS3C46MOX(Jupiter3) is Reset together. Output terminal ofXC61FN3112MRF is pulled up 100KΩ in the structure ofOpen drain.

3-3-3-2 WATCH DOG OUTPUT (/F_POR)

Since WATCH DOG TIMER, which is ProgrammableCounter in S3C46MOX(Jupiter3) is set as disable for INI-TIAL STATE, it shall be set as Disable so that it won’t oper-ate, and after it is initialized for operation, it shall be reusedby setting it Enable. When Watch Dog Reset occurs, it isabout 10mS depending on the value set at the initial stage.And Counter value of Watch Dog Timer is changed by theprogram. Reset signal (/F_POR,UI5-106) shall be generat-ed, and entire system shall be Reset and initialized.

< Figure 13. POWER RESET BLOCK DIAGRAM >

3-20

CIRCUIT DESCRIPTION


3-4 MEMORY

3-4-1 General InformationThe memories of this system are 1MB of Flash Memory(U7), 8MB of SDRAM (U8), and 8MB of SDRAM (U27).

3-4-2 Construction of the MemoryThe Flash Memory and SDRAM are selected by eachChip Select (/ROM_CS, /SCS1, /SD_RAS, and/SD_CAS), and data accesses with Half Word unit.

3-4-3 Memory Backup and Self Refresh3-4-3-1 Self Refresh Mode

It is a Mode for maintaining the stored data at SDRAMwhen Set Main Power is not supplying for a long time asthe case of the Battery back up. When POR (U15-46) islow, set the S3C46MOX (U15)/RAS(U8-18), /CAS(U8-17), CS(U8-19), and CLKE(U8-37) to LOW, and support/WE(U8-16) to HIGH to operate the Self Refresh. At thismoment, the consumption of the electronic current isremarkably reduced (1mA). The CLKE has to be main-tained as LOW at Self Refresh Mode, and all the inputsignals including Clock is ignored at this point. For anescape from the Self Refresh Mode, the Clock must besupported normally, and CLKE must be changed toHIGH.

3-4-3-2 Memory Backup Circuit

U1, U2, and U3 (DRAM I/F Circuit) supply the /RAS and/CAS signals (DRAM Control signal) via Invert signal (U3-1) of /F_POR and Gate (U1-1, U1-2), and control theEnable signal (SD_CKE) by /F_POR (Power on Reset).It means that DRAM Control Signal might not be affectedbefore /F_POR is released, that is, the power is instable.

BACKUP Power Circuit (R12, R13, Q8, R17, C31, D2,R21, C30) converts the main power and Backup powerby /F_POR signal. Q2 supplies proper amount of theelectronic current (hFE=120, 300mA) from the mainpower to operate SDRAM, and it is driven by SwitchingTR Q8 which is controlled by /F_POR signal.Backup in a short period of electricity failure is guaran-teed by using electrolysis CAP (1F/5.5V:C17) withBackup power. Serious resistance of R16 is converted tothe main power, so it never interrupts the main power bygiven a limit of current when C17 is charged. C31 helpsto minimize the power drop in case of power change.D2 and R21 are supplied to RTC Power (U15-87) viaVB2 for RTC Backup.

3-5 Image processing part (U21)

3-5-1 General description

Image Processor OA-980(U21) is mainly configured withOn-chip µ Controller(8bit), Scanner Interface Section(PI),Image Processing Section(IP), Memory InterfaceSection(MI), JBIG Comp & Decomp Section, Rotate andInkjet Engine Section, Printer Interface Section(PO), 1284Parallel Port Interfaced and Host Interface Section(HI).(See Figure 14 )

3-5-1-1 Physical

3-5-1-2 Features & Functions

• 10bit scanning interface: Supports CIS and CCD interface.Needs external ADC(up to 16bit).

• Image processing Section: Full quality RGB to CMYK or 6 color conversionPhoto/Text detect allows mixed documents.Arbitrary image scaling using true interpolation.Automatic contrast and brightness correction.Error diffusion or programmable dither arrays.

• JBIG compression block: JBIG/MH/MR/MMR Comp. & Decomp.

• Inkjet engine format: Rotates data to suit the Lexmark engine format

• Printer Interface section: Supports a single byte DMA with 150MHz clock speed.

• Microcontroller interface part: 8bit multiplexed bus acts as address and data bus

• General purpose input and output port: 30 GPIO pins.

Core Process Drive power Package Design/frequency

8bit Micro- 0.35U 3.3V 208pin OASIScontroller CMOS 75MHz QFP


CIRCUIT DESCRIPTION

Repair Manual

3-5-2 OA-980 Description by functions

3-5-2-1 Clock Control Section

Internal drive frequency operates classified into two parts.Almost all On-chip µ Controller(8bit) Module drives byMain_clock, and Printer Interface Section(PO) only drivesby Base_clock. Main_clock and Base_clock may be setwith frequency each desires by receiving Clock suppliedfrom outside by PLL Logic.

At present, system Main_clock and Base_clock are eachset in 48MHz, and may be checked at SDRAM_CLK ofSDRAM(U27). Clock supplied from outside does not useseparate crystal, but 48MHz is supplied by IP_CLK,CLK_Out of Jupiter3(U15).

The one which pulled up Main_EXT(pin46) andBase_EXT(pin43) is the Option using internal PLL, and, atthe time of Pull-up, it does not use internal PLL, but just useClock supplied to Main_CLK(pin45) and Base_CLK(pin42)as Main_clock and Base_clock.

3-5-2-2 Internal Microcontroller

8bit RISC Microcontroller is built-in, and Address areawhich Micro-controller control is 64kbyte. At the same timewhen cache is built in for control of more efficient SDRAM,it possesses Hook function, namely the internal Boot ROM256byte required for self-initialization function, too.

1. Memory Map

2. Power On/Off Reset

• Power On Reset

Depending on the signal state of Reset_L(pin35), OA-980 may be reset in the manner of hardware. Reset is onat “Low” state and, at “High” state, Reset is Off.Accordingly, in order for OA-980 to operate normally,after the System initialization, the /IP_RST ofJupiter3(U15-31) shall be converted to “High” state. Inorder for safe Hardware Reset to be accomplished, itshould be maintained in “Low” state for more than 1000Main_clock(10uS).

• Power Off Reset

PWR_down(pin107), for SDRAM(U27) to advance to theSelf Refresh Mode Reset_L(pin35) at the Power SafeMode, shall advance to the Reset Mode earlier than theminimum of 1uS. This System does not use it.

3. Hook function : Self-initialization function

In case self ROM is connected to OA-980 as in Figure (15),although the execution file is downloaded to SDRAM, theexecution file is initialized by receiving download fromMemory. This execution file is the ROM File supporting sothat all functions of Image processing related to OA-980 aswell as register setting value required for initialization(Copy,PC scan, MultiMediaCard Print) may operate normally.

<Figure 14. OA-980 Block Diagram>

0x0000 .... 0x00ff Boot ROM0x0100 SDRAM program store

.... and0xfbff SDRAM stack

0xfc00 .... 0xffff HW registers

3-22

CIRCUIT DESCRIPTION


Hardware Reset "High"

Boot ROM checks

connection of ROM

After Software Reset, advance to

preparation mode to download execution

file from Jupiter 3

Download execution file on SDRAM(U27)

from

"Ready"

ROM connected

No ROM

Download the execution file to SDRAM (U27)

from Flash Memory (U9) of Jupiter 3

Initialize OA-980 by the execution file

downloaded on SDRAM (U27) & have it to

enter in the operation mode.

<Figure 15. Boot Code Flow Diagram>


CIRCUIT DESCRIPTION

Repair Manual

3-5-2-3 Host Interface Section(HI : Jupiter3 interface section)

Unlike the existing DuoIP sequence, OA-980 exchangesCommand and data with Jupiter 3 in the Multiplexed 8bitBus(data & address) mode. Namely, it does not receiveAddress and Data simultaneously, but receive data afterreceiving Address first using Data Bus of Jupiter3.

HI Section also supports the data movement in the DMAmode. Accordingly, when transmitting large capacity ofImage data(RGB data of MultiMedCard), it uses the DMAmode.

1. Multiplexed 8bit Bus(data & address) mode

once Jupiter3 may not support Multiplexed 8bit Bus(data &address) mode used by OA-980, it configured a circuit addi-tionally so that mutual Interface may be possible by makingrequired signal using two NOR GATE(UR16) and one ORGate(U40).

As REG_ADDR_VAL(pin27) signal is the signal for OA-980to play a role of informing that value input into 8bit of OA-980 Bus is not Data but Address value, when ADDR(10) is“High” and /IP_CS, /WR “Low,” “High” shall be generated asshown in the circuit diagram. See figure (16). At this time,since /WR_L(pin31), the Write signal of OA-980, should bemaintained in “High,” the signal shall be generated in caseactual Write is accomplished with one OR Gate(U18),namely, only when ADDR(10) is “Low,” WhenREG_ADDR_VAL (pin27) is “High,” input the Address valueof OA-980, and when “Low, from the standpoint of Jupiter3,it may Read or Write One Byte Data using two Cycles byReading or Writing relevant Data of (to) Address.

<Figure 16. Hi Block Timing diagram(1)>

3-24

CIRCUIT DESCRIPTION


2. DMA mode

DMA mode is the method of Reading or Writing Data inBlock unit by activating two DMA Channels of OA-980respectively. When A8 or A9 is “Low” and when /IP_CS is“Low,” GDMA of Jupiter3 Reads or Writes in Memory toMemory mode, as the appropriate DMA Channel is activat-ed. See Figure (17). Of course, it performs required DMAregister setting in Multiplexed 8bit Bus(data & address)mode before DMA is accomplished.

3-5-2-4 Scanner Interface Section(PI)

It directly controls 16bit ADC and 600dpi color CCD con-nected to CCD, processes Shading and Gamma correc-tion, the basic course required for Image process of RGB12bit(8+4bit) data transferred from ADC, then performs thefunction of storing the data in SDRAM of OA-980 throughMI Block.

<Figure 17. Hi Block Timing diagram(2)>


CIRCUIT DESCRIPTION

Repair Manual

3-5-2-5 Image Processing Section(IP)

After performing color compensating required for theSystem for RGB digital data input, it conducts the role ofconverting to CMYK data printable. IP Block consists of fourModules mainly.

- Photo text detect

- Zoom and dpi adjust

- Color space conversion

- Half toning and loss less JPEG

3-5-2-6 Memory Interface Section(MI)

MI Block consists of four Channels, located between exter-nal SDRAM(U27) and blocks inside OA-980, and is con-trolled so that the flow of all data may be accomplished moreefficiently.

3-5-2-7 JBIG Comp & Decomp Section

By condensing Image data processed at Blocks into JBIGalgorithm and save them in external SDRAM(U27), it shallhave Memory domain used more efficiently. Naturally, evenwhen moving Image data which was condensed to JBIG, toother block, it is conveyed to Image data freed from conden-sation.

3-5-2-8 Rotate and Inkjet Engine Section

After Image CMYK Data which ended all image processingis converted to Format so that Inkjet Printer Engine mayprint, it plays the role of saving them on the externalSDRAM(U27).

The Data stored in the external SDRAM(U27) is transferredto Head Control Part of Jupiter3 through MI and HI Block ofOA-980 by DMA of Jupiter3, and then printed by Spitfire.

3-5-2-9 Printer Interface Section(PO)

When the Image process required for PC Scan (See Fig.19) is completed, OA-980 requests that /IP_REQ signal inPO_Block should take the Scan Image Data from theExternal DMA Block of Jupiter3(U15). The External DMABlock of Jupiter3(U15) generates not only /IP_ACK signalto bring Data by Byte as the unit but also /RD signal to bringthe Data. The External DMA Block of Jupiter3(U15) storesthe Data in SDRAM(U9) and then restore /IP_ACK as"High" to receive a next Data/.

As DMA Timing properties between Jupiter and OA-980 donot match, /IP_ACK0 is separately created to prevent BUScollision by using one OR-Gate(U18-3) so that OA-980 mayuse the BUS only in /RD in the way of inputting the /ACKsignal into OA-980 only when /RD is actually produced,while Jupiter3 may use in /WR, as shown in the Timing ofFig. 18. That is, since OA-980 sends Data to BUS during/ACK signal section, BUS collision occurs between DMA ofJupiter3 and /WR section, where /RD, /WR are all carriedout during /ACK.

<Figure 18. PO Block DMA Timing Diagram>

3-26

CIRCUIT DESCRIPTION


3-5-3 Copy Data Flow for OA-980


CIRCUIT DESCRIPTION

Repair Manual

3-5-4 OA-980 I/O PORT

3-28

CIRCUIT DESCRIPTION



CIRCUIT DESCRIPTION

Repair Manual

3-6 CCD MODULE and ADC Part

3-6-1 CCD Module General Description

CCD Module has the structure transferring RGB data tobe converted into the digital signal through ADC on thebasis of the level of analog signal to OA-980, the ImageProcessor, which divides the signals reflected by emittinglight to document into R, G, B data according to each fre-quency.The voltage used in the CCD Module are 11.75V for ana-log signal of RGB, 5V as input for CCD and other ele-ments. The input part of CCD Module consists ofCCD_TG, CCD_CLK1,CCD_CLK2 and CCD_RS, theoutput of OA-980(U21), CCD_TG controls the scan line,which is set variously according to copy mode, color andmono, and scan resolution. CCD_CLK1 and CCD_CLK2are clocks by each pixel, CD_RS is reset signal of eachpixel. Since the pixel of 1/2 cycle of CCD_CLK1 andCCD_CLK2 is sampled, color signal sends RGB data tooutput for 1/2 cycle, and controls the pixel of 1/2 cycle formono. Therefore, the output signal from the CCD Moduleclassifies the signals received by RGB channel accordingto each frequency band and uses each videosignal(CN1) as the input data of ADC(U16).

TG, CLK,RS to be used are as follows.

< TG, CLK,RS >

Color Copy Mono Copy

CCD_TG 5mS 2.5mS

CCD_CLK1,CCD_CLK2 1.6uS 800uS

CCD_RS 800uS 400uS

< TG, CLK,RS >

3-30

CIRCUIT DESCRIPTION


3-6-2 ADC

Description ADC(U16) is the input data that change theanalog signal of RGB to the digital signal of 16bit (8bit +8bit) so that it may be used as the input of OA-980(U21),image processor, while VSMP(_ADC_VSMP) is used as asampling signal for each pixel of RGB. That is, it controlsthe signal for one pixel like CLK1,CLK2 of CCD and itsmaximum sampling rate is of color 2MHz mono 4MHz.MCLK(ADC_CLK) is CLK for the signal of VSMP, the rela-tion between MCLK and VSMP is as follows. The relations among SCK(ADC_SCK), SDI(ADC_SDI) and

SEN(ADC_SEN) are equivalent to the control bit for regis-ter setting to mode, output signal appears in 8bit unit from

OP0 to OP7, and 5V/3.3V will be used as the power source.

Color Mono

VSMP 800ns(1.25MHz) 400ns(2.5MHz)

ADC_CLK 133ns(7.5MHz) 133ns(7.5MHz)

VSMP:MCLK 1:6 1:3

RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB

BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB

GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB RA RBGA GB BA BB


16.5 MCLK PERIODS

ADC_CLK

VSMP

OP[7:0](DEL = 00)

OP[7:0](DEL = 01)

OP[7:0](DEL = 10)

OP[7:0](DEL = 11)


BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB

GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB RA RBGA GB BA BB


16.5 MCLK PERIODS

ADC_CLK

VSMP

OP[7:0](DEL = 00)

OP[7:0](DEL = 01)

OP[7:0](DEL = 10)

OP[7:0](DEL = 11)

<Figure 20. Color mode MCLK, VSMP>

<Figure 20-1. Color mode MCLK, VSMP>


CIRCUIT DESCRIPTION

Repair Manual

3-7 THUNDERBOLT ASIC description

3-7-1 Entire description

THUNDERBOLT ASIC is configured with SERIAL INTERFACE INPUT PORT interfacing Main controller, 2 DC-DC ConverterControllers, Power On Reset Generation Circuit, and Motor drive part.

3-7-2 THUNDERBOLT FUNCTION DESCRIPTION

3-7-2-1 SERIAL INTERFACE INPUT PORT

To MAIN CONTROLLER(S3C46MOX(Jupiter3)), /TBCS,TBCLK,TBDO are connected with MAIN CONTROLLER (S3C46MOX(Jupiter3)), and see the figure for Timing.

/ TBCS

TBCLK

TBDO

Tcs-sclkTcs-sclk

bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13SDI stays at last value

MSBLSB

Data Latcked on the rising edge of SCLK

time

TdhdTdsu

< Figure 21. SERIAL INTERFACE INPUT Timing Diagram >

Parameter Description Min Typ Max UnitsFclk Serial clock frequency 2.5 4 MHz

Tclh SCLK high width 125 200 - nsec

Tcll SCLK low width 125 200 - nsec

Tcs-sclk Delay nCS falling to first SCLK rising 250 800 - nsec

Tsclk-cs Delay last SCLK rising edge to nCS rising 250 400 - nsec

Tdsu Data valid to SCLK set up time 125 200 - nsec

Tdhd Data hold time 125 200 - nsec

Trd SDI rise time 5 20 nsec

Tfd SDI fall time 5 20 nsec

Trc SCLK rise time 5 20 nsec

Tfc SCLK fall time 5 20 nsec

< Figure 21-1. SERIAL INTERFACE INPUT Timing Specification >

3-32

CIRCUIT DESCRIPTION


3-7-2-2 DC-DC Converter Controller

This System uses VCC by converting it to +5V, and +3.3V, the power source of the system, is obtained from the +5V convert-ed by using REGULATOR IC to use. VPH is used as the head power by converting it to +11.82V.

3-7-2-3 Power On Reset Generation Circuit

This System does not use Power On Reset Generation Circuit.

3-7-2-4 Motor drive part

This System uses DC Motor for CR(Carriage Return) MOTOR, and Stepper motor for LF(Line Feed) motor.

• CR(Carriage Return) MOTOR drive circuit description

1 CR MOTOR specification

CR MOTOR performs reciprocating movement of CARRIAGE from side to side so that INK CARTRIDGE may print on thepaper.

• MOTOR TYPE : PM DC MOTOR “declination”

• Drive voltage : +30VDC

• Winding line resistance : 12Ω ± 2Ω

• Driver IC : Thunderbolt

2. CR MOTOR drive

2-1. DC Motor operation

DC Motor drive uses positive phase terminal(+) and anti-phase terminal(-) bound together respectively using 2nd MotorDriver(MD2) of Thunderbolt ASIC inside, and controls two-way operation of DC motor, by receiving input of "DIR_DCM,"7th bit among "PWM"(DC-motor Pulse Width Modulation) signal, output of Jupiter-III, and 13Bit Serial Port Inputs("TBDO"Signal) coming into Thunderbolt ASIC transmitted from Jupiter-III. This Driver is driven by VBULK power source(+30V),and on terms of Motor Stall not being generated, it is designed to supply 750mA current, and 2.4A current to output ter-minal for maximum length of 100ms.

< Figure 22. DC-DC Converter Controller Diagram>


CIRCUIT DESCRIPTION

Repair Manual

2-2. Driver Spec.

1) Absolute Maximum Rating

2) DC Specification

3) AC/Transient Specifications

4) Truth Table

3. LF(Line Feed) MOTOR drive circuit description

3-1. LF MOTOR

• MOTOR TYPE : 2-2 Bi-polar Stepper Motor

• Drive Voltage : +30V

• Spherical line resistance : 5Ω ± 7%

• Driver IC : Thunderbolt

3-2. LF Motor Operation

LF Motor(Stepper Motor) drive uses the first Motor Driver(MD1) in Thunderbolt ASIC, and Drive Pulse is output from 4terminals of A+, A-, B+,and B-. two H letter type Drivers. Drive Pulse controls size and flow direction of current(A+ =>A- or A- => A+) according to bit7-bit No.13 signals among 13Bit Serial Port Inputs("TBDO" Signal) coming intoThunderbolt ASIC transmitted from Jupiter-III. This Driver is driven by VBULK power source (+30V), and on terms ofmotor stall not being generated, it is designed to supply current of 600mA, maximum 700A current to each phase ofmotor.

Name Description Condition Min Max Units

Vout DC Motor Driver Output Voltage 42 Volts

Iout DC Motor Driver Output Current 2.4 A

Name Description Condition Min Nom Max Units

fPWM PWM frequency Ta = 25C 19 20 21 KHz

DIR_DCM PWM #NAME? #NAME? #NAME? #NAME?0 0 On Off On Off0 1 Off On On Off1 0 On Off On Off1 1 Off Off Off On


I peak Peak DC Motor Driver Output Current Not Stalled 0.75A Volts

I out DC Motor Driver Sustaining Current On Time=100ms 1.6 2.4 A

3-34

CIRCUIT DESCRIPTION


3-3. Driver Spec.

1) Absolute Maximum Rating

2) DC Specification


V out DC Motor Driver Output Voltage 42 Volts

I out DC Motor Driver Output Current 0.7 A


I peak Peak DC Motor Driver Output Current Not Stalled 0.6A Volts


CIRCUIT DESCRIPTION

Repair Manual

3-8-1 Overview

OPE BOARD is separated from the Main Board functional-ly, and operates entire Micom(HT48C5A-000Z) in theBoard. OPE and Main exchange mutual information usingUART(universal asynchronous receiver/transmitter) chan-nel. Also, Resetting of OPE is designed to control at theMain. Micom in OPE performs key-scanning and LCD, LEDdisplay control, and senses document detect, Scan positionand so on. When information is generated from OPE(keytouch, sensor level change, etc.), it sends specific codecoping with the situation to Main, and the Main operatessystem by analyzing this code. If the Main tries to displaydata on OPE, the Main sends data to OPE via UART lineon the basis of the format specified, and OPE displays it toLCD.

• This system does not apply document detect and SCANposition.

3-8-2 UART

OPE and MAIN exchange information mutually by usingasynchronous communication mode(UART), and in fullduplex. Band rate is 9600bps, and uses 7.37MHz resonatoras oscillating element. It engages in communication with8bit data without parity bit. UART line has two lines for Txand Rx, and the default level is in the 'high' state. For com-munication, the start bit(low level) is transmitted before 8bitdata. When the data transmission(8bit) is completed, thehigh state is maintained as the stop bit(high level) is trans-mitted. Data is transmitted from LSB(DO), and MSB(D7) istransmitted lastly.

3-9-1 UART communication

1) UART TX FORMAT

Codes for change of KEY, TOUCH, SENSOR LEVEL andso on are transmitted in single code without PRE/POSTDATA, and OK or Error messages to check if communica-tion is performed properly are also transmitted in singlecode. Provided that, in case the Main requested a certainvalue(LCD, other register) particularly, data requested istransmitted followed by sending Post Data('EOH') first.

2) UART RX FORMAT

Data being received will be arranged to be received accord-ing to the following specified format to know what data theyare.

DATA are received in the sequence of A,B,C, and D, andthe Check sum to check if the transmission is made prop-erly will be found by doing XOR data from A to C.

◊ OPE

3-8 Basic concept

3-9 UART operation

start stopbit data 8bit (D0 ~ D7) bit

D0 D1 D2 D3 D4 D5 D6 D7

a) Type of data received

b) Number of data (n+1) received after.

----------

c) DATA(N)

----------

d) Check sum(1)

3-36

CIRCUIT DESCRIPTION


3-9-2 UART communication DATA

1) UART transmission DATA(received by the Main side)

(Note) 1. After this, keep waiting until there is response from the Main.

2. The case of longer time(longer than 10ms) elapsed longer than waiting time required for Interface is regarded as fail

3. After this code went out, then data requested it goes out.

• KEY MATRIX

Types Status DATA used port Level Remarks

key data ON 11H~ 88H PORT PC0~PORT PC7 L

OFF af H H

SCAN POSITION sensor ON a5 H PORT PB3 H SCX-1150F not applied

OFF a4 H L

DOC. detector sensor ON a1 H PORT PB-5 L Check if the scan cover is opened.

OFF a0 H H

For initial use of initial OPE ee H After power on, generated only once

UART communication OK b0 H (Note 2)

ERR c0 H

LCD interface of OPE OK df H When failed in the interface once &when succeeded first(Note 2)

ERR d0 H

Self initial generation of OPE e2 H LCD data keeps status quo

Send data requested by the Main e0 H Data types:LCD, other(Note 3)

(1_H) (2_H) (3_H) (4_H) (5_H) (6_H) (7_H) (8_H)

(_1H) Quality Copy Page 1 RESERVED 2 RESERVED 3 M1

(_2H) Zoom Rate Special Copy 4 RESERVED 5 RESERVED 6 M2

(_3H) Copy_black Copy_Color 7 RESERVED 8 RESERVED 9 M3

(_4H) Setup Vol_Left * RESERVED 0 RESERVED # M4

(_5H) Enter Vol_Right Resolution RESERVED FAX_Black RESERVED M8 M5

(_6H) CANCEL Contrast FAX Forw RESERVED FAX_Color RESERVED M9 M6

(_7H) Receive Mode Search/Delete Redial/Pause RESERVED OHD RESERVED M10 M7

(_8H) RESERVED RESERVED Ink Save RESERVED Paper Save RESERVED Toll Save Scan to

<SCX-1150F OPE B’D KEY MATRIX>


CIRCUIT DESCRIPTION

Repair Manual

2) Received DATA(transmitted by MAIN)

1. DATA TYPE

2. NO. OF DATA

• In case DATA is N BYTE, N+1

3. DATA

In case DATA TYPE is LCD DATA, it is configured with ASCII CODE to be displayed.In case DATA TYPE is LED DATA, it is 1 BYTE.

LED DATA BIT ASSIGNMENT:

4. CHECK SUM

The value done XOR all of them from DATA TYPE to DATA.

5. Change of LCD types

<2 LINE * Change to 16 character LCD>

DATA TYPE : b1 HNO. OF DATA : 2DATA : 26 HCHECK SUM : b1h XOR 2 XOR 16h = a5 h

<1 LINE * Change to 16 character LCD>

DATA TYPE : b1 HNO. OF DATA : 2DATA : 26 HCHECK SUM : b1h XOR 2 XOR 26h = 95 hDEFAULT : 2 LINE 16 Character LCD

In case the MAIN does not change the LCD types, it is the Default LCD state of OPE MICOM.

* SCX-1150F uses 1 LINE LCD.

DATA types Meaning Remarks

a1 H LCD DISPLAY DATA(FULL LINE)

a2 H LCD DISPLAY DATA(1'ST LINE)

a3 H LCD DISPLAY DATA(2'ST LINE)

a4 H LED DATA

b1 H Change of LCD types

DATA BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

LED NO. LED 0 LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 LED 7

3-38

CIRCUIT DESCRIPTION


3-10 I/O PORT configuration and use usage

It has 32 I/O Ports, and 24 Ports of them are arranged to decide I/O direction with Software Control, and the rest 8 Ports arearranged to be used for Input or Output only. All of I/O Ports are classified into four Blocks according to the characteristics ofI/O Control, and each Block consists of 8 Ports.

1) Assignment of Port PAX

-. PA0 : RESERVED

-. PA1 : LED 1

-. PA2 : RESERVED

-. PA3 : RESERVED

-. PA4 : RESERVED

-. PA5 : RESERVED

-. PA6 : RESERVED

-. PA7 : RESERVED

2) Assignment of port PBX

-. PB0(Output) : LCD Enable

-. PB1(Output) : LCD R/W

-. PB2(Output) : LCD RS

-. PB3(Input) : GND

-. PB4(Input) : Unused (Pull-up)

-. PB5(Input) : GND

-. PB6(Output) : UART TXD in Main UART

-. PB7(Input) : UART RXD from Main UART

Type I/O Control I/O direction USE Remarks

PA X Byte Control I/O => Output LED Control

PB X Byte Control In : 4, Out : 4 UART, LCD, Sensor

PC X Byte Control I/O => Input Key Input

PD X Byte Control I/O => Output LCD Data, Key Scan


CIRCUIT DESCRIPTION

Repair Manual

3-11 FAX Transceiver

3-11-1 General Information- This circuit treats the Transmit signal of modem and between LIU and modem.

3-11-2. Modem(U19)- FM336 is a Single Chip Fax Modem. It functions as a modem, DTMF Detection, and DTMF signal function. The main

ports of this modem are as follows. TXA 1, 2 (PIN 28, 29) is a sending output port from modem, and RIN (PIN32) is areceiving input port. /POR (PIN34) is a signal from OA-980 (U21), which initializes the modem without system power off.D0~D7 (PIN87~95) are Data Bus. RS0~RS4 (PIN 96,97,2,3,4) are Register Selection signals inside of modem and definethe Modes. /CS (PIN5) is a Modem Chip Selection signal. /RD (PIN 7) is a control signal for reading, and /WR (PIN6) isa control signal for writing. IRQ (PIN79) is a Modem Interrupt Output signal. The speed of FM336 is MAX. 33.6K bps.

3-11-3. Sending- This circuit treats a sending output of Analog signal from modem (U19, FM 336). The output signal by each mode is out-

putted the Differential TX signal from modem TXA1, 2(PIN28, 29), and the Differential TX signal goes to telephone line viaMatching Transformer (600:600, T2) LIUB’d.

3-11-4. Receiving- The analog signal via Matching Transformer (600:600, T2) of LIU Bíd is directly transmitted to Receiving input RIN

(PIN32) of modem.

MODEM

FM336

(U19)

TXA1

RIN FAX

TXA2

Matching

Transformer(T2)

LIU PBAMAIN PBA

< Fax Transceiver >

3-40

CIRCUIT DESCRIPTION


3-11-5. FM336 FEATURES

• 2-wire half

- duplex fax modem modes with send and receive data rates up to 33600 bps.- V.34, V.17, V.29, V.27 ter, and V.21 channel 2- Short train option in V.17 and V.27 ter

• 2-wire full

- duplex data modem modes- V.21, V.23 (75 bps TX/1200 bps RX or 1200 bps TX/ 75 bps RX)

• PSTN session starting- V.8 signaling

• HDLC support at all speeds- Flag generation, 0 bit stuffing, ITU CRC- 16 or CRC- 32 calculation and generation- Flag detection, 0 bit deletion, ITU CRC- 16 or CRC- 32 check sum error detection- FSK flag pattern detection during high speed receiving

• Tone modes and features

- Programmable single or dual tone generation- DTMF receive- Tone detection with three programmable tone detectors

• Serial synchronous data

• Parallel synchronous data

• Automatic Rate Adaptation (ARA) in V.34 Half-Duplex

• TTL and CMOS compatible DTE interface

- ITU-T V.24 (EIA/TIA-232-E) (data/control)- Microprocessor bus (data/configuration/control)

• Receive dynamic range: 0 dBm to –43 dBm for V.17, V.33, V.29, V.27terand V.21, –9 dBm to –43 dBm for V.34 half-duplex

• Programmable RLSD turn-on and turn-off thresholds

• Programmable transmit level: 0 to -15 dBm

• Adjustable speaker output to monitor received signal

• DMA support interrupt lines

• Two 16-byte FIFO data buffers for burst data transfer with extension up to 255 bytes

• NRZI encoding/decoding

• Diagnostic capability

• +3.3V operation with +5V tolerant inputs

• +5V analog signal interface

• Typical power consumption:- Sleep mode: 20 mW

- Normal mode: 250 mWa

• 100-pin PQFP package


CIRCUIT DESCRIPTION

Repair Manual

3-11-6. Signaling Rates, and Data Rates

3-42

CIRCUIT DESCRIPTION


3-11-7. Modem Functions Interface Signals


CIRCUIT DESCRIPTION

Repair Manual

1 RESERVED - - 51 RESERVED - -2 RS2 IA HOST Interface 52 VSUB GND -3 RS3 IA HOST Interface 53 VSS GND -4 RS4 IA HOST Interface 54 NC - NC5 /CS IA HOST Interface 55 NC - NC6 /WR IA HOST Interface 56 Sleep MI Modem Interconnect7 /RD IA HOST Interface 57 VDD1 PWR -8 /RDCLK OA DTE Serial Interface 58 RESERVED - -9 /RLSD OA DTE Serial Interface 59 RESERVED - -10 TDCLK OA DTE Serial Interface 60 NC - NC11 TXD IA DTE Serial Interface 61 SR1IO MI Modem Interconnect12 /CTS OA DTE Serial Interface 62 VCORE PWR -13 VDD1 PWR - 63 VDD1 PWR -14 RESERVED - - 64 XTCLK IA DTE Serial Interface15 RESERVED - - 65 VSS GND -16 VSS GND - 66 RESERVED - -17 NC - NC 67 RXD OA DTE Serial Interface18 /RESET OA Modem Interconnect 68 /DTR IA DTE Serial Interface19 SR4OUT OA Modem Interconnect 69 VDD1 PWR -20 NC - NC 70 IA_SLEEP MI Modem Interconnect21 SR4IN IA Modem Interconnect 71 VGG PWR -22 CLK_OUT OA Modem Interconnect 72 YCLK OA Overhead Signal23 EYESYNC OA Diagnostic Signal 73 XCLK OA Overhead Signal24 EYECLK OA Diagnostic Signal 74 EYEXY OA Diagnostic Signal25 MAVSS GND - 75 /DSR OA DTE Serial Interface26 MAVDD PWR - 76 /RI OA Telephone Line Interface27 SPKR O(DF) Telephone Line Interface 77 RINGD IA Telephone Line Interface28 TXA2 O(DD) Telephone Line Interface 78 /RTS IA DTE Serial Interface29 TXA1 O(DD) Telephone Line Interface 79 IRQ OA HOST Interface30 VREF MI Modem Interconnect 80 VSS GND -31 VC MI Modem Interconnect 81 GPO0 MI Modem Interconnect32 RIN I(DA) Telephone Line Interface 82 RESERVED - -33 MAVSS AGND - 83 RESERVED - -34 /POR IA Modem Interconnect 84 VDD1 PWR -35 RESERVED - - 85 XTALI/CLKIN I Overhead Signal36 RESERVED - - 86 XTALO O Overhead Signal37 /TALK O(DD) Telephone Line Interface 87 D0 IA/OB HOST Interface38 VDD PWR - 88 D1 IA/OB HOST Interface39 RESERVED - - 89 D2 IA/OB HOST Interface40 RESERVED - - 90 D3 IA/OB HOST Interface41 NC - NC 91 D4 IA/OB HOST Interface42 M_CNTRL_SIN IA Modem Interconnect 92 VDD1 PWR -43 M_CLKIN IA Modem Interconnect 93 D5 IA/OB HOST Interface44 M_TXSIN IA Modem Interconnect 94 D6 IA/OB HOST Interface45 M_SCK IA Modem Interconnect 95 D7 IA/OB HOST Interface46 M_RXOUT IA Modem Interconnect 96 RS0 IA/OB HOST Interface47 M_STROBE IA Modem Interconnect 97 RS1 IA/OB HOST Interface48 RESERVED - - 98 PLL_VDD PWR -49 OH O(DD) Telephone Line Interface 99 VSS GND -50 VDD PWR - 100 PLL_GND GND -

1. I/O types:

MI = Modem interconnect.IA, IB = Digital input.OA, OB = Digital output.

I(DA) = Analog input.O(DD), O(DF) = Analog output.

2. NC = No external connection required.

RESERVED = No external connection allowed.3. Interface Legend:

HOST = Modem Control Unit (Host)DTE = Data Terminal Equipment

3-11-8. FM336 Pin Signals

3-44

CIRCUIT DESCRIPTION


TXA1, TXA2 O(DD) Transm it Analog 1 and 2. The TXA1 and TXA2 outputs are differential outputs 180 degrees out of phasewith each other. Each output can drive a 300‰ load.

RIN O(DA) Receive Analog. RIN is a single-ended receive data input from the telephone line interface or an optionalexternal hybrid circuit.

RINGD IA Ring Detect. The RINGD input is monitored for pulses in the range of 15 Hz to 68 Hz. The frequencydetection range may be changed by the host in DSP RAM. The circuit driving RINGD should be a 4N35optoisolator or equivalent. The circuit driving RINGD should not respond to momentary bursts of ringingless than 125 ms in duration, or less than 40 VRMS (15 Hz to 68 Hz) across TIP and RING. Detected ringsignals are reflected on the /RI output signal as well as the RI bit.

/TALK O(DD) Relay B Contro l. The /TALK open collector output can directly drive a +5V reed relay coil with a minimumresistance of 360 ohms (13.9 mA max. @ 5.0V) and a must-operate voltage no greater than 4.0 VDC. Aclamp diode, such as a 1N4148, should be installed across the relay coil. An external transistor can beused to drive heavier loads (electro-mechanical relays). /TALK is controlled by host setting/resetting of theRB bit.In a typical application, /TALK is connected to the normally closed Talk/Data relay (/TALK). In this case,/TALK active opens the relay to disconnect the handset from the telephone line.

OH O(DD) Relay A Cont rol. The OH open collector output can directly drive a +5V reed relay coil with a minimumresistance of 360 ohms (13.9 mA max. @ 5.0V) and a must-operate voltage no greater than 4.0 VDC. Aclamp diode, such as a 1N4148, should be installed across the relay coil. An external transistor can beused to drive heavier loads (electro-mechanical relays). OH is controlled by host setting/resetting of the RAbit.In a typical application, OH is connected to the normally open Off-Hook relay (OHRC). In this case, OHactive closes the relay to connect the modem to the telephone line.Alternatively, in a typical application, OH is connected to the normally open Caller ID relay (CALLID). Whenthe modem detects a Calling Number Delivery (CND) message, the OH output is asserted to close theCALLID relay in order to AC couple the CND information to the modem RIN input (without closing the off-hook relay and allowing loop current flow which would indicate an off-hook condition).

/RI OA Ring Indicator. /RI output follows the ringing signal present on the line with a low level (0 V) during the ONtime, and a high level (+3.3 V) during the OFF time coincident with the ringing signal. The RI status bitreflects the state of the /RI output.

Three signals provide the timing and data necessary to create an oscilloscope quadrature eye pattern. Theeye pattern is a display of received baseband constellation. By observing this constellation, common linedisturbances can usually be identified.

EYEXY OA Serial Eye Pattern X/Y Output. EYEXY is a serial output containing two 11-bit diagnostic words (EYEXand EYEY) for display on the oscilloscope X axis (EYEX) and Y axis (EYEY). EYEX is the first word clockedout; EYEY follows. Each word has 8-bits of significance. EYEXY is clocked by the rising edge of EYECLK.This serial digital data must be converted to parallel digital form by a serial-to-parallel converter, and then toanalog form by two digital-to-analog (D/A) converters.

EYECLK OA Serial Eye Pattern Clock. EYECLK is a 336 kHz output clock for use by the serial-to-parallel converters.The low-to-high transitions of RDCLK coincide with the low-to-high transitions of EYECLK. EYECLK,therefore, can be used as a receiver multiplexer clock.

EYESYNC OA Serial Eye Pattern Strobe. EYESYNC is a strobe for loading the D/A converters.

SPKR O(DF) Speaker Analog Output. The SPKR output reflects the received analog input signal. The SPKR on/off andthree levels of attenuation are controlled by bits in DSP RAM. When the speaker is turned off, the SPKRoutput is clamped to the voltage at the VC pin. The SPKR output can drive an impedance as low as 300ohms. In a typical application, the SPKR output is an input to an external LM386 audio power amplifier.

3-11-9. FM336 Signals Definitions


CIRCUIT DESCRIPTION

Repair Manual

FM336 Signals Definitions (Cont’d)

3-46

CIRCUIT DESCRIPTION




CIRCUIT DESCRIPTION

Repair Manual


3-48

CIRCUIT DESCRIPTION


3-12 LIU PBA

3-12-1 Background of Line Connection Part

This LIU is designed for the standards (FCC, CTR 21 etc.) of America and Europe where donít allow the Handset, andthe line interface is applied for sending/receiving 33.6k bps. However, contact by 33.6k bps allows just for using FM336modem of Connexant Co., and provisions is given as below for some countries, require the special function.

- Greater Britain: 3,4,8, (#3, #4: TIP, Ring, #8:Shunt)- United States and some other countries: 3,4 (TIP, Ring)

United States and some other countries, where apply CTR21 (Common Technical Requirements), are using ModularJack #3, #4, and the Modular Jack Harness is designed for joint use of America and Europe counties.

3-12-2 Functions

3-12-2-1 DC Conditions

The normal conducting rage of LIU is 12mA-90mA. Because no more than 60mA current cannot flow in terminal byapplying the CTR21 standard, no more than 60mA DC flows in the Current intercept circuit when the current, whichflows via Bridge Diode (BD1) and Q2, is connected to LINE_A, LINE_B, and LINE_C. It means an entire line current,flows through LIU, isn’t over 60mA.

- CTR21 standard: 12mA-60mA- United States and other countries standard: 12mA-90mA

The characters of DC are defined as bellows with voltage of the Line input from the Gate input part of Q1 and R20,which is connected to the Source of Q1.

-VDCR=VLI + ILINEXR20

(VDCR: Tip-Ring DC voltage), ILNE: Line currentVLI: Line Input voltage, VLI=BVD1+VCE (Q2)+VDS (Q1)In this part, a voltage drop is not considered to Q3 (2SA 1156), R12, R11, etc. at the moment of forming DC loop withapplying CTR21 standard. The DC resistance of terminal is about 70W higher when applying CTR21 standard thanapplying America standard. Not only CML1 (Relay), but also U6 (PC817) must be turned on for forming a DC Loop. The base of Q6 (KSC945)must be controlled by /DP terminal, and U6 must be turned on to flow the current in Q1,Q2,and R20 via the bridge diode(BD1) at the same time the CML_1 When the base of the Q4 gets the line voltage from DTR terminal, Q3 is turned onand flows to Q2 via R11 by applying the CTR21 standard. When the line current is more than 60mA, Q5 is turned on,but Q3 and Q4 are turned off. The most of current is wasted at R12 (1kW, 2W), so it canít flow more than 60mA. The1% of tolerance resistance must be use for R11 under the condition of turning on the Q5.

3-12-2-2AC ConditionsAC Impedance of the LIU is basically 600ohm, and it is possible to make it as complex impedance by using C36, R47,and R48.- United States: vertical impedance ‡ 600W (±30%)

CTR21: vertical impedance ‡ 270ohm + 750ohm//150nF (more than 1- 4dB)

3-12-2-3 MF Dialing


CIRCUIT DESCRIPTION

Repair Manual

DTMF dialing is controlled by modem, and sends the signal at the suitable level and with on-off time according to thenational spec of each country.

- Freq. Tolerances: ± 1.5%High Group: 1209, 1336, 1477, 1633 HzLow Group: 697, 770, 852, 941 Hz

3-12-2-4 DP DialingThe DP Dialing controls the DP signals from the main via /DP terminal. When the signal goes to America, the DP signalis adjusted to 40:60 of M/B (Make/Break ratio), and when the signal goes to Europe, the DP signal is adjusted to 33:66of M/B. The DP signal is made by U6 (PC817), and the current, flows in the base of Q2 by Coupler, controls on/off func-tion. The DC current in telephone line is controlled by the on/off of Q2, and as a result, the DP Dial signal is created.-CTR21 doesn’t have a telephone function but line connection (#3, #4). It has no DP conditions and is suitable to thestandard if the terminal does do only DTMF Dial.

3-12-2-5 RingerRing Signal from the Line (TIP, Ring) goes to U9 (PC814) via C5, R3, ZD1, and ZD2. U9 detects the signal and outputsit to Main BíD. C5 is the Ringer Capacitor and normally 1UF/250V is used. R3 is a resistance to control the AC current,and by controlling the R3, the REN value is adjusted to higher or lower.

4


SCHEMATIC DIAGRAMS

Repair Manual

4. Schematic Diagrams

4-1 Main Circuit Diagram (1/8)

Main BoardREV 0.2

SCX-1150F

6 DIAGRAM

B

5

SHEET 7

7

D

1 2

ALL R

IGHT

S RE

SERV

ED

4

SHEET 2

SHEET 3

SHEET 4

MODEM PART

JUPITER.SCH MODEM.SCH

DRIV.SCH

SCANIP.SCH

SAMS

UNG

ELE

CTRO

NICS

CO.

, LTD

.

G

A

REF NO

C

D

E

PARALLEL PORT PART

G

PARA.SCH

1/8

2 3 4

P

6

C

A

B

C

3

E

5

E

ED. DATE

SHEET 8

2

1

SIGN

AR

DRIVER PART

.

SHEET 5

HECK

CONN.SCH

N

MEM.SCH

.

DW

1

.

3

CONNETOR PART

CONTROLLER PART

MEMORY PART

SEC

IMAGE PROCESSING PART

SHEET 6

4-2

SCHEMATIC DIAGRAMS


Main Circuit Diagram (2/8)

SCX-1150F

R26

Q7KSA1203_YTF

0R30

100 R27

CN4-3

0

CN14-10

K

REF NO

G.

P

A

.

SIGN

CCD

A

B

CONNECTION

E

B

4

1

E

C

3

7

D

4

B

Main Board

1

C

E(UNUSED)

5

2

C

C

D

6

A

H

R35 0

W

OPE_MAGIC

ED.

6

ALL

RIG

HTS

RESE

RVED

N

2/8

3

G

D

REV 0.2

DATE

2

E

SAM

SUNG

ELE

CTRO

NICS

CO

., LT

D.2 3

SEC51

R E

CN16-15

C

.

LIU

CN16-7CN16-8

5V

DGND

10K

CN16-12

CN1-7

R153

CN16-3

5V

R375

C333

680

100nF

DGND

100nF

CN14-6

C334

Q12SC2812L6-TA

13

21K

R366

3.3V

CN5-11

0R209

CN1-17

L8 0

3.3V

5V 5V

L7

3

2

Q42SC2812L6-TA 1

C194100pF

13

100pFC81

DGND

11.75V

100nFC209

2

14

0L10

L9

11

100 R36

CN12-2

0R37

R33R2810K 10K

TP365

47K

R149

CN1-8

50V330uFC50

47K

R136

R138

47K

L12 0

FGND

L11

CN14-35

FGND

CN5-22CN5-23

CN1-3

CN5-4

CN1-1

CN5-3

100pFC337

DGND

R135

R137 1K

1K

5

C39

47pF

CN16-5

CN1-6

CN5-10

DGND

4

DGND

CN8-4

DGND

CN5-9

CN14-28

DGND

DGND

CN14-31

C98

CN1-15

C95

10nF

3

10nF

CN7-11

R144

100nFC205

DGND

CN1-26

CN4-2

C20422pF

0L6

DGND

L5

5045-03A

CN3-1

30V

CN1-22

DGND

CN5-7

C338100pF

100nFC197

DIN15

CN16-1

CN14-27

C33100nF

22pFC203

CN5-12CN5-13

GND30

CN13-2

CN16-6

C49100nF

3.3V

CN1-25

U6

CD74HCT244M

CN1-13

AGND

CN16-9

CN4-15045-04A

30V

USB20-4W2100

CN8-1

5V

CN11-4

CN14-17

CN14-8

INV_POWER

CN6-1

3711-000225

CN4-4

DGND

CN1-20

R147

R148

47K

47K

11.75V

R4422

CN6-3CN6-4

CN6-2

C80100pF

2KR126

DGND

2K

C35

47pF

1

R123

47pF

C32

DGND

3711-002815CN9-1

CN14-16

16V100uFC118

8

CN14-3

CN5-14

CN14-15

DGND

BD10

1.5K

CN1-10

R155

CN14-2

5V

DGND

CN14-20

100pFC181

100R145

CN14-23

CN14-33

GND12

CN14-11

CN16-2

100nFC119

C58220pF

9CN14-34

34 4.7K

R146

100nFC66

1001/8W

R24

DGND

CN14-7

CN1-18

5.1KR8

R2347K

DGND

CN14-22

47pF

C38

5V

DGND

100 R29

CN1-12

INV_POWER

CN16-14

CN1-14

GND12

7

CN5-16CN5-17

CN5-15

R378

TP366

5V

CN14-9

0

CN1-24

11.75VA

CN5-2

FPC_24

CN5-1

BD60,5%

TP230

6

RPI-441C1U5

CN1-4

BD12

CN14-25

100nFC208

CN14-1

CN14-32

100 R34

5V

CN11-2

TP77

CN14-36

12

5VA

BD13

DGND

CN14-21

CN1-16

BD11

C82100pF

10K

10KR377

R25

CN5-8

CN14-4

CN1-5

5V

AGND

CN1-21

CN14-26

CN14-13

CN14-5

CN5-5

DGND

C336100pF

TP78

CN14-29

TP367

13

2

DGND

2SC2812L6-TAQ5

C3

3.3V

CN11-1

R152

25V100uF

CN1-19

2

CN8-2

DGND

5V

4.7KR373

CN16-4

DGND

11.75V

RB420D T147D8

100nFC97

CN1-11

AGND

CN13-1

CN1-23

AGND

5V

CN5-24

AGND

3KR125

10

R207

47K

10KR154

CN14-12

R3810K

CN16-13

CN1-9

CN14-18

220pFC7

CN5-18CN5-19

CN5-6

10K

DGND

5

5V

R43

CN3-3

5V

220pFC1

C67

CN14-19

16V100uF

CN6-5

CN16-11

TP363

TP364

CN14-30

CN5-21

CN14-14

30V

DGND

CN5-20

0,5%BD7

C182100nF

CN8-3

DGND

5V

AGND

CN11-3

CN1-2

CN16-10

R4522K

GND30

CN12-1

10nFC96

GND30

CN14-24

3KR124

_ERROR

_INIT

CN3-2

3711-000198|scon_pin3_2.5mm

_P_PICKUP

REG1_SEN

LAMP_ON

_STB

_CML_ON

E_DP

ADF_IA0ADF_PHA

_D_SCAN_D_DET_ADF_DET

VOUT_G

VOUT_R

VOUT_B

CCD_RS

HOME

OPE_TXD

OPE_TXDD_OPE_RST

_OPE_RES

OPE_RXD_OPE_RESOPE_TXDD

ADF_IB1ADF_IB0

ADF_PHBADF_IA1

_HOOK_OFF_RING_DET

MODEM_RX

DP

RECALL

MODEM_TX1

REMOTE

MODEM_TX2

CCD_TG

CCD_CLK1

CCD_CLK2

CR_NA

CD(0:7)

SLCTPEBUSY_ACK

_SLCTIN

_AUTOFD

LF_NBLF_ALF_NALF_B

SCAN_NBSCAN_BSCAN_NASCAN_A

COVER_OPEN

PH_ID2

PENABLEPLOAD

PDATA3PDATA2PDATA1PDATA0

PCLK

LDCSLATCHCTL

ACLKAGATE

_SF_POR

OK2PRT

CHYCHX

SPK_OUT-

SPK_OUT+

CR_A

PULLUP

PH_ID1

600ohm BEDA

600ohm BEDA

600ohm BEDA

0ohm

600ohm BEDA


SCHEMATIC DIAGRAMS

Repair Manual


Main BoardREV 0.2

SCX-1150F

E

G

3/8

B

D

RE

P

6

CONTROLLER2

DATEED.

A

SEC

C G

6

C

2

1 3

D

.

A

REF NO

.

C

1SA

MSU

NG E

LECT

RONI

CS C

O.,

LTD.

5

7

H

3

5

E

4

D

N

1

W

ALL

RIG

HTS

RESE

RVED

A

2

B

SIGN

.

4

E

K

C

3

R34.7K

1nFC215

DGND

100R208

R100 0

R77100nF100K

100nFC110C87

3.3V

100nF

C216

100

R102

R89

R91

10M

DGND

100

R59 100

R85 100

PLLGND

C2201nF

4.7KR94

DGND

4.7KR101

R55 100

4.7KR84

R644.7K

100R11U15

S3C46MOX

DGND

R92 4.7K

1/16W100RA1

2GND

I01 3OUT

R80

LF25CDTU11

3.3V

C89820pF

DGND

50V

C651uF

R93 100

4.7KR88

R83 100

3.3V

BD4

100uFC76

16V

XC61FN3112MRU13

DGND

100nFC78

R51 100

R50

820pFC93

2.5V

100

1/16W

RA5

1/16W

RA4

100nFC113

PLLGND

DGND

100nFC99

3.3V

C79100nF

C112 22pF

DGND

TP3

1001/16W

RA2

100R95

100R60

22pFC219

100nFC111

100

100

R86

R73

R56

100nFC91

100nFC92

100

C77100nF

DGND

4.7KR74

DGND

R71 100

100R72

3.3V

DGND

SD16150J7-10.000MX1

22pFC218

C70100pF

C2170.68nF

R634.7K

22pFC125

0.32768MHzX3

3.3V

0R76

4.7KR75

DGND

4.7KR78

3.3V

R90 100

DGND

3.3V

FS781BZBU37

100nFC64

1/16W

RA3

DGND

R61 100

C9010nF

4.7KR65

3.3V

R87 100

R58 100100R57

3.3V

C109

100n

F

100nFC88

BD14CIM21J121NES

DGND

3.3KR204

4.7KR62

DGND

100R107

DGND

TBCLKTBDO

_TBCS

VB2

PENABLE

245DIR

KEYCLICK

_IP_RST

_ROM_CS_IP_CS_MODEM_CS_GPIO_CS

_SCAS_SRAS_SCS0_SCS1

TDO

_F_POR

PCLKLATCHCTLAGATEACLK

PDATA0PDATA1PDATA2PDATA3

LDCSPLOAD

PH_ID1_MODEM_IRQ_IP_INT

PD(0:7)

OPE_RXDOPE_TXD

_IP_ACK_IP_REQ

CHXXCHYY

ADDR(0:19)

DATA(0:15)

_P_INIT

_P_ERROR

P_PE

_P_ACK

DQM1DQM0

_POR

PH_ID2

SCLK

SCKE

PWM

OK2PRT

_POR

_P_STB

_P_AUTOFD

P_SLCT

_P_SLCTIN

P_BUSY

_RD

_TRSTTDITCK

TMS

A20A21

IPCLK

VBUS

USB_DPUSB_DM

PULLUP

_WR

_OPE_RSTA22

_P_PICKUPCOVER_OPEN600ohm BEDA

600ohm BEDA

4-4

SCHEMATIC DIAGRAMS



Main BoardREV 0.2

SCX-1150F

ALL R

IGHT

S RE

SERV

ED2 5

2

W

B

KG

ED.

(UNUSED)

E

743

G

5 SEC

P

1

D

REF NO

.

3

200

.

6

1

4/8

SIGN

E

SAMS

UNG

ELE

CTRO

NICS

CO.

, LTD

.

AC

E

B

E

2

H

1

N

C

4

A

R

3

3.3V

DGND

100KR371

6

DATE

MEMORY

C.

C

D

A

D

R21

C68100nF

U2-174VHC08MX

U2-274VHC08MX

16V

DGND

C31

10uF

3.3V

16V10uF

C30

C57100nF

R13 180K

C37100nF

C53100nF

DGND

100pFC8

100nFC69

VB

MC74VHC32DR2U1-3

MC74VHC32DR2U1-4

DGND

68KR12

VB

U8K4S641632D-TC75

U1-1MC74VHC32DR2

5.5V,5V

R32 0

1.5KR17

3.3V

U2-474VHC08MX

DGND

100nFC4

100nFC18

C5100nF

DGND

VB

DGND

DGND

MMSD914T1D2

R9 10K R10 10K

0R41

DGND

0R22

R420

DGND

VB2

DGND

100nFC51

C10100pF

DGND

Q2KSA1182-Y

DGND

100nFC52

U7

1107-001302

DGND

MC74VHC32DR2U1-2

3.3V

DGND

C55100nF

2SC2812L6-TAQ8

U3-174VHC27

DGND

C91nF

200

C61nF

R16

74VHC08MXU2-3

CHX

CHXX

CHYY

CHY

ADDR(1:19)

SD_CKE

_SD_RAS

_SRAS

_SD_CAS

_SCAS

DATA(0:15)

_ROM_CS_RD_WR

A20

_F_POR

_F_POR

ADDR(1:12)

DATA(0:15)

_SD_RAS_SD_CAS

A21A22

_SCS0_WR

DQM0DQM1

SCLKSD_CKE


SCHEMATIC DIAGRAMS

Repair Manual


Main BoardREV 0.2

SCX-1150F

64

B

2

PE

01.08.06

B

E

6AL

L RI

GHT

S RE

SERV

ED

3

5

DATE

D

1

.G

SIGN

DRIVER

C

5/83

W

2

.

4

A D

REF NO

C

A

5

C

SAM

SUNG

ELE

CTRO

NICS

CO

., LT

D.

N

K

1

A

ED.

G

H

C

D

SEC

E

1

R

3

E

2

.

7

22pFC75

22pFC15

30VA

C84100nF

2007-007004

R1512K

2K

5V

2007-000669

R18

U22C74LCX245FT-ELP

C85100nF

GND30

56KR66

DGND

47nFC13

DGND

0R39

R387

R388 0

0

GND30

2007-000669

R19 2K

U417E0201

U14TEA3718S

R201K

150uHL2JB27-00001A

C2247nF

GND30

ZD21N4735A0403-000141

0403-0001501N4743AZD1

0R389

22pFC12

R8110K

R5 0.68

0.68R31

2007-007845|R6432_RES

DGND

DGND

C27100nF

1KR67

DGND

30VA

100R47

2007-000842

R14 3K

BD3CIB32P600NES

100nFC121

GND30

3.3V

DGND

TEA3718SU10

0.5R79

C59

5V

GND30

GND30

22pF

56KR46

GND30

R4 0

C34

R70

1nF

10K

C1622pF

C7222pF

820pFC83

GND30

30VB

MC74VHC32DR2

U18-2

GND30

DGND

5V

DGND

30VB

3.3V

C2447nF

C2347nF

30VA

C63

5V

820pF

2401-000880

3.3V

MC74VHC32DR2U18-1

50V220uF

C28

22pFC73

GND30

2.7KR54

C41

2401-001363

GND30

11.75V

DGND

16V470uF

5V

0R6

GND30

100R48

C152100nF

22pFC71

47nFC36

R53 1K

GND12

D1SS26

GND30

100R68

GND30

30VB

100R69

1nFC21

2203-000440

47nFC14

2203-000989

DGND

0402-001212

SS26D3

2203-000626

22pF

30V

1nF

GND30

C11

C108

C19

100nF

22pF

C61100nF

GND30

C74

GND30

C29 22uF50V

C2510nF

C26100nF

100R82

GND30

5V

C62

DGND

BD1

100nF

JB27-00001A

L1 150uH

DGND

C201nF

100nFC40

GND30

R49 100

MM74HCT273WMU17

BD2 0,5%

GND30

C86

DGND

231

820pF

2103-001041

R7500ohm

820pFC60 R52

0.5

CIB32P600NESBD5

LF_ALF_NALF_BLF_NB

E_DP

RECALL

_GPIO_CS

_SPK_CTL

RX_CTL

TX_CTL

_CML_ON

DP

TONE_CTL

DATA(0:7)

SCAN_NASCAN_BSCAN_NB

SCAN_A

PWM

CR_ACR_NA

SCAN_IB0SCAN_IB1

SCAN_IA1

DATA(0:3)_HOOK_OFF

_RING_DET

_WR

_RD

TBCLK

TBDO

_TBCS

SCAN_PHA

SCAN_PHB

SCAN_IA0

120 ohm BEDA

4-6

SCHEMATIC DIAGRAMS



Main BoardREV 0.2

SCX-1150F

3

2

C

D

7

.

2

ALL

RIG

HTS

RESE

RVED

SIGN

6/8

D

E

01.08.06

6

E

4

G

E

4

B

5

5

C

C

P

1

K

6

1

W

.

N

2

A

SAM

SUNG

ELE

CTRO

NICS

CO

., LT

D.

C

ED.

IMAGE PROCESS

.

B

A

DATE

3

H

1

3

DA

SEC

R

REF NO

G

E

R374

DGND

100n

FC2

01

33

1

TP2331

R98

TP268

R1044.7K

100

RA6100

1/16W

C162100nF

TP2311

TP321

TP2341

C196

100n

F

C128100nF

3.3V

R115 100

C19810uF16V

TP301

100nFC164

U16WM8192

100nFC151

TP2321

C177

100n

F

TP291

TP460

DGND

TP2351

100nFC103

10nFC102

3.3V

TP459

U3-2

DGND

74VHC27

R117 100

100nFC165

C139100nF

C105 100nF

100n

FC2

00

3.3V

C14310uF16V

R1054.7K

3.3V

1TP238

C116100nF

R134

AGND

4.7K

C131100nF

100nFC130

16V10uF

C180

DGND

100R205

AGND

C114100nF

C202

100n

F

U18-4

MC74VHC32DR2

1000nFC104

100nFC94

3.3V

R118 1K

100nF

BD8

C178

0R119

1

TP331

TP26

MC74VHC32DR2

U18-3

1TP236

16V

C12710uF

100n

F

DGND

C179

OA-980

U21

R1164.7K

DGND

100nF

DGND

C142

16V10uF

C129

3.3V

5V

3.3V

TP251

TP457

C17610uF16V

C153

DGND

C163100nF

100nF

TP281

10uF16V

C107

DGND

DGND

74VHC27U3-3

TP45810uF

47KR97

100nFC106

TP311

DGND

5VA

TP2691

DGND

TP271

DGND

DGND

U27K4S641632C

R1284.7K

100nFC115

TP450

100n

FC1

93

0

AGND

4.7K R120R206

TP2371

3.3V

100nFC140

VOL_00

VOL_20VOL_10

LAMP_ON

_SF_POR_MODEM_RST

_IP_RST

_WR_L

_IP_ACK0

ADDR(10)

_WR

_IP_ACK

_RD

HOME

ADF_PHAADF_PHB

ADDR(10)

MAINEXT

CCD_RS

CCD_CLK1

VOUT_BVOUT_G

ADF_IB1ADF_IB0

ADF_IA1ADF_IA0

_ADF_DETREG1_SEN

_IP_INT

_IP_REQ_IP_ACK0

_ADC_VSMP

ADC_SENADC_SDI

ADC_CLK

SCAN_PHASCAN_PHB

SCAN_IA1SCAN_IA0

SCAN_IB1SCAN_IB0

ADC_SCKADC_SENADC_SDI

_D_DET_D_SCAN

VOUT_R

ADC_SCK

CCD_CLK2

SDRAMDATA(0:15)

SDRAMDATA(0:15)

DATA(0:7)

_IP_CS_WR

BASEEXT

ADDR(9:8)

DATA(0:7)

BASEEXT

MAINEXT

IPCLK

CCD_TG_ADC_VSMPADC_CLK

600ohm BEDA


SCHEMATIC DIAGRAMS

Repair Manual


Main BoardREV 0.2

SCX-1150F.

7/8

E

G

D

P

SIGN

SEC

DATE 1 01.08.06

C

SAM

SUNG

ELE

CTRO

NICS

CO

., LT

D.4

1

R

4

3

MODEM

D

E

D

G

3

A

B

ED.

R167

H

5

A

.

C

W

5

2

A

B

REF NO

6

6

. K

ALL

RIG

HTS

RESE

RVED

E

2

2

1 7

EN

C

C

3

R142

C188 100nF

47K

R163

100nFC184

47K

C213 1nF

R130 120K

R166

MC14053BD

U23-2

150K

U24-2

KA358D-T/F

100nFC146

U25-2KA358D-T/F

C210

3.3V

5V

1nF

300K

DGND

330K

R164

3.3V

MMSD914T1D6

DGND

100nFC136

11.75V

AGND

MC34119DR2

U34

R160

5V

330K

+3.0V

DGND

R14147K

AGND

100nFC187

130KR143

0R1

57

+3.0V

+3.0V

DGND

MC14053BD

U23-3

100nFC214

11.75VA

C147100nF

AGND

5V

+3.0V

R159 4.7K

C2121uF

DGND

11.75VA

10uHL4

R140 3K

U25-1

KA358D-T/F

R139 120K

DGND

AGND

MC14053BDU23-4

U19

FM336R6719-12

MMSD914T1D7

DGND

C155100nF

27pFC122

1nFC166

10KR114

AGND

DGND

DGND

100nFC199

1nFC175

C149100nF

C134

5V

100nF

C1351nF

11.75VA

100nFC183

100nFC169

8.2KR129

AGND

C132 100nF

1nFC189

R10910K

10KR113

5V

C170100nF

C13822uF16V

R16510K

C145

AGND

100nF

11.75VA

150K

R162

C174 100nF

+3.0V

R12110K

330KR131

R37210K

AGND

C133100nF

R158

1M

C173100nF

1MR379

DGND

16V22uFC150

AGND

R112 10K

100nFC168

27pF

C154

C123

1nF

C172100nF

25V22uFC156

1uFC211

R1224.7K

24KR127

91KR132

BD9CIM21J121NES

+3.0V

AGND

28.224MHzX2

R110100

C1441nF

C186 1nF

C148100nF

100nFC185

47KR133

Q3

2SC2812L6-TA

16V10uFC167

DGND

5V

KA358D-T/F

U24-1

DGND

5V

C206100nF

R156

1M

AGND

C171 100nF

0

DGND

+3.0V

C137

R161

100nF

U23-1

MC14053BD

C157100nF

KEYTONE

MMSD914T1D4

DGND

_SPK_CTL

TONE_CTL

TX

_MODEM_RST

TX_CTL

TONE_OUT

VOL_2

VOL_1

VOL_0

REMOTE

SPK_OUT+

SPK_OUT-

TONE_OUT

KEYCLICK

RX

_WR_RD

_MODEM_CS

MODEM_TX2MODEM_TX1

MODEM_RX

DATA(0:7)

ADDR(0:4)

_MODEM_IRQ

RX_CTL

RX

TX

4-8

SCHEMATIC DIAGRAMS



Main BoardREV 0.2

SCX-1150F

3.3V

W

3

5

C

DATE

5

.P

2

SEC

A

D

D

C

H

3

G

4

2

1

01.08.06

E

2

SAM

SUNG

ELE

CTRO

NICS

CO

., LT

D.

K

ED.

G.

ALL

RIG

HTS

RESE

RVED

RE

6

A

71

A

C

N

8/8

D

E

6

.

B

REF NO

E

1 3

B

C

PARALLEL PORT PART

SIGN

4

DGND

5V

100nFC192C191

100nF

3.3V

DGND

U26

TC74LVX4245MTCX

3.3V

HIC1

SUPER1284

RA8 39

100nFC195

5V

U33

TC74LVX4245MTCX

C190100nF

5V

100nFC207

DGND

DGND

RA739

CD(2)CD(3)

_P_STB

_P_ACKP_BUSYP_PEP_SLCT_P_ERRORVOL_00VOL_10VOL_20VOL_2

VOL_1VOL_0

DGND

CD(1)CD(0)

_STB

_INIT_ERROR_SLCTIN

_AUTOFD

SLCTPE

BUSY_ACK

_P_SLCTIN_P_AUTOFD

245DIR

PD(0:7)

PD(0)PD(1)PD(2)PD(3)PD(4)PD(5)PD(6)PD(7)

_P_INIT

CD(0:7)

CD(4)CD(5)CD(6)CD(7)


SCHEMATIC DIAGRAMS

Repair Manual

4-2 ADFCircuit Diagram

SCX-1150F ADF

0.5

0.5

510

4-10

SCHEMATIC DIAGRAMS


4-3 SMPS Circuit Diagram

Doc 01

MAGIC POWER SUPPLY CIRCUIT DIAGRAM (Magic-V3)

B

1 1Friday, July 20, 2001

Title

Size Document Number Rev

Date: Sheet of

F1LF1SQH0350 BD1

PC1

H

NT1TNR1 +3.3V0.8A

+30V1.3A

IL1CON1-1

CON1-2

CON1-3

CON1-4

PE

4

7

6

T1EE2525W

N

U2D4=SR204

C14=16V47uF

C11=50V470uF/KMG

ZD4=1W36V

3

R-30190

AC250V T 2A

R1=1W560K

10D561K

C1=224

C3=222

2KBP06M

DSC10D9

C5=400V120uF

R3=1/4W/180K

SSP5N80A

C6=1KV331

R5=47K

R4=1W0.42(MINI)

Q3=C1008-Y

C8=103D2=1N4148

PC1=PC123B

ZD2=4.3VB

C13=10V1000uF

R14=6.8K

R13=510

R15=6.8KF

C10=1uF

PC123B

Magic-V3 POWERSUPPLY(100-240Vac)

KA78R33

R10=330

Q4=C1008

C7=PC630V103

Q1

X

3

4

1

2

10

C4=222

C2=104

R2=1/4W180K

Q2=FQU2N60

ZD1=9.1V

C9=103

R6=510

R11=180

D1=1N4148

D3=1N4148

R8=330

R7=3.3KF

R9=33

B1=BEAD

9

D5=ER502

C12=50V47uF/KMG

R12=1K

ZD3=5.6V

R16=1.8KF

10D471K

R20=1/4W68K

R17=1W0.42(MINI)

R18=2W2.2K

1 3 2

B2=BEAD

3t

48t =550uH

3t

12t

2t

ZD5=27V

C15=1KV102

R19=1/4W/180K

R21=1/4W22

2

18

- +

t

CH1

CH3

GND

GND


SCHEMATIC DIAGRAMS

Repair Manual

4-4 LIU Circuit Diagram

(WHT)

B

10, 1%,0.25W

,1W

Size:

E

0.25W

1 4

C

Address

Time Changed:

2

1K,1%

(RED)

15nF/400V(GRN)

1K, 2W

63

1 7

Drawn by:

R&D CHK:

8

QA CHK:

D

*

COMPANY NAME

54

C

*

FCity

*

MFG ENGR CHK:

/250V

SCX-1150F

(BLK)

8

Drawing Number:

F

3

DOC CTRL CHK:

Changed by:

D

7

600:600

2

A

180K, 1/4W

(BLU)

Engineer:

010101

LIU8 1 6 A TL

A3

/250V

Date Changed:

unused

B

5

(YEL)

A

(BRW)

2.74K, 1%

150

(ORG)

120K

Page:

E

6

TITLE:

REV:6:33:26 pm

R9

JP19

5V

100

VAR3JP7

P2 6

12V

C31uF100V

D81N914

R1

R2200K

56K

(unused)(unused)

220

100R10

5V

R44

56

7

5V

FLT160uH

U3

MA91000045S

12

34

T2

100-1016

1

2 3

4

12KR15

10

R49

1N914D9

9

10

8

D4

1N914

1N914

D5

R482

C15

150pF

U10LCA190

INS

TPA

RJP

11

R23

15K

R22

12K

60uHFLT3

ZD21N4746A

12V

9

GND55V

8

100nFC11

6

P2 4

4

C51uF

R50

C10100nF

R46

ARS1

GND5

14

12

JP3

12

GND5

7

R11

GND5

P2

ARS2

1N4148D13

1nFC7

5

AGND

L1

10K

4.2mH

VAR5

R45

GND5

GND5

R8100

220R21

GND5

D101N914

13

VAR4

ARS4

21

33nFC1

FGND

1N914D11

1

5V

P2

35303-0850

R48

VAR1

V82ZA2

5

GND5

P2

P2 2

R13

R20

7

GND12

5V

33

GND5

5V

30K

5V

R7

1

2

4

3

5V

ARS3

PC817CU6

12V

5V

GND12

2

P2 3

BC547B

21

3

Q5

10uFC13

1N4746AZD1

43

5

50V

60uH

FLT2

G6S-2-Y

CML_1

R12

2

4

31

GND5

2

3 1

BD1W06G

3

2

1

Q4

MPSA45

1

23

VN2410MQ1

1

12

2SA1156-MQ2

BAT47

D2

G6S-2-Y

CML_1

23

1

AGND

R16

KSC945-YQ6

P1

35303-1450

1

15K

5V

R5

GND5

D1

BAT47

15nFC34

82

ZD5MTZ4.7B

C1633nF

VR61BTP

VAR2

1

2

4

3

AGND

U2

PC814

P2 81N4148D3 11

GND12

123

3

Q3

2SA1156-M

MTZ4.7BZD3

2SA1156-M

Q7

1

2

3

Q8KSC945-Y

23

1

10uF50V

C12

C36

1

2

4

3

P10

PC817CU7

R51

C9

D61N914ZD6

MTZ4.7B

MTZ4.7BZD4

5V

1N914D7

T1

SJ3030K

4

1

7

5

8

C4

0.47uF50V

15K

C14

GND5

R3

4.2mH

50V0.47uF

D121N4148

L2

T3

82107

PC814U9

MODEM_TxA2

L1-4

L1-2

JP5

_CML1_HOOK2_RING

DP

RECALL

line_B

line_A

_E_DP

MODEM_TxA2

_HOOK2

REMOTE

line_C

line_A

_E_DP

MODEM_TxA1

MODEM_RX

MODEM_RX

MODEM_TxA1

REMOTE

RECALL

L1-6

L1-5

L2-3

L2-4

L2-5

line_Bline_C

_CML1

_RING

DP

L1-5L1-4L1-3L1-2L1-6L2-3L2-4L2-5

L1-3

68nF

(unused)

(unused)

(unused)

(unused)

4-12

SCHEMATIC DIAGRAMS


4-5 OPE Circuit Diagram

TITLE:

SCX-1150F OPE Board

CN1-10

CN1-11

CN1-9

CN1-5

CN1-3

CN1-4

CN1-12

CN2-1

CN1-1

CN1-2

CN1-8

CN1-7

CN1-6

CN2-2

CN1-13

CN2-3

CN2-5

CN2-4

CN1-14

OPE_POW

OPE_POW

Samsung Electronics Digital Printing CS Group

Copyright (c) 2001. 10

This manual is made and described centering around

circuit diagram and circuit description needed

in the repair center in the form of appendix.

samsung scx 1150 mfp service manual

Documents

memory area

area oa9800x0200

area modem0x0400

circuit description3

circuit diagram

ffffgcs6 area dram8mb0x0c00

area extended gpio0x0600

external rom