saleem sabbagh & najeeb darawshy supervisors: mony orbach, technion & ilia averbouch, ibm...
DESCRIPTION
Boolean Satisfiability Problem Given a Boolean propositional formula, does there exist assignment of values such that the formula becomes true? e.g., given the formula f=(x1 ˅ x3 ˅ -x4) ˄ (x4) ˄ (x2 ˅ -x3) are there values of x1,x2,x3,x4 that produce f=‘1’TRANSCRIPT
FINAL PRESENTATION
Saleem Sabbagh & Najeeb DarawshySupervisors: Mony Orbach, Technion &
Ilia Averbouch, IBM
Smart FPGA Based SAT Solver
Started at: Spring 2012Duration: Semester
OUTLINE What is SAT Reminder - description and goals Memory Technique GSAT Flow diagram Controller Circuit diagram Resources usage and times Runtimes Conclusions Notes
WHAT IS SAT Boolean Satisfiability Problem Given a Boolean propositional formula,
does there exist assignment of values such that the formula becomes true?
e.g., given the formula f=(x1 ˅ x3 ˅ -x4) ˄ (x4) ˄ (x2 ˅ -x3)are there values of x1,x2,x3,x4 that produce f=‘1’
REMINDER - COMPILATION TIMES*Clock frequency is 50M [Hz]
20 25 30 35 40 50 75 100
125
150
175
200
225
500
75010
000
500100015002000250030003500400045005000
17.6 15.2 22.5 22.7519.33318.4 19.2519.25 20 22 24.75 30 29.5 59413.2
4729.4
Compilation Time Vs. #Variables
# Variables
Aver
age
Com
pila
tion
Tim
e [s
ec]
REMINDER - RUNTIMES*Clock frequency is 50M [Hz]
20 25 30 35 400500
10001500200025003000350040004500
0.0011776 0.0340384 21.36 35.588
4277.75Runtime Vs. #Variables
# Variables
Run
Tim
e [s
ec]
REMINDER In the first project this was our “what’s
next” slide. Two approaches
Improving compilation times by: Understanding Altera compilation algorithms to
enable faster SAT-specific FPGA ready files. Smart use of memory on FPGA to implement SAT.
Improving runtimes by designing smart sat solver instead of inefficient LFSR random generator
MEMORY TECHNIQUE Two memory entities
SAT is represented by ROM. Based on the DE2’s M4K built in memory blocks. We convert the DIMACS CNF SAT instance into a
memory description file and put it in the memory. The ROM address = variable’s number. content of the address = representation of the clauses
which the variable appears in. Each clause is represented by a shift register that
will save the number of variables that satisfy each clause according to the current assignment.
MEMORY TECHNIQUE – EXAMPLEc Example CNF format filec p cnf 4 31 3 -4 04 02 -3 0
Example.cnfDEPTH = 4 ; % Variables %WIDTH = 6 ; % Clauses*2 %ADDRESS_RADIX = DEC;DATA_RADIX = BIN;CONTENT
BEGIN0 : 000011;1 : 110000;2 : 100011;3 : 001110;
END;
Example.mif
0 1 2 30 0 1 0
For assignment 1101Clause number 1’s shift register status will be:
MEMORY TECHNIQUE – IN MEMORY SYSTEM CONTENT EDITOR
GSATGSAT(int Maxtries, int Variables) {
For (i=1 to Maxtries) {V = a random instantiation of the variables;For (i = 1 to Variables) {p = variable – who’s negation yields largest
increase in number of satisfied clauses;V = V with p flipped;}if (F(V) is true)return V;}
}*Take random variable in case of equality.
GSAT - EXAMPLE Initialize random assignment 01111 Total satisfied clauses = 20 (out of 21) Flip each variable and see how many added satisfied
clauses: Variable 1 : 0 new satisfied clauses. Variable 2 : -1 new satisfied clauses. Variable 3 : -2 new satisfied clauses. Variable 4 : 0 new satisfied clauses. Variable 5 : 1 new satisfied clauses. Maximum = variable 5, flip it. Assignment = 11111. Total satisfied clauses = 21 (out of 21) => SUCCESS!
New CNF instance
Memory Description File
FPGA
Results
FLOW DIAGRAM
PCConvert
In SystemMemory
Content EditorSignalTap
Reset
DE2
Init• Reset circuit• Random
Assignment
Clauses Init• Var by var run and
save to shiftreg
Flipping• Flip variable value• Sum satisfied
clauses• Advance var
Maximum• Increase attempts
if max <= 0• Flip max var and
save to shiftreg
Finish• Output satisfying
assignment
var == total vars
var =
= to
tal v
ars
satisfied == total clauses
atte
mpt
s ==
allo
wed
atte
mpt
s ==
allo
wed
CONTROLLER
CIRCUIT DIAGRAM
RESOURCES USAGE AND TIME LEs: 20,562/33,216 (62%) M4Ks: 102/105 (97%) Registers: 8,355/34,593 (24%) Compilation time: 4:12 minutes.
RUNTIMES*Clock frequency is 12.5M [Hz] (compared to 50M [Hz])
20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 951000
5
10
15
20
25
30
0.005016660.61473333
3333333
26.9939R² = 0.999924940853046
Runtime Vs. #Variables
RuntimePolynomial (Runtime)
# Variables
Run
Tim
e [s
ec]
CONCLUSIONS Runtime was reduced DRASTICALLY.
Due to GSAT implementation. From data appears to be polynomial increase of 4th order. We expect the more the number of variables is the
polynomial relationship will decrease, again due to a much harder locality problem.
Random runtimes for same instance due to initial random assignment.
Two degrees of freedom: total attempts, random bit. can improve runtimes.
Compilation time = NO compilation time. Use Quartus’s built-in In Memory Content Editor to change
the SAT for all variables sizes.
NOTES Tried two approaches for clauses representation in memory:
Encoded Clause Representation For each variable, only clauses which the variable appears in are included in the
memory and are represented by binary encode of the clause number. Less memory usage, more LEs, alters sat, only 14 clauses per variable special
design (decoders, special software support). Direct Clause Representation
All the clauses are included in the memory each is represented by two bits to indicate if the variables appears in it and what value satisfies it.
More memory usage, less LEs, doesn’t restrict design. We have developed two Java based applications
SAT converter from cnf to mif format according to our clause representation.
SAT satisfying value asserter. Currently our design supports 5-sat (5 variables per clause)
only, can be increased with minimal effort.
NOTES 2 Support maximum of 200 variables and 860 clauses due
to the limit of the M4Ks (of the DE2). 408Kb of memory was used. To measure runtimes we have used benchmark SAT
instances, as well as cpp based satisfiable/unsatisfiable SAT generator used in official SAT competitions which was used for runtimes analysis.
We have measured between 4 to 6 instances of SAT with the same variable number and took the average.
The standard deviation of the runtimes was of the same order of the average, meaning that the results vary a lot between instances due to the local minimum problem.
REAL TIME DEMONSTRATION Follow us please.
Thank you! Questions?