50mm

MiniPC

I-e PAT

A Solid State D

rive

RunCore PRO IV 50mm MiniPCIe PATA

Solid State Disk

Product Manual

Version 1.2 JUL, 2010

50mm

MiniPC

I-e PAT

A Solid State D

rive

Revision History Version #Number Description Date

Version 1.0 Original Release Dec 2009 Version 1.1 Addition of some items at Part Numbering

Scheme June 2010

Version 1.2 Remove warranty year in specification table, customer needs to refer on the Warranty Policy

document for more details.

July 2010

50mm

MiniPC

I-e PAT

A Solid State D

rive

Table of Contents I. General Description .................................................................................................... 4

1. Product Image ........................................................................................................ 4

2. Typical Applications .............................................................................................. 4

II. Key Features (Flash Management) ........................................................................... 5

1. Advance Wear-Leveling Algorithm ....................................................................... 5

2. S.M.A.R.T Function ............................................................................................... 5

3. Built-in Hardware ECC .......................................................................................... 5

III. Specifications ........................................................................................................... 6

1. Specification Summary .......................................................................................... 6

2. Device Certifications ............................................................................................. 6

3. Electrical Requirement ........................................................................................... 7

3.1 Supply Voltage ................................................................................................. 7

4. R/W Performance ................................................................................................... 7

IV. Block Diagram ......................................................................................................... 8

V. Interface ..................................................................................................................... 9

1. Pin Assignment ...................................................................................................... 9

2. Signal Description .................................................................................................. 9

VI. Physical Dimensions .............................................................................................. 11

VII. Command Sets ...................................................................................................... 12

1. ATA Commands ................................................................................................... 12

2. SMART Subcommand Sets ................................................................................. 14

VIII. Part Numbering Scheme ..................................................................................... 14

IX. Related Documentation ......................................................................................... 14

50mm

MiniPC

I-e PAT

A Solid State D

rive

I. General Description

The RunCore Pro IV 50mm Mini PCIe SSD has become the ideal choice for the storage

media of the ultra-mobile PC. With its small footprint and industry-standard design, the

Mini PCIe SSD format is fit for embedded solid state storage because it allows for high

capacity and high performance while ensuring compatibility in ultra-mobile application.

The product is compliant with ATA protocol and as standard mini PCIe SSD installed all

major OS, such as Windows 9X/Me/NT/XP/CE/Vista/Windows7, MAC, Linux and Unix.

The 50mm MiniPCIe SSD adopts advanced flash controller and NAND flash, contains the

cache size of 64MB.

1. Product Image

2. Typical Applications

Dell Inspiron Mini 9 Dell Vostro A90

50mm

MiniPC

I-e PAT

A Solid State D

rive

II. Key Features (Flash Management)

1. Advance Wear-Leveling Algorithm

The NAND flash devices are limited by a certain number of write cycles. When using a file

system, frequent file table updates is mandatory. If some area on the flash wears out

faster than others, it would significantly reduce the lifetime of the whole device, even if the

erase counts of others are far from the write cycle limit. Thus, if the write cycles can be

distributed evenly across the media, the lifetime of the media can be prolonged

significantly. The scheme is achieved both via buffer management and specific advanced

wear leveling to ensure that the lifetime of the flash media can be increased, and the disk

access performance is optimized as well.

2. S.M.A.R.T Function

S.M.A.R.T. is an acronym for Self-Monitoring, Analysis and Reporting Technology, an

open standard allowing disk drives to automatically monitor their own health and report

potential problems. It protects the user from unscheduled downtime by monitoring and

storing critical drive performance and calibration parameters. Ideally, this should allow

taking proactive actions to prevent impending drive failure. SMART feature adopts the

standard SMART command B0h to read data from the drive. When the SMART Utility

running on the host, it analyzes and reports the disk status to the host before the device is

in critical condition.

3. Built-in Hardware ECC

The ATA-Disk Module uses BCH Error Detection Code (EDC) and Error Correction Code

(ECC) algorithms which correct up to eight random single-bit errors for each 512-byte

block of data. High performance is fulfilled through hardware-based error detection and

correction.

50mm

MiniPC

I-e PAT

A Solid State D

rive

III. Specifications

1. Specification Summary

Table 1 50mm MiniPCIe PATA SSD Specifications

Performance, power consumption and weight vary with different capacity of products.

2. Device Certifications

Table 2 Certifications

Certification/Compliance Description

CE Compliant

Indicate conformity with the essential health and safety requirements set out in European. Directives Low Voltage

Directive and EMC directive.

Physical

Specifications

Interface MiniPCIe （Internal PATA Control）

Dimension 51mm×36mm×4mm

Capacity 16GB~64GB

Cache 64 MB

Flash Media MLC-NAND Flash

Performance

Sequential Read Up to 81 MB/s

Sequential Write Up to 58 MB/s

4KB Random Read 17 MB/s

4KB Random Write 5 MB/s

Electrical

Specification

Input Voltage 3.3V ± 5%

Power

Consumption

Idle = < 0.5 W

Typical = < 2.0 W (4KB Random write)

Reliability

and

Stability

Write endurance: >80years@10GB write/day（32GB）

Read endurance: unlimited

MTBF: >1,000,000 Hours

Operating Temperature Commercial( 0℃～+70℃)

Weight < 30g

50mm

MiniPC

I-e PAT

A Solid State D

rive

FCC Certified Federal Communications Commission Certified

RoHS Compliant Restriction of Hazardous Substance Directive

3. Electrical Requirement

3.1 Supply Voltage

Overrun the “Maximum Value” listed below will cause permanent damage to the device.

Table 3 Supply Voltage

Symbol Description Min. Value Max. Value Unit

TSGT Storage temperature -65 150 ℃

VCC3.3 Supply power 3.0 3.6 V

4. R/W Performance

Table 4 Read/Write Performance① ATTO Disk Bench

Capacity Read (MB/s) Write (MB/s)

16GB 81 38 32GB 81 52 64GB 81 58

① : Flash media type: MLC Measurement can be varied by its host system.

50mm

MiniPC

I-e PAT

A Solid State D

rive

IV. Block Diagram

Figure 1 MiniPCIe SSD Block Diagram

50mm

MiniPC

I-e PAT

A Solid State D

rive

V. Interface

1. Pin Assignment

Table5 the miniPCIe interface signal assignment Pin

Number Signal Name Pin Type

Pin Number

Signal Name Pin Type

1 D00 I/O 27 GND Ground

2 D15 I/O 28 -IORD I

3 D01 I/O 29 GND Ground

4 GND Ground 30 DMACK I

5 D02 I/O 31 NC

6 D14 I/O 32 -DMARQ O

7 D03 I/O 33 NC

8 D13 I/O 34 GND Ground

9 GND Ground 35 GND Ground

10 D12 I/O 36 NC

11 D04 I/O 37 A00 I

12 D11 I/O 38 NC

13 D05 I/O 39 A01 I

14 D10 I/O 40 GND Ground

15 GND Ground 41 A02 I

16 D09 I/O 42 IORDY O

17 D06 I/O 43 NC

18 GND Ground 44 INTRQ O

19 D07 I/O 45 PDIAG

20 D08 I/O 46 -CS0 I

21 GND Ground 47 VCC Power

22 -RESET I 48 -CS1 I

23 NC 49 VCC Power

24 -IOWR I 50 GND Ground

25 NC 51 VCC Power

26 GND Ground 52 -DASP I

2. Signal Description

Table 6 the miniPCIe interface signal description Signal Name Type Pin Number Description

50mm

MiniPC

I-e PAT

A Solid State D

rive

-DASP (True IDE Mode)

I/O 52

In True IDE Mode, this input/output is the Disk

Active/Slave Present signal in the Master/Slave

handshake protocol.

D15-D00 (True IDE Mode)

I/O

2, 6, 10, 12,14, 16, 20, 19, 17, 13,

11, 7, 5, 3, 1,

In True IDE Mode, all Task File operations occur in bytemode on the low order bus D00-D07 while all data transfers are 16 bit using D00-D15.

-IOWR (True IDE Mode except UDMA protocol active)

STOP (All Modes: UDMA protocol active)

I 24

In True IDE Mode, this signal has the same function as

in PC Card I/O Mode. In all modes, when UDMA mode protocol is active, the assertion of this signal causes the termination of the UDMA data burst.

-IORD (True IDE Mode except UDMA protocol active)

-HDMARDY (All Modes: UDMA protocol DMA Read)

HSTROBE (All Modes: UDMA protocol DMA Write)

I 28

In True IDE Mode, this signal has the same function as

in PC Card I/O Mode.

In all modes when UDMA mode DMA Read is active,

this signal is asserted by the host to indicate that the

host is ready to receive UDMA data-in bursts. The host

may negate -HDMARDY to pause an UDMA transfer In

all modes when UDMA mode DMA Write is active, this

signal is the Data out strobe generated by the host. Both

the rising and falling Edge of HSTROBE cause data to

be latched by the device. The host may stop generating

HSTROBE edges to pause an UDMA data-out burst

INTRQ (True IDE Mode)

O 44 In True IDE Mode, this signal is an active high interrupt request to the host.

A2-A0 (True IDE Mode)

I 41, 39, 37 In True IDE Mode only, A2:A0 are used to select the oneof eight Registers in the Task File. The remaining address lines should be Grounded.

-CS0, -CS1 (True IDE Mode)

I 46, 48

In True IDE Mode, -CS0 is the chip enable for the task file registers when -CS1 is used to select the Alternate Status Register and the mPCI-Express IDE Card Control Register.

-DMACK (True IDE Mode)

I 44

This is a DMA Acknowledge signal that is asserted by the host in response to DMARQ to initiate DMA transfers. In True IDE Mode, while DMA operations are not active, the card shall ignore the DMARQ signal, including a floating condition. If DMA operation is not supported by a True IDE Mode only host, this signal should be driven high or connected to VCC by the host.

50mm

MiniPC

I-e PAT

A Solid State D

rive

DMARQ

(True IDE Mode)

O 32

This signal is a DMA Request that is used for DMA data transfers between host and device. It shall be asserted by the device when it is ready to transfer data to or from the host. For Multiword DMA Transfers, the direction of data transfer is controlled by -IORD and - IOWR. This signal is used in a handshake manner with -DMACK, i.e., the device shall wait until the host asserts-DMACK before negating - DMARQ, and re-asserting -DMARQ if there is more data to transfer. In True IDE Mode, DMARQ shall not be driven when thedevice is not selected in the Drive-Head register. While a DMA operation is in progress, -CS0 and -CS1 shall beheld

VI. Physical Dimensions

Figure 2 the 50mm MiniPCIe PATA SSD Physical Dimension

Table 7 the 50mm MiniPCIe PATA SSD Physical Dimension Parameter Value

Length 50.9 ± 0.10 mm (2.008± 0.004) Width 36.1 ± 0.10 mm (1.417 ± 0.004) Height 4 mm (0.157) max

50mm

MiniPC

I-e PAT

A Solid State D

rive

12

VII. Command Sets

1. ATA Commands

The RunCore 50mm miniPCIe PATA SSD supports all the mandatory ATA commands defined in the ATA/ATAPI-7 specification.

Table 8 Supported ATA Command Lists

Command Name Command Code (Hex) Command Name

CommandCode (Hex)

CHECK POWER MODE

E5h or 98h Disable write cache EFh/82h

DEVICE CONFIGURATION

- Set transfer mode EFh/03h

DEVICE CONFIGURATION

B1h/C1h Enable DMA Setup FIS

Auto-Activate optimization EFh/10h/02h

DEVICE CONFIGURATION

B1h/C2h Disable DMA Setup FIS

Auto-Activate optimization EFh/90h/02h

DEVICE CONFIGURATION

B1h/C0h Enable Device-initiated interface power state

EFh/10h/03h

DEVICE CONFIGURATION SET

B1h/C3h Disable Device-initiated

interface power state EFh/10h/03h

DOW NLOAD MICROCODE

92h SET MAX -

EXECUTE DEVICE DIAGNOSTIC

90h SET MAX ADDRESS F9h/na

FLUSH CACHE E7h SET MAX FREEZE LOCK F9h/04h

FLUSH CACHE EXT EAh SET MAX LOCK F9h/02h

IDENTIFY DEVICE ECh SET MAX SET PASSWORD F9h/01h

IDLE E3h or 97h SET MAX UNLOCK F9h/03h

IDLE IMMEDIATE E1h or 95h SET MAX ADDRESS EXT 37h

INITIALIZE DEVICE PARAMETERS

91h SET MULTIPLE MODE C6h

NOP 00h/00h SLEEP E6h or 99h

50mm

MiniPC

I-e PAT

A Solid State D

rive

13

READ BUFFER E4h SMART -

READ DMA C8h SMART DISABLE

OPERATIONS B0h/D9h

READ DMA EXT 25h SMART ENABLE

OPERATIONS B0h/D8h

READ FPDMA QUEUED

60h SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE

B0h/D2h

READ LOG EXT 2Fh SMART ENABLE/DISABLE

AUTOMATIC OFF-LINE B0h/DBh

READ MULTIPLE C4h SMART EXECUTE OFF-LINE

IMMIDIATE B0h/D4h

READ MULTIPLE EXT 29h SMART READ DATA B0h/D0h

READ NATIVE MAX ADDRESS

F8h SMART READ LOG B0h/D5h

READ NATIVE MAX ADDRESS EXT

27h SMART RETURN STATUS B0h/DAh

READ SECTOR(S) 20h SMART SAVE ATTRIBUTE

VALUES B0h/D3h

READ SECTOR(S) EXT 24h SMART W RITE LOG B0h/D6h

READ VERIFY SECTOR(S)

40h STANDBY E2h or 96h

READ VERIFY SECTOR(S) EXT

42h STANDBY IMMEDIATE E0h or 94h

SECURITY DISABLE PASSWORD

F6h WRITE BUFFER E8h

SECURITY ERASE PREPARE

F3h WRITE DMA CAh

SECURITY ERASE UNIT

F4h WRITE DMA EXT 35h

SECURITY FREEZE LOCK

F5h WRITE FPDMA QUEUED 61h

SECURITY SET PASSWORD

F1h WRITE LOG EXT 3Fh

SECURITY UNLOCK F2h WRITE MULTIPLE C5h

SEEK 70h WRITE MULTIPLE EXT 39h

SET FEATURES - WRITE SECTOR(S) 30h

50mm

MiniPC

I-e PAT

A Solid State D

rive

14

Enable write cache EFh/02h WRITE SECTOR(S) EXT 34h

2. SMART Subcommand Sets

In order to select a subcommand the host must write the subcommand code to the device's Features Register before issuing the SMART function set command. The subcommands are listed below.

Table 9 SMART Subcommand Sets

VIII. Part Numbering Scheme

Please refer to PN naming Rule Guideline for more specific identification of

product.

IX. Related Documentation

For more information, visit www.runcore.com or contact support@runcore.com

Command Command Code (Hex)

SMART READ DATA D0h

SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE D2h

SMART SAVE ATTRIBUTE VALUES D3h

SMART EXECUTE OFF-LINE IMMIDIATE D4h

SMART READ LOG D5h

SMART W RITE LOG D6h

SMART ENABLE OPERATIONS D8h

SMART DISABLE OPERATIONS D9h

SMART RETURN STATUS DAh

SMART ENABLE/DISABLE AUTOMATIC OFF-LINE DBh