*Review: Design Objectives

*Co-design FlowSystemModelSystem SimulationInformal SpecificationHardware/Software PartitioningPartitionedModelSchedulePartitionedModel & Sch.HW/SW Co-simulationRefineAlgorithmic Design

*Co-design FlowPartitionedModel + Sch.CommunicationSynthesisSoftwareModelHardwareModelHW/SW Co-simulationCompilationSynthesisHW/SW Co-simulationGate-levelModelBinary Exec.ModelRefine

Winter 2010- CS 244*Co-design FlowGate-levelModelBinary Exec.ModelEmulate orPrototypeRefineFabrication

Winter 2010- CS 244

*Informal Specification & System Level ModelInformal Specification loosely defines high level behavior, constraints, and optimization objectives of the systemAlgorithmic and implementation details absentPerformance estimates not presentSystem level model formally captures behavior, constraints, and optimization objectivesCan be simulated to obtain early performance estimatesFeedback to refine the system specificationCan serve as a golden model for validation of intermediate or final stagesAlgorithmic design

*Hardware Software PartitioningDecompose (i.e., partition) the function F of the system into N sub-functions F1, F2, F3 FNDecompose the constraints and design objectives of the system into sub-constraints and design sub-objectivesCluster F1, F2, F3, , Fn into M partitions to run on M processors

*SchedulingScheduling is to obtain an execution sequence such that dependencies are obeyedStaticDuring design time the schedule is fixed (the common case)DynamicDuring execution time, the schedule is determined (reconfigurable computing)F1F2F3F4F5F6F7F8

Winter 2010- CS 244*SchedulingA deadline D for the entire scheduleAn execution time for each Ti for each FiASAP (as soon as possible)ALAP (as late as possible)F1F2F3F4F5F6F7F833312643

Winter 2010- CS 244

*Partitioning (Clustering)Iterative partitioningStart with a partition and improveGradient searchControlled random searchModified Kernighan/Lin and FM algorithmPartitions a set of nodes (functions) into two bins (processors)Minimize edges between bins (communication cost, wires, etc.)Cost function for moving a node from one partition to anotherILPGenetic evolutionSimulated annealing

Iterative Partitioning AlgorithmsThe computation time in an iterative algorithm is spent evaluating large numbers of partitionsIterative algorithms differ from one another primarily in the ways in which they modify the partition and in which they accept or reject bad modifications

Kernighan-Lin (Min-Cut) AlgorithmsTwo-way partitioning exampleStart with 2 equal subgraphsExchange k pairs in each iterationContinue until no further improvementGain functionf(internal external) cost

*Hierarchical Clustering Example

*Alternate Partitioning TechniquesStart with all functionality in software and move portions into hardware which are time-critical and can not be allocated to software (software-oriented partitioning)Start with all functionality in hardware and move portions into software implementation (hardware-oriented partitioning)

*More Partitioning IssuesPartitioning into hardware and software affects overall system cost and performanceHardware implementationProvides higher performance via hardware speeds and parallel execution of operationsIncurs additional design expenseSoftware implementationLower performanceIncurs high cost of developing and maintaining (complex) software

*Functional Co-simulationSome of the M processors are single-purpose (e.g., those with a single function mapped on to them), others are general purposeFunctions mapped onto the general-purpose processors are implemented in software and simulated on virtual machines with performance modelsFunctions mapped onto the single-purpose processors are simulated at the behavioral level with performance modelsCommunication is done via abstract channelsFeedback is used to refine the partitioning and scheduling tasks

*Communication Synthesis & Bus-accurate Co-simulationAbstract channels A1, A2 An are mapped onto a set of communication channels C1, C2 CmSimilar to functional partitioningSimilar to hardware/software schedulingChannels correspond to physical artifacts of the architectureHardware and software models are annotated with detailed communication constructsA hardware model and software model is obtained and co-simulatedCommunication synthesis (or possibly higher levels of design) are refined

*Compilation & Synthesis & Cycle-accurate Co-simulationCompiler used to generate binary executables for general-purpose processorsSynthesis used to generate gate-level models of single-purpose processorsSynthesis used to generate gate-level models of general-purpose processorsCycle accurate co-simulation of the entire system Note: mixed level co-simulation is common

*Emulate/Prototype and FabricationUse hardware (e.g, FPGAs) to emulate a system as fast as possible (relative to real-time)FabricationPlace & routeMask designChip testingManufacturing fault modelsTest vector generationPackaging

*ConclusionSatisfying performance, cost, and quality metrics of a system entails hardware and software codesignPartitioning is at the heart of codesignFunctionalCommunicationSchedulingPartitioning techniquesConstructiveIterativeHeuristics often used to bound the running time

*In the graph above, C represents a solution which would consume fewer resources (in HW and SW) than A or B, yet it might be very difficult to find, and solution A may be good enough.Multivariate optimization is a much-studied problem in CS. The interested reader should investigate this area to understand the problems inherent in optimal partitioning.

[Gajski94].

*In the graph above, C represents a solution which would consume fewer resources (in HW and SW) than A or B, yet it might be very difficult to find, and solution A may be good enough.Multivariate optimization is a much-studied problem in CS. The interested reader should investigate this area to understand the problems inherent in optimal partitioning.

[Gajski94].