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ARM Processors

(Advanced RISC Machines)

G N V Ratnakishor

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Introduction to 16/32 bit processors

A 32-bit processor with an instruction setfacilitating a subset of instructions for 16-bitcoding is called 16/32-bit processor

ARM has 32-bit instruction set supported by a 16-bit compressed code, called Thumb instructionset.

MCUs based on ARM architecture provides thefollowingPrecise computing

Minimum power dissipation

Smaller code-size for given computations

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Applications

Mobile phones

Image processing

Video games

Robotics

Adaptive control systems

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ARM uses RISC superscalar processor

architecture

Processor retains the best of CISC features

also.

ARM architectures are used as core or chip.

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ARM basic features

1. RISC feature

2. 32-bit ARM CISC like instruction set

implemented with low power dissipation

3. 16-bit Thumb extension for low code density

4. Multiple variants

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ARMs RISC features

Same length instructions

Single cycle execution due to three-stage pipeline.

Hardwired implementation

Large register set

Load-Store architecture

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Three stage pipeline

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ARM variants

1. v1 ARM1

2. v2 ARM2

3. v2as ARM3, and ARM2504. v3 ARM6, ARM7, and ARM8

5. v4 Strong ARM, and ARM9

6. v6 ARM10

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Processor modes

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ARM register set

ARM has 37 registers all of which are 32-bits long

1 dedicated program counter

1 dedicated current program status register (CPSR)

5 dedicated saved program status registers (SPSR)

30 general purpose registers.

Each mode can access

A particular set of r0-r12 registers

A particular r13 (SP) and r14 (link register, lr)

The program counter (PC)

The current program status register (CPSR)

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ARM/THUMB programming model

Overview of the memory organization in ARM

family MCUs.ARM

Princeton

Architecture

(ARM7)

Harvard

Architecture

(ARM9)

Word(32-bits)

(B3-B2-B1-B0)

B0

B1

B2

B3

B3

B2

B1

B0

Address 0

Address 1

Address 2

Address 3

Littleendian

Bigendian

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ARM processor operates on 32-bit words at an

instance and can also operate separately on each

byte or on half words.

When used in relation to the ARM: Byte means 8 bits

Halfword means 16 bits (two bytes)

Word means 32 bits (four bytes)

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CPU architecture

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RALU (Register Arithmetic Logic Unit)

Three address machine with two source operands and one

destination operands.

Source 1: one of the source operands from a register. Source 2:

Can be either from register+memory, or from register, or an immediate

operand.

Can also be first operand with rotate or shift instructions.

Result is stored in destination register.

IR (Instruction Register)

Holds the current instruction byte

ID (Instruction Decoder) Decode the IR byte and activate the appropriate signals for

hardwired implementation of instruction at IR.

C di i l T d B h L i

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Conditional Test and Branch Logic

Additional circuit to test the flags and initiate appropriateprogram flow path by branching.

CSPR

Current Program Status Register for each mode

Conditional code flags: N(Negative flag), Z(Zero flag),C(Carryflag), and V(Overflow flag)

T bit : 0 for ARM state

1 for Thumb state

SPSR

Saved Program Status Word

Saves program status register from CPSR on branch andlink(routine call)

SPSR is stacked for each processor mode

32-bit MAC

Needed for DSP and control applications

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Instruction set

Conditional execution and flags:

ARM instructions can be made to execute

conditionally by post fixing them with the

appropriate condition code field.

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By default, data processing instructions do not

affect condition code flags but the flags can be

optionally set by using s.

CMP does not need s

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Branch instructions

An unconditional jump:

LABEL .

..B LABEL ; unconditional branch

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D i i i

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Data processing instructions:

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M lti l i t ti

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Multiply instructions:

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